1 <counter_set name="ARMv7_Cortex_A15_cnt" count="6"/>
2 <category name="Cortex-A15" counter_set="ARMv7_Cortex_A15_cnt" per_cpu="yes" supports_event_based_sampling="yes">
3 <event counter="ARMv7_Cortex_A15_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
4 <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>
5 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
6 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
7 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
8 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
9 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
10 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
11 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
12 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
13 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
14 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
15 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
16 <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
17 <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>
18 <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
19 <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
20 <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
21 <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
22 <event event="0x19" title="Bus" name="Access" description="Bus - Access"/>
23 <event event="0x1a" title="Memory" name="Error" description="Local memory error"/>
24 <event event="0x1b" title="Instruction" name="Speculative" description="Instruction speculatively executed"/>
25 <event event="0x1c" title="Memory" name="Translation table" description="Write to translation table base architecturally executed"/>
26 <event event="0x1d" title="Bus" name="Cycle" description="Bus - Cycle"/>
27 <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
28 <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
29 <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
30 <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
31 <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-Back - Victim"/>
32 <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-Back - Cleaning and coherency"/>
33 <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
34 <event event="0x4c" title="TLB" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
35 <event event="0x4d" title="TLB" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
36 <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
37 <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
38 <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
39 <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
40 <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-Back - Victim"/>
41 <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-Back - Cleaning and coherency"/>
42 <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
43 <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
44 <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
45 <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
46 <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
47 <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
48 <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
49 <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
50 <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
51 <event event="0x6a" title="Memory" name="Unaligned" description="Unaligned access"/>
52 <event event="0x6c" title="Intrinsic" name="LDREX" description="Exclusive instruction speculatively executed - LDREX"/>
53 <event event="0x6d" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
54 <event event="0x6e" title="Intrinsic" name="STREX fail" description="Exclusive instruction speculatively executed - STREX fail"/>
55 <event event="0x70" title="Instruction" name="Load" description="Instruction speculatively executed - Load"/>
56 <event event="0x71" title="Instruction" name="Store" description="Instruction speculatively executed - Store"/>
57 <event event="0x72" title="Instruction" name="Load/Store" description="Instruction speculatively executed - Load or store"/>
58 <event event="0x73" title="Instruction" name="Integer" description="Instruction speculatively executed - Integer data processing"/>
59 <event event="0x74" title="Instruction" name="Advanced SIMD" description="Instruction speculatively executed - Advanced SIMD"/>
60 <event event="0x75" title="Instruction" name="VFP" description="Instruction speculatively executed - VFP"/>
61 <event event="0x76" title="Instruction" name="Software change" description="Instruction speculatively executed - Software change of the PC"/>
62 <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
63 <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
64 <event event="0x7a" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
65 <event event="0x7c" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
66 <event event="0x7d" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
67 <event event="0x7e" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
68 </category>