1 <counter_set name="Krait_cntX">\r
2 <counter name="Krait_cnt0"/>\r
3 <counter name="Krait_cnt1"/>\r
4 <counter name="Krait_cnt2"/>\r
5 <counter name="Krait_cnt3"/>\r
6 </counter_set>\r
7 <category name="Krait" counter_set="Krait_cntX" per_cpu="yes">\r
8 <event counter="Krait_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>\r
9 <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>\r
10 <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>\r
11 <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
12 <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>\r
13 <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>\r
14 <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
15 <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>\r
16 <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>\r
17 <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>\r
18 <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>\r
19 <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>\r
20 <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>\r
21 <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>\r
22 <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>\r
23 <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/>\r
24 <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>\r
25 <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>\r
26 <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>\r
27 </category>\r