1 /**
2 * Copyright (C) ARM Limited 2011-2012. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 #include "gator.h"
11 // gator_events_perf_pmu.c is used if perf is supported
12 #if GATOR_NO_PERF_SUPPORT
14 static const char *pmnc_name;
15 static int pmnc_counters;
17 // Per-CPU PMNC: config reg
18 #define PMNC_E (1 << 0) /* Enable all counters */
19 #define PMNC_P (1 << 1) /* Reset all counters */
20 #define PMNC_C (1 << 2) /* Cycle counter reset */
21 #define PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
22 #define PMNC_X (1 << 4) /* Export to ETM */
23 #define PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
24 #define PMNC_MASK 0x3f /* Mask for writable bits */
26 // ccnt reg
27 #define CCNT_REG (1 << 31)
29 #define CCNT 0
30 #define CNT0 1
31 #define CNTMAX (4+1)
33 static unsigned long pmnc_enabled[CNTMAX];
34 static unsigned long pmnc_event[CNTMAX];
35 static unsigned long pmnc_key[CNTMAX];
37 static DEFINE_PER_CPU(int[CNTMAX * 2], perfCnt);
39 enum scorpion_perf_types {
40 SCORPION_ICACHE_EXPL_INV = 0x4c,
41 SCORPION_ICACHE_MISS = 0x4d,
42 SCORPION_ICACHE_ACCESS = 0x4e,
43 SCORPION_ICACHE_CACHEREQ_L2 = 0x4f,
44 SCORPION_ICACHE_NOCACHE_L2 = 0x50,
45 SCORPION_HIQUP_NOPED = 0x51,
46 SCORPION_DATA_ABORT = 0x52,
47 SCORPION_IRQ = 0x53,
48 SCORPION_FIQ = 0x54,
49 SCORPION_ALL_EXCPT = 0x55,
50 SCORPION_UNDEF = 0x56,
51 SCORPION_SVC = 0x57,
52 SCORPION_SMC = 0x58,
53 SCORPION_PREFETCH_ABORT = 0x59,
54 SCORPION_INDEX_CHECK = 0x5a,
55 SCORPION_NULL_CHECK = 0x5b,
56 SCORPION_EXPL_ICIALLU = 0x5c,
57 SCORPION_IMPL_ICIALLU = 0x5d,
58 SCORPION_NONICIALLU_BTAC_INV = 0x5e,
59 SCORPION_ICIMVAU_IMPL_ICIALLU = 0x5f,
60 SCORPION_SPIPE_ONLY_CYCLES = 0x60,
61 SCORPION_XPIPE_ONLY_CYCLES = 0x61,
62 SCORPION_DUAL_CYCLES = 0x62,
63 SCORPION_DISPATCH_ANY_CYCLES = 0x63,
64 SCORPION_FIFO_FULLBLK_CMT = 0x64,
65 SCORPION_FAIL_COND_INST = 0x65,
66 SCORPION_PASS_COND_INST = 0x66,
67 SCORPION_ALLOW_VU_CLK = 0x67,
68 SCORPION_VU_IDLE = 0x68,
69 SCORPION_ALLOW_L2_CLK = 0x69,
70 SCORPION_L2_IDLE = 0x6a,
71 SCORPION_DTLB_IMPL_INV_SCTLR_DACR = 0x6b,
72 SCORPION_DTLB_EXPL_INV = 0x6c,
73 SCORPION_DTLB_MISS = 0x6d,
74 SCORPION_DTLB_ACCESS = 0x6e,
75 SCORPION_ITLB_MISS = 0x6f,
76 SCORPION_ITLB_IMPL_INV = 0x70,
77 SCORPION_ITLB_EXPL_INV = 0x71,
78 SCORPION_UTLB_D_MISS = 0x72,
79 SCORPION_UTLB_D_ACCESS = 0x73,
80 SCORPION_UTLB_I_MISS = 0x74,
81 SCORPION_UTLB_I_ACCESS = 0x75,
82 SCORPION_UTLB_INV_ASID = 0x76,
83 SCORPION_UTLB_INV_MVA = 0x77,
84 SCORPION_UTLB_INV_ALL = 0x78,
85 SCORPION_S2_HOLD_RDQ_UNAVAIL = 0x79,
86 SCORPION_S2_HOLD = 0x7a,
87 SCORPION_S2_HOLD_DEV_OP = 0x7b,
88 SCORPION_S2_HOLD_ORDER = 0x7c,
89 SCORPION_S2_HOLD_BARRIER = 0x7d,
90 SCORPION_VIU_DUAL_CYCLE = 0x7e,
91 SCORPION_VIU_SINGLE_CYCLE = 0x7f,
92 SCORPION_VX_PIPE_WAR_STALL_CYCLES = 0x80,
93 SCORPION_VX_PIPE_WAW_STALL_CYCLES = 0x81,
94 SCORPION_VX_PIPE_RAW_STALL_CYCLES = 0x82,
95 SCORPION_VX_PIPE_LOAD_USE_STALL = 0x83,
96 SCORPION_VS_PIPE_WAR_STALL_CYCLES = 0x84,
97 SCORPION_VS_PIPE_WAW_STALL_CYCLES = 0x85,
98 SCORPION_VS_PIPE_RAW_STALL_CYCLES = 0x86,
99 SCORPION_EXCEPTIONS_INV_OPERATION = 0x87,
100 SCORPION_EXCEPTIONS_DIV_BY_ZERO = 0x88,
101 SCORPION_COND_INST_FAIL_VX_PIPE = 0x89,
102 SCORPION_COND_INST_FAIL_VS_PIPE = 0x8a,
103 SCORPION_EXCEPTIONS_OVERFLOW = 0x8b,
104 SCORPION_EXCEPTIONS_UNDERFLOW = 0x8c,
105 SCORPION_EXCEPTIONS_DENORM = 0x8d,
106 #ifdef CONFIG_ARCH_MSM_SCORPIONMP
107 SCORPIONMP_NUM_BARRIERS = 0x8e,
108 SCORPIONMP_BARRIER_CYCLES = 0x8f,
109 #else
110 SCORPION_BANK_AB_HIT = 0x8e,
111 SCORPION_BANK_AB_ACCESS = 0x8f,
112 SCORPION_BANK_CD_HIT = 0x90,
113 SCORPION_BANK_CD_ACCESS = 0x91,
114 SCORPION_BANK_AB_DSIDE_HIT = 0x92,
115 SCORPION_BANK_AB_DSIDE_ACCESS = 0x93,
116 SCORPION_BANK_CD_DSIDE_HIT = 0x94,
117 SCORPION_BANK_CD_DSIDE_ACCESS = 0x95,
118 SCORPION_BANK_AB_ISIDE_HIT = 0x96,
119 SCORPION_BANK_AB_ISIDE_ACCESS = 0x97,
120 SCORPION_BANK_CD_ISIDE_HIT = 0x98,
121 SCORPION_BANK_CD_ISIDE_ACCESS = 0x99,
122 SCORPION_ISIDE_RD_WAIT = 0x9a,
123 SCORPION_DSIDE_RD_WAIT = 0x9b,
124 SCORPION_BANK_BYPASS_WRITE = 0x9c,
125 SCORPION_BANK_AB_NON_CASTOUT = 0x9d,
126 SCORPION_BANK_AB_L2_CASTOUT = 0x9e,
127 SCORPION_BANK_CD_NON_CASTOUT = 0x9f,
128 SCORPION_BANK_CD_L2_CASTOUT = 0xa0,
129 #endif
130 MSM_MAX_EVT
131 };
133 struct scorp_evt {
134 u32 evt_type;
135 u32 val;
136 u8 grp;
137 u32 evt_type_act;
138 };
140 static const struct scorp_evt sc_evt[] = {
141 {SCORPION_ICACHE_EXPL_INV, 0x80000500, 0, 0x4d},
142 {SCORPION_ICACHE_MISS, 0x80050000, 0, 0x4e},
143 {SCORPION_ICACHE_ACCESS, 0x85000000, 0, 0x4f},
144 {SCORPION_ICACHE_CACHEREQ_L2, 0x86000000, 0, 0x4f},
145 {SCORPION_ICACHE_NOCACHE_L2, 0x87000000, 0, 0x4f},
146 {SCORPION_HIQUP_NOPED, 0x80080000, 0, 0x4e},
147 {SCORPION_DATA_ABORT, 0x8000000a, 0, 0x4c},
148 {SCORPION_IRQ, 0x80000a00, 0, 0x4d},
149 {SCORPION_FIQ, 0x800a0000, 0, 0x4e},
150 {SCORPION_ALL_EXCPT, 0x8a000000, 0, 0x4f},
151 {SCORPION_UNDEF, 0x8000000b, 0, 0x4c},
152 {SCORPION_SVC, 0x80000b00, 0, 0x4d},
153 {SCORPION_SMC, 0x800b0000, 0, 0x4e},
154 {SCORPION_PREFETCH_ABORT, 0x8b000000, 0, 0x4f},
155 {SCORPION_INDEX_CHECK, 0x8000000c, 0, 0x4c},
156 {SCORPION_NULL_CHECK, 0x80000c00, 0, 0x4d},
157 {SCORPION_EXPL_ICIALLU, 0x8000000d, 0, 0x4c},
158 {SCORPION_IMPL_ICIALLU, 0x80000d00, 0, 0x4d},
159 {SCORPION_NONICIALLU_BTAC_INV, 0x800d0000, 0, 0x4e},
160 {SCORPION_ICIMVAU_IMPL_ICIALLU, 0x8d000000, 0, 0x4f},
162 {SCORPION_SPIPE_ONLY_CYCLES, 0x80000600, 1, 0x51},
163 {SCORPION_XPIPE_ONLY_CYCLES, 0x80060000, 1, 0x52},
164 {SCORPION_DUAL_CYCLES, 0x86000000, 1, 0x53},
165 {SCORPION_DISPATCH_ANY_CYCLES, 0x89000000, 1, 0x53},
166 {SCORPION_FIFO_FULLBLK_CMT, 0x8000000d, 1, 0x50},
167 {SCORPION_FAIL_COND_INST, 0x800d0000, 1, 0x52},
168 {SCORPION_PASS_COND_INST, 0x8d000000, 1, 0x53},
169 {SCORPION_ALLOW_VU_CLK, 0x8000000e, 1, 0x50},
170 {SCORPION_VU_IDLE, 0x80000e00, 1, 0x51},
171 {SCORPION_ALLOW_L2_CLK, 0x800e0000, 1, 0x52},
172 {SCORPION_L2_IDLE, 0x8e000000, 1, 0x53},
174 {SCORPION_DTLB_IMPL_INV_SCTLR_DACR, 0x80000001, 2, 0x54},
175 {SCORPION_DTLB_EXPL_INV, 0x80000100, 2, 0x55},
176 {SCORPION_DTLB_MISS, 0x80010000, 2, 0x56},
177 {SCORPION_DTLB_ACCESS, 0x81000000, 2, 0x57},
178 {SCORPION_ITLB_MISS, 0x80000200, 2, 0x55},
179 {SCORPION_ITLB_IMPL_INV, 0x80020000, 2, 0x56},
180 {SCORPION_ITLB_EXPL_INV, 0x82000000, 2, 0x57},
181 {SCORPION_UTLB_D_MISS, 0x80000003, 2, 0x54},
182 {SCORPION_UTLB_D_ACCESS, 0x80000300, 2, 0x55},
183 {SCORPION_UTLB_I_MISS, 0x80030000, 2, 0x56},
184 {SCORPION_UTLB_I_ACCESS, 0x83000000, 2, 0x57},
185 {SCORPION_UTLB_INV_ASID, 0x80000400, 2, 0x55},
186 {SCORPION_UTLB_INV_MVA, 0x80040000, 2, 0x56},
187 {SCORPION_UTLB_INV_ALL, 0x84000000, 2, 0x57},
188 {SCORPION_S2_HOLD_RDQ_UNAVAIL, 0x80000800, 2, 0x55},
189 {SCORPION_S2_HOLD, 0x88000000, 2, 0x57},
190 {SCORPION_S2_HOLD_DEV_OP, 0x80000900, 2, 0x55},
191 {SCORPION_S2_HOLD_ORDER, 0x80090000, 2, 0x56},
192 {SCORPION_S2_HOLD_BARRIER, 0x89000000, 2, 0x57},
194 {SCORPION_VIU_DUAL_CYCLE, 0x80000001, 4, 0x5c},
195 {SCORPION_VIU_SINGLE_CYCLE, 0x80000100, 4, 0x5d},
196 {SCORPION_VX_PIPE_WAR_STALL_CYCLES, 0x80000005, 4, 0x5c},
197 {SCORPION_VX_PIPE_WAW_STALL_CYCLES, 0x80000500, 4, 0x5d},
198 {SCORPION_VX_PIPE_RAW_STALL_CYCLES, 0x80050000, 4, 0x5e},
199 {SCORPION_VX_PIPE_LOAD_USE_STALL, 0x80000007, 4, 0x5c},
200 {SCORPION_VS_PIPE_WAR_STALL_CYCLES, 0x80000008, 4, 0x5c},
201 {SCORPION_VS_PIPE_WAW_STALL_CYCLES, 0x80000800, 4, 0x5d},
202 {SCORPION_VS_PIPE_RAW_STALL_CYCLES, 0x80080000, 4, 0x5e},
203 {SCORPION_EXCEPTIONS_INV_OPERATION, 0x8000000b, 4, 0x5c},
204 {SCORPION_EXCEPTIONS_DIV_BY_ZERO, 0x80000b00, 4, 0x5d},
205 {SCORPION_COND_INST_FAIL_VX_PIPE, 0x800b0000, 4, 0x5e},
206 {SCORPION_COND_INST_FAIL_VS_PIPE, 0x8b000000, 4, 0x5f},
207 {SCORPION_EXCEPTIONS_OVERFLOW, 0x8000000c, 4, 0x5c},
208 {SCORPION_EXCEPTIONS_UNDERFLOW, 0x80000c00, 4, 0x5d},
209 {SCORPION_EXCEPTIONS_DENORM, 0x8c000000, 4, 0x5f},
211 #ifdef CONFIG_ARCH_MSM_SCORPIONMP
212 {SCORPIONMP_NUM_BARRIERS, 0x80000e00, 3, 0x59},
213 {SCORPIONMP_BARRIER_CYCLES, 0x800e0000, 3, 0x5a},
214 #else
215 {SCORPION_BANK_AB_HIT, 0x80000001, 3, 0x58},
216 {SCORPION_BANK_AB_ACCESS, 0x80000100, 3, 0x59},
217 {SCORPION_BANK_CD_HIT, 0x80010000, 3, 0x5a},
218 {SCORPION_BANK_CD_ACCESS, 0x81000000, 3, 0x5b},
219 {SCORPION_BANK_AB_DSIDE_HIT, 0x80000002, 3, 0x58},
220 {SCORPION_BANK_AB_DSIDE_ACCESS, 0x80000200, 3, 0x59},
221 {SCORPION_BANK_CD_DSIDE_HIT, 0x80020000, 3, 0x5a},
222 {SCORPION_BANK_CD_DSIDE_ACCESS, 0x82000000, 3, 0x5b},
223 {SCORPION_BANK_AB_ISIDE_HIT, 0x80000003, 3, 0x58},
224 {SCORPION_BANK_AB_ISIDE_ACCESS, 0x80000300, 3, 0x59},
225 {SCORPION_BANK_CD_ISIDE_HIT, 0x80030000, 3, 0x5a},
226 {SCORPION_BANK_CD_ISIDE_ACCESS, 0x83000000, 3, 0x5b},
227 {SCORPION_ISIDE_RD_WAIT, 0x80000009, 3, 0x58},
228 {SCORPION_DSIDE_RD_WAIT, 0x80090000, 3, 0x5a},
229 {SCORPION_BANK_BYPASS_WRITE, 0x8000000a, 3, 0x58},
230 {SCORPION_BANK_AB_NON_CASTOUT, 0x8000000c, 3, 0x58},
231 {SCORPION_BANK_AB_L2_CASTOUT, 0x80000c00, 3, 0x59},
232 {SCORPION_BANK_CD_NON_CASTOUT, 0x800c0000, 3, 0x5a},
233 {SCORPION_BANK_CD_L2_CASTOUT, 0x8c000000, 3, 0x5b},
234 #endif
235 };
237 static inline void scorpion_pmnc_write(u32 val)
238 {
239 val &= PMNC_MASK;
240 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));
241 }
243 static inline u32 scorpion_pmnc_read(void)
244 {
245 u32 val;
246 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
247 return val;
248 }
250 static inline u32 scorpion_ccnt_read(void)
251 {
252 u32 val;
253 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
254 return val;
255 }
257 static inline u32 scorpion_cntn_read(void)
258 {
259 u32 val;
260 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
261 return val;
262 }
264 static inline u32 scorpion_pmnc_enable_counter(unsigned int cnt)
265 {
266 u32 val;
268 if (cnt >= CNTMAX) {
269 pr_err("gator: CPU%u enabling wrong PMNC counter %d\n", smp_processor_id(), cnt);
270 return -1;
271 }
273 if (cnt == CCNT)
274 val = CCNT_REG;
275 else
276 val = (1 << (cnt - CNT0));
278 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
280 return cnt;
281 }
283 static inline u32 scorpion_pmnc_disable_counter(unsigned int cnt)
284 {
285 u32 val;
287 if (cnt >= CNTMAX) {
288 pr_err("gator: CPU%u disabling wrong PMNC counter %d\n", smp_processor_id(), cnt);
289 return -1;
290 }
292 if (cnt == CCNT)
293 val = CCNT_REG;
294 else
295 val = (1 << (cnt - CNT0));
297 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
299 return cnt;
300 }
302 static inline int scorpion_pmnc_select_counter(unsigned int cnt)
303 {
304 u32 val;
306 if ((cnt == CCNT) || (cnt >= CNTMAX)) {
307 pr_err("gator: CPU%u selecting wrong PMNC counter %d\n", smp_processor_id(), cnt);
308 return -1;
309 }
311 val = (cnt - CNT0);
312 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
314 return cnt;
315 }
317 static u32 scorpion_read_lpm0(void)
318 {
319 u32 val;
320 asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val));
321 return val;
322 }
324 static void scorpion_write_lpm0(u32 val)
325 {
326 asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val));
327 }
329 static u32 scorpion_read_lpm1(void)
330 {
331 u32 val;
332 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
333 return val;
334 }
336 static void scorpion_write_lpm1(u32 val)
337 {
338 asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val));
339 }
341 static u32 scorpion_read_lpm2(void)
342 {
343 u32 val;
344 asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val));
345 return val;
346 }
348 static void scorpion_write_lpm2(u32 val)
349 {
350 asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val));
351 }
353 static u32 scorpion_read_l2lpm(void)
354 {
355 u32 val;
356 asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val));
357 return val;
358 }
360 static void scorpion_write_l2lpm(u32 val)
361 {
362 asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val));
363 }
365 static u32 scorpion_read_vlpm(void)
366 {
367 u32 val;
368 asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val));
369 return val;
370 }
372 static void scorpion_write_vlpm(u32 val)
373 {
374 asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val));
375 }
377 struct scorpion_access_funcs {
378 u32 (*read) (void);
379 void (*write) (u32);
380 };
382 struct scorpion_access_funcs scor_func[] = {
383 {scorpion_read_lpm0, scorpion_write_lpm0},
384 {scorpion_read_lpm1, scorpion_write_lpm1},
385 {scorpion_read_lpm2, scorpion_write_lpm2},
386 {scorpion_read_l2lpm, scorpion_write_l2lpm},
387 {scorpion_read_vlpm, scorpion_write_vlpm},
388 };
390 u32 venum_orig_val;
391 u32 fp_orig_val;
393 static void scorpion_pre_vlpm(void)
394 {
395 u32 venum_new_val;
396 u32 fp_new_val;
398 /* CPACR Enable CP10 access*/
399 asm volatile("mrc p15, 0, %0, c1, c0, 2" : "=r" (venum_orig_val));
400 venum_new_val = venum_orig_val | 0x00300000;
401 asm volatile("mcr p15, 0, %0, c1, c0, 2" : : "r" (venum_new_val));
402 /* Enable FPEXC */
403 asm volatile("mrc p10, 7, %0, c8, c0, 0" : "=r" (fp_orig_val));
404 fp_new_val = fp_orig_val | 0x40000000;
405 asm volatile("mcr p10, 7, %0, c8, c0, 0" : : "r" (fp_new_val));
406 }
408 static void scorpion_post_vlpm(void)
409 {
410 /* Restore FPEXC*/
411 asm volatile("mcr p10, 7, %0, c8, c0, 0" : : "r" (fp_orig_val));
412 /* Restore CPACR*/
413 asm volatile("mcr p15, 0, %0, c1, c0, 2" : : "r" (venum_orig_val));
414 }
416 #define COLMN0MASK 0x000000ff
417 #define COLMN1MASK 0x0000ff00
418 #define COLMN2MASK 0x00ff0000
419 static u32 scorpion_get_columnmask(u32 setval)
420 {
421 if (setval & COLMN0MASK)
422 return 0xffffff00;
423 else if (setval & COLMN1MASK)
424 return 0xffff00ff;
425 else if (setval & COLMN2MASK)
426 return 0xff00ffff;
427 else
428 return 0x80ffffff;
429 }
431 static void scorpion_evt_setup(u32 gr, u32 setval)
432 {
433 u32 val;
434 if (gr == 4)
435 scorpion_pre_vlpm();
436 val = scorpion_get_columnmask(setval) & scor_func[gr].read();
437 val = val | setval;
438 scor_func[gr].write(val);
439 if (gr == 4)
440 scorpion_post_vlpm();
441 }
443 static int get_scorpion_evtinfo(unsigned int evt_type, struct scorp_evt *evtinfo)
444 {
445 u32 idx;
446 if ((evt_type < 0x4c) || (evt_type >= MSM_MAX_EVT))
447 return 0;
448 idx = evt_type - 0x4c;
449 if (sc_evt[idx].evt_type == evt_type) {
450 evtinfo->val = sc_evt[idx].val;
451 evtinfo->grp = sc_evt[idx].grp;
452 evtinfo->evt_type_act = sc_evt[idx].evt_type_act;
453 return 1;
454 }
455 return 0;
456 }
458 static inline void scorpion_pmnc_write_evtsel(unsigned int cnt, u32 val)
459 {
460 if (scorpion_pmnc_select_counter(cnt) == cnt) {
461 if (val < 0x40) {
462 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
463 } else {
464 u32 zero = 0;
465 struct scorp_evt evtinfo;
466 // extract evtinfo.grp and evtinfo.tevt_type_act from val
467 if (get_scorpion_evtinfo(val, &evtinfo) == 0) return;
468 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (evtinfo.evt_type_act));
469 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (zero));
470 scorpion_evt_setup(evtinfo.grp, val);
471 }
472 }
473 }
475 static void scorpion_pmnc_reset_counter(unsigned int cnt)
476 {
477 u32 val = 0;
479 if (cnt == CCNT) {
480 scorpion_pmnc_disable_counter(cnt);
482 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val));
484 if (pmnc_enabled[cnt] != 0)
485 scorpion_pmnc_enable_counter(cnt);
487 } else if (cnt >= CNTMAX) {
488 pr_err("gator: CPU%u resetting wrong PMNC counter %d\n", smp_processor_id(), cnt);
489 } else {
490 scorpion_pmnc_disable_counter(cnt);
492 if (scorpion_pmnc_select_counter(cnt) == cnt)
493 asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (val));
495 if (pmnc_enabled[cnt] != 0)
496 scorpion_pmnc_enable_counter(cnt);
497 }
498 }
500 static int gator_events_scorpion_create_files(struct super_block *sb, struct dentry *root)
501 {
502 struct dentry *dir;
503 int i;
505 for (i = 0; i < pmnc_counters; i++) {
506 char buf[40];
507 if (i == 0) {
508 snprintf(buf, sizeof buf, "%s_ccnt", pmnc_name);
509 } else {
510 snprintf(buf, sizeof buf, "%s_cnt%d", pmnc_name, i-1);
511 }
512 dir = gatorfs_mkdir(sb, root, buf);
513 if (!dir) {
514 return -1;
515 }
516 gatorfs_create_ulong(sb, dir, "enabled", &pmnc_enabled[i]);
517 gatorfs_create_ro_ulong(sb, dir, "key", &pmnc_key[i]);
518 if (i > 0) {
519 gatorfs_create_ulong(sb, dir, "event", &pmnc_event[i]);
520 }
521 }
523 return 0;
524 }
526 static int gator_events_scorpion_online(int** buffer)
527 {
528 unsigned int cnt, len = 0, cpu = smp_processor_id();
530 if (scorpion_pmnc_read() & PMNC_E) {
531 scorpion_pmnc_write(scorpion_pmnc_read() & ~PMNC_E);
532 }
534 /* Initialize & Reset PMNC: C bit and P bit */
535 scorpion_pmnc_write(PMNC_P | PMNC_C);
537 for (cnt = CCNT; cnt < CNTMAX; cnt++) {
538 unsigned long event;
540 if (!pmnc_enabled[cnt])
541 continue;
543 // disable counter
544 scorpion_pmnc_disable_counter(cnt);
546 event = pmnc_event[cnt] & 255;
548 // Set event (if destined for PMNx counters), We don't need to set the event if it's a cycle count
549 if (cnt != CCNT)
550 scorpion_pmnc_write_evtsel(cnt, event);
552 // reset counter
553 scorpion_pmnc_reset_counter(cnt);
555 // Enable counter, do not enable interrupt for this counter
556 scorpion_pmnc_enable_counter(cnt);
557 }
559 // enable
560 scorpion_pmnc_write(scorpion_pmnc_read() | PMNC_E);
562 // read the counters and toss the invalid data, return zero instead
563 for (cnt = 0; cnt < pmnc_counters; cnt++) {
564 if (pmnc_enabled[cnt]) {
565 int value;
566 if (cnt == CCNT) {
567 value = scorpion_ccnt_read();
568 } else if (scorpion_pmnc_select_counter(cnt) == cnt) {
569 value = scorpion_cntn_read();
570 } else {
571 value = 0;
572 }
573 scorpion_pmnc_reset_counter(cnt);
575 per_cpu(perfCnt, cpu)[len++] = pmnc_key[cnt];
576 per_cpu(perfCnt, cpu)[len++] = 0;
577 }
578 }
580 if (buffer)
581 *buffer = per_cpu(perfCnt, cpu);
583 return len;
584 }
586 static int gator_events_scorpion_offline(int** buffer)
587 {
588 scorpion_pmnc_write(scorpion_pmnc_read() & ~PMNC_E);
589 return 0;
590 }
592 static void gator_events_scorpion_stop(void)
593 {
594 unsigned int cnt;
596 for (cnt = CCNT; cnt < CNTMAX; cnt++) {
597 pmnc_enabled[cnt] = 0;
598 pmnc_event[cnt] = 0;
599 }
600 }
602 static int gator_events_scorpion_read(int **buffer)
603 {
604 int cnt, len = 0;
605 int cpu = smp_processor_id();
607 // a context switch may occur before the online hotplug event, thus need to check that the pmu is enabled
608 if (!(scorpion_pmnc_read() & PMNC_E)) {
609 return 0;
610 }
612 for (cnt = 0; cnt < pmnc_counters; cnt++) {
613 if (pmnc_enabled[cnt]) {
614 int value;
615 if (cnt == CCNT) {
616 value = scorpion_ccnt_read();
617 } else if (scorpion_pmnc_select_counter(cnt) == cnt) {
618 value = scorpion_cntn_read();
619 } else {
620 value = 0;
621 }
622 scorpion_pmnc_reset_counter(cnt);
624 per_cpu(perfCnt, cpu)[len++] = pmnc_key[cnt];
625 per_cpu(perfCnt, cpu)[len++] = value;
626 }
627 }
629 if (buffer)
630 *buffer = per_cpu(perfCnt, cpu);
632 return len;
633 }
635 static struct gator_interface gator_events_scorpion_interface = {
636 .create_files = gator_events_scorpion_create_files,
637 .stop = gator_events_scorpion_stop,
638 .online = gator_events_scorpion_online,
639 .offline = gator_events_scorpion_offline,
640 .read = gator_events_scorpion_read,
641 };
643 int gator_events_scorpion_init(void)
644 {
645 unsigned int cnt;
647 switch (gator_cpuid()) {
648 case SCORPION:
649 pmnc_name = "Scorpion";
650 pmnc_counters = 4;
651 break;
652 case SCORPIONMP:
653 pmnc_name = "ScorpionMP";
654 pmnc_counters = 4;
655 break;
656 default:
657 return -1;
658 }
660 pmnc_counters++; // CNT[n] + CCNT
662 for (cnt = CCNT; cnt < CNTMAX; cnt++) {
663 pmnc_enabled[cnt] = 0;
664 pmnc_event[cnt] = 0;
665 pmnc_key[cnt] = gator_events_get_key();
666 }
668 return gator_events_install(&gator_events_scorpion_interface);
669 }
671 gator_events_init(gator_events_scorpion_init);
673 #else
674 int gator_events_scorpion_init(void)
675 {
676 return -1;
677 }
678 #endif