gator: Version 5.15
authorJon Medhurst <tixy@linaro.org>
Tue, 11 Jun 2013 08:49:00 +0000 (09:49 +0100)
committerJon Medhurst <tixy@linaro.org>
Tue, 11 Jun 2013 08:49:00 +0000 (09:49 +0100)
Signed-off-by: Jon Medhurst <tixy@linaro.org>
50 files changed:
README_Streamline.txt [changed mode: 0644->0755]
daemon/Android.mk
daemon/Buffer.cpp
daemon/CapturedXML.cpp
daemon/Child.cpp
daemon/ConfigurationXML.cpp
daemon/Counter.h
daemon/EventsXML.cpp [new file with mode: 0644]
daemon/EventsXML.h [new file with mode: 0644]
daemon/Fifo.cpp
daemon/Fifo.h
daemon/Hwmon.cpp
daemon/KMod.cpp
daemon/LocalCapture.cpp
daemon/OlySocket.cpp
daemon/OlyUtility.cpp
daemon/OlyUtility.h
daemon/SessionData.h
daemon/StreamlineSetup.cpp
daemon/StreamlineSetup.h
daemon/common.mk
daemon/configuration.xml
daemon/escape.c
daemon/events-ARM11.xml
daemon/events-ARM11MPCore.xml
daemon/events-CCI-400.xml
daemon/events-Cortex-A15.xml
daemon/events-Cortex-A5.xml
daemon/events-Cortex-A53.xml
daemon/events-Cortex-A57.xml
daemon/events-Cortex-A7.xml
daemon/events-Cortex-A8.xml
daemon/events-Cortex-A9.xml
daemon/events-Krait-architected.xml
daemon/events-Linux.xml
daemon/events-Mali-T6xx.xml
daemon/events-Mali-T6xx_hw.xml
daemon/events-Scorpion.xml
daemon/events-ScorpionMP.xml
driver/gator_backtrace.c
driver/gator_events_l2c-310.c
driver/gator_events_mali_400.c
driver/gator_events_mali_t6xx_hw.c
driver/gator_events_perf_pmu.c
driver/gator_iks.c
driver/gator_main.c
driver/gator_marshaling.c
driver/gator_pack.c
driver/gator_trace_gpu.c
driver/gator_trace_sched.c

old mode 100644 (file)
new mode 100755 (executable)
index 5472c07..6a55f60
@@ -30,7 +30,6 @@ menuconfig options (depending on the kernel version, the location of these confi
   - CPU Frequency scaling\r
     - [*] CPU Frequency scaling (enables CONFIG_CPU_FREQ)\r
 - Kernel hacking\r
-  - [*] Mutex debugging: basic checks (optional, enables CONFIG_DEBUG_MUTEXES)\r
   - [*] Compile the kernel with debug info (optional, enables CONFIG_DEBUG_INFO)\r
   - [*] Tracers\r
     - [*] Trace process context switches and events (#)\r
@@ -43,7 +42,6 @@ CONFIG_PROFILING
 CONFIG_HIGH_RES_TIMERS\r
 CONFIG_LOCAL_TIMERS (for SMP systems)\r
 CONFIG_PERF_EVENTS and CONFIG_HW_PERF_EVENTS (kernel versions 3.0 and greater)\r
-CONFIG_DEBUG_MUTEXES (optional, provides 'mutex' as a reason code when a thread stops running)\r
 CONFIG_DEBUG_INFO (optional, used for analyzing the kernel)\r
 CONFIG_CPU_FREQ (optional, provides frequency setting of the CPU)\r
 \r
@@ -101,7 +99,7 @@ Further, the l2c-310 counter can be disabled by providing an offset of zero, ex:
 *** Compiling an application or shared library ***\r
 \r
 Recommended compiler settings:\r
-       "-g": Debug symbols needed for best analysis results.\r
+       "-g": Debug information, such as line numbers, needed for best analysis results.\r
        "-fno-inline": Speed improvement when processing the image files and most accurate analysis results.\r
        "-fno-omit-frame-pointer": ARM EABI frame pointers (Code Sourcery cross compiler) allow recording of the call stack with each sample taken when in ARM state (i.e. not -mthumb).\r
        "-marm": This option is required if your compiler is configured with --with-mode=thumb, otherwise call stack unwinding will not work.\r
index 86483f351341379fa96be67923665148d56feb9f..4798a0a918135f2f58b992f9efb4a727b0af6959 100644 (file)
@@ -12,6 +12,7 @@ LOCAL_SRC_FILES := \
        Collector.cpp \\r
        ConfigurationXML.cpp \\r
        Driver.cpp \\r
+       EventsXML.cpp \\r
        Fifo.cpp \\r
        Hwmon.cpp \\r
        KMod.cpp \\r
index ee391bc4f7db511423913698429feaa578646833..56cf42cb7749a9a627abd08429d28cd1b1f9e16c 100644 (file)
@@ -140,173 +140,46 @@ void Buffer::check (const uint64_t time) {
        }
 }
 
-void Buffer::packInt (const int32_t x) {
-       const int write0 = (writePos + 0) & mask;
-       const int write1 = (writePos + 1) & mask;
-
-       if ((x & 0xffffff80) == 0) {
-               buf[write0] = x & 0x7f;
-               writePos = write1;
-       } else if ((x & 0xffffc000) == 0) {
-               const int write2 = (writePos + 2) & mask;
-               buf[write0] = x | 0x80;
-               buf[write1] = (x >> 7) & 0x7f;
-               writePos = write2;
-       } else if ((x & 0xffe00000) == 0) {
-               const int write2 = (writePos + 2) & mask;
-               const int write3 = (writePos + 3) & mask;
-               buf[write0] = x | 0x80;
-               buf[write1] = (x >> 7) | 0x80;
-               buf[write2] = (x >> 14) & 0x7f;
-               writePos = write3;
-       } else if ((x & 0xf0000000) == 0) {
-               const int write2 = (writePos + 2) & mask;
-               const int write3 = (writePos + 3) & mask;
-               const int write4 = (writePos + 4) & mask;
-               buf[write0] = x | 0x80;
-               buf[write1] = (x >> 7) | 0x80;
-               buf[write2] = (x >> 14) | 0x80;
-               buf[write3] = (x >> 21) & 0x7f;
-               writePos = write4;
-       } else {
-               const int write2 = (writePos + 2) & mask;
-               const int write3 = (writePos + 3) & mask;
-               const int write4 = (writePos + 4) & mask;
-               const int write5 = (writePos + 5) & mask;
-               buf[write0] = x | 0x80;
-               buf[write1] = (x >> 7) | 0x80;
-               buf[write2] = (x >> 14) | 0x80;
-               buf[write3] = (x >> 21) | 0x80;
-               buf[write4] = (x >> 28) & 0x0f;
-               writePos = write5;
+void Buffer::packInt (int32_t x) {
+       int packedBytes = 0;
+       int more = true;
+       while (more) {
+               // low order 7 bits of x
+               char b = x & 0x7f;
+               x >>= 7;
+
+               if ((x == 0 && (b & 0x40) == 0) || (x == -1 && (b & 0x40) != 0)) {
+                       more = false;
+               } else {
+                       b |= 0x80;
+               }
+
+               buf[(writePos + packedBytes) & mask] = b;
+               packedBytes++;
        }
+
+       writePos = (writePos + packedBytes) & mask;
 }
 
-void Buffer::packInt64 (const int64_t x) {
-       const int write0 = (writePos + 0) & mask;
-       const int write1 = (writePos + 1) & mask;
-
-       if ((x & 0xffffffffffffff80LL) == 0) {
-               buf[write0] = x & 0x7f;
-               writePos = write1;
-       } else if ((x & 0xffffffffffffc000LL) == 0) {
-               const int write2 = (writePos + 2) & mask;
-               buf[write0] = x | 0x80;
-               buf[write1] = (x >> 7) & 0x7f;
-               writePos = write2;
-       } else if ((x & 0xffffffffffe00000LL) == 0) {
-               const int write2 = (writePos + 2) & mask;
-               const int write3 = (writePos + 3) & mask;
-               buf[write0] = x | 0x80;
-               buf[write1] = (x >> 7) | 0x80;
-               buf[write2] = (x >> 14) & 0x7f;
-               writePos = write3;
-       } else if ((x & 0xfffffffff0000000LL) == 0) {
-               const int write2 = (writePos + 2) & mask;
-               const int write3 = (writePos + 3) & mask;
-               const int write4 = (writePos + 4) & mask;
-               buf[write0] = x | 0x80;
-               buf[write1] = (x >> 7) | 0x80;
-               buf[write2] = (x >> 14) | 0x80;
-               buf[write3] = (x >> 21) & 0x7f;
-               writePos = write4;
-       } else if ((x & 0xfffffff800000000LL) == 0) {
-               const int write2 = (writePos + 2) & mask;
-               const int write3 = (writePos + 3) & mask;
-               const int write4 = (writePos + 4) & mask;
-               const int write5 = (writePos + 5) & mask;
-               buf[write0] = x | 0x80;
-               buf[write1] = (x >> 7) | 0x80;
-               buf[write2] = (x >> 14) | 0x80;
-               buf[write3] = (x >> 21) | 0x80;
-               buf[write4] = (x >> 28) & 0x7f;
-               writePos = write5;
-       } else if ((x & 0xfffffc0000000000LL) == 0) {
-               const int write2 = (writePos + 2) & mask;
-               const int write3 = (writePos + 3) & mask;
-               const int write4 = (writePos + 4) & mask;
-               const int write5 = (writePos + 5) & mask;
-               const int write6 = (writePos + 6) & mask;
-               buf[write0] = x | 0x80;
-               buf[write1] = (x >> 7) | 0x80;
-               buf[write2] = (x >> 14) | 0x80;
-               buf[write3] = (x >> 21) | 0x80;
-               buf[write4] = (x >> 28) | 0x80;
-               buf[write5] = (x >> 35) & 0x7f;
-               writePos = write6;
-       } else if ((x & 0xfffe000000000000LL) == 0) {
-               const int write2 = (writePos + 2) & mask;
-               const int write3 = (writePos + 3) & mask;
-               const int write4 = (writePos + 4) & mask;
-               const int write5 = (writePos + 5) & mask;
-               const int write6 = (writePos + 6) & mask;
-               const int write7 = (writePos + 7) & mask;
-               buf[write0] = x | 0x80;
-               buf[write1] = (x >> 7) | 0x80;
-               buf[write2] = (x >> 14) | 0x80;
-               buf[write3] = (x >> 21) | 0x80;
-               buf[write4] = (x >> 28) | 0x80;
-               buf[write5] = (x >> 35) | 0x80;
-               buf[write6] = (x >> 42) & 0x7f;
-               writePos = write7;
-       } else if ((x & 0xff00000000000000LL) == 0) {
-               const int write2 = (writePos + 2) & mask;
-               const int write3 = (writePos + 3) & mask;
-               const int write4 = (writePos + 4) & mask;
-               const int write5 = (writePos + 5) & mask;
-               const int write6 = (writePos + 6) & mask;
-               const int write7 = (writePos + 7) & mask;
-               const int write8 = (writePos + 8) & mask;
-               buf[write0] = x | 0x80;
-               buf[write1] = (x >> 7) | 0x80;
-               buf[write2] = (x >> 14) | 0x80;
-               buf[write3] = (x >> 21) | 0x80;
-               buf[write4] = (x >> 28) | 0x80;
-               buf[write5] = (x >> 35) | 0x80;
-               buf[write6] = (x >> 42) | 0x80;
-               buf[write7] = (x >> 49) & 0x7f;
-               writePos = write8;
-       } else if ((x & 0x8000000000000000LL) == 0) {
-               const int write2 = (writePos + 2) & mask;
-               const int write3 = (writePos + 3) & mask;
-               const int write4 = (writePos + 4) & mask;
-               const int write5 = (writePos + 5) & mask;
-               const int write6 = (writePos + 6) & mask;
-               const int write7 = (writePos + 7) & mask;
-               const int write8 = (writePos + 8) & mask;
-               const int write9 = (writePos + 9) & mask;
-               buf[write0] = x | 0x80;
-               buf[write1] = (x >> 7) | 0x80;
-               buf[write2] = (x >> 14) | 0x80;
-               buf[write3] = (x >> 21) | 0x80;
-               buf[write4] = (x >> 28) | 0x80;
-               buf[write5] = (x >> 35) | 0x80;
-               buf[write6] = (x >> 42) | 0x80;
-               buf[write7] = (x >> 49) | 0x80;
-               buf[write8] = (x >> 56) & 0x7f;
-               writePos = write9;
-       } else {
-               const int write2 = (writePos + 2) & mask;
-               const int write3 = (writePos + 3) & mask;
-               const int write4 = (writePos + 4) & mask;
-               const int write5 = (writePos + 5) & mask;
-               const int write6 = (writePos + 6) & mask;
-               const int write7 = (writePos + 7) & mask;
-               const int write8 = (writePos + 8) & mask;
-               const int write9 = (writePos + 9) & mask;
-               const int write10 = (writePos + 10) & mask;
-               buf[write0] = x | 0x80;
-               buf[write1] = (x >> 7) | 0x80;
-               buf[write2] = (x >> 14) | 0x80;
-               buf[write3] = (x >> 21) | 0x80;
-               buf[write4] = (x >> 28) | 0x80;
-               buf[write5] = (x >> 35) | 0x80;
-               buf[write6] = (x >> 42) | 0x80;
-               buf[write7] = (x >> 49) | 0x80;
-               buf[write8] = (x >> 56) | 0x80;
-               buf[write9] = (x >> 63) & 0x7f;
-               writePos = write10;
+void Buffer::packInt64 (int64_t x) {
+       int packedBytes = 0;
+       int more = true;
+       while (more) {
+               // low order 7 bits of x
+               char b = x & 0x7f;
+               x >>= 7;
+
+               if ((x == 0 && (b & 0x40) == 0) || (x == -1 && (b & 0x40) != 0)) {
+                       more = false;
+               } else {
+                       b |= 0x80;
+               }
+
+               buf[(writePos + packedBytes) & mask] = b;
+               packedBytes++;
        }
+
+       writePos = (writePos + packedBytes) & mask;
 }
 
 void Buffer::frame () {
index 8b037cbe887abb15a2c967f45cb711a882fe096a..af726df71d598c9ba0237e5702faffd5f6deb688 100644 (file)
@@ -51,30 +51,12 @@ mxml_node_t* CapturedXML::getTree(bool includeTime) {
                                counters = mxmlNewElement(captured, "counters");
                        }
                        mxml_node_t *const node = mxmlNewElement(counters, "counter");
-                       mxmlElementSetAttr(node, "title", counter.getTitle());
-                       mxmlElementSetAttr(node, "name", counter.getName());
-                       mxmlElementSetAttrf(node, "key", "0x%08x", counter.getKey());
+                       mxmlElementSetAttrf(node, "key", "0x%x", counter.getKey());
                        mxmlElementSetAttr(node, "type", counter.getType());
-                       mxmlElementSetAttrf(node, "event", "0x%08x", counter.getEvent());
-                       if (counter.isPerCPU()) {
-                               mxmlElementSetAttr(node, "per_cpu", "yes");
-                       }
+                       mxmlElementSetAttrf(node, "event", "0x%x", counter.getEvent());
                        if (counter.getCount() > 0) {
                                mxmlElementSetAttrf(node, "count", "%d", counter.getCount());
                        }
-                       if (strlen(counter.getDisplay()) > 0) {
-                               mxmlElementSetAttr(node, "display", counter.getDisplay());
-                       }
-                       if (strlen(counter.getUnits()) > 0) {
-                               mxmlElementSetAttr(node, "units", counter.getUnits());
-                       }
-                       if (counter.getModifier() != 1) {
-                               mxmlElementSetAttrf(node, "modifier", "%d", counter.getModifier());
-                       }
-                       if (counter.isAverageSelection()) {
-                               mxmlElementSetAttr(node, "average_selection", "yes");
-                       }
-                       mxmlElementSetAttr(node, "description", counter.getDescription());
                }
        }
 
index c7848477f79a07dfb283af7468b808c309e7a9fe..286c7e7ba3987540a13db1855a3d9aa5a09ce268 100644 (file)
@@ -100,14 +100,15 @@ static void* durationThread(void* pVoid) {
 }
 
 static void* stopThread(void* pVoid) {
-       int length;
-       char type;
        OlySocket* socket = child->socket;
 
        prctl(PR_SET_NAME, (unsigned long)&"gatord-stopper", 0, 0, 0);
        while (gSessionData->mSessionIsActive) {
                // This thread will stall until the APC_STOP or PING command is received over the socket or the socket is disconnected
-               const int result = socket->receiveNBytes(&type, sizeof(type));
+               unsigned char header[5];
+               const int result = socket->receiveNBytes((char*)&header, sizeof(header));
+               const char type = header[0];
+               const int length = (header[1] << 0) | (header[2] << 8) | (header[3] << 16) | (header[4] << 24);
                if (result == -1) {
                        child->endSession();
                } else if (result > 0) {
@@ -115,10 +116,6 @@ static void* stopThread(void* pVoid) {
                                logg->logMessage("INVESTIGATE: Received unknown command type %d", type);
                        } else {
                                // verify a length of zero
-                               if (socket->receiveNBytes((char*)&length, sizeof(length)) < 0) {
-                                       break;
-                               }
-
                                if (length == 0) {
                                        if (type == COMMAND_APC_STOP) {
                                                logg->logMessage("Stop command received.");
index 9d51f26eb70931e2170169a572921a1a1bf23bb0..fb00202f65694b3913c0e81b1bf2f3dc47bc2573 100644 (file)
 #include "OlyUtility.h"
 #include "SessionData.h"
 
-static const char* ATTR_COUNTER           = "counter";
-static const char* ATTR_REVISION          = "revision";
-static const char* ATTR_TITLE             = "title";
-static const char* ATTR_NAME              = "name";
-static const char* ATTR_EVENT             = "event";
-static const char* ATTR_COUNT             = "count";
-static const char* ATTR_PER_CPU           = "per_cpu";
-static const char* ATTR_DESCRIPTION       = "description";
-static const char* ATTR_EBS               = "supports_event_based_sampling";
-static const char* ATTR_DISPLAY           = "display";
-static const char* ATTR_UNITS             = "units";
-static const char* ATTR_MODIFIER          = "modifier";
-static const char* ATTR_AVERAGE_SELECTION = "average_selection";
+static const char* ATTR_COUNTER            = "counter";
+static const char* ATTR_REVISION           = "revision";
+static const char* ATTR_EVENT              = "event";
+static const char* ATTR_COUNT              = "count";
 
 ConfigurationXML::ConfigurationXML() {
        const char * configuration_xml;
@@ -87,7 +78,7 @@ int ConfigurationXML::parse(const char* configurationXML) {
        int ret;
 
        // clear counter overflow
-       gSessionData->mCounterOverflow = false;
+       gSessionData->mCounterOverflow = 0;
        mIndex = 0;
 
        // disable all counters prior to parsing the configuration xml
@@ -123,7 +114,7 @@ void ConfigurationXML::validate(void) {
                const Counter & counter = gSessionData->mCounters[i];
                if (counter.isEnabled()) {
                        if (strcmp(counter.getType(), "") == 0) {
-                               logg->logError(__FILE__, __LINE__, "Invalid required attribute in configuration.xml:\n  counter=\"%s\"\n  title=\"%s\"\n  name=\"%s\"\n  event=%d\n", counter.getType(), counter.getTitle(), counter.getName(), counter.getEvent());
+                               logg->logError(__FILE__, __LINE__, "Invalid required attribute in configuration.xml:\n  counter=\"%s\"\n  event=%d\n", counter.getType(), counter.getEvent());
                                handleException();
                        }
 
@@ -142,7 +133,7 @@ void ConfigurationXML::validate(void) {
        }
 }
 
-#define CONFIGURATION_REVISION 2
+#define CONFIGURATION_REVISION 3
 int ConfigurationXML::configurationsTag(mxml_node_t *node) {
        const char* revision_string;
        
@@ -156,13 +147,17 @@ int ConfigurationXML::configurationsTag(mxml_node_t *node) {
                return 1; // revision issue
        }
 
+       // A revision >= CONFIGURATION_REVISION is okay
+       // Greater than can occur when Streamline is newer than gator
+
        return 0;
 }
 
 void ConfigurationXML::configurationTag(mxml_node_t *node) {
        // handle all other performance counters
        if (mIndex >= MAX_PERFORMANCE_COUNTERS) {
-               gSessionData->mCounterOverflow = true;
+               mIndex++;
+               gSessionData->mCounterOverflow = mIndex;
                return;
        }
 
@@ -170,24 +165,15 @@ void ConfigurationXML::configurationTag(mxml_node_t *node) {
        Counter & counter = gSessionData->mCounters[mIndex];
        counter.clear();
        if (mxmlElementGetAttr(node, ATTR_COUNTER)) counter.setType(mxmlElementGetAttr(node, ATTR_COUNTER));
-       if (mxmlElementGetAttr(node, ATTR_TITLE)) counter.setTitle(mxmlElementGetAttr(node, ATTR_TITLE));
-       if (mxmlElementGetAttr(node, ATTR_NAME)) counter.setName(mxmlElementGetAttr(node, ATTR_NAME));
-       if (mxmlElementGetAttr(node, ATTR_DESCRIPTION)) counter.setDescription(mxmlElementGetAttr(node, ATTR_DESCRIPTION));
        if (mxmlElementGetAttr(node, ATTR_EVENT)) counter.setEvent(strtol(mxmlElementGetAttr(node, ATTR_EVENT), NULL, 16));
        if (mxmlElementGetAttr(node, ATTR_COUNT)) counter.setCount(strtol(mxmlElementGetAttr(node, ATTR_COUNT), NULL, 10));
-       if (mxmlElementGetAttr(node, ATTR_PER_CPU)) counter.setPerCPU(util->stringToBool(mxmlElementGetAttr(node, ATTR_PER_CPU), false));
-       if (mxmlElementGetAttr(node, ATTR_EBS)) counter.setEBSCapable(util->stringToBool(mxmlElementGetAttr(node, ATTR_EBS), false));
-       if (mxmlElementGetAttr(node, ATTR_DISPLAY)) counter.setDisplay(mxmlElementGetAttr(node, ATTR_DISPLAY));
-       if (mxmlElementGetAttr(node, ATTR_UNITS)) counter.setUnits(mxmlElementGetAttr(node, ATTR_UNITS));
-       if (mxmlElementGetAttr(node, ATTR_MODIFIER)) counter.setModifier(strtol(mxmlElementGetAttr(node, ATTR_MODIFIER), NULL, 10));
-       if (mxmlElementGetAttr(node, ATTR_AVERAGE_SELECTION)) counter.setAverageSelection(util->stringToBool(mxmlElementGetAttr(node, ATTR_AVERAGE_SELECTION), false));
        counter.setEnabled(true);
 
        // Associate a driver with each counter
        for (Driver *driver = Driver::getHead(); driver != NULL; driver = driver->getNext()) {
                if (driver->claimCounter(counter)) {
                        if (counter.getDriver() != NULL) {
-                               logg->logError(__FILE__, __LINE__, "More than one driver has claimed %s: %s", counter.getTitle(), counter.getName());
+                               logg->logError(__FILE__, __LINE__, "More than one driver has claimed %s:%i", counter.getType(), counter.getEvent());
                                handleException();
                        }
                        counter.setDriver(driver);
@@ -196,12 +182,14 @@ void ConfigurationXML::configurationTag(mxml_node_t *node) {
 
        // If no driver is associated with the counter, disable it
        if (counter.getDriver() == NULL) {
-               logg->logMessage("No driver has claimed %s (%s: %s)", counter.getType(), counter.getTitle(), counter.getName());
+               logg->logMessage("No driver has claimed %s:%i", counter.getType(), counter.getEvent());
                counter.setEnabled(false);
        }
 
-       // update counter index
-       mIndex++;
+       if (counter.isEnabled()) {
+               // update counter index
+               mIndex++;
+       }
 }
 
 void ConfigurationXML::getDefaultConfigurationXml(const char * & xml, unsigned int & len) {
index 041020b4e285931f581c5355bcfaa40f92a8fc35..231a85d6e3b55d5c57597f37ce663206d8b34dc8 100644 (file)
@@ -24,52 +24,25 @@ public:
 
        void clear () {
                mType[0] = '\0';
-               mTitle[0] = '\0';
-               mName[0] = '\0';
-               mDescription[0] = '\0';
-               mDisplay[0] = '\0';
-               mUnits[0] = '\0';
-               mModifier = 1;
                mEnabled = false;
                mEvent = 0;
                mCount = 0;
                mKey = 0;
-               mPerCPU = false;
-               mEBSCapable = false;
-               mAverageSelection = false;
                mDriver = NULL;
        }
 
        void setType(const char *const type) { strncpy(mType, type, sizeof(mType)); mType[sizeof(mType) - 1] = '\0'; }
-       void setTitle(const char *const title) { strncpy(mTitle, title, sizeof(mTitle)); mTitle[sizeof(mTitle) - 1] = '\0'; }
-       void setName(const char *const name) { strncpy(mName, name, sizeof(mName)); mName[sizeof(mName) - 1] = '\0'; }
-       void setDescription(const char *const description) { strncpy(mDescription, description, sizeof(mDescription)); mDescription[sizeof(mDescription) - 1] = '\0'; }
-       void setDisplay(const char *const display) { strncpy(mDisplay, display, sizeof(mDisplay)); mDisplay[sizeof(mDisplay) - 1] = '\0'; }
-       void setUnits(const char *const units) { strncpy(mUnits, units, sizeof(mUnits)); mUnits[sizeof(mUnits) - 1] = '\0'; }
-       void setModifier(const int modifier) { mModifier = modifier; }
        void setEnabled(const bool enabled) { mEnabled = enabled; }
        void setEvent(const int event) { mEvent = event; }
        void setCount(const int count) { mCount = count; }
        void setKey(const int key) { mKey = key; }
-       void setPerCPU(const bool perCPU) { mPerCPU = perCPU; }
-       void setEBSCapable(const bool ebsCapable) { mEBSCapable = ebsCapable; }
-       void setAverageSelection(const bool averageSelection) { mAverageSelection = averageSelection; }
        void setDriver(Driver *const driver) { mDriver = driver; }
 
        const char *getType() const { return mType;}
-       const char *getTitle() const { return mTitle; }
-       const char *getName() const { return mName; }
-       const char *getDescription() const { return mDescription; }
-       const char *getDisplay() const { return mDisplay; }
-       const char *getUnits() const { return mUnits; }
-       int getModifier() const { return mModifier; }
        bool isEnabled() const { return mEnabled; }
        int getEvent() const { return mEvent; }
        int getCount() const { return mCount; }
        int getKey() const { return mKey; }
-       bool isPerCPU() const { return mPerCPU; }
-       bool isEBSCapable() const { return mEBSCapable; }
-       bool isAverageSelection() const { return mAverageSelection; }
        Driver *getDriver() const { return mDriver; }
 
 private:
@@ -78,19 +51,10 @@ private:
        Counter & operator=(const Counter &);
 
        char mType[MAX_STRING_LEN];
-       char mTitle[MAX_STRING_LEN];
-       char mName[MAX_STRING_LEN];
-       char mDescription[MAX_DESCRIPTION_LEN];
-       char mDisplay[MAX_STRING_LEN];
-       char mUnits[MAX_STRING_LEN];
-       int mModifier;
        bool mEnabled;
        int mEvent;
        int mCount;
        int mKey;
-       bool mPerCPU;
-       bool mEBSCapable;
-       bool mAverageSelection;
        Driver *mDriver;
 };
 
diff --git a/daemon/EventsXML.cpp b/daemon/EventsXML.cpp
new file mode 100644 (file)
index 0000000..2a80482
--- /dev/null
@@ -0,0 +1,70 @@
+/**
+ * Copyright (C) ARM Limited 2013. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "EventsXML.h"
+
+#include "CapturedXML.h"
+#include "Logging.h"
+#include "OlyUtility.h"
+#include "SessionData.h"
+
+char* EventsXML::getXML() {
+#include "events_xml.h" // defines and initializes char events_xml[] and int events_xml_len
+       char path[PATH_MAX];
+       mxml_node_t *xml;
+       FILE *fl;
+
+       // Avoid unused variable warning
+       (void)events_xml_len;
+
+       // Load the provided or default events xml
+       if (gSessionData->mEventsXMLPath) {
+               strncpy(path, gSessionData->mEventsXMLPath, PATH_MAX);
+       } else {
+               util->getApplicationFullPath(path, PATH_MAX);
+               strncat(path, "events.xml", PATH_MAX - strlen(path) - 1);
+       }
+       fl = fopen(path, "r");
+       if (fl) {
+               xml = mxmlLoadFile(NULL, fl, MXML_NO_CALLBACK);
+               fclose(fl);
+       } else {
+               logg->logMessage("Unable to locate events.xml, using default");
+               xml = mxmlLoadString(NULL, (char *)events_xml, MXML_NO_CALLBACK);
+       }
+
+       // Add dynamic events from the drivers
+       mxml_node_t *events = mxmlFindElement(xml, xml, "events", NULL, NULL, MXML_DESCEND);
+       if (!events) {
+               logg->logMessage("Unable to find <events> node in the events.xml");
+               handleException();
+       }
+       for (Driver *driver = Driver::getHead(); driver != NULL; driver = driver->getNext()) {
+               driver->writeEvents(events);
+       }
+
+       char* string = mxmlSaveAllocString(xml, mxmlWhitespaceCB);
+       mxmlDelete(xml);
+
+       return string;
+}
+
+void EventsXML::write(const char* path) {
+       char file[PATH_MAX];
+
+       // Set full path
+       snprintf(file, PATH_MAX, "%s/events.xml", path);
+       
+       char* buf = getXML();
+       if (util->writeToDisk(file, buf) < 0) {
+               logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify the path.", file);
+               handleException();
+       }
+
+       free(buf);
+}
diff --git a/daemon/EventsXML.h b/daemon/EventsXML.h
new file mode 100644 (file)
index 0000000..8e693ef
--- /dev/null
@@ -0,0 +1,18 @@
+/**
+ * Copyright (C) ARM Limited 2013. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef EVENTS_XML
+#define EVENTS_XML
+
+class EventsXML {
+public:
+       char* getXML();
+       void write(const char* path);
+};
+
+#endif // EVENTS_XML
index f0b0178705061664dc1d319691f8eab8b023f7a5..250a4d023bf265f72e170fdc24a5678421294cb7 100644 (file)
  * published by the Free Software Foundation.
  */
 
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
 #include "Fifo.h"
+
+#include <stdlib.h>
+#ifdef WIN32
+#define valloc malloc
+#endif
+
 #include "Logging.h"
 
 // bufferSize is the amount of data to be filled
 // singleBufferSize is the maximum size that may be filled during a single write
 // (bufferSize + singleBufferSize) will be allocated
 Fifo::Fifo(int singleBufferSize, int bufferSize, sem_t* readerSem) {
-       mWrite = mRead = mReadCommit = mRaggedEnd = 0;
-       mWrapThreshold = bufferSize;
-       mSingleBufferSize = singleBufferSize;
-       mReaderSem = readerSem;
-       mBuffer = (char*)valloc(bufferSize + singleBufferSize);
-       mEnd = false;
-
-       if (mBuffer == NULL) {
-               logg->logError(__FILE__, __LINE__, "failed to allocate %d bytes", bufferSize + singleBufferSize);
-               handleException();
-       }
-
-       if (sem_init(&mWaitForSpaceSem, 0, 0)) {
-               logg->logError(__FILE__, __LINE__, "sem_init() failed");
-               handleException();
-       }
+  mWrite = mRead = mReadCommit = mRaggedEnd = 0;
+  mWrapThreshold = bufferSize;
+  mSingleBufferSize = singleBufferSize;
+  mReaderSem = readerSem;
+  mBuffer = (char*)valloc(bufferSize + singleBufferSize);
+  mEnd = false;
+
+  if (mBuffer == NULL) {
+    logg->logError(__FILE__, __LINE__, "failed to allocate %d bytes", bufferSize + singleBufferSize);
+    handleException();
+  }
+
+  if (sem_init(&mWaitForSpaceSem, 0, 0)) {
+    logg->logError(__FILE__, __LINE__, "sem_init() failed");
+    handleException();
+  }
 }
 
 Fifo::~Fifo() {
-       free(mBuffer);
-       sem_destroy(&mWaitForSpaceSem);
+  free(mBuffer);
+  sem_destroy(&mWaitForSpaceSem);
 }
 
 int Fifo::numBytesFilled() const {
-       return mWrite - mRead + mRaggedEnd;
+  return mWrite - mRead + mRaggedEnd;
 }
 
 char* Fifo::start() const {
-       return mBuffer;
+  return mBuffer;
 }
 
 bool Fifo::isEmpty() const {
-       return mRead == mWrite && mRaggedEnd == 0;
+  return mRead == mWrite && mRaggedEnd == 0;
 }
 
 bool Fifo::isFull() const {
-       return willFill(0);
+  return willFill(0);
 }
 
 // Determines if the buffer will fill assuming 'additional' bytes will be added to the buffer
 // 'full' means there is less than singleBufferSize bytes available contiguously; it does not mean there are zero bytes available
 bool Fifo::willFill(int additional) const {
-       if (mWrite > mRead) {
-               if (numBytesFilled() + additional < mWrapThreshold) {
-                       return false;
-               }
-       } else {
-               if (numBytesFilled() + additional < mWrapThreshold - mSingleBufferSize) {
-                       return false;
-               }
-       }
-       return true;
+  if (mWrite > mRead) {
+    if (numBytesFilled() + additional < mWrapThreshold) {
+      return false;
+    }
+  } else {
+    if (numBytesFilled() + additional < mWrapThreshold - mSingleBufferSize) {
+      return false;
+    }
+  }
+  return true;
 }
 
 // This function will stall until contiguous singleBufferSize bytes are available
 char* Fifo::write(int length) {
-       if (length <= 0) {
-               length = 0;
-               mEnd = true;
-       }
+  if (length <= 0) {
+    length = 0;
+    mEnd = true;
+  }
 
-       // update the write pointer
-       mWrite += length;
+  // update the write pointer
+  mWrite += length;
 
-       // handle the wrap-around
-       if (mWrite >= mWrapThreshold) {
-               mRaggedEnd = mWrite;
-               mWrite = 0;
-       }
+  // handle the wrap-around
+  if (mWrite >= mWrapThreshold) {
+    mRaggedEnd = mWrite;
+    mWrite = 0;
+  }
 
-       // send a notification that data is ready
-       sem_post(mReaderSem);
+  // send a notification that data is ready
+  sem_post(mReaderSem);
 
-       // wait for space
-       while (isFull()) {
-               sem_wait(&mWaitForSpaceSem);
-       }
+  // wait for space
+  while (isFull()) {
+    sem_wait(&mWaitForSpaceSem);
+  }
 
-       return &mBuffer[mWrite];
+  return &mBuffer[mWrite];
 }
 
 void Fifo::release() {
-       // update the read pointer now that the data has been handled
-       mRead = mReadCommit;
+  // update the read pointer now that the data has been handled
+  mRead = mReadCommit;
 
-       // handle the wrap-around
-       if (mRead >= mWrapThreshold) {
-               mRaggedEnd = mRead = mReadCommit = 0;
-       }
+  // handle the wrap-around
+  if (mRead >= mWrapThreshold) {
+    mRaggedEnd = mRead = mReadCommit = 0;
+  }
 
-       // send a notification that data is free (space is available)
-       sem_post(&mWaitForSpaceSem);
+  // send a notification that data is free (space is available)
+  sem_post(&mWaitForSpaceSem);
 }
 
 // This function will return null if no data is available
 char* Fifo::read(int *const length) {
-       // wait for data
-       if (isEmpty() && !mEnd) {
-               return NULL;
-       }
-
-       // obtain the length
-       do {
-               mReadCommit = mRaggedEnd ? mRaggedEnd : mWrite;
-               *length = mReadCommit - mRead;
-       } while (*length < 0); // plugs race condition without using semaphores
-
-       return &mBuffer[mRead];
+  // wait for data
+  if (isEmpty() && !mEnd) {
+    return NULL;
+  }
+
+  // obtain the length
+  do {
+    mReadCommit = mRaggedEnd ? mRaggedEnd : mWrite;
+    *length = mReadCommit - mRead;
+  } while (*length < 0); // plugs race condition without using semaphores
+
+  return &mBuffer[mRead];
 }
index d46e1afa9e192364d44d6ae81f8fadd18b6007e8..ada42b9fb5848f37eabdf34b66e0710cbc3f77f7 100644 (file)
@@ -9,27 +9,36 @@
 #ifndef        __FIFO_H__
 #define        __FIFO_H__
 
+#ifdef WIN32
+#include <windows.h>
+#define sem_t HANDLE
+#define sem_init(sem, pshared, value) ((*(sem) = CreateSemaphore(NULL, value, INFINITE, NULL)) == NULL)
+#define sem_wait(sem) WaitForSingleObject(*(sem), INFINITE)
+#define sem_post(sem) ReleaseSemaphore(*(sem), 1, NULL)
+#define sem_destroy(sem) CloseHandle(*(sem))
+#else
 #include <semaphore.h>
+#endif
 
 class Fifo {
 public:
-       Fifo(int singleBufferSize, int totalBufferSize, sem_t* readerSem);
-       ~Fifo();
-       int numBytesFilled() const;
-       bool isEmpty() const;
-       bool isFull() const;
-       bool willFill(int additional) const;
-       char* start() const;
-       char* write(int length);
-       void release();
-       char* read(int *const length);
+  Fifo(int singleBufferSize, int totalBufferSize, sem_t* readerSem);
+  ~Fifo();
+  int numBytesFilled() const;
+  bool isEmpty() const;
+  bool isFull() const;
+  bool willFill(int additional) const;
+  char* start() const;
+  char* write(int length);
+  void release();
+  char* read(int *const length);
 
 private:
-       int             mSingleBufferSize, mWrite, mRead, mReadCommit, mRaggedEnd, mWrapThreshold;
-       sem_t   mWaitForSpaceSem;
-       sem_t* mReaderSem;
-       char*   mBuffer;
-       bool    mEnd;
+  int mSingleBufferSize, mWrite, mRead, mReadCommit, mRaggedEnd, mWrapThreshold;
+  sem_t        mWaitForSpaceSem;
+  sem_t* mReaderSem;
+  char*        mBuffer;
+  bool mEnd;
 };
 
 #endif         //__FIFO_H__
index 9603411ecd139b50f540c22ccf590f7b70fd45fb..94752158436ca89b0e9442b8aebba3c60436a65c 100644 (file)
@@ -26,20 +26,30 @@ public:
        const char *getName() const { return name; }
        const char *getLabel() const { return label; }
        const char *getTitle() const { return title; }
+       bool isDuplicate() const { return duplicate; }
        const char *getDisplay() const { return display; }
        const char *getUnit() const { return unit; }
        int getModifier() const { return modifier; }
 
-       void setEnabled(const bool enabled) { this->enabled = enabled; }
+       void setEnabled(const bool enabled) {
+               this->enabled = enabled;
+               // canRead will clear enabled if the counter is not readable
+               canRead();
+       }
 
        double read();
+       bool canRead();
 
 private:
        void init(const sensors_chip_name *chip, const sensors_feature *feature);
 
        HwmonCounter *const next;
        const int key;
-       bool enabled;
+       int polled : 1,
+               readable : 1,
+               enabled : 1,
+               monotonic: 1,
+               duplicate : 1;
 
        const sensors_chip_name *chip;
        const sensors_feature *feature;
@@ -50,13 +60,12 @@ private:
        const char *display;
        const char *unit;
        int modifier;
-       bool monotonic;
        double previous_value;
 
        sensors_subfeature_type input;
 };
 
-HwmonCounter::HwmonCounter(HwmonCounter *next, int key, const sensors_chip_name *chip, const sensors_feature *feature) : next(next), key(key), enabled(false), chip(chip), feature(feature) {
+HwmonCounter::HwmonCounter(HwmonCounter *next, int key, const sensors_chip_name *chip, const sensors_feature *feature) : next(next), key(key), polled(false), readable(false), enabled(false), duplicate(false), chip(chip), feature(feature) {
 
        int len = sensors_snprintf_chip_name(NULL, 0, chip) + 1;
        char *chip_name = new char[len];
@@ -131,6 +140,14 @@ HwmonCounter::HwmonCounter(HwmonCounter *next, int key, const sensors_chip_name
                logg->logError(__FILE__, __LINE__, "Unsupported hwmon feature %i", feature->type);
                handleException();
        }
+
+       for (HwmonCounter * counter = next; counter != NULL; counter = counter->getNext()) {
+               if (strcmp(label, counter->getLabel()) == 0 && strcmp(title, counter->getTitle()) == 0) {
+                       duplicate = true;
+                       counter->duplicate = true;
+                       break;
+               }
+       }
 }
 
 HwmonCounter::~HwmonCounter() {
@@ -143,6 +160,7 @@ double HwmonCounter::read() {
        double result;
        const sensors_subfeature *subfeature;
 
+       // Keep in sync with canRead
        subfeature = sensors_get_subfeature(chip, feature, input);
        if (!subfeature) {
                logg->logError(__FILE__, __LINE__, "No input value for hwmon sensor %s", label);
@@ -160,6 +178,27 @@ double HwmonCounter::read() {
        return result;
 }
 
+bool HwmonCounter::canRead() {
+       if (!polled) {
+               double value;
+               const sensors_subfeature *subfeature;
+               bool result = true;
+
+               subfeature = sensors_get_subfeature(chip, feature, input);
+               if (!subfeature) {
+                       result = false;
+               } else {
+                       result = sensors_get_value(chip, subfeature->number, &value) == 0;
+               }
+
+               polled = true;
+               readable = result;
+       }
+
+       enabled &= readable;
+
+       return readable;
+}
 
 Hwmon::Hwmon() : counters(NULL) {
        int err = sensors_init(NULL);
@@ -191,7 +230,7 @@ Hwmon::~Hwmon() {
 
 HwmonCounter *Hwmon::findCounter(const Counter &counter) const {
        for (HwmonCounter * hwmonCounter = counters; hwmonCounter != NULL; hwmonCounter = hwmonCounter->getNext()) {
-               if (strcmp(hwmonCounter->getName(), counter.getType()) == 0) {
+               if (hwmonCounter->canRead() && strcmp(hwmonCounter->getName(), counter.getType()) == 0) {
                        return hwmonCounter;
                }
        }
@@ -230,6 +269,9 @@ void Hwmon::setupCounter(Counter &counter) {
 
 void Hwmon::writeCounters(mxml_node_t *root) const {
        for (HwmonCounter * counter = counters; counter != NULL; counter = counter->getNext()) {
+               if (!counter->canRead()) {
+                       continue;
+               }
                mxml_node_t *node = mxmlNewElement(root, "counter");
                mxmlElementSetAttr(node, "name", counter->getName());
        }
@@ -241,10 +283,17 @@ void Hwmon::writeEvents(mxml_node_t *root) const {
 
        char buf[1024];
        for (HwmonCounter * counter = counters; counter != NULL; counter = counter->getNext()) {
+               if (!counter->canRead()) {
+                       continue;
+               }
                mxml_node_t *node = mxmlNewElement(root, "event");
                mxmlElementSetAttr(node, "counter", counter->getName());
                mxmlElementSetAttr(node, "title", counter->getTitle());
-               mxmlElementSetAttr(node, "name", counter->getLabel());
+               if (counter->isDuplicate()) {
+                       mxmlElementSetAttrf(node, "name", "%s (0x%x)", counter->getLabel(), counter->getKey());
+               } else {
+                       mxmlElementSetAttr(node, "name", counter->getLabel());
+               }
                mxmlElementSetAttr(node, "display", counter->getDisplay());
                mxmlElementSetAttr(node, "units", counter->getUnit());
                if (counter->getModifier() != 1) {
index 5f12046cfe91476bc3ae1bf4abcc0c4163e2e5e4..04f33306487dd85a946f3180dfe6d15f6ea2fff3 100644 (file)
@@ -58,25 +58,23 @@ void KMod::setupCounter(Counter &counter) {
        }
 
        snprintf(text, sizeof(text), "%s/key", base);
-       int key;
+       int key = 0;
        Collector::readIntDriver(text, &key);
        counter.setKey(key);
 
        snprintf(text, sizeof(text), "%s/event", base);
        Collector::writeDriver(text, counter.getEvent());
-       if (counter.isEBSCapable()) {
-               snprintf(text, sizeof(text), "%s/count", base);
-               if (access(text, F_OK) == 0) {
-                       int count = counter.getCount();
-                       if (Collector::writeReadDriver(text, &count) && counter.getCount() > 0) {
-                               logg->logError(__FILE__, __LINE__, "Cannot enable EBS for %s:%s with a count of %d\n", counter.getTitle(), counter.getName(), counter.getCount());
-                               handleException();
-                       }
-                       counter.setCount(count);
-               } else if (counter.getCount() > 0) {
-                       logg->logError(__FILE__, __LINE__, "Event Based Sampling is only supported with kernel versions 3.0.0 and higher with CONFIG_PERF_EVENTS=y, and CONFIG_HW_PERF_EVENTS=y\n");
+       snprintf(text, sizeof(text), "%s/count", base);
+       if (access(text, F_OK) == 0) {
+               int count = counter.getCount();
+               if (Collector::writeReadDriver(text, &count) && counter.getCount() > 0) {
+                       logg->logError(__FILE__, __LINE__, "Cannot enable EBS for %s:%i with a count of %d\n", counter.getType(), counter.getEvent(), counter.getCount());
                        handleException();
                }
+               counter.setCount(count);
+       } else if (counter.getCount() > 0) {
+               logg->logError(__FILE__, __LINE__, "Event Based Sampling is only supported with kernel versions 3.0.0 and higher with CONFIG_PERF_EVENTS=y, and CONFIG_HW_PERF_EVENTS=y\n");
+               handleException();
        }
 }
 
index baa3dd9980fb2e2f8c3c2f22e9a3ac5d868fe82b..3235a34ae9c718f76db3cc426d43cc9e7325b6e4 100644 (file)
@@ -16,6 +16,7 @@
 #include "SessionData.h"
 #include "Logging.h"
 #include "OlyUtility.h"
+#include "EventsXML.h"
 
 LocalCapture::LocalCapture() {}
 
@@ -40,6 +41,10 @@ void LocalCapture::write(char* string) {
                logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify the path.", file);
                handleException();
        }
+
+       // Write events XML
+       EventsXML eventsXML;
+       eventsXML.write(gSessionData->mAPCDir);
 }
 
 char* LocalCapture::createUniqueDirectory(const char* initialPath, const char* ending) {
index 499f68cd1866e198dfc3f42d7f50674af6843aa6..132510df584a05228caaab33b8fad4ce8533e4c1 100644 (file)
@@ -6,6 +6,8 @@
  * published by the Free Software Foundation.
  */
 
+#include "OlySocket.h"
+
 #include <stdio.h>
 #ifdef WIN32
 #include <Winsock2.h>
@@ -15,7 +17,7 @@
 #include <unistd.h>
 #include <netdb.h>
 #endif
-#include "OlySocket.h"
+
 #include "Logging.h"
 
 #ifdef WIN32
index 2f85131a636d5146e2af26a7c3e0e220c1304d67..b29a1e91cc84ea6e38e290614f2e379c476596df 100644 (file)
@@ -6,6 +6,8 @@
  * published by the Free Software Foundation.
  */
 
+#include "OlyUtility.h"
+
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
@@ -19,8 +21,6 @@
 #include <mach-o/dyld.h>
 #endif
 
-#include "OlyUtility.h"
-
 OlyUtility* util = NULL;
 
 bool OlyUtility::stringToBool(const char* string, bool defValue) {
index 5c68a58f0bd507c601303084b4b697b2e529f91d..abab0a510a7c0cc5d1e10018aac64a537e79c834 100644 (file)
@@ -9,6 +9,8 @@
 #ifndef OLY_UTILITY_H
 #define OLY_UTILITY_H
 
+#include <stddef.h>
+
 #ifdef WIN32
 #define PATH_SEPARATOR '\\'
 #define CAIMAN_PATH_MAX MAX_PATH
index 5b6899b20796f7541b8745e521146030df40e4f9..22a8af0512165f5f1f301358b255dfb743194e2f 100644 (file)
@@ -16,7 +16,7 @@
 
 #define MAX_PERFORMANCE_COUNTERS       50
 
-#define PROTOCOL_VERSION       13
+#define PROTOCOL_VERSION       14
 #define PROTOCOL_DEV           1000    // Differentiates development versions (timestamp) from release versions
 
 struct ImageLinkList {
@@ -57,7 +57,7 @@ public:
        int mCpuId;
 
        // PMU Counters
-       bool mCounterOverflow;
+       int mCounterOverflow;
        Counter mCounters[MAX_PERFORMANCE_COUNTERS];
 
 private:
index 88c07a6224cfa73bee5d118cca3a48bda0d7f370..e196a7dba2c993151eff4328d06398ab23b07732 100644 (file)
@@ -20,6 +20,7 @@
 #include "StreamlineSetup.h"
 #include "ConfigurationXML.h"
 #include "Driver.h"
+#include "EventsXML.h"
 
 static const char* TAG_SESSION = "session";
 static const char* TAG_REQUEST = "request";
@@ -77,8 +78,8 @@ StreamlineSetup::StreamlineSetup(OlySocket* s) {
                free(data);
        }
 
-       if (gSessionData->mCounterOverflow) {
-               logg->logError(__FILE__, __LINE__, "Exceeded maximum number of %d performance counters", MAX_PERFORMANCE_COUNTERS);
+       if (gSessionData->mCounterOverflow > 0) {
+               logg->logError(__FILE__, __LINE__, "Only %i performance counters are permitted, %i are selected", MAX_PERFORMANCE_COUNTERS, gSessionData->mCounterOverflow);
                handleException();
        }
 }
@@ -87,12 +88,12 @@ StreamlineSetup::~StreamlineSetup() {
 }
 
 char* StreamlineSetup::readCommand(int* command) {
-       char type;
+       unsigned char header[5];
        char* data;
-       int response, length;
+       int response;
 
-       // receive type
-       response = mSocket->receiveNBytes(&type, sizeof(type));
+       // receive type and length
+       response = mSocket->receiveNBytes((char*)&header, sizeof(header));
 
        // After receiving a single byte, we are no longer waiting on a command
        gSessionData->mWaitingOnCommand = false;
@@ -102,12 +103,8 @@ char* StreamlineSetup::readCommand(int* command) {
                handleException();
        }
 
-       // receive length
-       response = mSocket->receiveNBytes((char*)&length, sizeof(length));
-       if (response < 0) {
-               logg->logError(__FILE__, __LINE__, "Target error: Unexpected socket disconnect");
-               handleException();
-       }
+       const char type = header[0];
+       const int length = (header[1] << 0) | (header[2] << 8) | (header[3] << 16) | (header[4] << 24);
 
        // add artificial limit
        if ((length < 0) || length > 1024 * 1024) {
@@ -198,51 +195,22 @@ void StreamlineSetup::handleDeliver(char* xml) {
        mxmlDelete(tree);
 }
 
-void StreamlineSetup::sendData(const char* data, int length, int type) {
-       mSocket->send((char*)&type, 1);
-       mSocket->send((char*)&length, sizeof(length));
+void StreamlineSetup::sendData(const char* data, uint32_t length, char type) {
+       unsigned char header[5];
+       header[0] = type;
+       header[1] = (length >> 0) & 0xff;
+       header[2] = (length >> 8) & 0xff;
+       header[3] = (length >> 16) & 0xff;
+       header[4] = (length >> 24) & 0xff;
+       mSocket->send((char*)&header, sizeof(header));
        mSocket->send((char*)data, length);
 }
 
 void StreamlineSetup::sendEvents() {
-#include "events_xml.h" // defines and initializes char events_xml[] and int events_xml_len
-       char path[PATH_MAX];
-       mxml_node_t *xml;
-       FILE *fl;
-
-       // Avoid unused variable warning
-       (void)events_xml_len;
-
-       // Load the provided or default events xml
-       if (gSessionData->mEventsXMLPath) {
-               strncpy(path, gSessionData->mEventsXMLPath, PATH_MAX);
-       } else {
-               util->getApplicationFullPath(path, PATH_MAX);
-               strncat(path, "events.xml", PATH_MAX - strlen(path) - 1);
-       }
-       fl = fopen(path, "r");
-       if (fl) {
-               xml = mxmlLoadFile(NULL, fl, MXML_NO_CALLBACK);
-               fclose(fl);
-       } else {
-               logg->logMessage("Unable to locate events.xml, using default");
-               xml = mxmlLoadString(NULL, (char *)events_xml, MXML_NO_CALLBACK);
-       }
-
-       // Add dynamic events from the drivers
-       mxml_node_t *events = mxmlFindElement(xml, xml, "events", NULL, NULL, MXML_DESCEND);
-       if (!events) {
-               logg->logMessage("Unable to find <events> node in the events.xml");
-               handleException();
-       }
-       for (Driver *driver = Driver::getHead(); driver != NULL; driver = driver->getNext()) {
-               driver->writeEvents(events);
-       }
-
-       char* string = mxmlSaveAllocString(xml, mxmlWhitespaceCB);
+       EventsXML eventsXML;
+       char* string = eventsXML.getXML();
        sendString(string, RESPONSE_XML);
        free(string);
-       mxmlDelete(xml);
 }
 
 void StreamlineSetup::sendConfiguration() {
@@ -302,8 +270,8 @@ void StreamlineSetup::writeConfiguration(char* xml) {
        // Re-populate gSessionData with the configuration, as it has now changed
        { ConfigurationXML configuration; }
 
-       if (gSessionData->mCounterOverflow) {
-               logg->logError(__FILE__, __LINE__, "Exceeded maximum number of %d performance counters", MAX_PERFORMANCE_COUNTERS);
+       if (gSessionData->mCounterOverflow > 0) {
+               logg->logError(__FILE__, __LINE__, "Only %i performance counters counters are permitted, %i are selected", MAX_PERFORMANCE_COUNTERS, gSessionData->mCounterOverflow);
                handleException();
        }
 }
index 841735d0cbf662b1b556a9406c8981e898cb49e4..a27a7ac97a13e25999195132bb2105ea382b7175 100644 (file)
@@ -32,7 +32,7 @@ private:
        char* readCommand(int*);
        void handleRequest(char* xml);
        void handleDeliver(char* xml);
-       void sendData(const char* data, int length, int type);
+       void sendData(const char* data, uint32_t length, char type);
        void sendString(const char* string, int type) {sendData(string, strlen(string), type);}
        void sendEvents();
        void sendConfiguration();
index 112b990db3f36f8d2d20c2e246649a0625eb3f7f..ee2415b8825c1a37acd9892cb0f2092d1bb69d0d 100644 (file)
@@ -24,7 +24,7 @@ events.xml: events_header.xml $(wildcard events-*.xml) events_footer.xml
 include $(wildcard *.d)
 include $(wildcard mxml/*.d)
 
-StreamlineSetup.cpp: events_xml.h
+EventsXML.cpp: events_xml.h
 ConfigurationXML.cpp: configuration_xml.h
 
 # Don't regenerate conf-lex.c or conf-parse.c
index 62ccd080e384166f65498f60d0587c6bcd50d50b..b44c00a79e88057d27d79613a10bc584a00cb0ec 100644 (file)
@@ -1,47 +1,57 @@
-<?xml version="1.0" encoding='UTF-8'?>
-<configurations revision="2">
-  <configuration counter="ARM_ARM11_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
-  <configuration counter="ARM_ARM11_cnt0" event="0x7" title="Instruction" name="Executed" per_cpu="yes" description="Instructions executed"/>
-  <configuration counter="ARM_ARM11_cnt1" event="0xb" title="Cache" name="Data miss" per_cpu="yes" description="Data cache miss, not including Cache Operations"/>
-  <configuration counter="ARM_ARM11MPCore_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
-  <configuration counter="ARM_ARM11MPCore_cnt0" event="0x08" title="Core" name="Instructions" per_cpu="yes" description="Instructions executed"/>
-  <configuration counter="ARM_ARM11MPCore_cnt1" event="0x0b" title="Cache" name="Data read miss" per_cpu="yes" description="Data cache miss, not including Cache Operations"/>
-  <configuration counter="ARM_Cortex-A5_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
-  <configuration counter="ARM_Cortex-A5_cnt0" event="0x8" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/>
-  <configuration counter="ARM_Cortex-A5_cnt1" event="0x1" title="Cache" name="Instruction refill" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
-  <configuration counter="ARM_Cortex-A7_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
-  <configuration counter="ARM_Cortex-A7_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/>
-  <configuration counter="ARM_Cortex-A7_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" supports_event_based_sampling="yes" description="Branch mispredicted or not predicted"/>
-  <configuration counter="ARM_Cortex-A7_cnt2" event="0x16" title="Cache" name="L2 data access" per_cpu="yes" supports_event_based_sampling="yes" description="Level 2 data cache access"/>
-  <configuration counter="ARM_Cortex-A8_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
-  <configuration counter="ARM_Cortex-A8_cnt0" event="0x8" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/>
-  <configuration counter="ARM_Cortex-A8_cnt1" event="0x44" title="Cache" name="L2 miss" per_cpu="yes" supports_event_based_sampling="yes" description="Any cacheable miss in the L2 cache"/>
-  <configuration counter="ARM_Cortex-A8_cnt2" event="0x43" title="Cache" name="L1 miss" per_cpu="yes" supports_event_based_sampling="yes" description="Any accesses to the L2 cache"/>
-  <configuration counter="ARM_Cortex-A8_cnt3" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" supports_event_based_sampling="yes" description="Branch mispredicted or not predicted"/>
-  <configuration counter="ARM_Cortex-A9_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
-  <configuration counter="ARM_Cortex-A9_cnt0" event="0x68" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Counts the number of instructions going through the Register Renaming stage. This number is an approximate number of the total number of instructions speculatively executed, and even more approximate of the total number of instructions architecturally executed"/>
-  <configuration counter="ARM_Cortex-A9_cnt1" event="0x06" title="Instruction" name="Memory read" per_cpu="yes" supports_event_based_sampling="yes" description="Memory-reading instruction architecturally executed"/>
-  <configuration counter="ARM_Cortex-A9_cnt2" event="0x07" title="Instruction" name="Memory write" per_cpu="yes" supports_event_based_sampling="yes" description="Memory-writing instruction architecturally executed"/>
-  <configuration counter="ARM_Cortex-A9_cnt3" event="0x03" title="Cache" name="Data refill" per_cpu="yes" supports_event_based_sampling="yes" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
-  <configuration counter="ARM_Cortex-A9_cnt4" event="0x04" title="Cache" name="Data access" per_cpu="yes" supports_event_based_sampling="yes" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
-  <configuration counter="ARM_Cortex-A15_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
-  <configuration counter="ARM_Cortex-A15_cnt0" event="0x8" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/>
-  <configuration counter="ARM_Cortex-A15_cnt1" event="0x16" title="Cache" name="L2 data access" per_cpu="yes" supports_event_based_sampling="yes" description="Level 2 data cache access"/>
-  <configuration counter="ARM_Cortex-A15_cnt2" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" supports_event_based_sampling="yes" description="Branch mispredicted or not predicted"/>
-  <configuration counter="ARM_Cortex-A15_cnt3" event="0x19" title="Bus" name="Access" per_cpu="yes" supports_event_based_sampling="yes" description="Bus - Access"/>
-  <configuration counter="Scorpion_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
-  <configuration counter="Scorpion_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/>
-  <configuration counter="Scorpion_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" supports_event_based_sampling="yes" description="Branch mispredicted or not predicted"/>
-  <configuration counter="ScorpionMP_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
-  <configuration counter="ScorpionMP_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/>
-  <configuration counter="ScorpionMP_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" supports_event_based_sampling="yes" description="Branch mispredicted or not predicted"/>
-  <configuration counter="Krait_ccnt" event="0xff" title="Clock" name="Cycles" per_cpu="yes" supports_event_based_sampling="yes" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
-  <configuration counter="Krait_cnt0" event="0x08" title="Instruction" name="Executed" per_cpu="yes" supports_event_based_sampling="yes" description="Instruction architecturally executed"/>
-  <configuration counter="Krait_cnt1" event="0x10" title="Branch" name="Mispredicted" per_cpu="yes" supports_event_based_sampling="yes" description="Branch mispredicted or not predicted"/>
-  <configuration counter="Linux_block_rq_wr" title="Disk IO" name="Write" units="B" description="Disk IO Bytes Written"/>
-  <configuration counter="Linux_block_rq_rd" title="Disk IO" name="Read" units="B" description="Disk IO Bytes Read"/>
-  <configuration counter="Linux_meminfo_memused" title="Memory" name="Used" display="maximum" units="B" average_selection="yes" description="Total used memory size"/>
-  <configuration counter="Linux_meminfo_memfree" title="Memory" name="Free" display="minimum" units="B" average_selection="yes" description="Available memory size"/>
-  <configuration counter="Linux_power_cpu_freq" title="Clock" name="Frequency" per_cpu="yes" display="maximum" units="Hz" average_selection="yes" description="Frequency setting of the CPU"/>
-  <configuration counter="L2C-310_cnt0" event="0x1" title="L2 Cache" name="CO" description="Eviction, CastOUT, of a line from the L2 cache"/>
+<?xml version="1.0" encoding="UTF-8"?>
+<configurations revision="3">
+  <configuration counter="ARM_ARM11_ccnt" event="0xff"/>
+  <configuration counter="ARM_ARM11_cnt0" event="0x7"/>
+  <configuration counter="ARM_ARM11_cnt1" event="0xb"/>
+  <configuration counter="ARM_ARM11MPCore_ccnt" event="0xff"/>
+  <configuration counter="ARM_ARM11MPCore_cnt0" event="0x08"/>
+  <configuration counter="ARM_ARM11MPCore_cnt1" event="0x0b"/>
+  <configuration counter="ARM_Cortex-A5_ccnt" event="0xff"/>
+  <configuration counter="ARM_Cortex-A5_cnt0" event="0x8"/>
+  <configuration counter="ARM_Cortex-A5_cnt1" event="0x1"/>
+  <configuration counter="ARM_Cortex-A7_ccnt" event="0xff"/>
+  <configuration counter="ARM_Cortex-A7_cnt0" event="0x08"/>
+  <configuration counter="ARM_Cortex-A7_cnt1" event="0x10"/>
+  <configuration counter="ARM_Cortex-A7_cnt2" event="0x16"/>
+  <configuration counter="ARM_Cortex-A8_ccnt" event="0xff"/>
+  <configuration counter="ARM_Cortex-A8_cnt0" event="0x8"/>
+  <configuration counter="ARM_Cortex-A8_cnt1" event="0x44"/>
+  <configuration counter="ARM_Cortex-A8_cnt2" event="0x43"/>
+  <configuration counter="ARM_Cortex-A8_cnt3" event="0x10"/>
+  <configuration counter="ARM_Cortex-A9_ccnt" event="0xff"/>
+  <configuration counter="ARM_Cortex-A9_cnt0" event="0x68"/>
+  <configuration counter="ARM_Cortex-A9_cnt1" event="0x06"/>
+  <configuration counter="ARM_Cortex-A9_cnt2" event="0x07"/>
+  <configuration counter="ARM_Cortex-A9_cnt3" event="0x03"/>
+  <configuration counter="ARM_Cortex-A9_cnt4" event="0x04"/>
+  <configuration counter="ARM_Cortex-A15_ccnt" event="0xff"/>
+  <configuration counter="ARM_Cortex-A15_cnt0" event="0x8"/>
+  <configuration counter="ARM_Cortex-A15_cnt1" event="0x16"/>
+  <configuration counter="ARM_Cortex-A15_cnt2" event="0x10"/>
+  <configuration counter="ARM_Cortex-A15_cnt3" event="0x19"/>
+  <configuration counter="ARM_Cortex-A53_ccnt" event="0x11"/>
+  <configuration counter="ARM_Cortex-A53_cnt0" event="0x8"/>
+  <configuration counter="ARM_Cortex-A53_cnt1" event="0x16"/>
+  <configuration counter="ARM_Cortex-A53_cnt2" event="0x10"/>
+  <configuration counter="ARM_Cortex-A53_cnt3" event="0x19"/>
+  <configuration counter="ARM_Cortex-A57_ccnt" event="0x11"/>
+  <configuration counter="ARM_Cortex-A57_cnt0" event="0x8"/>
+  <configuration counter="ARM_Cortex-A57_cnt1" event="0x16"/>
+  <configuration counter="ARM_Cortex-A57_cnt2" event="0x10"/>
+  <configuration counter="ARM_Cortex-A57_cnt3" event="0x19"/>
+  <configuration counter="Scorpion_ccnt" event="0xff"/>
+  <configuration counter="Scorpion_cnt0" event="0x08"/>
+  <configuration counter="Scorpion_cnt1" event="0x10"/>
+  <configuration counter="ScorpionMP_ccnt" event="0xff"/>
+  <configuration counter="ScorpionMP_cnt0" event="0x08"/>
+  <configuration counter="ScorpionMP_cnt1" event="0x10"/>
+  <configuration counter="Krait_ccnt" event="0xff"/>
+  <configuration counter="Krait_cnt0" event="0x08"/>
+  <configuration counter="Krait_cnt1" event="0x10"/>
+  <configuration counter="Linux_block_rq_wr"/>
+  <configuration counter="Linux_block_rq_rd"/>
+  <configuration counter="Linux_meminfo_memused"/>
+  <configuration counter="Linux_meminfo_memfree"/>
+  <configuration counter="Linux_power_cpu_freq"/>
+  <configuration counter="L2C-310_cnt0" event="0x1"/>
 </configurations>
index a1545158887975c4610a8580fad2ead8c8163218..3eec1f8d38d34d2e2c3b5ce290b07c65a0c19d4b 100644 (file)
@@ -50,14 +50,20 @@ int main(int argc, char *argv[]) {
   printf("static const unsigned char ");
   print_escaped_path(path);
   printf("[] = {");
-  for (; (ch = fgetc(in)) != EOF; ++len) {
+  for (;;) {
+    ch = fgetc(in);
     if (len != 0) {
       printf(",");
     }
     if (len % 12 == 0) {
       printf("\n ");
     }
-    printf(" 0x%.2x", ch);
+    // Write out a null character after the contents of the file but do not increment len
+    printf(" 0x%.2x", (ch == EOF ? 0 : ch));
+    if (ch == EOF) {
+      break;
+    }
+    ++len;
   }
   printf("\n};\nstatic const unsigned int ");
   print_escaped_path(path);
index 9f31313b725ce1094b964cd8d6cf1f6593de2755..57e3235463145a20e36ae9be3767a8ed22f23eff 100644 (file)
@@ -1,6 +1,6 @@
   <counter_set name="ARM_ARM11_cnt" count="3"/>
   <category name="ARM11" counter_set="ARM_ARM11_cnt" per_cpu="yes">
-    <event counter="ARM_ARM11_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+    <event counter="ARM_ARM11_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
     <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>
     <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>
     <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>
index 68ca9a56d44403e3e8a61ef6e290a86f3f3b3c03..2d5c5e199e664521c060d59c1e3549756d15e9a6 100644 (file)
@@ -1,6 +1,6 @@
   <counter_set name="ARM_ARM11MPCore_cnt" count="3"/>
   <category name="ARM11MPCore" counter_set="ARM_ARM11MPCore_cnt" per_cpu="yes">
-    <event counter="ARM_ARM11MPCore_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+    <event counter="ARM_ARM11MPCore_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
     <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>
     <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>
     <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>
index 2be0df33ca428913ab8460e12ffd243354b63923..86db2087e1f551588822c9fdd0f10e3baebfb9c9 100644 (file)
@@ -1,6 +1,6 @@
   <counter_set name="cci-400_cnt" count="4"/>
   <category name="CCI-400" counter_set="cci-400_cnt" per_cpu="no" supports_event_based_sampling="yes">
-    <event counter="cci-400_ccnt" event="0xff" title="CCI-400" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+    <event counter="cci-400_ccnt" event="0xff" title="CCI-400 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
 
     <option_set name="Slave">
       <option event_delta="0x00" name="S0" description="Slave interface 0"/>
index e3de814354b3fe1823d87648140bdcf090161bda..faa8b1cbcfb2c3a0f420297e678791650828079c 100644 (file)
@@ -1,6 +1,6 @@
   <counter_set name="ARM_Cortex-A15_cnt" count="6"/>
   <category name="Cortex-A15" counter_set="ARM_Cortex-A15_cnt" per_cpu="yes" supports_event_based_sampling="yes">
-    <event counter="ARM_Cortex-A15_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+    <event counter="ARM_Cortex-A15_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
     <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>
     <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
     <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
index 77dd8387e1473d179a775898da14c18571c52968..a5b15466be5221eb04abab8b3a5aac1a8d522063 100644 (file)
@@ -1,6 +1,6 @@
   <counter_set name="ARM_Cortex-A5_cnt" count="2"/>
   <category name="Cortex-A5" counter_set="ARM_Cortex-A5_cnt" per_cpu="yes" supports_event_based_sampling="yes">
-    <event counter="ARM_Cortex-A5_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+    <event counter="ARM_Cortex-A5_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
     <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
     <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
     <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
index 0ffa41223e7bbb0a8d881f352597c68290a6d7e9..577dcd94185e32777c8687504a669239b66b7ebe 100644 (file)
@@ -1,7 +1,7 @@
   <counter_set name="ARM_Cortex-A53_cnt" count="6"/>
   <category name="Cortex-A53" counter_set="ARM_Cortex-A53_cnt" per_cpu="yes" supports_event_based_sampling="yes">
     <!-- 0x11 CPU_CYCLES - Cycle -->
-    <event counter="ARM_Cortex-A53_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+    <event counter="ARM_Cortex-A53_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
     <!-- 0x00 SW_INCR - Instruction architecturally executed (condition check pass) - Software increment -->
     <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
     <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill -->
@@ -15,7 +15,7 @@
     <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill -->
     <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
     <!-- 0x08 INST_RETIRED - Instruction architecturally executed -->
-    <event event="0x08" title="-" name="INST_RETIRED" description="Instruction architecturally executed"/>
+    <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
     <!-- 0x09 EXC_TAKEN - Exception taken -->
     <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
     <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return -->
     <!-- 0x12 BR_PRED - Predictable branch speculatively executed -->
     <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
     <!-- 0x13 MEM_ACCESS - Data memory access -->
-    <event event="0x13" title="-" name="MEM_ACCESS" description="Data memory access"/>
+    <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
     <!-- 0x14 L1I_CACHE - Level 1 instruction cache access -->
-    <event event="0x14" title="-" name="L1I_CACHE" description="Level 1 instruction cache access"/>
+    <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/>
     <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back -->
-    <event event="0x15" title="-" name="L1D_CACHE_WB" description="Level 1 data cache Write-Back"/>
+    <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
     <!-- 0x16 L2D_CACHE - Level 2 data cache access -->
-    <event event="0x16" title="-" name="L2D_CACHE" description="Level 2 data cache access"/>
+    <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
     <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill -->
-    <event event="0x17" title="-" name="L2D_CACHE_REFILL" description="Level 2 data cache refill"/>
+    <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
     <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back -->
-    <event event="0x18" title="-" name="L2D_CACHE_WB" description="Level 2 data cache Write-Back"/>
+    <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
     <!-- 0x19 BUS_ACCESS - Bus access -->
-    <event event="0x19" title="-" name="BUS_ACCESS" description="Bus access"/>
+    <event event="0x19" title="Bus" name="Access" description="Bus access"/>
     <!-- 0x1A MEMORY_ERROR - Local memory error -->
-    <event event="0x1A" title="-" name="MEMORY_ERROR" description="Local memory error"/>
+    <event event="0x1A" title="Memory" name="Error" description="Local memory error"/>
     <!-- 0x1B INST_SPEC - Operation speculatively executed -->
-    <event event="0x1B" title="-" name="INST_SPEC" description="Operation speculatively executed"/>
+    <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/>
     <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base -->
-    <event event="0x1C" title="-" name="TTBR_WRITE_RETIRED" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
+    <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
     <!-- 0x1D BUS_CYCLES - Bus cycle -->
-    <event event="0x1D" title="-" name="BUS_CYCLES" description="Bus cycle"/>
+    <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/>
     <!-- 0x1E CHAIN - Odd performance counter chain mode -->
-    <event event="0x1E" title="-" name="CHAIN" description="Odd performance counter chain mode"/>
+    <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/>
     <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read -->
-    <event event="0x40" title="-" name="L1D_CACHE_LD" description="Level 1 data cache access - Read"/>
+    <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
     <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write -->
-    <event event="0x41" title="-" name="L1D_CACHE_ST" description="Level 1 data cache access - Write"/>
+    <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
     <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read -->
-    <event event="0x42" title="-" name="L1D_CACHE_REFILL_LD" description="Level 1 data cache refill - Read"/>
+    <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
     <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write -->
-    <event event="0x43" title="-" name="L1D_CACHE_REFILL_ST" description="Level 1 data cache refill - Write"/>
+    <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
     <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim -->
-    <event event="0x46" title="-" name="L1D_CACHE_WB_VICTIM" description="Level 1 data cache Write-back - Victim"/>
+    <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/>
     <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency -->
-    <event event="0x47" title="-" name="L1D_CACHE_WB_CLEAN" description="Level 1 data cache Write-back - Cleaning and coherency"/>
+    <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/>
     <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate -->
-    <event event="0x48" title="-" name="L1D_CACHE_INVAL" description="Level 1 data cache invalidate"/>
+    <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
     <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read -->
-    <event event="0x4C" title="-" name="L1D_TLB_REFILL_LD" description="Level 1 data TLB refill - Read"/>
+    <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
     <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write -->
-    <event event="0x4D" title="-" name="L1D_TLB_REFILL_ST" description="Level 1 data TLB refill - Write"/>
+    <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
     <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read -->
-    <event event="0x50" title="-" name="L2D_CACHE_LD" description="Level 2 data cache access - Read"/>
+    <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
     <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write -->
-    <event event="0x51" title="-" name="L2D_CACHE_ST" description="Level 2 data cache access - Write"/>
+    <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
     <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read -->
-    <event event="0x52" title="-" name="L2D_CACHE_REFILL_LD" description="Level 2 data cache refill - Read"/>
+    <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
     <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write -->
-    <event event="0x53" title="-" name="L2D_CACHE_REFILL_ST" description="Level 2 data cache refill - Write"/>
+    <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
     <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim -->
-    <event event="0x56" title="-" name="L2D_CACHE_WB_VICTIM" description="Level 2 data cache Write-back - Victim"/>
+    <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/>
     <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency -->
-    <event event="0x57" title="-" name="L2D_CACHE_WB_CLEAN" description="Level 2 data cache Write-back - Cleaning and coherency"/>
+    <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/>
     <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate -->
-    <event event="0x58" title="-" name="L2D_CACHE_INVAL" description="Level 2 data cache invalidate"/>
+    <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
     <!-- 0x60 BUS_ACCESS_LD - Bus access - Read -->
-    <event event="0x60" title="-" name="BUS_ACCESS_LD" description="Bus access - Read"/>
+    <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
     <!-- 0x61 BUS_ACCESS_ST - Bus access - Write -->
-    <event event="0x61" title="-" name="BUS_ACCESS_ST" description="Bus access - Write"/>
+    <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
     <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal -->
-    <event event="0x62" title="-" name="BUS_ACCESS_SHARED" description="Bus access - Normal"/>
+    <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/>
     <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal -->
-    <event event="0x63" title="-" name="BUS_ACCESS_NOT_SHARED" description="Bus access - Not normal"/>
+    <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/>
     <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal -->
-    <event event="0x64" title="-" name="BUS_ACCESS_NORMAL" description="Bus access - Normal"/>
+    <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
     <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral -->
-    <event event="0x65" title="-" name="BUS_ACCESS_PERIPH" description="Bus access - Peripheral"/>
+    <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
     <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read -->
-    <event event="0x66" title="-" name="MEM_ACCESS_LD" description="Data memory access - Read"/>
+    <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
     <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write -->
-    <event event="0x67" title="-" name="MEM_ACCESS_ST" description="Data memory access - Write"/>
+    <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
     <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read -->
-    <event event="0x68" title="-" name="UNALIGNED_LD_SPEC" description="Unaligned access - Read"/>
+    <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
     <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write -->
-    <event event="0x69" title="-" name="UNALIGNED_ST_SPEC" description="Unaligned access - Write"/>
+    <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
     <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access -->
-    <event event="0x6A" title="-" name="UNALIGNED_LDST_SPEC" description="Unaligned access"/>
+    <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/>
     <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX -->
-    <event event="0x6C" title="-" name="LDREX_SPEC" description="Exclusive operation speculatively executed - LDREX"/>
+    <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/>
     <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass -->
-    <event event="0x6D" title="-" name="STREX_PASS_SPEC" description="Exclusive instruction speculatively executed - STREX pass"/>
+    <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
     <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail -->
-    <event event="0x6E" title="-" name="STREX_FAIL_SPEC" description="Exclusive operation speculatively executed - STREX fail"/>
+    <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/>
     <!-- 0x70 LD_SPEC - Operation speculatively executed - Load -->
-    <event event="0x70" title="-" name="LD_SPEC" description="Operation speculatively executed - Load"/>
+    <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/>
     <!-- 0x71 ST_SPEC - Operation speculatively executed - Store -->
-    <event event="0x71" title="-" name="ST_SPEC" description="Operation speculatively executed - Store"/>
+    <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/>
     <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store -->
-    <event event="0x72" title="-" name="LDST_SPEC" description="Operation speculatively executed - Load or store"/>
+    <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/>
     <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing -->
-    <event event="0x73" title="-" name="DP_SPEC" description="Operation speculatively executed - Integer data processing"/>
+    <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/>
     <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD -->
-    <event event="0x74" title="-" name="ASE_SPEC" description="Operation speculatively executed - Advanced SIMD"/>
+    <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/>
     <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP -->
-    <event event="0x75" title="-" name="VFP_SPEC" description="Operation speculatively executed - VFP"/>
+    <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/>
     <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC -->
-    <event event="0x76" title="-" name="PC_WRITE_SPEC" description="Operation speculatively executed - Software change of the PC"/>
+    <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/>
     <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing -->
-    <event event="0x77" title="-" name="CRYPTO_SPEC" description="Operation speculatively executed, crypto data processing"/>
+    <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/>
     <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch -->
-    <event event="0x78" title="-" name="BR_IMMED_SPEC" description="Branch speculatively executed - Immediate branch"/>
+    <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
     <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return -->
-    <event event="0x79" title="-" name="BR_RETURN_SPEC" description="Branch speculatively executed - Procedure return"/>
+    <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
     <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch -->
-    <event event="0x7A" title="-" name="BR_INDIRECT_SPEC" description="Branch speculatively executed - Indirect branch"/>
+    <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
     <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB -->
-    <event event="0x7C" title="-" name="ISB_SPEC" description="Barrier speculatively executed - ISB"/>
+    <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
     <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB -->
-    <event event="0x7D" title="-" name="DSB_SPEC" description="Barrier speculatively executed - DSB"/>
+    <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
     <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB -->
-    <event event="0x7E" title="-" name="DMB_SPEC" description="Barrier speculatively executed - DMB"/>
+    <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
     <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous -->
-    <event event="0x81" title="-" name="EXC_UNDEF" description="Exception taken, other synchronous"/>
+    <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/>
     <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call -->
-    <event event="0x82" title="-" name="EXC_SVC" description="Exception taken, Supervisor Call"/>
+    <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/>
     <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort -->
-    <event event="0x83" title="-" name="EXC_PABORT" description="Exception taken, Instruction Abort"/>
+    <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/>
     <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError -->
-    <event event="0x84" title="-" name="EXC_DABORT" description="Exception taken, Data Abort or SError"/>
+    <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/>
     <!-- 0x86 EXC_IRQ - Exception taken, IRQ -->
-    <event event="0x86" title="-" name="EXC_IRQ" description="Exception taken, IRQ"/>
+    <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/>
     <!-- 0x87 EXC_FIQ - Exception taken, FIQ -->
-    <event event="0x87" title="-" name="EXC_FIQ" description="Exception taken, FIQ"/>
+    <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/>
     <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call -->
-    <event event="0x88" title="-" name="EXC_SMC" description="Exception taken, Secure Monitor Call"/>
+    <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/>
     <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call -->
-    <event event="0x8A" title="-" name="EXC_HVC" description="Exception taken, Hypervisor Call"/>
+    <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/>
     <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally -->
-    <event event="0x8B" title="-" name="EXC_TRAP_PABORT" description="Exception taken, Instruction Abort not taken locally"/>
+    <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/>
     <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally -->
-    <event event="0x8C" title="-" name="EXC_TRAP_DABORT" description="Exception taken, Data Abort or SError not taken locally"/>
-    <!-- 0x8D EXC_TRAP_OTHER - Exception taken  Other traps not taken locally -->
-    <event event="0x8D" title="-" name="EXC_TRAP_OTHER" description="Exception taken – Other traps not taken locally"/>
+    <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/>
+    <!-- 0x8D EXC_TRAP_OTHER - Exception taken - Other traps not taken locally -->
+    <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/>
     <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally -->
-    <event event="0x8E" title="-" name="EXC_TRAP_IRQ" description="Exception taken, IRQ not taken locally"/>
+    <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/>
     <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally -->
-    <event event="0x8F" title="-" name="EXC_TRAP_FIQ" description="Exception taken, FIQ not taken locally"/>
-    <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed  Load Acquire -->
-    <event event="0x90" title="-" name="RC_LD_SPEC" description="Release consistency instruction speculatively executed – Load Acquire"/>
-    <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed  Store Release -->
-    <event event="0x91" title="-" name="RC_ST_SPEC" description="Release consistency instruction speculatively executed – Store Release"/>
+    <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/>
+    <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed - Load Acquire -->
+    <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/>
+    <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed - Store Release -->
+    <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/>
   </category>
index e8c0a61127781193a20ef2fee7f35c2eb2f6fa07..b7178c0c742701adf63f9d1cdafa2456a9ae3d51 100644 (file)
@@ -1,8 +1,8 @@
   <counter_set name="ARM_Cortex-A57_cnt" count="6"/>
   <category name="Cortex-A57" counter_set="ARM_Cortex-A57_cnt" per_cpu="yes" supports_event_based_sampling="yes">
     <!-- 0x11 CPU_CYCLES - Cycle -->
-    <event counter="ARM_Cortex-A57_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
-    <!-- 0x00 SW_INCR - Instruction architecturally executed number (condition check pass) - Software increment -->
+    <event counter="ARM_Cortex-A57_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
+    <!-- 0x00 SW_INCR - Instruction architecturally executed (condition check pass) - Software increment -->
     <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
     <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill -->
     <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
@@ -15,7 +15,7 @@
     <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill -->
     <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
     <!-- 0x08 INST_RETIRED - Instruction architecturally executed -->
-    <event event="0x08" title="-" name="INST_RETIRED" description="Instruction architecturally executed"/>
+    <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
     <!-- 0x09 EXC_TAKEN - Exception taken -->
     <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
     <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return -->
     <!-- 0x12 BR_PRED - Predictable branch speculatively executed -->
     <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
     <!-- 0x13 MEM_ACCESS - Data memory access -->
-    <event event="0x13" title="-" name="MEM_ACCESS" description="Data memory access"/>
+    <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
     <!-- 0x14 L1I_CACHE - Level 1 instruction cache access -->
-    <event event="0x14" title="-" name="L1I_CACHE" description="Level 1 instruction cache access"/>
+    <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/>
     <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back -->
-    <event event="0x15" title="-" name="L1D_CACHE_WB" description="Level 1 data cache Write-Back"/>
+    <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
     <!-- 0x16 L2D_CACHE - Level 2 data cache access -->
-    <event event="0x16" title="-" name="L2D_CACHE" description="Level 2 data cache access"/>
+    <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
     <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill -->
-    <event event="0x17" title="-" name="L2D_CACHE_REFILL" description="Level 2 data cache refill"/>
+    <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
     <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back -->
-    <event event="0x18" title="-" name="L2D_CACHE_WB" description="Level 2 data cache Write-Back"/>
+    <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
     <!-- 0x19 BUS_ACCESS - Bus access -->
-    <event event="0x19" title="-" name="BUS_ACCESS" description="Bus access"/>
+    <event event="0x19" title="Bus" name="Access" description="Bus access"/>
     <!-- 0x1A MEMORY_ERROR - Local memory error -->
-    <event event="0x1A" title="-" name="MEMORY_ERROR" description="Local memory error"/>
+    <event event="0x1A" title="Memory" name="Error" description="Local memory error"/>
     <!-- 0x1B INST_SPEC - Operation speculatively executed -->
-    <event event="0x1B" title="-" name="INST_SPEC" description="Operation speculatively executed"/>
+    <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/>
     <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base -->
-    <event event="0x1C" title="-" name="TTBR_WRITE_RETIRED" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
+    <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
     <!-- 0x1D BUS_CYCLES - Bus cycle -->
-    <event event="0x1D" title="-" name="BUS_CYCLES" description="Bus cycle"/>
+    <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/>
     <!-- 0x1E CHAIN - Odd performance counter chain mode -->
-    <event event="0x1E" title="-" name="CHAIN" description="Odd performance counter chain mode"/>
+    <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/>
     <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read -->
-    <event event="0x40" title="-" name="L1D_CACHE_LD" description="Level 1 data cache access - Read"/>
+    <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
     <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write -->
-    <event event="0x41" title="-" name="L1D_CACHE_ST" description="Level 1 data cache access - Write"/>
+    <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
     <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read -->
-    <event event="0x42" title="-" name="L1D_CACHE_REFILL_LD" description="Level 1 data cache refill - Read"/>
+    <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
     <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write -->
-    <event event="0x43" title="-" name="L1D_CACHE_REFILL_ST" description="Level 1 data cache refill - Write"/>
+    <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
     <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim -->
-    <event event="0x46" title="-" name="L1D_CACHE_WB_VICTIM" description="Level 1 data cache Write-back - Victim"/>
+    <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/>
     <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency -->
-    <event event="0x47" title="-" name="L1D_CACHE_WB_CLEAN" description="Level 1 data cache Write-back - Cleaning and coherency"/>
+    <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/>
     <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate -->
-    <event event="0x48" title="-" name="L1D_CACHE_INVAL" description="Level 1 data cache invalidate"/>
+    <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
     <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read -->
-    <event event="0x4C" title="-" name="L1D_TLB_REFILL_LD" description="Level 1 data TLB refill - Read"/>
+    <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
     <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write -->
-    <event event="0x4D" title="-" name="L1D_TLB_REFILL_ST" description="Level 1 data TLB refill - Write"/>
+    <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
     <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read -->
-    <event event="0x50" title="-" name="L2D_CACHE_LD" description="Level 2 data cache access - Read"/>
+    <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
     <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write -->
-    <event event="0x51" title="-" name="L2D_CACHE_ST" description="Level 2 data cache access - Write"/>
+    <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
     <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read -->
-    <event event="0x52" title="-" name="L2D_CACHE_REFILL_LD" description="Level 2 data cache refill - Read"/>
+    <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
     <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write -->
-    <event event="0x53" title="-" name="L2D_CACHE_REFILL_ST" description="Level 2 data cache refill - Write"/>
+    <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
     <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim -->
-    <event event="0x56" title="-" name="L2D_CACHE_WB_VICTIM" description="Level 2 data cache Write-back - Victim"/>
+    <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/>
     <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency -->
-    <event event="0x57" title="-" name="L2D_CACHE_WB_CLEAN" description="Level 2 data cache Write-back - Cleaning and coherency"/>
+    <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/>
     <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate -->
-    <event event="0x58" title="-" name="L2D_CACHE_INVAL" description="Level 2 data cache invalidate"/>
+    <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
     <!-- 0x60 BUS_ACCESS_LD - Bus access - Read -->
-    <event event="0x60" title="-" name="BUS_ACCESS_LD" description="Bus access - Read"/>
+    <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
     <!-- 0x61 BUS_ACCESS_ST - Bus access - Write -->
-    <event event="0x61" title="-" name="BUS_ACCESS_ST" description="Bus access - Write"/>
+    <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
     <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal -->
-    <event event="0x62" title="-" name="BUS_ACCESS_SHARED" description="Bus access - Normal"/>
+    <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/>
     <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal -->
-    <event event="0x63" title="-" name="BUS_ACCESS_NOT_SHARED" description="Bus access - Not normal"/>
+    <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/>
     <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal -->
-    <event event="0x64" title="-" name="BUS_ACCESS_NORMAL" description="Bus access - Normal"/>
+    <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
     <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral -->
-    <event event="0x65" title="-" name="BUS_ACCESS_PERIPH" description="Bus access - Peripheral"/>
+    <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
     <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read -->
-    <event event="0x66" title="-" name="MEM_ACCESS_LD" description="Data memory access - Read"/>
+    <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
     <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write -->
-    <event event="0x67" title="-" name="MEM_ACCESS_ST" description="Data memory access - Write"/>
+    <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
     <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read -->
-    <event event="0x68" title="-" name="UNALIGNED_LD_SPEC" description="Unaligned access - Read"/>
+    <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
     <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write -->
-    <event event="0x69" title="-" name="UNALIGNED_ST_SPEC" description="Unaligned access - Write"/>
+    <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
     <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access -->
-    <event event="0x6A" title="-" name="UNALIGNED_LDST_SPEC" description="Unaligned access"/>
+    <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/>
     <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX -->
-    <event event="0x6C" title="-" name="LDREX_SPEC" description="Exclusive operation speculatively executed - LDREX"/>
+    <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/>
     <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass -->
-    <event event="0x6D" title="-" name="STREX_PASS_SPEC" description="Exclusive instruction speculatively executed - STREX pass"/>
+    <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
     <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail -->
-    <event event="0x6E" title="-" name="STREX_FAIL_SPEC" description="Exclusive operation speculatively executed - STREX fail"/>
+    <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/>
     <!-- 0x70 LD_SPEC - Operation speculatively executed - Load -->
-    <event event="0x70" title="-" name="LD_SPEC" description="Operation speculatively executed - Load"/>
+    <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/>
     <!-- 0x71 ST_SPEC - Operation speculatively executed - Store -->
-    <event event="0x71" title="-" name="ST_SPEC" description="Operation speculatively executed - Store"/>
+    <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/>
     <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store -->
-    <event event="0x72" title="-" name="LDST_SPEC" description="Operation speculatively executed - Load or store"/>
+    <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/>
     <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing -->
-    <event event="0x73" title="-" name="DP_SPEC" description="Operation speculatively executed - Integer data processing"/>
+    <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/>
     <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD -->
-    <event event="0x74" title="-" name="ASE_SPEC" description="Operation speculatively executed - Advanced SIMD"/>
+    <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/>
     <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP -->
-    <event event="0x75" title="-" name="VFP_SPEC" description="Operation speculatively executed - VFP"/>
+    <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/>
     <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC -->
-    <event event="0x76" title="-" name="PC_WRITE_SPEC" description="Operation speculatively executed - Software change of the PC"/>
+    <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/>
     <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing -->
-    <event event="0x77" title="-" name="CRYPTO_SPEC" description="Operation speculatively executed, crypto data processing"/>
+    <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/>
     <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch -->
-    <event event="0x78" title="-" name="BR_IMMED_SPEC" description="Branch speculatively executed - Immediate branch"/>
+    <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
     <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return -->
-    <event event="0x79" title="-" name="BR_RETURN_SPEC" description="Branch speculatively executed - Procedure return"/>
+    <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
     <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch -->
-    <event event="0x7A" title="-" name="BR_INDIRECT_SPEC" description="Branch speculatively executed - Indirect branch"/>
+    <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
     <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB -->
-    <event event="0x7C" title="-" name="ISB_SPEC" description="Barrier speculatively executed - ISB"/>
+    <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
     <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB -->
-    <event event="0x7D" title="-" name="DSB_SPEC" description="Barrier speculatively executed - DSB"/>
+    <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
     <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB -->
-    <event event="0x7E" title="-" name="DMB_SPEC" description="Barrier speculatively executed - DMB"/>
+    <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
     <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous -->
-    <event event="0x81" title="-" name="EXC_UNDEF" description="Exception taken, other synchronous"/>
+    <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/>
     <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call -->
-    <event event="0x82" title="-" name="EXC_SVC" description="Exception taken, Supervisor Call"/>
+    <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/>
     <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort -->
-    <event event="0x83" title="-" name="EXC_PABORT" description="Exception taken, Instruction Abort"/>
+    <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/>
     <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError -->
-    <event event="0x84" title="-" name="EXC_DABORT" description="Exception taken, Data Abort or SError"/>
+    <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/>
     <!-- 0x86 EXC_IRQ - Exception taken, IRQ -->
-    <event event="0x86" title="-" name="EXC_IRQ" description="Exception taken, IRQ"/>
+    <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/>
     <!-- 0x87 EXC_FIQ - Exception taken, FIQ -->
-    <event event="0x87" title="-" name="EXC_FIQ" description="Exception taken, FIQ"/>
+    <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/>
     <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call -->
-    <event event="0x88" title="-" name="EXC_SMC" description="Exception taken, Secure Monitor Call"/>
+    <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/>
     <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call -->
-    <event event="0x8A" title="-" name="EXC_HVC" description="Exception taken, Hypervisor Call"/>
+    <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/>
     <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally -->
-    <event event="0x8B" title="-" name="EXC_TRAP_PABORT" description="Exception taken, Instruction Abort not taken locally"/>
+    <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/>
     <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally -->
-    <event event="0x8C" title="-" name="EXC_TRAP_DABORT" description="Exception taken, Data Abort or SError not taken locally"/>
-    <!-- 0x8D EXC_TRAP_OTHER - Exception taken  Other traps not taken locally -->
-    <event event="0x8D" title="-" name="EXC_TRAP_OTHER" description="Exception taken – Other traps not taken locally"/>
+    <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/>
+    <!-- 0x8D EXC_TRAP_OTHER - Exception taken - Other traps not taken locally -->
+    <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/>
     <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally -->
-    <event event="0x8E" title="-" name="EXC_TRAP_IRQ" description="Exception taken, IRQ not taken locally"/>
+    <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/>
     <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally -->
-    <event event="0x8F" title="-" name="EXC_TRAP_FIQ" description="Exception taken, FIQ not taken locally"/>
-    <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed  Load Acquire -->
-    <event event="0x90" title="-" name="RC_LD_SPEC" description="Release consistency instruction speculatively executed – Load Acquire"/>
-    <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed  Store Release -->
-    <event event="0x91" title="-" name="RC_ST_SPEC" description="Release consistency instruction speculatively executed – Store Release"/>
+    <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/>
+    <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed - Load Acquire -->
+    <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/>
+    <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed - Store Release -->
+    <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/>
   </category>
index bbd7a26251596eef4b58c36b85f49db9a2f0e060..54d7264bc08e49b93bfbf97057cdbffc5c970cb5 100644 (file)
@@ -1,6 +1,6 @@
   <counter_set name="ARM_Cortex-A7_cnt" count="4"/>
   <category name="Cortex-A7" counter_set="ARM_Cortex-A7_cnt" per_cpu="yes" supports_event_based_sampling="yes">
-    <event counter="ARM_Cortex-A7_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+    <event counter="ARM_Cortex-A7_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
     <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>
     <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
     <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
index a301f1f21cc8960c4e93c6a05970d92c2d8d815e..f2518237983af904a8eeaab18cec9001f8001966 100644 (file)
@@ -1,6 +1,6 @@
   <counter_set name="ARM_Cortex-A8_cnt" count="4"/>
   <category name="Cortex-A8" counter_set="ARM_Cortex-A8_cnt" per_cpu="yes" supports_event_based_sampling="yes">
-    <event counter="ARM_Cortex-A8_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+    <event counter="ARM_Cortex-A8_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
     <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
     <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
     <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
@@ -22,7 +22,7 @@
     <event event="0x40" title="Cache" name="Write buffer full" description="Any write buffer full cycle"/>
     <event event="0x41" title="Cache" name="L2 store" description="Any store that is merged in the L2 memory system"/>
     <event event="0x42" title="Cache" name="Bufferable transaction" description="Any bufferable store transaction from load/store to L2 cache, excluding eviction or cast out data"/>
-    <event event="0x43" title="Cache" name="L1 miss" description="Any accesses to the L2 cache"/>
+    <event event="0x43" title="Cache" name="L2 access" description="Any accesses to the L2 cache"/>
     <event event="0x44" title="Cache" name="L2 miss" description="Any cacheable miss in the L2 cache"/>
     <event event="0x45" title="AXI" name="Read" description="The number of AXI read data transfers"/>
     <event event="0x46" title="AXI" name="Write" description="The number of AXI write data transfers"/>
index 9ebb3088094f2d2a8bd3b8077b4b062c495c9b05..75f09c80425e5f431fd7e8608777ea0a5bf8be4f 100644 (file)
@@ -1,6 +1,6 @@
   <counter_set name="ARM_Cortex-A9_cnt" count="6"/>
   <category name="Cortex-A9" counter_set="ARM_Cortex-A9_cnt" per_cpu="yes" supports_event_based_sampling="yes">
-    <event counter="ARM_Cortex-A9_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+    <event counter="ARM_Cortex-A9_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
     <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
     <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
     <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
index 4254666f794ec78183f929845132b3da6dc5ea90..b8d3bcb48de73827abcb5f10e446790d98bb8858 100644 (file)
@@ -1,6 +1,6 @@
   <counter_set name="Krait_cnt" count="4"/>
   <category name="Krait" counter_set="Krait_cnt" per_cpu="yes" supports_event_based_sampling="yes">
-    <event counter="Krait_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+    <event counter="Krait_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
     <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
     <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
     <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
index 42baf143886638eb60262a75aebbede1df845f17..05dc613a88a8ac9f7f94b92c0276661166b64b47 100644 (file)
@@ -9,7 +9,9 @@
     <event counter="Linux_meminfo_memused" title="Memory" name="Used" display="maximum" units="B" average_selection="yes" description="Total used memory size"/>
     <event counter="Linux_meminfo_memfree" title="Memory" name="Free" display="minimum" units="B" average_selection="yes" description="Available memory size"/>
     <event counter="Linux_meminfo_bufferram" title="Memory" name="Buffer" display="maximum" units="B" average_selection="yes" description="Memory used by OS disk buffers"/>
-    <event counter="Linux_power_cpu_freq" title="Clock" name="Frequency" per_cpu="yes" display="maximum" units="Hz" average_selection="yes" description="Frequency setting of the CPU"/>
-    <event counter="Linux_power_cpu_idle" title="Power" name="Idle" per_cpu="yes" display="maximum" average_selection="yes" description="CPU Idle State + 1, set the Sample Rate to None to prevent the hrtimer from interrupting the system"/>
+    <event counter="Linux_power_cpu_freq" title="Clock" name="Frequency" per_cpu="yes" display="maximum" units="Hz" series_composition="overlay" average_selection="yes" average_cores="yes" description="Frequency setting of the CPU"/>
+    <event counter="Linux_power_cpu_idle" title="Idle" name="State" per_cpu="yes" display="maximum" average_selection="yes" description="CPU Idle State + 1, set the Sample Rate to None to prevent the hrtimer from interrupting the system"/>
+    <event counter="Linux_cpu_wait_contention" title="CPU Contention" name="Wait" per_cpu="no" display="maximum" derived="yes" rendering_type="bar" average_selection="yes" percentage="yes" modifier="10000" description="Thread waiting on contended resource"/>
+    <event counter="Linux_cpu_wait_io" title="CPU I/O" name="Wait" per_cpu="no" display="maximum" derived="yes" rendering_type="bar" average_selection="yes" percentage="yes" modifier="10000" description="Thread waiting on I/O resource"/>
   </category>
 
index 3d795decaa9d36ec3a8681fe511b837217f73e8b..647e3d5b0fcf874e74c8e2b458ae71626952612c 100644 (file)
@@ -4,30 +4,30 @@
   </category>
 
   <category name="Mali-T6xx-PMShader" per_cpu="no">
-    <event counter="ARM_Mali-T6xx_PM_SHADER_0" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 0" description="Mali PM Shader: PM Shader Core 0."/>
-    <event counter="ARM_Mali-T6xx_PM_SHADER_1" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 1" description="Mali PM Shader: PM Shader Core 1."/>
-    <event counter="ARM_Mali-T6xx_PM_SHADER_2" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 2" description="Mali PM Shader: PM Shader Core 2."/>
-    <event counter="ARM_Mali-T6xx_PM_SHADER_3" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 3" description="Mali PM Shader: PM Shader Core 3."/>
-    <event counter="ARM_Mali-T6xx_PM_SHADER_4" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 4" description="Mali PM Shader: PM Shader Core 4."/>
-    <event counter="ARM_Mali-T6xx_PM_SHADER_5" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 5" description="Mali PM Shader: PM Shader Core 5."/>
-    <event counter="ARM_Mali-T6xx_PM_SHADER_6" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 6" description="Mali PM Shader: PM Shader Core 6."/>
-    <event counter="ARM_Mali-T6xx_PM_SHADER_7" display="average" average_selection="yes" units="%" title="Mali PM Shader" name="PM Shader Core 7" description="Mali PM Shader: PM Shader Core 7."/>
+    <event counter="ARM_Mali-T6xx_PM_SHADER_0" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 0" description="Mali PM Shader: PM Shader Core 0."/>
+    <event counter="ARM_Mali-T6xx_PM_SHADER_1" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 1" description="Mali PM Shader: PM Shader Core 1."/>
+    <event counter="ARM_Mali-T6xx_PM_SHADER_2" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 2" description="Mali PM Shader: PM Shader Core 2."/>
+    <event counter="ARM_Mali-T6xx_PM_SHADER_3" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 3" description="Mali PM Shader: PM Shader Core 3."/>
+    <event counter="ARM_Mali-T6xx_PM_SHADER_4" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 4" description="Mali PM Shader: PM Shader Core 4."/>
+    <event counter="ARM_Mali-T6xx_PM_SHADER_5" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 5" description="Mali PM Shader: PM Shader Core 5."/>
+    <event counter="ARM_Mali-T6xx_PM_SHADER_6" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 6" description="Mali PM Shader: PM Shader Core 6."/>
+    <event counter="ARM_Mali-T6xx_PM_SHADER_7" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 7" description="Mali PM Shader: PM Shader Core 7."/>
   </category>
 
   <category name="Mali-T6xx-PMTiler" per_cpu="no">
-    <event counter="ARM_Mali-T6xx_PM_TILER_0" display="average" average_selection="yes" units="%" title="Mali PM Tiler" name="PM Tiler Core 0" description="Mali PM Tiler: PM Tiler Core 0."/>
+    <event counter="ARM_Mali-T6xx_PM_TILER_0" display="average" average_selection="yes" percentage="yes" title="Mali PM Tiler" name="PM Tiler Core 0" description="Mali PM Tiler: PM Tiler Core 0."/>
   </category>
 
   <category name="Mali-T6xx-PML2" per_cpu="no">
-    <event counter="ARM_Mali-T6xx_PM_L2_0" display="average" average_selection="yes" units="%" title="Mali PM L2" name="PM L2 Core 0" description="Mali PM L2: PM L2 Core 0."/>
-    <event counter="ARM_Mali-T6xx_PM_L2_1" display="average" average_selection="yes" units="%" title="Mali PM L2" name="PM L2 Core 1" description="Mali PM L2: PM L2 Core 1."/>
+    <event counter="ARM_Mali-T6xx_PM_L2_0" display="average" average_selection="yes" percentage="yes" title="Mali PM L2" name="PM L2 Core 0" description="Mali PM L2: PM L2 Core 0."/>
+    <event counter="ARM_Mali-T6xx_PM_L2_1" display="average" average_selection="yes" percentage="yes" title="Mali PM L2" name="PM L2 Core 1" description="Mali PM L2: PM L2 Core 1."/>
   </category>
 
   <category name="Mali-T6xx-MMU_AS" per_cpu="no">
-    <event counter="ARM_Mali-T6xx_MMU_AS_0" display="average" average_selection="yes" units="%" title="Mali MMU Address Space" name="MMU Address Space 0" description="Mali MMU Address Space 0 usage."/>
-    <event counter="ARM_Mali-T6xx_MMU_AS_1" display="average" average_selection="yes" units="%" title="Mali MMU Address Space" name="MMU Address Space 1" description="Mali MMU Address Space 1 usage."/>
-    <event counter="ARM_Mali-T6xx_MMU_AS_2" display="average" average_selection="yes" units="%" title="Mali MMU Address Space" name="MMU Address Space 2" description="Mali MMU Address Space 2 usage."/>
-    <event counter="ARM_Mali-T6xx_MMU_AS_3" display="average" average_selection="yes" units="%" title="Mali MMU Address Space" name="MMU Address Space 3" description="Mali MMU Address Space 3 usage."/>
+    <event counter="ARM_Mali-T6xx_MMU_AS_0" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 0" description="Mali MMU Address Space 0 usage."/>
+    <event counter="ARM_Mali-T6xx_MMU_AS_1" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 1" description="Mali MMU Address Space 1 usage."/>
+    <event counter="ARM_Mali-T6xx_MMU_AS_2" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 2" description="Mali MMU Address Space 2 usage."/>
+    <event counter="ARM_Mali-T6xx_MMU_AS_3" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 3" description="Mali MMU Address Space 3 usage."/>
   </category>
 
   <category name="Mali-T6xx-MMU_page_fault" per_cpu="no">
index 7c7b1ea741ae898e74376dcb27bdcd491d1441b0..1fd9c4e59d817dd570698ea89e80a777edac52d1 100644 (file)
 
   <category name="Mali-T6xx-JobManager" per_cpu="no">
-    <event counter="ARM_Mali-T6xx_MESSAGES_SENT" title="Mali GPU Job Manager" name="Job Manager messages sent" description="Number of JCB messages sent by the Job Manager."/>
-    <event counter="ARM_Mali-T6xx_MESSAGES_RECEIVED" title="Mali GPU Job Manager" name="Job Manager messages received " description="Number of JCB messages received by the Job Manager."/>
-    <event counter="ARM_Mali-T6xx_GPU_ACTIVE" title="Mali GPU Job Manager" name="GPU active cycles" description="Number of cycles the GPU was active."/>
-    <event counter="ARM_Mali-T6xx_IRQ_ACTIVE" title="Mali GPU Job Manager" name="IRQ active cycles" description="Number of cycles with active interrupts."/>
 
-    <event counter="ARM_Mali-T6xx_JS0_JOBS" title="Mali GPU Job Manager" name="Job Slot 0 jobs complete" description="Number of jobs completed in Job Slot 0."/>
-    <event counter="ARM_Mali-T6xx_JS0_TASKS" title="Mali GPU Job Manager" name="Job Slot 0 tasks complete" description="Number of tasks completed in Job Slot 0."/>
-    <event counter="ARM_Mali-T6xx_JS0_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 0 active" description="Number of cycles Job Slot 0 was active."/>
-    <event counter="ARM_Mali-T6xx_JS0_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 0 wait read" description="Number of cycles Job Slot 0 stalled waiting for descriptors to be read."/>
-    <event counter="ARM_Mali-T6xx_JS0_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 0 wait issue" description="Number of cycles Job Slot 0 stalled unable to issue tasks because all available cores were full."/>
-    <event counter="ARM_Mali-T6xx_JS0_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 0 wait depend" description="Number of cycles Job Slot 0 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
-    <event counter="ARM_Mali-T6xx_JS0_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 0 wait finish" description="Number of cycles Job Slot 0 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
+    <event counter="ARM_Mali-T6xx_GPU_ACTIVE" title="Mali Job Manager Cycles" name="GPU cycles" description="Number of cycles the GPU was active"/>
+    <event counter="ARM_Mali-T6xx_IRQ_ACTIVE" title="Mali Job Manager Cycles" name="IRQ cycles" description="Number of cycles the GPU had a pending interrupt"/>
+    <event counter="ARM_Mali-T6xx_JS0_ACTIVE" title="Mali Job Manager Cycles" name="JS0 cycles" description="Number of cycles JS0 (fragment) was active"/>
+    <event counter="ARM_Mali-T6xx_JS1_ACTIVE" title="Mali Job Manager Cycles" name="JS1 cycles" description="Number of cycles JS1 (vertex/tiler/compute) was active"/>
+    <event counter="ARM_Mali-T6xx_JS2_ACTIVE" title="Mali Job Manager Cycles" name="JS2 cycles" description="Number of cycles JS2 (compute) was active"/>
 
-    <event counter="ARM_Mali-T6xx_JS1_JOBS" title="Mali GPU Job Manager" name="Job Slot 1 jobs complete" description="Number of jobs completed in Job Slot 1."/>
-    <event counter="ARM_Mali-T6xx_JS1_TASKS" title="Mali GPU Job Manager" name="Job Slot 1 tasks complete" description="Number of tasks completed in Job Slot 1."/>
-    <event counter="ARM_Mali-T6xx_JS1_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 1 active" description="Number of cycles Job Slot 1 was active."/>
-    <event counter="ARM_Mali-T6xx_JS1_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 1 wait read" description="Number of cycles Job Slot 1 stalled waiting for descriptors to be read."/>
-    <event counter="ARM_Mali-T6xx_JS1_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 1 wait issue" description="Number of cycles Job Slot 1 stalled unable to issue tasks because all available cores were full."/>
-    <event counter="ARM_Mali-T6xx_JS1_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 1 wait depend" description="Number of cycles Job Slot 1 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
-    <event counter="ARM_Mali-T6xx_JS1_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 1 wait finish" description="Number of cycles Job Slot 1 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
+    <event counter="ARM_Mali-T6xx_JS0_JOBS" title="Mali Job Manager Work" name="JS0 jobs" description="Number of Jobs (fragment) completed in JS0"/>
+    <event counter="ARM_Mali-T6xx_JS0_TASKS" title="Mali Job Manager Work" name="JS0 tasks" description="Number of Tasks completed in JS0"/>
+    <event counter="ARM_Mali-T6xx_JS1_JOBS" title="Mali Job Manager Work" name="JS1 jobs" description="Number of Jobs (vertex/tiler/compute) completed in JS1"/>
+    <event counter="ARM_Mali-T6xx_JS1_TASKS" title="Mali Job Manager Work" name="JS1 tasks" description="Number of Tasks completed in JS1"/>
+    <event counter="ARM_Mali-T6xx_JS2_TASKS" title="Mali Job Manager Work" name="JS2 tasks" description="Number of Tasks completed in JS2"/>
+    <event counter="ARM_Mali-T6xx_JS2_JOBS" title="Mali Job Manager Work" name="JS2 jobs" description="Number of Jobs (compute) completed in JS2"/>
 
-    <event counter="ARM_Mali-T6xx_JS2_JOBS" title="Mali GPU Job Manager" name="Job Slot 2 jobs complete" description="Number of jobs completed in Job Slot 2."/>
-    <event counter="ARM_Mali-T6xx_JS2_TASKS" title="Mali GPU Job Manager" name="Job Slot 2 tasks complete" description="Number of tasks completed in Job Slot 2."/>
-    <event counter="ARM_Mali-T6xx_JS2_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 2 active" description="Number of cycles Job Slot 2 was active."/>
-    <event counter="ARM_Mali-T6xx_JS2_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 2 wait read" description="Number of cycles Job Slot 2 stalled waiting for descriptors to be read."/>
-    <event counter="ARM_Mali-T6xx_JS2_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 2 wait issue" description="Number of cycles Job Slot 2 stalled unable to issue tasks because all available cores were full."/>
-    <event counter="ARM_Mali-T6xx_JS2_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 2 wait depend" description="Number of cycles Job Slot 2 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
-    <event counter="ARM_Mali-T6xx_JS2_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 2 wait finish" description="Number of cycles Job Slot 2 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
-<!--
-    <event counter="ARM_Mali-T6xx_JS3_JOBS" title="Mali GPU Job Manager" name="Job Slot 3 jobs complete" description="Number of jobs completed in Job Slot 3."/>
-    <event counter="ARM_Mali-T6xx_JS3_TASKS" title="Mali GPU Job Manager" name="Job Slot 3 tasks complete" description="Number of tasks completed in Job Slot 3."/>
-    <event counter="ARM_Mali-T6xx_JS3_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 3 active" description="Number of cycles Job Slot 3 was active."/>
-    <event counter="ARM_Mali-T6xx_JS3_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 3 wait read" description="Number of cycles Job Slot 3 stalled waiting for descriptors to be read."/>
-    <event counter="ARM_Mali-T6xx_JS3_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 3 wait issue" description="Number of cycles Job Slot 3 stalled unable to issue tasks because all available cores were full."/>
-    <event counter="ARM_Mali-T6xx_JS3_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 3 wait depend" description="Number of cycles Job Slot 3 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
-    <event counter="ARM_Mali-T6xx_JS3_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 3 wait finish" description="Number of cycles Job Slot 3 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
-
-    <event counter="ARM_Mali-T6xx_JS4_JOBS" title="Mali GPU Job Manager" name="Job Slot 4 jobs complete" description="Number of jobs completed in Job Slot 4."/>
-    <event counter="ARM_Mali-T6xx_JS4_TASKS" title="Mali GPU Job Manager" name="Job Slot 4 tasks complete" description="Number of tasks completed in Job Slot 4."/>
-    <event counter="ARM_Mali-T6xx_JS4_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 4 active" description="Number of cycles Job Slot 4 was active."/>
-    <event counter="ARM_Mali-T6xx_JS4_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 4 wait read" description="Number of cycles Job Slot 4 stalled waiting for descriptors to be read."/>
-    <event counter="ARM_Mali-T6xx_JS4_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 4 wait issue" description="Number of cycles Job Slot 4 stalled unable to issue tasks because all available cores were full."/>
-    <event counter="ARM_Mali-T6xx_JS4_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 4 wait depend" description="Number of cycles Job Slot 4 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
-    <event counter="ARM_Mali-T6xx_JS4_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 4 wait finish" description="Number of cycles Job Slot 4 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
-
-    <event counter="ARM_Mali-T6xx_JS5_JOBS" title="Mali GPU Job Manager" name="Job Slot 5 jobs complete" description="Number of jobs completed in Job Slot 5."/>
-    <event counter="ARM_Mali-T6xx_JS5_TASKS" title="Mali GPU Job Manager" name="Job Slot 5 tasks complete" description="Number of tasks completed in Job Slot 5."/>
-    <event counter="ARM_Mali-T6xx_JS5_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 5 active" description="Number of cycles Job Slot 5 was active."/>
-    <event counter="ARM_Mali-T6xx_JS5_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 5 wait read" description="Number of cycles Job Slot 5 stalled waiting for descriptors to be read."/>
-    <event counter="ARM_Mali-T6xx_JS5_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 5 wait issue" description="Number of cycles Job Slot 5 stalled unable to issue tasks because all available cores were full."/>
-    <event counter="ARM_Mali-T6xx_JS5_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 5 wait depend" description="Number of cycles Job Slot 5 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
-    <event counter="ARM_Mali-T6xx_JS5_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 5 wait finish" description="Number of cycles Job Slot 5 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
-
-    <event counter="ARM_Mali-T6xx_JS6_JOBS" title="Mali GPU Job Manager" name="Job Slot 6 jobs complete" description="Number of jobs completed in Job Slot 6."/>
-    <event counter="ARM_Mali-T6xx_JS6_TASKS" title="Mali GPU Job Manager" name="Job Slot 6 tasks complete" description="Number of tasks completed in Job Slot 6."/>
-    <event counter="ARM_Mali-T6xx_JS6_ACTIVE" title="Mali GPU Job Manager" name="Job Slot 6 active" description="Number of cycles Job Slot 6 was active."/>
-    <event counter="ARM_Mali-T6xx_JS6_WAIT_READ" title="Mali GPU Job Manager" name="Job Slot 6 wait read" description="Number of cycles Job Slot 6 stalled waiting for descriptors to be read."/>
-    <event counter="ARM_Mali-T6xx_JS6_WAIT_ISSUE" title="Mali GPU Job Manager" name="Job Slot 6 wait issue" description="Number of cycles Job Slot 6 stalled unable to issue tasks because all available cores were full."/>
-    <event counter="ARM_Mali-T6xx_JS6_WAIT_DEPEND" title="Mali GPU Job Manager" name="Job Slot 6 wait depend" description="Number of cycles Job Slot 6 stalled waiting for task dependencies, and the task could have been issued if not for the dependency."/>
-    <event counter="ARM_Mali-T6xx_JS6_WAIT_FINISH" title="Mali GPU Job Manager" name="Job Slot 6 wait finish" description="Number of cycles Job Slot 6 stalled after finishing the last job in the job chain, waiting for all active tasks to finish."/>
--->
   </category>
 
   <category name="Mali-T6xx-Tiler" per_cpu="no">
-<!--
-    <event counter="ARM_Mali-T6xx_JOBS_PROCESSED" title="Mali GPU Tiler" name="Jobs processed" description="Number of jobs processed."/>
--->
-    <event counter="ARM_Mali-T6xx_TRIANGLES" title="Mali GPU Tiler" name="Triangles processed" description="Number of triangles processed."/>
-    <event counter="ARM_Mali-T6xx_QUADS" title="Mali GPU Tiler" name="Quads processed" description="Number of quads processed."/>
-    <event counter="ARM_Mali-T6xx_POLYGONS" title="Mali GPU Tiler" name="Polygons processed" description="Number of polygons processed."/>
-    <event counter="ARM_Mali-T6xx_POINTS" title="Mali GPU Tiler" name="Points processed" description="Number of points processed."/>
-
-    <event counter="ARM_Mali-T6xx_LINES" title="Mali GPU Tiler" name="Lines processed" description="Number of lines processed."/>
-    <event counter="ARM_Mali-T6xx_VCACHE_HIT" title="Mali GPU Tiler" name="Vertex cache hits" description="Number of vertex cache hits."/>
-    <event counter="ARM_Mali-T6xx_VCACHE_MISS" title="Mali GPU Tiler" name="Vertex cache misses" description="Number of vertex cache misses."/>
-    <event counter="ARM_Mali-T6xx_FRONT_FACING" title="Mali GPU Tiler" name="Front facing primitives" description="Number of front facing primitives."/>
-
-    <event counter="ARM_Mali-T6xx_BACK_FACING" title="Mali GPU Tiler" name="Back facing primitives" description="Number of back facing primitives."/>
-    <event counter="ARM_Mali-T6xx_PRIM_VISIBLE" title="Mali GPU Tiler" name="Visible primitives" description="Number of visible primitives."/>
-    <event counter="ARM_Mali-T6xx_PRIM_CULLED" title="Mali GPU Tiler" name="Culled primitives" description="Number of culled primitives."/>
-    <event counter="ARM_Mali-T6xx_PRIM_CLIPPED" title="Mali GPU Tiler" name="Clipped primitives" description="Number of clipped primitives."/>
-
-    <event counter="ARM_Mali-T6xx_LEVEL0" title="Mali GPU Tiler" name="Level 0 primitives" description="Number of primitives tiled to hierarchy level 0."/>
-    <event counter="ARM_Mali-T6xx_LEVEL1" title="Mali GPU Tiler" name="Level 1 primitives" description="Number of primitives tiled to hierarchy level 1."/>
-    <event counter="ARM_Mali-T6xx_LEVEL2" title="Mali GPU Tiler" name="Level 2 primitives" description="Number of primitives tiled to hierarchy level 2."/>
-    <event counter="ARM_Mali-T6xx_LEVEL3" title="Mali GPU Tiler" name="Level 3 primitives" description="Number of primitives tiled to hierarchy level 3."/>
-
-    <event counter="ARM_Mali-T6xx_LEVEL4" title="Mali GPU Tiler" name="Level 4 primitives" description="Number of primitives tiled to hierarchy level 4."/>
-    <event counter="ARM_Mali-T6xx_LEVEL5" title="Mali GPU Tiler" name="Level 5 primitives" description="Number of primitives tiled to hierarchy level 5."/>
-    <event counter="ARM_Mali-T6xx_LEVEL6" title="Mali GPU Tiler" name="Level 6 primitives" description="Number of primitives tiled to hierarchy level 6."/>
-    <event counter="ARM_Mali-T6xx_LEVEL7" title="Mali GPU Tiler" name="Level 7 primitives" description="Number of primitives tiled to hierarchy level 7."/>
-
-    <event counter="ARM_Mali-T6xx_COMMAND_1" title="Mali GPU Tiler" name="Primitives tiled to 1 command" description="Number of primitives producing 1 command in tile list."/>
-    <event counter="ARM_Mali-T6xx_COMMAND_2" title="Mali GPU Tiler" name="Primitives tiled to 2 commands" description="Number of primitives producing 2 commands in tile list."/>
-    <event counter="ARM_Mali-T6xx_COMMAND_3" title="Mali GPU Tiler" name="Primitives tiled to 3 commands" description="Number of primitives producing 3 commands in tile list."/>
-    <event counter="ARM_Mali-T6xx_COMMAND_4" title="Mali GPU Tiler" name="Primitives tiled to 4 commands" description="Number of primitives producing 4 commands in tile list."/>
-
-    <event counter="ARM_Mali-T6xx_COMMAND_4_7" title="Mali GPU Tiler" name="Primitives tiled to 4-7 commands" description="Number of primitives producing 4-7 commands in tile list."/>
-    <event counter="ARM_Mali-T6xx_COMMAND_8_15" title="Mali GPU Tiler" name="Primitives tiled to 8-15 commands" description="Number of primitives producing 8-15 commands in tile list."/>
-    <event counter="ARM_Mali-T6xx_COMMAND_16_63" title="Mali GPU Tiler" name="Primitives tiled to 16-63 commands" description="Number of primitives producing 16-63 commands in tile list."/>
-    <event counter="ARM_Mali-T6xx_COMMAND_64" title="Mali GPU Tiler" name="Primitives tiled to >= 64 commands" description="Number of primitives producing >= 64 commands in tile list."/>
-
-    <event counter="ARM_Mali-T6xx_COMPRESS_IN" title="Mali GPU Tiler" name="Commands entering compressor" description="Number of commands entering compressor."/>
-    <event counter="ARM_Mali-T6xx_COMPRESS_OUT" title="Mali GPU Tiler" name="Compressed commands from compressor" description="Number of compressed commands produced by compressor."/>
-    <event counter="ARM_Mali-T6xx_COMPRESS_FLUSH" title="Mali GPU Tiler" name="Compressor state flushes" description="Number of compressor state flushes."/>
-    <event counter="ARM_Mali-T6xx_TIMESTAMPS" title="Mali GPU Tiler" name="Timestamps emitted" description="Number of timestamps emitted."/>
 
-    <event counter="ARM_Mali-T6xx_PCACHE_HIT" title="Mali GPU Tiler" name="Pointer-cache hits" description="Number of pointer-cache hits."/>
-    <event counter="ARM_Mali-T6xx_PCACHE_MISS" title="Mali GPU Tiler" name="Pointer-cache misses" description="Number of pointer-cache misses."/>
-    <event counter="ARM_Mali-T6xx_PCACHE_LINE" title="Mali GPU Tiler" name="Pointer-cache line-fills" description="Number of pointer-cache line-fills."/>
-    <event counter="ARM_Mali-T6xx_PCACHE_STALL" title="Mali GPU Tiler" name="Pointer-cache stalls" description="Number of pointer-cache stalls."/>
+    <event counter="ARM_Mali-T6xx_POLYGONS" title="Mali Tiler Primitives" name="Polygons" description="Number of polygons processed"/>
+    <event counter="ARM_Mali-T6xx_QUADS" title="Mali Tiler Primitives" name="Quads" description="Number of quads processed"/>
+    <event counter="ARM_Mali-T6xx_TRIANGLES" title="Mali Tiler Primitives" name="Triangles" description="Number of triangles processed"/>
+    <event counter="ARM_Mali-T6xx_LINES" title="Mali Tiler Primitives" name="Lines" description="Number of lines processed"/>
+    <event counter="ARM_Mali-T6xx_POINTS" title="Mali Tiler Primitives" name="Points" description="Number of points processed"/>
+
+    <event counter="ARM_Mali-T6xx_FRONT_FACING" title="Mali Tiler Culling" name="Front facing prims" description="Number of front facing primitives"/>
+    <event counter="ARM_Mali-T6xx_BACK_FACING" title="Mali Tiler Culling" name="Back facing prims" description="Number of back facing primitives"/>
+    <event counter="ARM_Mali-T6xx_PRIM_VISIBLE" title="Mali Tiler Culling" name="Visible prims" description="Number of visible primitives"/>
+    <event counter="ARM_Mali-T6xx_PRIM_CULLED" title="Mali Tiler Culling" name="Culled prims" description="Number of culled primitives"/>
+    <event counter="ARM_Mali-T6xx_PRIM_CLIPPED" title="Mali Tiler Culling" name="Clipped prims" description="Number of clipped primitives"/>
+
+    <event counter="ARM_Mali-T6xx_LEVEL0" title="Mali Tiler Hierarchy" name="L0 prims" description="Number of primitives in hierarchy level 0"/>
+    <event counter="ARM_Mali-T6xx_LEVEL1" title="Mali Tiler Hierarchy" name="L1 prims" description="Number of primitives in hierarchy level 1"/>
+    <event counter="ARM_Mali-T6xx_LEVEL2" title="Mali Tiler Hierarchy" name="L2 prims" description="Number of primitives in hierarchy level 2"/>
+    <event counter="ARM_Mali-T6xx_LEVEL3" title="Mali Tiler Hierarchy" name="L3 prims" description="Number of primitives in hierarchy level 3"/>
+    <event counter="ARM_Mali-T6xx_LEVEL4" title="Mali Tiler Hierarchy" name="L4 prims" description="Number of primitives in hierarchy level 4"/>
+    <event counter="ARM_Mali-T6xx_LEVEL5" title="Mali Tiler Hierarchy" name="L5 prims" description="Number of primitives in hierarchy level 5"/>
+    <event counter="ARM_Mali-T6xx_LEVEL6" title="Mali Tiler Hierarchy" name="L6 prims" description="Number of primitives in hierarchy level 6"/>
+    <event counter="ARM_Mali-T6xx_LEVEL7" title="Mali Tiler Hierarchy" name="L7 prims" description="Number of primitives in hierarchy level 7"/>
+
+    <event counter="ARM_Mali-T6xx_COMMAND_1" title="Mali Tiler Commands" name="Prims in 1 command" description="Number of primitives producing 1 command"/>
+    <event counter="ARM_Mali-T6xx_COMMAND_2" title="Mali Tiler Commands" name="Prims in 2 command" description="Number of primitives producing 2 commands"/>
+    <event counter="ARM_Mali-T6xx_COMMAND_3" title="Mali Tiler Commands" name="Prims in 3 command" description="Number of primitives producing 3 commands"/>
+    <event counter="ARM_Mali-T6xx_COMMAND_4" title="Mali Tiler Commands" name="Prims in 4 command" description="Number of primitives producing 4 commands"/>
+    <event counter="ARM_Mali-T6xx_COMMAND_4_7" title="Mali Tiler Commands" name="Prims in 4-7 commands" description="Number of primitives producing 4-7 commands"/>
+    <event counter="ARM_Mali-T6xx_COMMAND_5_7" title="Mali Tiler Commands" name="Prims in 5-7 commands" description="Number of primitives producing 5-7 commands"/>
+    <event counter="ARM_Mali-T6xx_COMMAND_8_15" title="Mali Tiler Commands" name="Prims in 8-15 commands" description="Number of primitives producing 8-15 commands"/>
+    <event counter="ARM_Mali-T6xx_COMMAND_16_63" title="Mali Tiler Commands" name="Prims in 16-63 commands" description="Number of primitives producing 16-63 commands"/>
+    <event counter="ARM_Mali-T6xx_COMMAND_64" title="Mali Tiler Commands" name="Prims in &gt;= 64 commands" description="Number of primitives producing &gt;= 64 commands"/>
 
-    <event counter="ARM_Mali-T6xx_WRBUF_HIT" title="Mali GPU Tiler" name="Write-buffer hits" description="Number of write-buffer hits."/>
-    <event counter="ARM_Mali-T6xx_WRBUF_MISS" title="Mali GPU Tiler" name="Write-buffer misses" description="Number of write-buffer misses."/>
-    <event counter="ARM_Mali-T6xx_WRBUF_LINE" title="Mali GPU Tiler" name="Write-buffer full-lines written out" description="Number of complete cache lines written out from the write buffer."/>
-    <event counter="ARM_Mali-T6xx_WRBUF_PARTIAL" title="Mali GPU Tiler" name="Write-buffer partial-lines written out" description="Number of incomplete cache lines written out from the write buffer."/>
-
-    <event counter="ARM_Mali-T6xx_WRBUF_STALL" title="Mali GPU Tiler" name="Write-buffer stalls" description="Number of write-buffer stalls."/>
-    <event counter="ARM_Mali-T6xx_ACTIVE" title="Mali GPU Tiler" name="Tiler active cycles" description="Number of cycles the tiler is active."/>
-    <event counter="ARM_Mali-T6xx_LOADING_DESC" title="Mali GPU Tiler" name="Cycles loading descriptors" description="Number of cycle spent loading descriptors while the tiler frontend is otherwise idle."/>
-    <event counter="ARM_Mali-T6xx_INDEX_WAIT" title="Mali GPU Tiler" name="Cycles index fetch miss" description="Number of cycles the vertex cache could accept an index, but due to a miss, the index fetcher could not provide one."/>
-
-    <event counter="ARM_Mali-T6xx_INDEX_RANGE_WAIT" title="Mali GPU Tiler" name="Cycles index out of range" description="Number of cycles the index fetcher provides an index, but the index is outside the range of currently shaded vertices. Only relevant for fused jobs."/>
-    <event counter="ARM_Mali-T6xx_VERTEX_WAIT" title="Mali GPU Tiler" name="Cycles vertex cache miss" description="Number of cycles the primitive assembly could accept a vertex, but due to a vertex cache miss, the vertex fetcher is unable to provide a vertex."/>
-    <event counter="ARM_Mali-T6xx_PCACHE_WAIT" title="Mali GPU Tiler" name="Cycles pointer cache miss" description="Number of cycles the command compressor could accept a command, but due to a cache miss, the pointer cache is unable to provide the polygon list pointer."/>
-    <event counter="ARM_Mali-T6xx_WRBUF_WAIT" title="Mali GPU Tiler" name="Cycles no write buffer entry" description="Number of cycles a command could be written to the write buffer, but no write buffer entry is available."/>
-
-    <event counter="ARM_Mali-T6xx_BUS_READ" title="Mali GPU Tiler" name="Data beats from L2 cache read." description="Number of data beats (64-bit) on read from the L2 cache."/>
-    <event counter="ARM_Mali-T6xx_BUS_WRITE" title="Mali GPU Tiler" name="Data beats from L2 cache write" description="Number of data beats (64-bit) on written to the L2 cache."/>
-
-    <event counter="ARM_Mali-T6xx_UTLB_STALL" title="Mali GPU Tiler" name="uTLB cycles stall" description="uTLB: Cycles with stall on input AXI address channel."/>
-
-    <event counter="ARM_Mali-T6xx_UTLB_REPLAY_MISS" title="Mali GPU Tiler" name="uTLB replay buffer cache misses" description="uTLB: Number of cache misses on accesses from replay buffer."/>
-    <event counter="ARM_Mali-T6xx_UTLB_REPLAY_FULL" title="Mali GPU Tiler" name="uTLB cycle reply buffer full" description="uTLB: Number of cycles replay buffer is full."/>
-    <event counter="ARM_Mali-T6xx_UTLB_NEW_MISS" title="Mali GPU Tiler" name="uTLB cache misses on new request" description="uTLB: Number of cache misses on new requests."/>
-    <event counter="ARM_Mali-T6xx_UTLB_HIT" title="Mali GPU Tiler" name="uTLB cache hits" description="uTLB: Number of cache hits."/>
   </category>
 
   <category name="Mali-T6xx-ShaderCore" per_cpu="no">
-<!--
-    <event counter="ARM_Mali-T6xx_SHADER_CORE_ACTIVE" title="Mali GPU Shader Core" name="Shader core active cycles" description="Number of cycles the shader core active."/>
--->
-    <event counter="ARM_Mali-T6xx_FRAG_ACTIVE" title="Fragment" name="Fragment active cycles" description="Number of cycles fragment processing was active."/>
-    <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES" title="Fragment" name="Primitives" description="Number of primitives."/>
-    <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES_DROPPED" title="Fragment" name="Primitives dropped" description="Primitives dropped due to Polygon List Reader coverage."/>
-    <event counter="ARM_Mali-T6xx_FRAG_CYCLE_DESC" title="Fragment" name="Stall: Waiting for descriptors" description="Number of cycles spent waiting for descriptors / 2."/>
-
-    <event counter="ARM_Mali-T6xx_FRAG_CYCLES_PLR" title="Fragment" name="Stall: Waiting for PLR" description="Cycles spent waiting for Polygon List Reader."/>
-    <event counter="ARM_Mali-T6xx_FRAG_CYCLES_VERT" title="Fragment" name="Stall: Waiting for vertices" description="Cycles spent waiting for vertices."/>
-    <event counter="ARM_Mali-T6xx_FRAG_CYCLES_TRISETUP" title="Fragment" name="Stall: Waiting for trisetup" description="Cycles spent waiting for trisetup."/>
-    <event counter="ARM_Mali-T6xx_FRAG_CYCLES_RAST" title="Fragment" name="Stall: Waiting for rasterizer" description="Cycles spent waiting for rasterizer."/>
-
-    <event counter="ARM_Mali-T6xx_FRAG_THREADS" title="Fragment" name="Fragment threads started" description="Number of fragment threads started."/>
-    <event counter="ARM_Mali-T6xx_FRAG_DUMMY_THREADS" title="Fragment" name="Dummy threads started" description="Number of dummy threads started."/>
-    <event counter="ARM_Mali-T6xx_FRAG_QUADS_RAST" title="Fragment" name="Quads rasterized" description="Number of quads rasterized."/>
-    <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_TEST" title="Fragment" name="Quads doing early ZS test" description="Number of quads doing early ZS test."/>
-
-    <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_KILLED" title="Fragment" name="Quads killed early ZS test" description="Number of quads killed in early ZS test."/>
-    <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_TEST" title="Fragment" name="Threads doing late ZS test" description="Number of threads doing in late ZS test."/>
-    <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_KILLED" title="Fragment" name="Threads killed late ZS test" description="Number of threads killed in late ZS test."/>
-    <event counter="ARM_Mali-T6xx_FRAG_CYCLE_NO_TILE" title="Fragment" name="cycles waiting for physical tile buffers" description="Number of cycles spent waiting while no physical tile buffers were available for rendering."/>
-
-    <event counter="ARM_Mali-T6xx_FRAG_NUM_TILES" title="Fragment" name="Tiles rendered" description="Number of tiles rendered."/>
-    <event counter="ARM_Mali-T6xx_FRAG_TRANS_ELIM" title="Fragment" name="Transaction elimination signature matches" description="Transaction elimination signature matches."/>
-    <event counter="ARM_Mali-T6xx_COMPUTE_ACTIVE" title="Compute" name="Compute active cycles" description="Number of cycles compute processing was active."/>
-    <event counter="ARM_Mali-T6xx_COMPUTE_TASKS" title="Compute" name="Tasks" description="Number of tasks."/>
 
-    <event counter="ARM_Mali-T6xx_COMPUTE_THREADS" title="Compute" name="Compute threads started" description="Number of compute threads started."/>
-    <event counter="ARM_Mali-T6xx_COMPUTE_CYCLES_DESC" title="Compute" name="Stall: Waiting for descriptors" description="Number of cycles spent waiting for descriptors."/>
-    <event counter="ARM_Mali-T6xx_TRIPIPE_ACTIVE" title="Tripipe" name="Tripipe active cycles" description="Number of cycles the Tripipe was active."/>
-    <event counter="ARM_Mali-T6xx_ARITH_WORDS" title="Arithmetic Pipeline" name="Instructions per pipe" description="Number of instruction words in the arithmetic pipelines, divided by the number of arithmetic pipelines."/>
+    <event counter="ARM_Mali-T6xx_TRIPIPE_ACTIVE" title="Mali Core Cycles" name="Tripipe cycles" description="Number of cycles the Tripipe was active"/>
+    <event counter="ARM_Mali-T6xx_FRAG_ACTIVE" title="Mali Core Cycles" name="Fragment cycles" description="Number of cycles fragment processing was active"/>
+    <event counter="ARM_Mali-T6xx_COMPUTE_ACTIVE" title="Mali Core Cycles" name="Compute cycles" description="Number of cycles vertex\compute processing was active"/>
+    <event counter="ARM_Mali-T6xx_FRAG_CYCLE_NO_TILE" title="Mali Core Cycles" name="Fragment cycles waiting for tile" description="Number of cycles spent waiting for a physical tile buffer"/>
+
+    <event counter="ARM_Mali-T6xx_FRAG_THREADS" title="Mali Core Threads" name="Fragment threads" description="Number of fragment threads started"/>
+    <event counter="ARM_Mali-T6xx_FRAG_DUMMY_THREADS" title="Mali Core Threads" name="Dummy fragment threads" description="Number of dummy fragment threads started"/>
+    <event counter="ARM_Mali-T6xx_COMPUTE_THREADS" title="Mali Core Threads" name="Compute threads" description="Number of vertex\compute threads started"/>
+    <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_TEST" title="Mali Core Threads" name="Frag threads doing late ZS" description="Number of threads doing late ZS test"/>
+    <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_KILLED" title="Mali Core Threads" name="Frag threads killed late ZS" description="Number of threads killed by late ZS test"/>
+    <event counter="ARM_Mali-T6xx_FRAG_THREADS_LZS_TEST" title="Mali Core Threads" name="Frag threads doing late ZS" description="Number of threads doing late ZS test"/>
+    <event counter="ARM_Mali-T6xx_FRAG_THREADS_LZS_KILLED" title="Mali Core Threads" name="Frag threads killed late ZS" description="Number of threads killed by late ZS test"/>
+
+    <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES" title="Mali Fragment Primitives" name="Primitives loaded" description="Number of primitives loaded from tiler"/>
+    <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES_DROPPED" title="Mali Fragment Primitives" name="Primitives dropped" description="Number of primitives dropped because out of tile"/>
+    <event counter="ARM_Mali-T6xx_FRAG_PRIMITIVES" title="Mali Fragment Primitives" name="Primitives loaded" description="Number of primitives loaded from tiler"/>
+    <event counter="ARM_Mali-T6xx_FRAG_PRIMITIVES_DROPPED" title="Mali Fragment Primitives" name="Primitives dropped" description="Number of primitives dropped because out of tile"/>
+
+    <event counter="ARM_Mali-T6xx_FRAG_QUADS_RAST" title="Mali Fragment Quads" name="Quads rasterized" description="Number of quads rasterized"/>
+    <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_TEST" title="Mali Fragment Quads" name="Quads doing early ZS" description="Number of quads doing early ZS test"/>
+    <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_KILLED" title="Mali Fragment Quads" name="Quads killed early Z" description="Number of quads killed by early ZS test"/>
+
+    <event counter="ARM_Mali-T6xx_FRAG_NUM_TILES" title="Mali Fragment Tasks" name="Tiles rendered" description="Number of tiles rendered"/>
+    <event counter="ARM_Mali-T6xx_FRAG_TRANS_ELIM" title="Mali Fragment Tasks" name="Tile writes killed by TE" description="Number of tile writes skipped by transaction elimination"/>
+
+    <event counter="ARM_Mali-T6xx_ARITH_WORDS" title="Mali Arithmetic Pipe" name="A instructions" description="Number of instructions completed by the the A-pipe (normalized per pipeline)"/>
+
+    <event counter="ARM_Mali-T6xx_LS_WORDS" title="Mali Load/Store Pipe" name="LS instructions" description="Number of instructions completed by the LS-pipe"/>
+    <event counter="ARM_Mali-T6xx_LS_ISSUES" title="Mali Load/Store Pipe" name="LS instruction issues" description="Number of instructions issued to the LS-pipe, including restarts"/>
+
+    <event counter="ARM_Mali-T6xx_TEX_WORDS" title="Mali Texture Pipe" name="T instructions" description="Number of instructions completed by the T-pipe"/>
+    <event counter="ARM_Mali-T6xx_TEX_THREADS" title="Mali Texture Pipe" name="T instruction issues" description="Number of instructions issused to the T-pipe, including restarts"/>
+    <event counter="ARM_Mali-T6xx_TEX_RECIRC_FMISS" title="Mali Texture Pipe" name="Cache misses" description="Number of instructions in the T-pipe, recirculated due to cache miss"/>
+
+    <event counter="ARM_Mali-T6xx_LSC_READ_HITS" title="Mali Load/Store Cache" name="Read hits" description="Number of read hits in the Load/Store cache"/>
+    <event counter="ARM_Mali-T6xx_LSC_READ_MISSES" title="Mali Load/Store Cache" name="Read misses" description="Number of read misses in the Load/Store cache"/>
+    <event counter="ARM_Mali-T6xx_LSC_WRITE_HITS" title="Mali Load/Store Cache" name="Write hits" description="Number of write hits in the Load/Store cache"/>
+    <event counter="ARM_Mali-T6xx_LSC_WRITE_MISSES" title="Mali Load/Store Cache" name="Write misses" description="Number of write misses in the Load/Store cache"/>
+    <event counter="ARM_Mali-T6xx_LSC_ATOMIC_HITS" title="Mali Load/Store Cache" name="Atomic hits" description="Number of atomic hits in the Load/Store cache"/>
+    <event counter="ARM_Mali-T6xx_LSC_ATOMIC_MISSES" title="Mali Load/Store Cache" name="Atomic misses" description="Number of atomic misses in the Load/Store cache"/>
+    <event counter="ARM_Mali-T6xx_LSC_LINE_FETCHES" title="Mali Load/Store Cache" name="Line fetches" description="Number of line fetches in the Load/Store cache"/>
+    <event counter="ARM_Mali-T6xx_LSC_DIRTY_LINE" title="Mali Load/Store Cache" name="Dirty line evictions" description="Number of dirty line evictions in the Load/Store cache"/>
+    <event counter="ARM_Mali-T6xx_LSC_SNOOPS" title="Mali Load/Store Cache" name="Snoops in to LSC" description="Number of coherent memory snoops in to the Load/Store cache"/>
 
-    <event counter="ARM_Mali-T6xx_ARITH_CYCLES_REG" title="Arithmetic Pipeline" name="Stall: Register scheduling" description="Number of cycles lost in the arithmetic pipelines due to register scheduling, divided by the number of arithmetic pipelines."/>
-    <event counter="ARM_Mali-T6xx_ARITH_CYCLES_L0" title="Arithmetic Pipeline" name="Stall: Icache miss per pipe" description="Number of cycles lost in the arithmetic pipelines due to L0 instruction cache misses, divided by the number of arithmetic pipelines."/>
-    <event counter="ARM_Mali-T6xx_ARITH_FRAG_DEPEND" title="Arithmetic Pipeline" name="Stall: Fragment dependency fails per pipe" description="Number of fragment dependency check failures in the arithmetic pipelines, divided by the number of arithmetic pipelines."/>
-    <event counter="ARM_Mali-T6xx_LS_WORDS" title="Load/Store Pipeline" name="Load/Store instruction words completed" description="Number of instruction words completed in the Load/Store pipeline."/>
-
-    <event counter="ARM_Mali-T6xx_LS_ISSUES" title="Load/Store Pipeline" name="Full pipeline issues" description="Number of full pipeline issues in the Load/Store pipeline."/>
-    <event counter="ARM_Mali-T6xx_LS_RESTARTS" title="Load/Store Pipeline" name="Stall: Unpairable instruction" description="Number of restarts due to unpairable instructions in the Load/Store pipeline."/>
-    <event counter="ARM_Mali-T6xx_LS_REISSUES_MISS" title="Load/Store Pipeline" name="Stall: Cache misses" description="Number of full pipe re-issues due to cache misses or TLB misses in the Load/Store pipeline."/>
-    <event counter="ARM_Mali-T6xx_LS_REISSUES_VD" title="Load/Store Pipeline" name="Stall: Varying misses" description="Number of full pipe re-issues due to varying data being unavailable in the Load/Store pipeline."/>
-
-    <event counter="ARM_Mali-T6xx_LS_REISSUE_ATTRIB_MISS" title="Load/Store Pipeline" name="Stall: Attribute cache misses" description="Number of full pipe re-issues due to attribute cache misses in the Load/Store pipeline."/>
-    <event counter="ARM_Mali-T6xx_LS_NO_WB" title="Load/Store Pipeline" name="Writeback not used, pause buffer used" description="Writeback not used, and something into pause buffer in the Load/Store pipeline."/>
-    <event counter="ARM_Mali-T6xx_TEX_WORDS" title="Texturing Pipeline" name="Texturing pipeline instruction words completed" description="Number of instruction words completed in the texturing pipeline."/>
-    <event counter="ARM_Mali-T6xx_TEX_BUBBLES" title="Texturing Pipeline" name="Stall: Waiting for barrier" description="Number of bubbles with threads waiting for barrier in the texturing pipeline."/>
-
-    <event counter="ARM_Mali-T6xx_TEX_WORDS_L0" title="Texturing Pipeline" name="Stall: Icache misses" description="Number of instruction words in the texturing pipeline restart loop 1 due to L0 instruction cache miss."/>
-    <event counter="ARM_Mali-T6xx_TEX_WORDS_DESC" title="Texturing Pipeline" name="Stall: Descriptor misses" description="Number of instruction words in the texturing pipeline restart loop 1 due to descriptor misses."/>
-    <event counter="ARM_Mali-T6xx_TEX_THREADS" title="Texturing Pipeline" name="Threads in loop 2" description="Number of threads in the texturing pipeline through loop 2 address calculation."/>
-    <event counter="ARM_Mali-T6xx_TEX_RECIRC_FMISS" title="Texturing Pipeline" name="Stall: Texture cache misses" description="Number of instructions in the texturing pipeline recirculated due to complete texture cache miss."/>
-
-    <event counter="ARM_Mali-T6xx_TEX_RECIRC_DESC" title="Texturing Pipeline" name="Stall: Surface Descriptor misses" description="Number of instructions in the texturing pipeline recirculated due to surface descriptor miss."/>
-    <event counter="ARM_Mali-T6xx_TEX_RECIRC_MULTI" title="Texturing Pipeline" name="Reissue: multipass" description="Number of instructions in the texturing pipeline recirculated due to multipass."/>
-    <event counter="ARM_Mali-T6xx_TEX_RECIRC_PMISS" title="Texturing Pipeline" name="Stall: Partial misses" description="Number of instructions in the texturing pipeline recirculated due to partial cache miss."/>
-    <event counter="ARM_Mali-T6xx_TEX_RECIRC_CONF" title="Texturing Pipeline" name="Stall: Bank conflict" description="Number of instructions in the texturing pipeline recirculated due to texture cache bank conflict."/>
-
-    <event counter="ARM_Mali-T6xx_LSC_READ_HITS" title="Load/Store Cache" name="Read hits" description="Number of read hits in the Load/Store Cache."/>
-    <event counter="ARM_Mali-T6xx_LSC_READ_MISSES" title="Load/Store Cache" name="Read misses" description="Number of read misses in the Load/Store Cache."/>
-    <event counter="ARM_Mali-T6xx_LSC_WRITE_HITS" title="Load/Store Cache" name="Write hits" description="Number of write hits in the Load/Store Cache."/>
-    <event counter="ARM_Mali-T6xx_LSC_WRITE_MISSES" title="Load/Store Cache" name="Write misses" description="Number of write misses in the Load/Store Cache."/>
-
-    <event counter="ARM_Mali-T6xx_LSC_ATOMIC_HITS" title="Load/Store Cache" name="Atomic hits" description="Number of atomic hits in the Load/Store Cache."/>
-    <event counter="ARM_Mali-T6xx_LSC_ATOMIC_MISSES" title="Load/Store Cache" name="Atomic misses" description="Number of atomic misses in the Load/Store Cache."/>
-    <event counter="ARM_Mali-T6xx_LSC_LINE_FETCHES" title="Load/Store Cache" name="Line fetches" description="Number of line fetches in the Load/Store Cache."/>
-    <event counter="ARM_Mali-T6xx_LSC_DIRTY_LINE" title="Load/Store Cache" name="Dirty line evictions" description="Number of dirty line evictions in the Load/Store Cache."/>
-
-    <event counter="ARM_Mali-T6xx_LSC_SNOOPS" title="Load/Store Cache" name="Snoops in LSC" description="Snoops in the Load/Store Cache."/>
-    <event counter="ARM_Mali-T6xx_AXI_TLB_STALL" title="AXI uTLB" name="Stall: TLB AXI address channel" description="AXI address channel stall generated."/>
-    <event counter="ARM_Mali-T6xx_AXI_TLB_MIESS" title="AXI uTLB" name="Stall: TLB Cache misses" description="New request cache miss."/>
-    <event counter="ARM_Mali-T6xx_AXI_TLB_TRANSACTION" title="AXI uTLB" name="AXI transactions" description="Number of AXI transactions."/>
-
-    <event counter="ARM_Mali-T6xx_LS_TLB_MISS" title="LS uTLB" name="Cache misses per interface" description="Number of cache misses / number of interfaces."/>
-    <event counter="ARM_Mali-T6xx_LS_TLB_HIT" title="LS uTLB" name="Cache hits per interface" description="Number of cache hits / number of interfaces."/>
-    <event counter="ARM_Mali-T6xx_AXI_BEATS_READ" title="AXI" name="Beats read" description="Number of beats read."/>
-    <event counter="ARM_Mali-T6xx_AXI_BEATS_WRITTEN" title="AXI" name="Beats written" description="Number of beats written."/>
   </category>
 
   <category name="Mali-T6xx-L2AndMMU" per_cpu="no">
-    <event counter="ARM_Mali-T6xx_MMU_TABLE_WALK" title="MMU" name="Page table walks" description="Number of page table walks started."/>
-    <event counter="ARM_Mali-T6xx_MMU_REPLAY_MISS" title="MMU" name="Cache misses from replay buffer" description="Number of cache misses on accesses from replay buffer."/>
-    <event counter="ARM_Mali-T6xx_MMU_REPLAY_FULL" title="MMU" name="MMU full replay buffer (cycles)" description="Number of cycles replay buffer is full."/>
-    <event counter="ARM_Mali-T6xx_MMU_NEW_MISS" title="MMU" name="Cache misses on new requests" description="Number of cache misses on new requests."/>
-
-    <event counter="ARM_Mali-T6xx_MMU_HIT" title="MMU" name="MMU cache hits" description="Number of cache hits."/>
-
-    <event counter="ARM_Mali-T6xx_UTLB_STALL" title="uTLB" name="Stall on input AXI (cycles)" description="Cycles with stall on input AXI address channel."/>
-    <event counter="ARM_Mali-T6xx_UTLB_REPLAY_MISS" title="uTLB" name="Cache misses from replay buffer" description="Number of cache misses on accesses from replay buffer."/>
-    <event counter="ARM_Mali-T6xx_UTLB_REPLAY_FULL" title="uTLB" name="uTLB full replay buffer (cycles)" description="Number of cycles replay buffer is full."/>
-    <event counter="ARM_Mali-T6xx_UTLB_NEW_MISS" title="uTLB" name="Cache misses on new requests" description="Number of cache misses on new requests."/>
-
-    <event counter="ARM_Mali-T6xx_UTLB_HIT" title="uTLB" name="uTLB cache hits" description="Number of cache hits."/>
-
-    <event counter="ARM_Mali-T6xx_L2_WRITE_BEATS" title="L2 Cache" name="External bus write beats" description="External bus write beats."/>
-    <event counter="ARM_Mali-T6xx_L2_READ_BEATS" title="L2 Cache" name="External bus read beats" description="External bus read beats."/>
-
-    <event counter="ARM_Mali-T6xx_L2_ANY_LOOKUP" title="L2 Cache" name="Transaction/snoop tag lookups" description="A transaction or a snoop response completes the tag lookup."/>
-    <event counter="ARM_Mali-T6xx_L2_READ_LOOKUP" title="L2 Cache" name="Read transaction tag lookups" description="Any read transaction completes the tag lookup."/>
-    <event counter="ARM_Mali-T6xx_L2_SREAD_LOOKUP" title="L2 Cache" name="Shareable read transaction tag lookups" description="Shareable read transaction tag lookup."/>
-    <event counter="ARM_Mali-T6xx_L2_READ_REPLAY" title="L2 Cache" name="Replayed read transactions" description="Any read transaction is replayed (not serialized)."/>
-
-    <event counter="ARM_Mali-T6xx_L2_READ_SNOOP" title="L2 Cache" name="Read transaction snoops" description="Read transaction issues a snoop."/>
-    <event counter="ARM_Mali-T6xx_L2_READ_HIT" title="L2 Cache" name="L2 Cache read hits" description="A read hits in the L2 Cache."/>
-    <event counter="ARM_Mali-T6xx_L2_CLEAN_MISS" title="L2 Cache" name="CleanUnique misses" description="A CleanUnique misses in the L2 Cache, line allocated without a linefill."/>
-    <event counter="ARM_Mali-T6xx_L2_WRITE_LOOKUP" title="L2 Cache" name="Write transaction tag lookups" description="Any write transaction completes the tag lookup."/>
-
-    <event counter="ARM_Mali-T6xx_L2_SWRITE_LOOKUP" title="L2 write" name="Shareable write transaction tag lookup" description="Shareable write transaction tag lookup."/>
-    <event counter="ARM_Mali-T6xx_L2_WRITE_REPLAY" title="L2 write" name="Replayed write transaction" description="Any write transaction is replayed (not serialized)."/>
-    <event counter="ARM_Mali-T6xx_L2_WRITE_SNOOP" title="L2 write" name="Write transaction snoops" description="Write transaction issues a snoop."/>
-    <event counter="ARM_Mali-T6xx_L2_WRITE_HIT" title="L2 write" name="L2 write hits" description="A write hits in the L2 Cache."/>
-
-    <event counter="ARM_Mali-T6xx_L2_EXT_READ_FULL" title="L2 Cache" name="External read attempted with full BIU" description="External read attempted, but the BIU read buffer is full."/>
-    <event counter="ARM_Mali-T6xx_L2_EXT_READ_HALF" title="L2 Cache" name="External read requested with more then half full BIU" description="External read requested when the BIU read buffer is more than half full."/>
-    <event counter="ARM_Mali-T6xx_L2_EXT_WRITE_FULL" title="L2 Cache" name="External write attempted with full BIU" description="External write attempted, but the BIU write buffer is full."/>
-    <event counter="ARM_Mali-T6xx_L2_EXT_WRITE_HALF" title="L2 Cache" name="External write requested with more then half full BIU" description="External write requested when the BIU write buffer is more than half full."/>
-
-    <event counter="ARM_Mali-T6xx_L2_EXT_READ" title="L2 Cache" name="External read" description="External read."/>
-    <event counter="ARM_Mali-T6xx_L2_EXT_READ_LINE" title="L2 Cache" name="External read - linefill" description="External read - linefill."/>
-    <event counter="ARM_Mali-T6xx_L2_EXT_WRITE" title="L2 Cache" name="External write." description="External write."/>
-    <event counter="ARM_Mali-T6xx_L2_EXT_WRITE_LINE" title="L2 Cache" name="External write - writeback." description="External write - writeback."/>
-
-    <event counter="ARM_Mali-T6xx_L2_EXT_WRITE_SMALL" title="L2 Cache" name="External write - burst size less than 64B" description="External write - burst size less than 64B."/>
-    <event counter="ARM_Mali-T6xx_L2_EXT_BARRIER" title="L2 Cache" name="External barrier" description="External barrier (even if disabled)."/>
-    <event counter="ARM_Mali-T6xx_L2_EXT_AR_STALL" title="L2 Cache" name="External interconnect stalls (AR)" description="A valid read address (AR) is stalled by the external interconnect."/>
-    <event counter="ARM_Mali-T6xx_L2_EXT_R_BUF_FULL" title="L2 Cache" name="External read stalls (full buffer)" description="External read stalled due to the response buffer being full."/>
 
-    <event counter="ARM_Mali-T6xx_L2_EXT_RD_BUF_FULL" title="L2 Cache" name="External read not allocated" description="External read could not allocate an entry in the read data buffer."/>
-    <event counter="ARM_Mali-T6xx_L2_EXT_R_RAW" title="L2 Cache" name="External read stalled (RAW)" description="External read stalled due to the RAW hazard."/>
-    <event counter="ARM_Mali-T6xx_L2_EXT_W_STALL" title="L2 Cache" name="External interconnect stalls (W channel)" description="Valid write data (W channel) is stalled by the external interconnect."/>
-    <event counter="ARM_Mali-T6xx_L2_EXT_W_BUF_FULL" title="L2 Cache" name="External write stalls (full buffer)" description="External write stalled due to the response buffer being full."/>
+    <event counter="ARM_Mali-T6xx_L2_WRITE_BEATS" title="Mali L2 Cache" name="External write beats" description="Number of external bus write beats"/>
+    <event counter="ARM_Mali-T6xx_L2_READ_BEATS" title="Mali L2 Cache" name="External read beats" description="Number of external bus read beats"/>
+    <event counter="ARM_Mali-T6xx_L2_READ_SNOOP" title="Mali L2 Cache" name="Read snoops" description="Number of read transaction snoops"/>
+    <event counter="ARM_Mali-T6xx_L2_READ_HIT" title="Mali L2 Cache" name="L2 read hits" description="Number of reads hitting in the L2 cache"/>
+    <event counter="ARM_Mali-T6xx_L2_WRITE_SNOOP" title="Mali L2 Cache" name="Write snoops" description="Number of write transaction snoops"/>
+    <event counter="ARM_Mali-T6xx_L2_WRITE_HIT" title="Mali L2 Cache" name="L2 write hits" description="Number of writes hitting in the L2 cache"/>
+    <event counter="ARM_Mali-T6xx_L2_EXT_AR_STALL" title="Mali L2 Cache" name="External bus stalls (AR)" description="Number of cycles a valid read address (AR) is stalled by the external interconnect"/>
+    <event counter="ARM_Mali-T6xx_L2_EXT_W_STALL" title="Mali L2 Cache" name="External bus stalls (W)" description="Number of cycles a valid write data (W channel) is stalled by the external interconnect"/>
 
-    <event counter="ARM_Mali-T6xx_L2_EXT_R_W_HAZARD" title="L2 Cache" name="External read stalled (WAW or WAR)" description="External read stalled due to the WAW or WAR hazard."/>
-    <event counter="ARM_Mali-T6xx_L2_TAG_HAZARD" title="L2 Cache" name="Replayed transactions due to tag hazard" description="A transaction will be replayed due to a tag hazard."/>
-    <event counter="ARM_Mali-T6xx_L2_SNOOP_FULL" title="L2 Cache" name="Cycles with full snoop buffer" description="Counts every cycle when the snoop buffer is full."/>
-    <event counter="ARM_Mali-T6xx_L2_REPLAY_FULL" title="L2 Cache" name="Cycles with full replay buffer" description="Counts every cycle when the replay buffer is full."/>
   </category>
index d08a5a239974a5dbc64f1c748d1b32cef0183610..fa716fdc4840920c4621f8141667728386658bc8 100644 (file)
@@ -1,6 +1,6 @@
   <counter_set name="Scorpion_cnt" count="4"/>
   <category name="Scorpion" counter_set="Scorpion_cnt" per_cpu="yes" supports_event_based_sampling="yes">
-    <event counter="Scorpion_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+    <event counter="Scorpion_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
     <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
     <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
     <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
index dad4c70ed4e12b3f196a09c069f380a01d21e840..c648ccefb287cdcfb76ebee15d6a4670702ebdbd 100644 (file)
@@ -1,6 +1,6 @@
   <counter_set name="ScorpionMP_cnt" count="4"/>
   <category name="ScorpionMP" counter_set="ScorpionMP_cnt" per_cpu="yes" supports_event_based_sampling="yes">
-    <event counter="ScorpionMP_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
+    <event counter="ScorpionMP_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
     <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
     <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
     <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
index 94f01e6790e74bd1d946c1fe7675a103434ca782..0670d6cea9bdf5cf4eebeb94ac1d47978a0e0cdc 100644 (file)
 /*
  * EABI backtrace stores {fp,lr} on the stack.
  */
-struct frame_tail_eabi {
+struct stack_frame_eabi {
        union {
                struct {
-                       unsigned long fp;       // points to prev_lr
+                       unsigned long fp;
+                       // May be the fp in the case of a leaf function or clang
                        unsigned long lr;
+                       // If lr is really the fp, lr2 is the corresponding lr
+                       unsigned long lr2;
                };
                // Used to read 32 bit fp/lr from a 64 bit kernel
                struct {
                        u32 fp_32;
+                       // same as lr above
                        u32 lr_32;
+                       // same as lr2 above
+                       u32 lr2_32;
                };
        };
 };
@@ -27,61 +33,76 @@ struct frame_tail_eabi {
 static void arm_backtrace_eabi(int cpu, struct pt_regs *const regs, unsigned int depth)
 {
 #if defined(__arm__) || defined(__aarch64__)
-       struct frame_tail_eabi *tail;
-       struct frame_tail_eabi *next;
-       struct frame_tail_eabi buftail;
+       struct stack_frame_eabi *curr;
+       struct stack_frame_eabi bufcurr;
 #if defined(__arm__)
        const bool is_compat = false;
        unsigned long fp = regs->ARM_fp;
        unsigned long sp = regs->ARM_sp;
        unsigned long lr = regs->ARM_lr;
-       const int frame_offset = 4;
+       const int gcc_frame_offset = sizeof(unsigned long);
 #else
        // Is userspace aarch32 (32 bit)
        const bool is_compat = compat_user_mode(regs);
        unsigned long fp = (is_compat ? regs->regs[11] : regs->regs[29]);
        unsigned long sp = (is_compat ? regs->compat_sp : regs->sp);
        unsigned long lr = (is_compat ? regs->compat_lr : regs->regs[30]);
-       const int frame_offset = (is_compat ? 4 : 0);
+       const int gcc_frame_offset = (is_compat ? sizeof(u32) : 0);
 #endif
+       // clang frame offset is always zero
        int is_user_mode = user_mode(regs);
 
+       // pc (current function) has already been added
+
        if (!is_user_mode) {
                return;
        }
 
-       /* entry preamble may not have executed */
+       // Add the lr (parent function)
+       // entry preamble may not have executed
        gator_add_trace(cpu, lr);
 
-       /* check tail is valid */
+       // check fp is valid
        if (fp == 0 || fp < sp) {
                return;
        }
 
-       tail = (struct frame_tail_eabi *)(fp - frame_offset);
+       // Get the current stack frame
+       curr = (struct stack_frame_eabi *)(fp - gcc_frame_offset);
+       if ((unsigned long)curr & 3) {
+               return;
+       }
 
-       while (depth-- && tail && !((unsigned long)tail & 3)) {
-               /* Also check accessibility of one struct frame_tail beyond */
-               if (!access_ok(VERIFY_READ, tail, sizeof(struct frame_tail_eabi)))
-                       return;
-               if (__copy_from_user_inatomic(&buftail, tail, sizeof(struct frame_tail_eabi)))
+       while (depth-- && curr) {
+               if (!access_ok(VERIFY_READ, curr, sizeof(struct stack_frame_eabi)) ||
+                               __copy_from_user_inatomic(&bufcurr, curr, sizeof(struct stack_frame_eabi))) {
                        return;
+               }
+
+               fp = (is_compat ? bufcurr.fp_32 : bufcurr.fp);
+               lr = (is_compat ? bufcurr.lr_32 : bufcurr.lr);
+
+#define calc_next(reg) ((reg) - gcc_frame_offset)
+               // Returns true if reg is a valid fp
+#define validate_next(reg, curr) \
+               ((reg) != 0 && (calc_next(reg) & 3) == 0 && (unsigned long)(curr) < calc_next(reg))
+
+               // Try lr from the stack as the fp because gcc leaf functions do not push lr
+               // If gcc_frame_offset is non-zero, the lr will also be the clang fp
+               // This assumes code is at a lower address than the stack
+               if (validate_next(lr, curr)) {
+                       fp = lr;
+                       lr = (is_compat ? bufcurr.lr2_32 : bufcurr.lr2);
+               }
 
-               lr = (is_compat ? buftail.lr_32 : buftail.lr);
                gator_add_trace(cpu, lr);
 
-               /* frame pointers should progress back up the stack, towards higher addresses */
-               next = (struct frame_tail_eabi *)(lr - frame_offset);
-               if (tail >= next || lr == 0) {
-                       fp = (is_compat ? buftail.fp_32 : buftail.fp);
-                       next = (struct frame_tail_eabi *)(fp - frame_offset);
-                       /* check tail is valid */
-                       if (tail >= next || fp == 0) {
-                               return;
-                       }
+               if (!validate_next(fp, curr)) {
+                       return;
                }
 
-               tail = next;
+               // Move to the next stack frame
+               curr = (struct stack_frame_eabi *)calc_next(fp);
        }
 #endif
 }
@@ -89,11 +110,12 @@ static void arm_backtrace_eabi(int cpu, struct pt_regs *const regs, unsigned int
 #if defined(__arm__) || defined(__aarch64__)
 static int report_trace(struct stackframe *frame, void *d)
 {
-       unsigned int *depth = d, cookie = NO_COOKIE, cpu = get_physical_cpu();
+       unsigned int *depth = d, cookie = NO_COOKIE;
        unsigned long addr = frame->pc;
 
        if (*depth) {
 #if defined(MODULE)
+               unsigned int cpu = get_physical_cpu();
                struct module *mod = __module_address(addr);
                if (mod) {
                        cookie = get_cookie(cpu, current, mod->name, false);
index e646215f37f65c36353cf2ad89900747b464ea0b..21aa4a214d97c02c09a9dfdea253e0cce7e8ae0d 100644 (file)
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#if defined(CONFIG_OF)
 #include <linux/of.h>
 #include <linux/of_address.h>
+#endif
 #include <asm/hardware/cache-l2x0.h>
 
 #include "gator.h"
@@ -152,16 +154,23 @@ static void __iomem *gator_events_l2c310_probe(void)
 #endif
        };
        int i;
-
+       void __iomem *base;
 #if defined(CONFIG_OF)
-       if (of_have_populated_dt())
-               return of_iomap(of_find_compatible_node(NULL,
-                               NULL, "arm,pl310-cache"), 0);
+       struct device_node *node = of_find_all_nodes(NULL);
+
+       if (node) {
+               of_node_put(node);
+
+               node = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
+               base = of_iomap(node, 0);
+               of_node_put(node);
+
+               return base;
+       }
 #endif
 
        for (i = 0; i < ARRAY_SIZE(variants); i++) {
-               void __iomem *base = ioremap(variants[i], SZ_4K);
-
+               base = ioremap(variants[i], SZ_4K);
                if (base) {
                        u32 cache_id = readl(base + L2X0_CACHE_ID);
 
index c5fd989886c3e2b5a3ad952a1fbd88fff7e4b160..38c97d148f8a57e83be5075ea7776f0be1155eae 100644 (file)
 #include "gator_events_mali_common.h"
 #include "gator_events_mali_400.h"
 
-#if !defined(GATOR_MALI_INTERFACE_STYLE)
-/*
- * At the moment, we only have users with the old style interface, so
- * make our life easier by making it the default...
- */
-#define GATOR_MALI_INTERFACE_STYLE (2)
-#endif
-
 /*
  * There are (currently) three different variants of the comms between gator and Mali:
  * 1 (deprecated): No software counter support
index fb2e15cecbb51939cf1a8f50a9cb8490fa1f64ce..4f49c1da10e7052c0196d2eae42ccbd148c0bfd5 100644 (file)
 
 #include "gator_events_mali_common.h"
 
+/* If API version is not specified then assume API version 1. */
+#ifndef MALI_DDK_GATOR_API_VERSION
+#define MALI_DDK_GATOR_API_VERSION 1
+#endif
+
+#if (MALI_DDK_GATOR_API_VERSION != 1) && (MALI_DDK_GATOR_API_VERSION != 2)
+#error MALI_DDK_GATOR_API_VERSION is invalid (must be 1 for r1/r2 DDK, or 2 for r3 DDK).
+#endif
+
 /*
  * Mali-T6xx
  */
 typedef struct kbase_device *kbase_find_device_type(int);
 typedef kbase_context *kbase_create_context_type(kbase_device *);
 typedef void kbase_destroy_context_type(kbase_context *);
+
+#if MALI_DDK_GATOR_API_VERSION == 1
 typedef void *kbase_va_alloc_type(kbase_context *, u32);
 typedef void kbase_va_free_type(kbase_context *, void *);
+#elif MALI_DDK_GATOR_API_VERSION == 2
+typedef void *kbase_va_alloc_type(kbase_context *, u32, kbase_hwc_dma_mapping * handle);
+typedef void kbase_va_free_type(kbase_context *, kbase_hwc_dma_mapping * handle);
+#endif
+
 typedef mali_error kbase_instr_hwcnt_enable_type(kbase_context *, kbase_uk_hwcnt_setup *);
 typedef mali_error kbase_instr_hwcnt_disable_type(kbase_context *);
 typedef mali_error kbase_instr_hwcnt_clear_type(kbase_context *);
@@ -358,6 +374,11 @@ static const char *const hardware_counter_names[] = {
 /* Memory to dump hardware counters into */
 static void *kernel_dump_buffer;
 
+#if MALI_DDK_GATOR_API_VERSION == 2
+/* DMA state used to manage lifetime of the buffer */
+kbase_hwc_dma_mapping kernel_dump_buffer_handle;
+#endif
+
 /* kbase context and device */
 static kbase_context *kbcontext = NULL;
 static struct kbase_device *kbdevice = NULL;
@@ -524,9 +545,14 @@ static int start(void)
                 *             * number of blocks (always 8 for midgard)
                 *             * number of counters per block (always 64 for midgard)
                 *             * number of bytes per counter (always 4 in midgard)
-                * For a Mali-T6xx with a single core group = 1 * 8 * 64 * 4
+                * For a Mali-T6xx with a single core group = 1 * 8 * 64 * 4 = 2048
+                * For a Mali-T6xx with a dual core group   = 2 * 8 * 64 * 4 = 4096
                 */
-               kernel_dump_buffer = kbase_va_alloc_symbol(kbcontext, 2048);
+#if MALI_DDK_GATOR_API_VERSION == 1
+               kernel_dump_buffer = kbase_va_alloc_symbol(kbcontext, 4096);
+#elif MALI_DDK_GATOR_API_VERSION == 2
+               kernel_dump_buffer = kbase_va_alloc_symbol(kbcontext, 4096, &kernel_dump_buffer_handle);
+#endif
                if (!kernel_dump_buffer) {
                        pr_debug("gator: Mali-T6xx: error trying to allocate va\n");
                        goto destroy_context;
@@ -556,7 +582,11 @@ static int start(void)
        return 0;
 
 free_buffer:
+#if MALI_DDK_GATOR_API_VERSION == 1
        kbase_va_free_symbol(kbcontext, kernel_dump_buffer);
+#elif MALI_DDK_GATOR_API_VERSION == 2
+       kbase_va_free_symbol(kbcontext, &kernel_dump_buffer_handle);
+#endif
 
 destroy_context:
        kbase_destroy_context_symbol(kbcontext);
@@ -588,7 +618,13 @@ static void stop(void)
                kbcontext = NULL;
 
                kbase_instr_hwcnt_disable_symbol(temp_kbcontext);
+
+#if MALI_DDK_GATOR_API_VERSION == 1
                kbase_va_free_symbol(temp_kbcontext, kernel_dump_buffer);
+#elif MALI_DDK_GATOR_API_VERSION == 2
+               kbase_va_free_symbol(temp_kbcontext, &kernel_dump_buffer_handle);
+#endif
+
                kbase_destroy_context_symbol(temp_kbcontext);
 
                pr_debug("gator: Mali-T6xx: hardware counters stopped\n");
index 34a6bc78756af0655e40dcd9256aec2b7d68b285..53b2d0a5afbffa55e8974c6d6ec4859b3a9957cc 100644 (file)
 
 extern bool event_based_sampling;
 
+// Maximum number of per-core counters - currently reserves enough space for two full hardware PMUs for big.LITTLE
 #define CNTMAX 16
 #define CCI_400 4
+// Maximum number of uncore counters
 // + 1 for the cci-400 cycles counter
 #define UCCNT (CCI_400 + 1)
 
+// A gator_attr is needed for every counter
 struct gator_attr {
+       // Set once in gator_events_perf_pmu_*_init - the name of the event in the gatorfs
        char name[40];
+       // Exposed in gatorfs - set by gatord to enable this counter
        unsigned long enabled;
+       // Set once in gator_events_perf_pmu_*_init - the perf type to use, see perf_type_id in the perf_event.h header file.
        unsigned long type;
+       // Exposed in gatorfs - set by gatord to select the event to collect
        unsigned long event;
+       // Exposed in gatorfs - set by gatord with the sample period to use and enable EBS for this counter
        unsigned long count;
+       // Exposed as read only in gatorfs - set once in __attr_init as the key to use in the APC data
        unsigned long key;
 };
 
+// Per-core counter attributes
 static struct gator_attr attrs[CNTMAX];
+// Number of initialized per-core counters
 static int attr_count;
+// Uncore counter attributes
 static struct gator_attr uc_attrs[UCCNT];
+// Number of initialized uncore counters
 static int uc_attr_count;
 
 struct gator_event {
@@ -458,7 +471,7 @@ int gator_events_perf_pmu_init(void)
                                break;
                        }
                }
-               // Assume that valid PMUs are contigious
+               // Assume that valid PMUs are contiguous
                if (IS_ERR(pe)) {
                        break;
                }
@@ -470,6 +483,7 @@ int gator_events_perf_pmu_init(void)
                                found_cpu = true;
                                gator_events_perf_pmu_cpu_init(gator_cpu, type);
                        }
+                       // Initialize gator_attrs for dynamic PMUs here
                }
 
                perf_event_release_kernel(pe);
@@ -483,6 +497,8 @@ int gator_events_perf_pmu_init(void)
                gator_events_perf_pmu_cpu_init(gator_cpu, PERF_TYPE_RAW);
        }
 
+       // Initialize gator_attrs for non-dynamic PMUs here
+
        if (attr_count > CNTMAX) {
                printk(KERN_ERR "gator: Too many perf counters\n");
                return -1;
index 6f45c5482058cbb5d9034cfdddfab70cde5bc6cb..932be26bfcf7f57d7995a289a85aa27c398b52d8 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2013. All rights reserved.
+ * Copyright (C) ARM Limited 2013. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 88650f60bd5f436fc66dfadacb65a1544e30e947..46fe31d2505dbe4f49cfbfaba3c127e914b9d190 100644 (file)
@@ -8,7 +8,7 @@
  */
 
 // This version must match the gator daemon version
-static unsigned long gator_protocol_version = 13;
+static unsigned long gator_protocol_version = 14;
 
 #include <linux/slab.h>
 #include <linux/cpu.h>
@@ -50,9 +50,9 @@ static unsigned long gator_protocol_version = 13;
 
 #if (GATOR_PERF_SUPPORT) && (!(GATOR_PERF_PMU_SUPPORT))
 #ifndef CONFIG_PERF_EVENTS
-#warning gator requires the kernel to have CONFIG_PERF_EVENTS defined to support pmu hardware counters
+#error gator requires the kernel to have CONFIG_PERF_EVENTS defined to support pmu hardware counters
 #elif !defined CONFIG_HW_PERF_EVENTS
-#warning gator requires the kernel to have CONFIG_HW_PERF_EVENTS defined to support pmu hardware counters
+#error gator requires the kernel to have CONFIG_HW_PERF_EVENTS defined to support pmu hardware counters
 #endif
 #endif
 
@@ -162,8 +162,8 @@ static void gator_commit_buffer(int cpu, int buftype, u64 time);
 static int buffer_bytes_available(int cpu, int buftype);
 static bool buffer_check_space(int cpu, int buftype, int bytes);
 static int contiguous_space_available(int cpu, int bufytpe);
-static void gator_buffer_write_packed_int(int cpu, int buftype, unsigned int x);
-static void gator_buffer_write_packed_int64(int cpu, int buftype, unsigned long long x);
+static void gator_buffer_write_packed_int(int cpu, int buftype, int x);
+static void gator_buffer_write_packed_int64(int cpu, int buftype, long long x);
 static void gator_buffer_write_bytes(int cpu, int buftype, const char *x, int len);
 static void gator_buffer_write_string(int cpu, int buftype, const char *x);
 static void gator_add_trace(int cpu, unsigned long address);
@@ -389,6 +389,8 @@ static bool buffer_commit_ready(int *cpu, int *buftype)
                                return true;
                        }
        }
+       *cpu = -1;
+       *buftype = -1;
        return false;
 }
 
@@ -476,14 +478,14 @@ static void gator_commit_buffer(int cpu, int buftype, u64 time)
        if (length < 0) {
                length += gator_buffer_size[buftype];
        }
-       length = length - type_length - sizeof(int);
+       length = length - type_length - sizeof(s32);
 
        if (length <= FRAME_HEADER_SIZE) {
                // Nothing to write, only the frame header is present
                return;
        }
 
-       for (byte = 0; byte < sizeof(int); byte++) {
+       for (byte = 0; byte < sizeof(s32); byte++) {
                per_cpu(gator_buffer, cpu)[buftype][(commit + type_length + byte) & gator_buffer_mask[buftype]] = (length >> byte * 8) & 0xFF;
        }
 
@@ -595,7 +597,7 @@ static void gator_timer_offline(void *migrate)
 
        // Offline any events and output counters
        time = gator_get_time();
-       if (marshal_event_header()) {
+       if (marshal_event_header(time)) {
                list_for_each_entry(gi, &gator_events, list) {
                        if (gi->offline) {
                                len = gi->offline(&buffer, migrate);
@@ -644,11 +646,13 @@ static void gator_timer_online(void *migrate)
        struct gator_interface *gi;
        int len, cpu = get_physical_cpu();
        int *buffer;
+       u64 time;
 
        gator_trace_power_online();
 
        // online any events and output counters
-       if (marshal_event_header()) {
+       time = gator_get_time();
+       if (marshal_event_header(time)) {
                list_for_each_entry(gi, &gator_events, list) {
                        if (gi->online) {
                                len = gi->online(&buffer, migrate);
@@ -656,7 +660,7 @@ static void gator_timer_online(void *migrate)
                        }
                }
                // Only check after writing all counters so that time and corresponding counters appear in the same frame
-               buffer_check(cpu, BLOCK_COUNTER_BUF, gator_get_time());
+               buffer_check(cpu, BLOCK_COUNTER_BUF, time);
        }
 
        if (!migrate) {
@@ -745,8 +749,6 @@ static u64 gator_get_time(void)
                if (!printed_monotonic_warning && delta > 500000) {
                        printk(KERN_ERR "%s: getrawmonotonic is not monotonic  cpu: %i  delta: %lli\nSkew in Streamline data may be present at the fine zoom levels\n", __FUNCTION__, cpu, delta);
                        printed_monotonic_warning = true;
-               } else {
-                       pr_debug("%s: getrawmonotonic is not monotonic  cpu: %i  delta: %lli\n", __FUNCTION__, cpu, delta);
                }
                timestamp = prev_timestamp;
        }
@@ -894,6 +896,7 @@ static int gator_init(void)
                if (gator_events_list[i])
                        gator_events_list[i]();
 
+       gator_trace_sched_init();
        gator_trace_power_init();
 
        return 0;
@@ -1227,83 +1230,81 @@ static int userspace_buffer_release(struct inode *inode, struct file *file)
        return 0;
 }
 
-static ssize_t userspace_buffer_read(struct file *file, char __user *buf,
-                                    size_t count, loff_t *offset)
+static ssize_t userspace_buffer_read(struct file *file, char __user *buf, size_t count, loff_t *offset)
 {
-       int retval = -EINVAL;
-       int commit = 0, length1, length2, read;
+       int commit, length1, length2, read;
        char *buffer1;
-       char *buffer2 = NULL;
+       char *buffer2;
        int cpu, buftype;
+       int written = 0;
 
-       /* do not handle partial reads */
-       if (count != userspace_buffer_size || *offset)
+       // ensure there is enough space for a whole frame
+       if (count < userspace_buffer_size || *offset) {
                return -EINVAL;
+       }
 
        // sleep until the condition is true or a signal is received
        // the condition is checked each time gator_buffer_wait is woken up
-       buftype = cpu = -1;
        wait_event_interruptible(gator_buffer_wait, buffer_commit_ready(&cpu, &buftype) || !gator_started);
 
-       if (signal_pending(current))
+       if (signal_pending(current)) {
                return -EINTR;
-
-       length2 = 0;
-       retval = -EFAULT;
-
-       mutex_lock(&gator_buffer_mutex);
+       }
 
        if (buftype == -1 || cpu == -1) {
-               retval = 0;
-               goto out;
+               return 0;
        }
 
-       read = per_cpu(gator_buffer_read, cpu)[buftype];
-       commit = per_cpu(gator_buffer_commit, cpu)[buftype];
+       mutex_lock(&gator_buffer_mutex);
 
-       /* May happen if the buffer is freed during pending reads. */
-       if (!per_cpu(gator_buffer, cpu)[buftype]) {
-               retval = -EFAULT;
-               goto out;
-       }
+       do {
+               read = per_cpu(gator_buffer_read, cpu)[buftype];
+               commit = per_cpu(gator_buffer_commit, cpu)[buftype];
 
-       /* determine the size of two halves */
-       length1 = commit - read;
-       buffer1 = &(per_cpu(gator_buffer, cpu)[buftype][read]);
-       buffer2 = &(per_cpu(gator_buffer, cpu)[buftype][0]);
-       if (length1 < 0) {
-               length1 = gator_buffer_size[buftype] - read;
-               length2 = commit;
-       }
+               // May happen if the buffer is freed during pending reads.
+               if (!per_cpu(gator_buffer, cpu)[buftype]) {
+                       break;
+               }
 
-       /* start, middle or end */
-       if (length1 > 0) {
-               if (copy_to_user(&buf[0], buffer1, length1)) {
-                       goto out;
+               // determine the size of two halves
+               length1 = commit - read;
+               length2 = 0;
+               buffer1 = &(per_cpu(gator_buffer, cpu)[buftype][read]);
+               buffer2 = &(per_cpu(gator_buffer, cpu)[buftype][0]);
+               if (length1 < 0) {
+                       length1 = gator_buffer_size[buftype] - read;
+                       length2 = commit;
                }
-       }
 
-       /* possible wrap around */
-       if (length2 > 0) {
-               if (copy_to_user(&buf[length1], buffer2, length2)) {
-                       goto out;
+               if (length1 + length2 > count - written) {
+                       break;
                }
-       }
 
-       per_cpu(gator_buffer_read, cpu)[buftype] = commit;
-       retval = length1 + length2;
+               // start, middle or end
+               if (length1 > 0 && copy_to_user(&buf[written], buffer1, length1)) {
+                       break;
+               }
 
-       /* kick just in case we've lost an SMP event */
-       wake_up(&gator_buffer_wait);
+               // possible wrap around
+               if (length2 > 0 && copy_to_user(&buf[written + length1], buffer2, length2)) {
+                       break;
+               }
 
-       // Wake up annotate_write if more space is available
-       if (buftype == ANNOTATE_BUF) {
-               wake_up(&gator_annotate_wait);
-       }
+               per_cpu(gator_buffer_read, cpu)[buftype] = commit;
+               written += length1 + length2;
+
+               // Wake up annotate_write if more space is available
+               if (buftype == ANNOTATE_BUF) {
+                       wake_up(&gator_annotate_wait);
+               }
+       }       while (buffer_commit_ready(&cpu, &buftype));
 
-out:
        mutex_unlock(&gator_buffer_mutex);
-       return retval;
+
+       // kick just in case we've lost an SMP event
+       wake_up(&gator_buffer_wait);
+
+       return written > 0 ? written : -EFAULT;
 }
 
 const struct file_operations gator_event_buffer_fops = {
@@ -1376,6 +1377,9 @@ void gator_op_create_files(struct super_block *sb, struct dentry *root)
                if (gi->create_files)
                        gi->create_files(sb, dir);
 
+       // Sched Events
+       sched_trace_create_files(sb, dir);
+
        // Power interface
        gator_trace_power_create_files(sb, dir);
 }
index 627b441eb44ec2088308cde4f2eafc9eeceaa15b..72dd5efb6625a70cb9a60ebd6bf9bfabbea7356a 100644 (file)
@@ -28,7 +28,13 @@ static void marshal_summary(long long timestamp, long long uptime, const char *
        gator_buffer_write_string(cpu, SUMMARY_BUF, NEWLINE_CANARY);
        gator_buffer_write_packed_int64(cpu, SUMMARY_BUF, timestamp);
        gator_buffer_write_packed_int64(cpu, SUMMARY_BUF, uptime);
+       gator_buffer_write_string(cpu, SUMMARY_BUF, "uname");
        gator_buffer_write_string(cpu, SUMMARY_BUF, uname);
+#if GATOR_IKS_SUPPORT
+       gator_buffer_write_string(cpu, SUMMARY_BUF, "iks");
+       gator_buffer_write_string(cpu, SUMMARY_BUF, "");
+#endif
+       gator_buffer_write_string(cpu, SUMMARY_BUF, "");
        // Commit the buffer now so it can be one of the first frames read by Streamline
        gator_commit_buffer(cpu, SUMMARY_BUF, gator_get_time());
        local_irq_restore(flags);
@@ -102,7 +108,7 @@ static void marshal_backtrace_footer(void)
        buffer_check(cpu, BACKTRACE_BUF, gator_get_time());
 }
 
-static bool marshal_event_header(void)
+static bool marshal_event_header(u64 time)
 {
        unsigned long flags, cpu = get_physical_cpu();
        bool retval = false;
@@ -110,7 +116,7 @@ static bool marshal_event_header(void)
        local_irq_save(flags);
        if (buffer_check_space(cpu, BLOCK_COUNTER_BUF, MAXSIZE_PACK32 + MAXSIZE_PACK64)) {
                gator_buffer_write_packed_int(cpu, BLOCK_COUNTER_BUF, 0);       // key of zero indicates a timestamp
-               gator_buffer_write_packed_int64(cpu, BLOCK_COUNTER_BUF, gator_get_time());
+               gator_buffer_write_packed_int64(cpu, BLOCK_COUNTER_BUF, time);
                retval = true;
        }
        local_irq_restore(flags);
@@ -343,7 +349,7 @@ static void marshal_frame(int cpu, int buftype)
        }
 
        // leave space for 4-byte unpacked length
-       per_cpu(gator_buffer_write, cpu)[buftype] = (per_cpu(gator_buffer_write, cpu)[buftype] + 4) & gator_buffer_mask[buftype];
+       per_cpu(gator_buffer_write, cpu)[buftype] = (per_cpu(gator_buffer_write, cpu)[buftype] + sizeof(s32)) & gator_buffer_mask[buftype];
 
        // add frame type and core number
        gator_buffer_write_packed_int(cpu, buftype, frame);
index 2bddcbebc65ef2d5caba3ed7a584f7bd1b7a0216..2c082f283adc18037964cb70c40ae03d5f0d7b3c 100644 (file)
  *
  */
 
-static void gator_buffer_write_packed_int(int cpu, int buftype, unsigned int x)
+static void gator_buffer_write_packed_int(int cpu, int buftype, int x)
 {
        uint32_t write = per_cpu(gator_buffer_write, cpu)[buftype];
        uint32_t mask = gator_buffer_mask[buftype];
        char *buffer = per_cpu(gator_buffer, cpu)[buftype];
-       int write0 = (write + 0) & mask;
-       int write1 = (write + 1) & mask;
+       int packedBytes = 0;
+       int more = true;
+       while (more) {
+               // low order 7 bits of x
+               char b = x & 0x7f;
+               x >>= 7;
 
-       if ((x & 0xffffff80) == 0) {
-               buffer[write0] = x & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write1;
-       } else if ((x & 0xffffc000) == 0) {
-               int write2 = (write + 2) & mask;
-               buffer[write0] = x | 0x80;
-               buffer[write1] = (x >> 7) & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write2;
-       } else if ((x & 0xffe00000) == 0) {
-               int write2 = (write + 2) & mask;
-               int write3 = (write + 3) & mask;
-               buffer[write0] = x | 0x80;
-               buffer[write1] = (x >> 7) | 0x80;
-               buffer[write2] = (x >> 14) & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write3;
-       } else if ((x & 0xf0000000) == 0) {
-               int write2 = (write + 2) & mask;
-               int write3 = (write + 3) & mask;
-               int write4 = (write + 4) & mask;
-               buffer[write0] = x | 0x80;
-               buffer[write1] = (x >> 7) | 0x80;
-               buffer[write2] = (x >> 14) | 0x80;
-               buffer[write3] = (x >> 21) & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write4;
-       } else {
-               int write2 = (write + 2) & mask;
-               int write3 = (write + 3) & mask;
-               int write4 = (write + 4) & mask;
-               int write5 = (write + 5) & mask;
-               buffer[write0] = x | 0x80;
-               buffer[write1] = (x >> 7) | 0x80;
-               buffer[write2] = (x >> 14) | 0x80;
-               buffer[write3] = (x >> 21) | 0x80;
-               buffer[write4] = (x >> 28) & 0x0f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write5;
+               if ((x == 0 && (b & 0x40) == 0) || (x == -1 && (b & 0x40) != 0)) {
+                       more = false;
+               } else {
+                       b |= 0x80;
+               }
+
+               buffer[(write + packedBytes) & mask] = b;
+               packedBytes++;
        }
+
+       per_cpu(gator_buffer_write, cpu)[buftype] = (write + packedBytes) & mask;
 }
 
-static void gator_buffer_write_packed_int64(int cpu, int buftype, unsigned long long x)
+static void gator_buffer_write_packed_int64(int cpu, int buftype, long long x)
 {
        uint32_t write = per_cpu(gator_buffer_write, cpu)[buftype];
        uint32_t mask = gator_buffer_mask[buftype];
        char *buffer = per_cpu(gator_buffer, cpu)[buftype];
-       int write0 = (write + 0) & mask;
-       int write1 = (write + 1) & mask;
+       int packedBytes = 0;
+       int more = true;
+       while (more) {
+               // low order 7 bits of x
+               char b = x & 0x7f;
+               x >>= 7;
 
-       if ((x & 0xffffffffffffff80LL) == 0) {
-               buffer[write0] = x & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write1;
-       } else if ((x & 0xffffffffffffc000LL) == 0) {
-               int write2 = (write + 2) & mask;
-               buffer[write0] = x | 0x80;
-               buffer[write1] = (x >> 7) & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write2;
-       } else if ((x & 0xffffffffffe00000LL) == 0) {
-               int write2 = (write + 2) & mask;
-               int write3 = (write + 3) & mask;
-               buffer[write0] = x | 0x80;
-               buffer[write1] = (x >> 7) | 0x80;
-               buffer[write2] = (x >> 14) & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write3;
-       } else if ((x & 0xfffffffff0000000LL) == 0) {
-               int write2 = (write + 2) & mask;
-               int write3 = (write + 3) & mask;
-               int write4 = (write + 4) & mask;
-               buffer[write0] = x | 0x80;
-               buffer[write1] = (x >> 7) | 0x80;
-               buffer[write2] = (x >> 14) | 0x80;
-               buffer[write3] = (x >> 21) & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write4;
-       } else if ((x & 0xfffffff800000000LL) == 0) {
-               int write2 = (write + 2) & mask;
-               int write3 = (write + 3) & mask;
-               int write4 = (write + 4) & mask;
-               int write5 = (write + 5) & mask;
-               buffer[write0] = x | 0x80;
-               buffer[write1] = (x >> 7) | 0x80;
-               buffer[write2] = (x >> 14) | 0x80;
-               buffer[write3] = (x >> 21) | 0x80;
-               buffer[write4] = (x >> 28) & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write5;
-       } else if ((x & 0xfffffc0000000000LL) == 0) {
-               int write2 = (write + 2) & mask;
-               int write3 = (write + 3) & mask;
-               int write4 = (write + 4) & mask;
-               int write5 = (write + 5) & mask;
-               int write6 = (write + 6) & mask;
-               buffer[write0] = x | 0x80;
-               buffer[write1] = (x >> 7) | 0x80;
-               buffer[write2] = (x >> 14) | 0x80;
-               buffer[write3] = (x >> 21) | 0x80;
-               buffer[write4] = (x >> 28) | 0x80;
-               buffer[write5] = (x >> 35) & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write6;
-       } else if ((x & 0xfffe000000000000LL) == 0) {
-               int write2 = (write + 2) & mask;
-               int write3 = (write + 3) & mask;
-               int write4 = (write + 4) & mask;
-               int write5 = (write + 5) & mask;
-               int write6 = (write + 6) & mask;
-               int write7 = (write + 7) & mask;
-               buffer[write0] = x | 0x80;
-               buffer[write1] = (x >> 7) | 0x80;
-               buffer[write2] = (x >> 14) | 0x80;
-               buffer[write3] = (x >> 21) | 0x80;
-               buffer[write4] = (x >> 28) | 0x80;
-               buffer[write5] = (x >> 35) | 0x80;
-               buffer[write6] = (x >> 42) & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write7;
-       } else if ((x & 0xff00000000000000LL) == 0) {
-               int write2 = (write + 2) & mask;
-               int write3 = (write + 3) & mask;
-               int write4 = (write + 4) & mask;
-               int write5 = (write + 5) & mask;
-               int write6 = (write + 6) & mask;
-               int write7 = (write + 7) & mask;
-               int write8 = (write + 8) & mask;
-               buffer[write0] = x | 0x80;
-               buffer[write1] = (x >> 7) | 0x80;
-               buffer[write2] = (x >> 14) | 0x80;
-               buffer[write3] = (x >> 21) | 0x80;
-               buffer[write4] = (x >> 28) | 0x80;
-               buffer[write5] = (x >> 35) | 0x80;
-               buffer[write6] = (x >> 42) | 0x80;
-               buffer[write7] = (x >> 49) & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write8;
-       } else if ((x & 0x8000000000000000LL) == 0) {
-               int write2 = (write + 2) & mask;
-               int write3 = (write + 3) & mask;
-               int write4 = (write + 4) & mask;
-               int write5 = (write + 5) & mask;
-               int write6 = (write + 6) & mask;
-               int write7 = (write + 7) & mask;
-               int write8 = (write + 8) & mask;
-               int write9 = (write + 9) & mask;
-               buffer[write0] = x | 0x80;
-               buffer[write1] = (x >> 7) | 0x80;
-               buffer[write2] = (x >> 14) | 0x80;
-               buffer[write3] = (x >> 21) | 0x80;
-               buffer[write4] = (x >> 28) | 0x80;
-               buffer[write5] = (x >> 35) | 0x80;
-               buffer[write6] = (x >> 42) | 0x80;
-               buffer[write7] = (x >> 49) | 0x80;
-               buffer[write8] = (x >> 56) & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write9;
-       } else {
-               int write2 = (write + 2) & mask;
-               int write3 = (write + 3) & mask;
-               int write4 = (write + 4) & mask;
-               int write5 = (write + 5) & mask;
-               int write6 = (write + 6) & mask;
-               int write7 = (write + 7) & mask;
-               int write8 = (write + 8) & mask;
-               int write9 = (write + 9) & mask;
-               int write10 = (write + 10) & mask;
-               buffer[write0] = x | 0x80;
-               buffer[write1] = (x >> 7) | 0x80;
-               buffer[write2] = (x >> 14) | 0x80;
-               buffer[write3] = (x >> 21) | 0x80;
-               buffer[write4] = (x >> 28) | 0x80;
-               buffer[write5] = (x >> 35) | 0x80;
-               buffer[write6] = (x >> 42) | 0x80;
-               buffer[write7] = (x >> 49) | 0x80;
-               buffer[write8] = (x >> 56) | 0x80;
-               buffer[write9] = (x >> 63) & 0x7f;
-               per_cpu(gator_buffer_write, cpu)[buftype] = write10;
+               if ((x == 0 && (b & 0x40) == 0) || (x == -1 && (b & 0x40) != 0)) {
+                       more = false;
+               } else {
+                       b |= 0x80;
+               }
+
+               buffer[(write + packedBytes) & mask] = b;
+               packedBytes++;
        }
+
+       per_cpu(gator_buffer_write, cpu)[buftype] = (write + packedBytes) & mask;
 }
index c94f6a0cbebccf296296246f44a8cf27e2a70163..61ecbe34e1eaac2ed4fe21f18e7555825e016e95 100644 (file)
@@ -82,9 +82,12 @@ static void mali_gpu_stop(int unit, int core)
        int last_pid = 0;
 
        spin_lock(&mali_gpu_jobs_lock);
+       if (mali_gpu_jobs[unit][core].count == 0) {
+               spin_unlock(&mali_gpu_jobs_lock);
+               return;
+       }
        --mali_gpu_jobs[unit][core].count;
        count = mali_gpu_jobs[unit][core].count;
-       BUG_ON(count < 0);
        if (count) {
                last_core = mali_gpu_jobs[unit][core].last_core;
                last_tgid = mali_gpu_jobs[unit][core].last_tgid;
index eb989b5c32e61869b6905e702d40a1f7ac089017..e989f6a06d0527d13b81037921e244987adef8eb 100644 (file)
 #define TASK_MAP_ENTRIES               1024    /* must be power of 2 */
 #define TASK_MAX_COLLISIONS            2
 
-static DEFINE_PER_CPU(uint64_t *, taskname_keys);
-static DEFINE_PER_CPU(int, collecting);
-
 enum {
        STATE_WAIT_ON_OTHER = 0,
        STATE_CONTENTION,
        STATE_WAIT_ON_IO,
+       CPU_WAIT_TOTAL
 };
 
+static DEFINE_PER_CPU(uint64_t *, taskname_keys);
+static DEFINE_PER_CPU(int, collecting);
+
+// this array is never read as the cpu wait charts are derived counters
+// the files are needed, nonetheless, to show that these counters are available
+static ulong cpu_wait_enabled[CPU_WAIT_TOTAL];
+static ulong sched_cpu_key[CPU_WAIT_TOTAL];
+
+static int sched_trace_create_files(struct super_block *sb, struct dentry *root)
+{
+       struct dentry *dir;
+
+       // CPU Wait - Contention
+       dir = gatorfs_mkdir(sb, root, "Linux_cpu_wait_contention");
+       if (!dir) {
+               return -1;
+       }
+       gatorfs_create_ulong(sb, dir, "enabled", &cpu_wait_enabled[STATE_CONTENTION]);
+       gatorfs_create_ro_ulong(sb, dir, "key", &sched_cpu_key[STATE_CONTENTION]);
+
+       // CPU Wait - I/O
+       dir = gatorfs_mkdir(sb, root, "Linux_cpu_wait_io");
+       if (!dir) {
+               return -1;
+       }
+       gatorfs_create_ulong(sb, dir, "enabled", &cpu_wait_enabled[STATE_WAIT_ON_IO]);
+       gatorfs_create_ro_ulong(sb, dir, "key", &sched_cpu_key[STATE_WAIT_ON_IO]);
+
+       return 0;
+}
+
 void emit_pid_name(struct task_struct *task)
 {
        bool found = false;
@@ -70,7 +99,8 @@ static void collect_counters(void)
        struct gator_interface *gi;
        u64 time;
 
-       if (marshal_event_header()) {
+       time = gator_get_time();
+       if (marshal_event_header(time)) {
                list_for_each_entry(gi, &gator_events, list) {
                        if (gi->read) {
                                len = gi->read(&buffer);
@@ -81,7 +111,6 @@ static void collect_counters(void)
                        }
                }
                // Only check after writing all counters so that time and corresponding counters appear in the same frame
-               time = gator_get_time();
                buffer_check(cpu, BLOCK_COUNTER_BUF, time);
 
 #if GATOR_LIVE
@@ -216,3 +245,12 @@ void gator_trace_sched_stop(void)
                kfree(per_cpu(taskname_keys, cpu));
        }
 }
+
+void gator_trace_sched_init(void)
+{
+       int i;
+       for (i = 0; i < CPU_WAIT_TOTAL; i++) {
+               cpu_wait_enabled[i] = 0;
+               sched_cpu_key[i] = gator_events_get_key();
+       }
+}