gator-daemon: ARM DS-5.9 Streamline gator daemon (RC2)
authorJon Medhurst <tixy@linaro.org>
Mon, 20 Feb 2012 12:58:11 +0000 (12:58 +0000)
committerJon Medhurst <tixy@linaro.org>
Mon, 20 Feb 2012 12:58:11 +0000 (12:58 +0000)
47 files changed:
daemon/Android.mk
daemon/CapturedXML.cpp
daemon/CapturedXML.h
daemon/Child.cpp
daemon/Child.h
daemon/Collector.cpp
daemon/Collector.h
daemon/ConfigurationXML.cpp
daemon/ConfigurationXML.h
daemon/Fifo.cpp
daemon/Fifo.h
daemon/LocalCapture.cpp
daemon/LocalCapture.h
daemon/Logging.cpp
daemon/Logging.h
daemon/Makefile
daemon/OlySocket.cpp
daemon/OlySocket.h
daemon/OlyUtility.cpp
daemon/OlyUtility.h
daemon/RequestXML.cpp
daemon/RequestXML.h
daemon/Sender.cpp
daemon/Sender.h
daemon/SessionData.cpp
daemon/SessionData.h
daemon/SessionXML.cpp
daemon/SessionXML.h
daemon/StreamlineSetup.cpp
daemon/StreamlineSetup.h
daemon/XMLOut.cpp
daemon/XMLOut.h
daemon/XMLReader.cpp
daemon/XMLReader.h
daemon/events-ARM11.xml
daemon/events-Cortex-A15.xml
daemon/events-Cortex-A5.xml
daemon/events-Cortex-A7.xml [new file with mode: 0644]
daemon/events-Cortex-A8.xml
daemon/events-Cortex-A9.xml
daemon/events-Krait-architected.xml [new file with mode: 0644]
daemon/events-L2C-310.xml
daemon/events-Linux.xml
daemon/events-Mali-400.xml [new file with mode: 0644]
daemon/events-Scorpion.xml
daemon/events-ScorpionMP.xml
daemon/main.cpp

index ac3094c8f4b66dd79f4443d41bacd7faa31d0f0b..14aeda2d11444bdf90e9ad7e031e1a8789e6c780 100644 (file)
@@ -1,34 +1,34 @@
-LOCAL_PATH:= $(call my-dir)
-include $(CLEAR_VARS)
-
-$(shell cd $(LOCAL_PATH);cat events_header.xml events-*\.xml events_footer.xml > events.xml;xxd -i events.xml > events_xml.h;xxd -i configuration.xml > configuration_xml.h)
-
-LOCAL_CFLAGS +=  -Wall -O3 -ftree-vectorize
-
-LOCAL_SRC_FILES:= \
-       CapturedXML.cpp \
-       Child.cpp \
-       Collector.cpp \
-       ConfigurationXML.cpp \
-       Fifo.cpp \
-       LocalCapture.cpp \
-       Logging.cpp \
-       main.cpp \
-       OlySocket.cpp \
-       OlyUtility.cpp \
-       RequestXML.cpp \
-       Sender.cpp \
-       SessionData.cpp \
-       SessionXML.cpp \
-       StreamlineSetup.cpp \
-       XMLOut.cpp \
-       XMLReader.cpp 
-
-LOCAL_C_INCLUDES := $(LOCAL_PATH) 
-
-LOCAL_MODULE:= gatord
-LOCAL_MODULE_TAGS:= optional
-
-LOCAL_LDLIBS := -lz -llog
-
-include $(BUILD_EXECUTABLE)
+LOCAL_PATH:= $(call my-dir)\r
+include $(CLEAR_VARS)\r
+\r
+$(shell cd $(LOCAL_PATH);cat events_header.xml events-*\.xml events_footer.xml > events.xml;xxd -i events.xml > events_xml.h;xxd -i configuration.xml > configuration_xml.h)\r
+\r
+LOCAL_CFLAGS +=  -Wall -O3 -ftree-vectorize\r
+\r
+LOCAL_SRC_FILES:= \\r
+       CapturedXML.cpp \\r
+       Child.cpp \\r
+       Collector.cpp \\r
+       ConfigurationXML.cpp \\r
+       Fifo.cpp \\r
+       LocalCapture.cpp \\r
+       Logging.cpp \\r
+       main.cpp \\r
+       OlySocket.cpp \\r
+       OlyUtility.cpp \\r
+       RequestXML.cpp \\r
+       Sender.cpp \\r
+       SessionData.cpp \\r
+       SessionXML.cpp \\r
+       StreamlineSetup.cpp \\r
+       XMLOut.cpp \\r
+       XMLReader.cpp \r
+\r
+LOCAL_C_INCLUDES := $(LOCAL_PATH) \r
+\r
+LOCAL_MODULE:= gatord\r
+LOCAL_MODULE_TAGS:= optional\r
+\r
+LOCAL_LDLIBS := -lz -llog\r
+\r
+include $(BUILD_EXECUTABLE)\r
index 5d1f295fdd25394a655e5a093da192bb45723cfa..51076dd48717b3f0677a494ed1de73080985ff10 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -30,7 +30,7 @@ const char* CapturedXML::getXML() {
        xmlHeader();
 
        for (x=0; x<MAX_PERFORMANCE_COUNTERS; x++) {
-               if (gSessionData.mPerfCounterEnabled[x]) {
+               if (gSessionData->mPerfCounterEnabled[x]) {
                        perfCounters = true;
                        break;
                }
@@ -39,38 +39,38 @@ const char* CapturedXML::getXML() {
        startElement("captured");
        attributeInt("version", 1);
        attributeInt("protocol", PROTOCOL_VERSION);
-       if (gSessionData.mBytes > 0) { // Send the following only after the capture is complete
+       if (gSessionData->mBytes > 0) { // Send the following only after the capture is complete
                if (time(NULL) > 1267000000) { // If the time is reasonable (after Feb 23, 2010)
                        attributeUInt("created", time(NULL)); // Valid until the year 2038
                }
-               attributeUInt("bytes", gSessionData.mBytes);
+               attributeUInt("bytes", gSessionData->mBytes);
        }
        startElement("target");
-       attributeString("name", gSessionData.mCoreName);
-       attributeInt("sample_rate", gSessionData.mSampleRate);
-       attributeInt("cores", gSessionData.mCores);
+       attributeString("name", gSessionData->mCoreName);
+       attributeInt("sample_rate", gSessionData->mSampleRate);
+       attributeInt("cores", gSessionData->mCores);
        endElement("target");
        if (perfCounters) {
                startElement("counters");
                for (x = 0; x < MAX_PERFORMANCE_COUNTERS; x++) {
-                       if (gSessionData.mPerfCounterEnabled[x]) {
+                       if (gSessionData->mPerfCounterEnabled[x]) {
                                startElement("counter");
-                               attributeString("title", gSessionData.mPerfCounterTitle[x]);
-                               attributeString("name", gSessionData.mPerfCounterName[x]);
-                               attributeHex8("color", gSessionData.mPerfCounterColor[x]);
-                               attributeHex8("key", gSessionData.mPerfCounterKey[x]);
-                               attributeString("type", gSessionData.mPerfCounterType[x]);
-                               attributeHex8("event", gSessionData.mPerfCounterEvent[x]);
-                               if (gSessionData.mPerfCounterPerCPU[x]) {
+                               attributeString("title", gSessionData->mPerfCounterTitle[x]);
+                               attributeString("name", gSessionData->mPerfCounterName[x]);
+                               attributeHex8("color", gSessionData->mPerfCounterColor[x]);
+                               attributeHex8("key", gSessionData->mPerfCounterKey[x]);
+                               attributeString("type", gSessionData->mPerfCounterType[x]);
+                               attributeHex8("event", gSessionData->mPerfCounterEvent[x]);
+                               if (gSessionData->mPerfCounterPerCPU[x]) {
                                        attributeBool("per_cpu", true);
                                }
-                               if (strlen(gSessionData.mPerfCounterOperation[x]) > 0) {
-                                       attributeString("operation", gSessionData.mPerfCounterOperation[x]);
+                               if (strlen(gSessionData->mPerfCounterOperation[x]) > 0) {
+                                       attributeString("operation", gSessionData->mPerfCounterOperation[x]);
                                }
-                               if (gSessionData.mPerfCounterCount[x] > 0) {
-                                       attributeInt("count", gSessionData.mPerfCounterCount[x]);
+                               if (gSessionData->mPerfCounterCount[x] > 0) {
+                                       attributeInt("count", gSessionData->mPerfCounterCount[x]);
                                }
-                               attributeString("description", gSessionData.mPerfCounterDescription[x]);
+                               attributeString("description", gSessionData->mPerfCounterDescription[x]);
                                endElement("counter");
                        }
                }
index aafeefe5372fbd926a742fb0a7079801e0340148..d37c59e37ac0257b2ddc2a7a5e841071e27c174e 100644 (file)
@@ -1,5 +1,6 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 6cfbe609d46200c6209e20c98cce184a149c6839..fe5a1f061f9bd3ae943355a77b747df74e057fc0 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
 #include "Sender.h"
 #include "OlyUtility.h"
 #include "StreamlineSetup.h"
+#include "ConfigurationXML.h"
 
 static sem_t haltPipeline, senderThreadStarted, startProfile; // Shared by Child and spawned threads
 static Fifo* collectorFifo = NULL;   // Shared by Child.cpp and spawned threads
 static Sender* sender = NULL;        // Shared by Child.cpp and spawned threads
-Collector* collector = NULL;         // shared by Child.cpp and ConfigurationXML.cpp
+Collector* collector = NULL;
 Child* child = NULL;                 // shared by Child.cpp and main.cpp
 
 extern void cleanUp();
@@ -44,7 +45,7 @@ void handleException() {
                        sender->writeData(logg->getLastError(), strlen(logg->getLastError()), RESPONSE_ERROR);
 
                        // cannot close the socket before Streamline issues the command, so wait for the command before exiting
-                       if (gSessionData.mWaitingOnCommand) {
+                       if (gSessionData->mWaitingOnCommand) {
                                char discard;
                                child->socket->receiveNBytes(&discard, 1);
                        }
@@ -54,7 +55,7 @@ void handleException() {
                }
        }
 
-       if (gSessionData.mLocalCapture)
+       if (gSessionData->mLocalCapture)
                cleanUp();
 
        exit(1);
@@ -80,11 +81,11 @@ void child_handler(int signum) {
 void* durationThread(void* pVoid) {
        prctl(PR_SET_NAME, (unsigned int)&"gatord-duration", 0, 0, 0);
        sem_wait(&startProfile);
-       if (gSessionData.mSessionIsActive) {
+       if (gSessionData->mSessionIsActive) {
                // Time out after duration seconds
                // Add a second for host-side filtering
-               sleep(gSessionData.mDuration + 1);
-               if (gSessionData.mSessionIsActive) {
+               sleep(gSessionData->mDuration + 1);
+               if (gSessionData->mSessionIsActive) {
                        logg->logMessage("Duration expired.");
                        child->endSession();
                }
@@ -99,7 +100,7 @@ void* stopThread(void* pVoid) {
        OlySocket* socket = child->socket;
 
        prctl(PR_SET_NAME, (unsigned int)&"gatord-stopper", 0, 0, 0);
-       while (gSessionData.mSessionIsActive) {
+       while (gSessionData->mSessionIsActive) {
                // This thread will stall until the APC_STOP or PING command is received over the socket or the socket is disconnected
                if (socket->receiveNBytes(&type, sizeof(type)) > 0) {
                        if ((type != COMMAND_APC_STOP) && (type != COMMAND_PING)) {
@@ -149,6 +150,7 @@ void* senderThread(void* pVoid) {
 Child::Child(char* path) {
        initialization();
        sessionXMLPath = path;
+       gSessionData->mLocalCapture = true;
 }
 
 Child::Child(OlySocket* sock, int conn) {
@@ -162,7 +164,7 @@ Child::~Child() {
 
 void Child::initialization() {
        // Set up different handlers for signals
-       gSessionData.mSessionIsActive = true;
+       gSessionData->mSessionIsActive = true;
        signal(SIGINT, child_handler);
        signal(SIGTERM, child_handler);
        signal(SIGABRT, child_handler);
@@ -178,7 +180,7 @@ void Child::initialization() {
 }
 
 void Child::endSession() {
-       gSessionData.mSessionIsActive = false;
+       gSessionData->mSessionIsActive = false;
        collector->stop();
        sem_post(&haltPipeline);
 }
@@ -198,7 +200,10 @@ void Child::run() {
                handleException();
        }
 
-       // Set up the driver
+       // Populate gSessionData with the configuration
+       new ConfigurationXML();
+
+       // Set up the driver; must be done after gSessionData->mPerfCounterType[] is populated
        collector = new Collector();
 
        // Start up and parse session xml
@@ -207,23 +212,25 @@ void Child::run() {
                StreamlineSetup ss(socket);
        } else {
                xmlString = util->readFromDisk(sessionXMLPath);
-               gSessionData.mLocalCapture = true;
                if (xmlString == 0) {
                        logg->logError(__FILE__, __LINE__, "Unable to read session xml file: %s", sessionXMLPath);
                        handleException();
                }
-               gSessionData.parseSessionXML(xmlString);
+               gSessionData->parseSessionXML(xmlString);
                localCapture = new LocalCapture();
-               localCapture->createAPCDirectory(gSessionData.target_path, gSessionData.title);
-               localCapture->copyImages(gSessionData.images);
+               localCapture->createAPCDirectory(gSessionData->target_path, gSessionData->title);
+               localCapture->copyImages(gSessionData->images);
                localCapture->write(xmlString);
-               sender->createDataFile(gSessionData.apcDir);
+               sender->createDataFile(gSessionData->apcDir);
                delete xmlString;
        }
 
+       // Write configuration into the driver
+       collector->enablePerfCounters();
+
        // Create user-space buffers
        int fifoBufferSize = collector->getBufferSize();
-       int numCollectorBuffers = (gSessionData.mTotalBufferSize * 1024 * 1024 + fifoBufferSize - 1) / fifoBufferSize;
+       int numCollectorBuffers = (gSessionData->mTotalBufferSize * 1024 * 1024 + fifoBufferSize - 1) / fifoBufferSize;
        numCollectorBuffers = (numCollectorBuffers < 4) ? 4 : numCollectorBuffers;
        logg->logMessage("Created %d %d-byte collector buffers", numCollectorBuffers, fifoBufferSize);
        collectorFifo = new Fifo(numCollectorBuffers, fifoBufferSize);
@@ -232,11 +239,11 @@ void Child::run() {
        collectBuffer = collectorFifo->start();
 
        // Sender thread shall be halted until it is signaled for one shot mode
-       sem_init(&haltPipeline, 0, gSessionData.mOneShot ? 0 : 2);
+       sem_init(&haltPipeline, 0, gSessionData->mOneShot ? 0 : 2);
 
        // Create the duration, stop, and sender threads
        bool thread_creation_success = true;
-       if (gSessionData.mDuration > 0 && pthread_create(&durationThreadID, NULL, durationThread, NULL))
+       if (gSessionData->mDuration > 0 && pthread_create(&durationThreadID, NULL, durationThread, NULL))
                thread_creation_success = false;
        else if (socket && pthread_create(&stopThreadID, NULL, stopThread, NULL))
                thread_creation_success = false;
@@ -261,7 +268,7 @@ void Child::run() {
                bytesCollected = collector->collect(collectBuffer);
 
                // In one shot mode, stop collection once all the buffers are filled
-               if (gSessionData.mOneShot && gSessionData.mSessionIsActive) {
+               if (gSessionData->mOneShot && gSessionData->mSessionIsActive) {
                        // Depth minus 1 because write() has not yet been called
                        if ((bytesCollected == -1) || (collectorFifo->numWriteToReadBuffersFilled() == collectorFifo->depth() - 1)) {
                                logg->logMessage("One shot");
@@ -283,9 +290,9 @@ void Child::run() {
        }
 
        // Write the captured xml file
-       if (gSessionData.mLocalCapture) {
+       if (gSessionData->mLocalCapture) {
                CapturedXML capturedXML;
-               capturedXML.write(gSessionData.apcDir);
+               capturedXML.write(gSessionData->apcDir);
        }
 
        logg->logMessage("Profiling ended.");
index 950eb94302069e9eecf9282a2f0acaf6d77a88f6..eee5ac70f9e06f688e77178b6f05eb17dfd7af45 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 18f6dee92a9989f1cbdffa055ad382de779ce615..c6f837628f14b30e174bc33ec6471e93390f68d3 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
 #include "Collector.h"
 #include "SessionData.h"
 #include "Logging.h"
-#include "ConfigurationXML.h"
 
 extern void handleException();
 
 // Driver initialization independent of session settings
 Collector::Collector() {
+       char text[sizeof(gSessionData->mPerfCounterType[0]) + 20]; // sufficiently large to hold all events/<types>/<file>
+
        bufferFD = 0;
 
        checkVersion();
@@ -32,9 +33,9 @@ Collector::Collector() {
                handleException();
        }
 
-       readIntDriver("cpu_cores", &gSessionData.mCores);
-       if (gSessionData.mCores == 0) {
-               gSessionData.mCores = 1;
+       readIntDriver("cpu_cores", &gSessionData->mCores);
+       if (gSessionData->mCores == 0) {
+               gSessionData->mCores = 1;
        }
 
        bufferSize = 512 * 1024;
@@ -45,8 +46,11 @@ Collector::Collector() {
 
        getCoreName();
 
-       // populate performance counter session data
-       new ConfigurationXML();
+       // Read unchanging keys from driver which are created at insmod'ing of gator.ko
+       for (int i = 0; i < MAX_PERFORMANCE_COUNTERS; i++) {
+               snprintf(text, sizeof(text), "events/%s/key", gSessionData->mPerfCounterType[i]);
+               readIntDriver(text, &gSessionData->mPerfCounterKey[i]);
+       }
 }
 
 Collector::~Collector() {
@@ -60,28 +64,31 @@ Collector::~Collector() {
 }
 
 void Collector::enablePerfCounters() {
-       char base[sizeof(gSessionData.mPerfCounterType[0]) + 10]; // sufficiently large to hold all events/<types>
-       char text[sizeof(gSessionData.mPerfCounterType[0]) + 20]; // sufficiently large to hold all events/<types>/<file>
+       char base[sizeof(gSessionData->mPerfCounterType[0]) + 10]; // sufficiently large to hold all events/<types>
+       char text[sizeof(gSessionData->mPerfCounterType[0]) + 20]; // sufficiently large to hold all events/<types>/<file>
 
        for (int i=0; i<MAX_PERFORMANCE_COUNTERS; i++) {
-               if (!gSessionData.mPerfCounterEnabled[i]) {
+               if (!gSessionData->mPerfCounterEnabled[i]) {
                        continue;
                }
-               snprintf(base, sizeof(base), "events/%s", gSessionData.mPerfCounterType[i]);
+               snprintf(base, sizeof(base), "events/%s", gSessionData->mPerfCounterType[i]);
                snprintf(text, sizeof(text), "%s/event", base);
-               writeDriver(text, gSessionData.mPerfCounterEvent[i]);
-               snprintf(text, sizeof(text), "%s/key", base);
-               readIntDriver(text, &gSessionData.mPerfCounterKey[i]);
-               if (gSessionData.mPerfCounterEBSCapable[i]) {
+               writeDriver(text, gSessionData->mPerfCounterEvent[i]);
+               if (gSessionData->mPerfCounterEBSCapable[i]) {
                        snprintf(text, sizeof(text), "%s/count", base);
-                       if (writeReadDriver(text, &gSessionData.mPerfCounterCount[i]))
-                               gSessionData.mPerfCounterCount[i] = 0;
-                       if (gSessionData.mPerfCounterCount[i] > 0)
-                               logg->logMessage("EBS enabled for %s with a count of %d", gSessionData.mPerfCounterName[i], gSessionData.mPerfCounterCount[i]);
+                       if (access(resolvePath(text), F_OK) == 0) {
+                               if (writeReadDriver(text, &gSessionData->mPerfCounterCount[i]) && gSessionData->mPerfCounterCount[i] > 0) {
+                                       logg->logError(__FILE__, __LINE__, "Cannot enable EBS for %s with a count of %d\n", gSessionData->mPerfCounterName[i], gSessionData->mPerfCounterCount[i]);
+                                       handleException();
+                               }
+                       } else if (gSessionData->mPerfCounterCount[i] > 0) {
+                               logg->logError(__FILE__, __LINE__, "Event Based Sampling is only supported with kernel versions 3.0.0 and higher with CONFIG_PERF_EVENTS=y, and CONFIG_HW_PERF_EVENTS=y\n");
+                               handleException();
+                       }
                }
                snprintf(text, sizeof(text), "%s/enabled", base);
-               if (writeReadDriver(text, &gSessionData.mPerfCounterEnabled[i])) {
-                       gSessionData.mPerfCounterEnabled[i] = 0;
+               if (writeReadDriver(text, &gSessionData->mPerfCounterEnabled[i])) {
+                       gSessionData->mPerfCounterEnabled[i] = 0;
                }
        }
 }
@@ -117,27 +124,26 @@ void Collector::checkVersion() {
 
 void Collector::start() {
        // Set the maximum backtrace depth
-       if (writeReadDriver("backtrace_depth", &gSessionData.mBacktraceDepth)) {
+       if (writeReadDriver("backtrace_depth", &gSessionData->mBacktraceDepth)) {
                logg->logError(__FILE__, __LINE__, "Unable to set the driver backtrace depth");
                handleException();
        }
 
        // open the buffer which calls userspace_buffer_open() in the driver
-       char* fullpath = resolvePath("buffer");
-       bufferFD = open(fullpath, O_RDONLY);
+       bufferFD = open(resolvePath("buffer"), O_RDONLY);
        if (bufferFD < 0) {
                logg->logError(__FILE__, __LINE__, "The gator driver did not set up properly. Please view the linux console or dmesg log for more information on the failure.");
                handleException();
        }
 
        // set the tick rate of the profiling timer
-       if (writeReadDriver("tick", &gSessionData.mSampleRate) != 0) {
+       if (writeReadDriver("tick", &gSessionData->mSampleRate) != 0) {
                logg->logError(__FILE__, __LINE__, "Unable to set the driver tick");
                handleException();
        }
 
        // notify the kernel of the streaming mode, currently used for network stats
-       int streaming = (int)!gSessionData.mOneShot;
+       int streaming = (int)!gSessionData->mOneShot;
        if (writeReadDriver("streaming", &streaming) != 0) {
                logg->logError(__FILE__, __LINE__, "Unable to set streaming");
                handleException();
@@ -178,7 +184,7 @@ int Collector::collect(char* buffer) {
 
 void Collector::getCoreName() {
        char temp[256]; // arbitrarily large amount
-       strcpy(gSessionData.mCoreName, "unknown");
+       strcpy(gSessionData->mCoreName, "unknown");
 
        FILE* f = fopen("/proc/cpuinfo", "r");  
        if (f == NULL) {
@@ -198,8 +204,8 @@ void Collector::getCoreName() {
                                        "The core name in the captured xml file will be 'unknown'.");
                                return;
                        }
-                       strncpy(gSessionData.mCoreName, (char *)((int)position + 2), sizeof(gSessionData.mCoreName));
-                       gSessionData.mCoreName[sizeof(gSessionData.mCoreName) - 1] = 0; // strncpy does not guarantee a null-terminated string
+                       strncpy(gSessionData->mCoreName, (char *)((int)position + 2), sizeof(gSessionData->mCoreName));
+                       gSessionData->mCoreName[sizeof(gSessionData->mCoreName) - 1] = 0; // strncpy does not guarantee a null-terminated string
                        fclose(f);
                        return;
                }
index bcdfc23f759c2727c70230af08492c78cd228994..1cfe84e1b976d0a04f51fb403f8bad571a29c8e7 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 6348818fd795332153feb028f94d08e91476a213..e1bec0fd4fa89ddb9118355827a3f575f8cfd26a 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
 #include <dirent.h>
 #include "ConfigurationXML.h"
 #include "Logging.h"
-#include "Collector.h"
 #include "OlyUtility.h"
 #include "SessionData.h"
 
 extern void handleException();
-extern Collector* collector;
 
 static const char*     ATTR_COUNTER     = "counter";
 static const char*  ATTR_VERSION     = "version";
@@ -35,10 +33,14 @@ ConfigurationXML::ConfigurationXML() {
        index = 0;
        char* path = (char *)malloc(PATH_MAX);
 
-       if (util->getApplicationFullPath(path, PATH_MAX) != 0) {
-               logg->logMessage("Unable to determine the full path of gatord, the cwd will be used");
+       if (gSessionData->configurationXMLPath) {
+               strncpy(path, gSessionData->configurationXMLPath, PATH_MAX);
+       } else {
+               if (util->getApplicationFullPath(path, PATH_MAX) != 0) {
+                       logg->logMessage("Unable to determine the full path of gatord, the cwd will be used");
+               }
+               strncat(path, "configuration.xml", PATH_MAX - strlen(path) - 1);
        }
-       strncat(path, "configuration.xml", PATH_MAX - strlen(path) - 1);
        mConfigurationXML = util->readFromDisk(path);
 
        if (mConfigurationXML == NULL) {
@@ -49,7 +51,10 @@ ConfigurationXML::ConfigurationXML() {
                mConfigurationXML[configuration_xml_len] = 0;
        }
 
-       gSessionData.initializeCounters();
+       // disable all counters prior to parsing the configuration xml
+       for (int i = 0; i < MAX_PERFORMANCE_COUNTERS; i++) {
+               gSessionData->mPerfCounterEnabled[i] = 0;
+       }
 
        int ret = parse(mConfigurationXML);
        if (ret == 1) {
@@ -63,7 +68,6 @@ ConfigurationXML::ConfigurationXML() {
                handleException();
        }
 
-       collector->enablePerfCounters();
        free(path);
 }
 
@@ -91,20 +95,20 @@ int ConfigurationXML::parse(const char* configurationXML) {
 
 bool ConfigurationXML::isValid(void) {
        for (int i = 0; i < MAX_PERFORMANCE_COUNTERS; i++) {
-               if (gSessionData.mPerfCounterEnabled[i]) {
-                       if (strcmp(gSessionData.mPerfCounterType[i], "") == 0 ||
-                                       strcmp(gSessionData.mPerfCounterTitle[i], "") == 0 ||
-                                       strcmp(gSessionData.mPerfCounterName[i], "") == 0) {
-                               logg->logMessage("Invalid required attribute\n  counter=\"%s\"\n  title=\"%s\"\n  name=\"%s\"\n  event=%d\n", gSessionData.mPerfCounterType[i], gSessionData.mPerfCounterTitle[i], gSessionData.mPerfCounterName[i], gSessionData.mPerfCounterEvent[i]);
+               if (gSessionData->mPerfCounterEnabled[i]) {
+                       if (strcmp(gSessionData->mPerfCounterType[i], "") == 0 ||
+                                       strcmp(gSessionData->mPerfCounterTitle[i], "") == 0 ||
+                                       strcmp(gSessionData->mPerfCounterName[i], "") == 0) {
+                               logg->logMessage("Invalid required attribute\n  counter=\"%s\"\n  title=\"%s\"\n  name=\"%s\"\n  event=%d\n", gSessionData->mPerfCounterType[i], gSessionData->mPerfCounterTitle[i], gSessionData->mPerfCounterName[i], gSessionData->mPerfCounterEvent[i]);
                                return false; // failure
                        }
 
                        // iterate through the remaining enabled performance counters
                        for (int j = i + 1; j < MAX_PERFORMANCE_COUNTERS; j++) {
-                               if (gSessionData.mPerfCounterEnabled[j]) {
+                               if (gSessionData->mPerfCounterEnabled[j]) {
                                        // check if the type or device are the same
-                                       if (strcmp(gSessionData.mPerfCounterType[i], gSessionData.mPerfCounterType[j]) == 0) {
-                                               logg->logMessage("Duplicate performance counter type: %s", gSessionData.mPerfCounterType[i]);
+                                       if (strcmp(gSessionData->mPerfCounterType[i], gSessionData->mPerfCounterType[j]) == 0) {
+                                               logg->logMessage("Duplicate performance counter type: %s", gSessionData->mPerfCounterType[i]);
                                                return false; // failure
                                        }
                                }
@@ -133,17 +137,17 @@ int ConfigurationXML::configurationTag(XMLReader* in) {
        }
 
        // read attributes
-       in->getAttribute(ATTR_COUNTER, gSessionData.mPerfCounterType[index], sizeof(gSessionData.mPerfCounterType[index]), "");
-       in->getAttribute(ATTR_TITLE, gSessionData.mPerfCounterTitle[index], sizeof(gSessionData.mPerfCounterTitle[index]), "");
-       in->getAttribute(ATTR_NAME, gSessionData.mPerfCounterName[index], sizeof(gSessionData.mPerfCounterName[index]), "");
-       in->getAttribute(ATTR_DESCRIPTION, gSessionData.mPerfCounterDescription[index], sizeof(gSessionData.mPerfCounterDescription[index]), "");
-       gSessionData.mPerfCounterEvent[index] = in->getAttributeAsInteger(ATTR_EVENT, 0);
-       gSessionData.mPerfCounterCount[index] = in->getAttributeAsInteger(ATTR_COUNT, 0);
-       gSessionData.mPerfCounterColor[index] = in->getAttributeAsInteger(ATTR_COLOR, 0);
-       gSessionData.mPerfCounterPerCPU[index] = in->getAttributeAsBoolean(ATTR_PER_CPU, false);
-       gSessionData.mPerfCounterEBSCapable[index] = in->getAttributeAsBoolean(ATTR_EBS, false);
-       in->getAttribute(ATTR_OPERATION, gSessionData.mPerfCounterOperation[index], sizeof(gSessionData.mPerfCounterOperation[index]), "");
-       gSessionData.mPerfCounterEnabled[index] = true;
+       in->getAttribute(ATTR_COUNTER, gSessionData->mPerfCounterType[index], sizeof(gSessionData->mPerfCounterType[index]), "");
+       in->getAttribute(ATTR_TITLE, gSessionData->mPerfCounterTitle[index], sizeof(gSessionData->mPerfCounterTitle[index]), "");
+       in->getAttribute(ATTR_NAME, gSessionData->mPerfCounterName[index], sizeof(gSessionData->mPerfCounterName[index]), "");
+       in->getAttribute(ATTR_DESCRIPTION, gSessionData->mPerfCounterDescription[index], sizeof(gSessionData->mPerfCounterDescription[index]), "");
+       gSessionData->mPerfCounterEvent[index] = in->getAttributeAsInteger(ATTR_EVENT, 0);
+       gSessionData->mPerfCounterCount[index] = in->getAttributeAsInteger(ATTR_COUNT, 0);
+       gSessionData->mPerfCounterColor[index] = in->getAttributeAsInteger(ATTR_COLOR, 0);
+       gSessionData->mPerfCounterPerCPU[index] = in->getAttributeAsBoolean(ATTR_PER_CPU, false);
+       gSessionData->mPerfCounterEBSCapable[index] = in->getAttributeAsBoolean(ATTR_EBS, false);
+       in->getAttribute(ATTR_OPERATION, gSessionData->mPerfCounterOperation[index], sizeof(gSessionData->mPerfCounterOperation[index]), "");
+       gSessionData->mPerfCounterEnabled[index] = true;
 
        // update counter index
        index++;
index 57a426e91a8da849a74df40a2711f6d1ef934380..047c4b077056e11fc2a730614d3b43d6f230a88f 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 6ffebba08b59ab7d79417d59a97b08b1ac956f2b..1456183b0f0df8d4688f3d577e71e7525445196f 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 14688a99a8741ed5e9a512b5e3d645c6ea909cc0..51e2bcd6a7f888662b9ba664abc7349ca8c483e9 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 510a6c32bbab2fd422572b78d3dc3e5736f3ff76..4a2d6d755e6b3c2f57fa74f0bf96fe93f7c0cc7b 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -24,9 +24,9 @@ LocalCapture::LocalCapture() {}
 LocalCapture::~LocalCapture() {}
 
 void LocalCapture::createAPCDirectory(char* target_path, char* name) {
-       gSessionData.apcDir = createUniqueDirectory(target_path, ".apc", name);
-       if ((removeDirAndAllContents(gSessionData.apcDir) != 0 || mkdir(gSessionData.apcDir, S_IRWXU | S_IRWXG | S_IROTH | S_IXOTH) != 0)) {
-               logg->logError(__FILE__, __LINE__, "Unable to create directory %s", gSessionData.apcDir);
+       gSessionData->apcDir = createUniqueDirectory(target_path, ".apc", name);
+       if ((removeDirAndAllContents(gSessionData->apcDir) != 0 || mkdir(gSessionData->apcDir, S_IRWXU | S_IRWXG | S_IROTH | S_IXOTH) != 0)) {
+               logg->logError(__FILE__, __LINE__, "Unable to create directory %s", gSessionData->apcDir);
                handleException();
        }
 }
@@ -35,7 +35,7 @@ void LocalCapture::write(char* string) {
        char* file = (char*)malloc(PATH_MAX);
 
        // Set full path
-       snprintf(file, PATH_MAX, "%s/session.xml", gSessionData.apcDir);
+       snprintf(file, PATH_MAX, "%s/session.xml", gSessionData->apcDir);
 
        // Write the file
        if (util->writeToDisk(file, string) < 0) {
@@ -192,9 +192,9 @@ void LocalCapture::copyImages(ImageLinkList* ptr) {
        char* dstfilename = (char*)malloc(PATH_MAX);
 
        while (ptr) {
-               strncpy(dstfilename, gSessionData.apcDir, PATH_MAX);
+               strncpy(dstfilename, gSessionData->apcDir, PATH_MAX);
                dstfilename[PATH_MAX - 1] = 0; // strncpy does not guarantee a null-terminated string
-               if (gSessionData.apcDir[strlen(gSessionData.apcDir) - 1] != '/')
+               if (gSessionData->apcDir[strlen(gSessionData->apcDir) - 1] != '/')
                        strncat(dstfilename, "/", PATH_MAX - strlen(dstfilename) - 1);
                strncat(dstfilename, util->getFilePart(ptr->path), PATH_MAX - strlen(dstfilename) - 1);
                if (util->copyFile(ptr->path, dstfilename))
index 0bb6f94b986a749ea7c422b1058ae28c05199efb..4f5f8186e09f75b3d29e39a70cc7cbb900a1d620 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index d34209c3ee7b9c2f2e99716e2508c88539f04401..3e6f8a388a463a35f9f81916cec25476ee888873 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -30,8 +30,6 @@
 Logging* logg = NULL;
 
 Logging::Logging(bool debug) {
-       mFileCreated = false;
-       mWarningXMLPath[0] = 0;
        mDebug = debug;
        MUTEX_INIT();
 
@@ -40,9 +38,6 @@ Logging::Logging(bool debug) {
 }
 
 Logging::~Logging() {
-       if (mFileCreated) {
-               util->appendToDisk(mWarningXMLPath, "</warnings>");
-       }
 }
 
 void Logging::logError(const char* file, int line, const char* fmt, ...) {
@@ -59,18 +54,6 @@ void Logging::logError(const char* file, int line, const char* fmt, ...) {
        vsnprintf(mErrBuf + strlen(mErrBuf), sizeof(mErrBuf) - 2 - strlen(mErrBuf), fmt, args); //  subtract 2 for \n and \0
        va_end(args);
 
-       // Add the message to the warning file if the warning file was created
-       if (mWarningXMLPath[0] != 0) {
-               if (!mFileCreated) {
-                       if (util->writeToDisk(mWarningXMLPath, "<?xml version=\"1.0\" encoding='UTF-8'?>\n<warnings version=\"1\">\n") < 0) {
-                               return;
-                       }
-                       mFileCreated = true;
-               }
-               util->appendToDisk(mWarningXMLPath, "  <warning text=\"");
-               util->appendToDisk(mWarningXMLPath, mErrBuf);
-               util->appendToDisk(mWarningXMLPath, "\"/>\n");
-       }
        if (strlen(mErrBuf) > 0) {
                strcat(mErrBuf, "\n");
        }
index cd8d7cd1e21d8f58aacbaf340de02535e50bb9a2..424796658f7dd0e111b66dbb708cd96972db2bc0 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
 #include <limits.h>
 #ifdef WIN32
 #include <windows.h>
-#define GATOR_PATH_MAX MAX_PATH
 #else
 #include <pthread.h>
-#define GATOR_PATH_MAX PATH_MAX
 #endif
 
 #define DRIVER_ERROR "\n Driver issue:\n  >> gator.ko must be built against the current kernel version & configuration\n  >> gator.ko should be co-located with gatord in the same directory\n  >>   OR insmod gator.ko prior to launching gatord"
@@ -28,16 +26,13 @@ public:
        ~Logging();
        void logError(const char* file, int line, const char* fmt, ...);
        void logMessage(const char* fmt, ...);
-       void SetWarningFile(char* path) {strncpy(mWarningXMLPath, path, GATOR_PATH_MAX); mWarningXMLPath[GATOR_PATH_MAX - 1] = 0;}
        char* getLastError() {return mErrBuf;}
        char* getLastMessage() {return mLogBuf;}
 
 private:
-       char    mWarningXMLPath[GATOR_PATH_MAX];
        char    mErrBuf[4096]; // Arbitrarily large buffer to hold a string
        char    mLogBuf[4096]; // Arbitrarily large buffer to hold a string
        bool    mDebug;
-       bool    mFileCreated;
 #ifdef WIN32
        HANDLE  mLoggingMutex;
 #else
index 2a41e31f9c3e7e10b851d4f7d707f7b387859a78..4aaf219d7842f0030469535d177bda8cd431dd1b 100644 (file)
@@ -19,14 +19,13 @@ CPP=$(CROSS_COMPILE)g++
 # -mthumb-interwork is required for interworking to ARM or Thumb stdlibc
 CFLAGS=-O3 -Wall -Werror -march=armv5t -mthumb-interwork
 TARGET=gatord
-CPP_SRC = $(wildcard *.cpp) $(wildcard ../../reptilia/*.cpp)
+CPP_SRC = $(wildcard *.cpp)
 TGT_OBJS = $(CPP_SRC:%.cpp=%.o)
-INCLUDES = -I../../reptilia
 
 all: $(TARGET)
 
 %.o: %.cpp *.h
-       $(CPP) $(INCLUDES) -c $(CFLAGS) -o $@ $<
+       $(CPP) -c $(CFLAGS) -o $@ $<
 
 $(TARGET): convert $(TGT_OBJS)
        $(CPP) -s -o $@ $(TGT_OBJS) -lc -lrt -lpthread
@@ -38,4 +37,4 @@ convert:
        xxd -i configuration.xml > configuration_xml.h
 
 clean:
-       rm -f *.o $(TARGET) events.xml events_xml.h configuration_xml.h ../../reptilia/*.o
+       rm -f *.o $(TARGET) events.xml events_xml.h configuration_xml.h
index 9b031dcfe56ccea01ea1f837a400f25f70cb28c1..8a9ca970b9422e21a00a6a76209bf8d4009eb90e 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 9ba6ee8eb6eb709dbdbf0f3182d337eff82924bf..2fe6e59516f956d78d7a64398801e71378ef8a7b 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 6216726013f7caa3a38df88603d9419a6d76d10a..1b15d33d0e56970caa2f4f5404f2debf68e3849f 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index e516c01cdd1655d7b9b2304bf17e4609d2923612..0fa021dc364864697bf864c1ecb8892e975184bc 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 3dd7a43a811ba33171c1bdf86bd71e701bf44db1..e8f24d2d25dbd946bf351b063ace27bf555d995e 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2011. All rights reserved.
+ * Copyright (C) ARM Limited 2011-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index eff242e5b2903875797478e6d7f29ba398beaebe..bebd04809aeaf9ac24918246ffb6ac1cca5e0df3 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index c547d671982893bd697b16f69958019bdbd4726a..9792c3677a36e4d731ab7af5f2b0e107f6ec9b58 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -41,7 +41,7 @@ Sender::Sender(OlySocket* socket) {
                char magic[] = {'G', 'A', 'T', 'O', 'R', '\n'};
                dataSocket->send(magic, sizeof(magic));
 
-               gSessionData.mWaitingOnCommand = true;
+               gSessionData->mWaitingOnCommand = true;
                logg->logMessage("Completed magic sequence");
        }
 
index 147f19065a13552635f8e2471f8ba9d959355312..3444b852b01ee8855d3f7ac5e070243d6a22d3fc 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index f84253a3b7516a28a19c934104ac43860abb07f7..4adcfcd6c20b77d4e7cda134343cf412b57b8cf7 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,7 +12,7 @@
 #include "Logging.h"
 extern void handleException();
 
-SessionData gSessionData;
+SessionData* gSessionData = NULL;
 
 SessionData::SessionData() {
        initialize();
@@ -27,6 +27,7 @@ void SessionData::initialize() {
        mLocalCapture = false;
        mOneShot = false;
        strcpy(mCoreName, "unknown");
+       configurationXMLPath = NULL;
        apcDir = NULL;
        mSampleRate = 0;
        mDuration = 0;
@@ -34,6 +35,8 @@ void SessionData::initialize() {
        mBacktraceDepth = 0;
        mTotalBufferSize = 0;
        mCores = 1;
+
+       initializeCounters();
 }
 
 void SessionData::initializeCounters() {
@@ -62,39 +65,39 @@ void SessionData::parseSessionXML(char* xmlString) {
        if (session.parameters.output_path == 0 && session.parameters.target_path == 0) {
                logg->logError(__FILE__, __LINE__, "No capture path (target or host) was provided.");
                handleException();
-       } else if (gSessionData.mLocalCapture && session.parameters.target_path == 0) {
+       } else if (gSessionData->mLocalCapture && session.parameters.target_path == 0) {
                logg->logError(__FILE__, __LINE__, "Missing target_path tag in session xml required for a local capture.");
                handleException();
        }
 
        // Set session data values
        if (strcmp(session.parameters.sample_rate, "high") == 0) {
-               gSessionData.mSampleRate = 10000;
+               gSessionData->mSampleRate = 10000;
        } else if (strcmp(session.parameters.sample_rate, "normal") == 0) {
-               gSessionData.mSampleRate = 1000;
+               gSessionData->mSampleRate = 1000;
        } else { // "low"
-               gSessionData.mSampleRate = 100;
+               gSessionData->mSampleRate = 100;
        }
-       gSessionData.mBacktraceDepth = session.parameters.call_stack_unwinding == true ? 128 : 0;
-       gSessionData.mDuration = session.parameters.duration;
+       gSessionData->mBacktraceDepth = session.parameters.call_stack_unwinding == true ? 128 : 0;
+       gSessionData->mDuration = session.parameters.duration;
 
        // Determine buffer size (in MB) based on buffer mode
-       gSessionData.mOneShot = true;
+       gSessionData->mOneShot = true;
        if (strcmp(session.parameters.buffer_mode, "streaming") == 0) {
-               gSessionData.mOneShot = false;
-               gSessionData.mTotalBufferSize = 1;
+               gSessionData->mOneShot = false;
+               gSessionData->mTotalBufferSize = 1;
        } else if (strcmp(session.parameters.buffer_mode, "small") == 0) {
-               gSessionData.mTotalBufferSize = 1;
+               gSessionData->mTotalBufferSize = 1;
        } else if (strcmp(session.parameters.buffer_mode, "normal") == 0) {
-               gSessionData.mTotalBufferSize = 4;
+               gSessionData->mTotalBufferSize = 4;
        } else if (strcmp(session.parameters.buffer_mode, "large") == 0) {
-               gSessionData.mTotalBufferSize = 16;
+               gSessionData->mTotalBufferSize = 16;
        } else {
                logg->logError(__FILE__, __LINE__, "Invalid value for buffer mode in session xml.");
                handleException();
        }
 
-       gSessionData.images = session.parameters.images;
-       gSessionData.target_path = session.parameters.target_path;
-       gSessionData.title = session.parameters.title;
+       gSessionData->images = session.parameters.images;
+       gSessionData->target_path = session.parameters.target_path;
+       gSessionData->title = session.parameters.title;
 }
index f3ae4a35614ebbdec429e54b29ada9cfc05fb78c..cc188f8e694ac6ba1fdd05b7e6408b508083c862 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,7 +13,7 @@
 #define MAX_STRING_LEN                         80
 #define MAX_DESCRIPTION_LEN                    400
 
-#define PROTOCOL_VERSION       7
+#define PROTOCOL_VERSION       8
 #define PROTOCOL_DEV           1000    // Differentiates development versions (timestamp) from release versions
 
 struct ImageLinkList {
@@ -31,6 +31,7 @@ public:
 
        char mCoreName[MAX_STRING_LEN];
        struct ImageLinkList *images;
+       char* configurationXMLPath;
        char* target_path;
        char* apcDir;
        char* title;
@@ -62,6 +63,6 @@ public:
        char mPerfCounterOperation[MAX_PERFORMANCE_COUNTERS][MAX_STRING_LEN];
 };
 
-extern SessionData gSessionData;
+extern SessionData* gSessionData;
 
 #endif // SESSION_DATA_H
index 5034e48229c95e2e1562ca02dd55b6d87ddba73d..4604d7cf1937a036c3a2e4f39d4a31849cb256d3 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index b52b57f12ba0cfd55e4f412666650145ecce8157..4649685bc9e197224932f2335dbbbf590725b284 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 80a4ebbdb58733240af5a4b2d87f9da4bf7d0a9b..5662ee8c76ff8f092bc7a0925cbc8b9d4f78bc09 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2011. All rights reserved.
+ * Copyright (C) ARM Limited 2011-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -41,7 +41,7 @@ StreamlineSetup::StreamlineSetup(OlySocket* s) {
        // Receive commands from Streamline (master)
        while (!ready) {
                // receive command over socket
-               gSessionData.mWaitingOnCommand = true;
+               gSessionData->mWaitingOnCommand = true;
                data = readCommand(&type);
 
                // parse and handle data
@@ -57,16 +57,12 @@ StreamlineSetup::StreamlineSetup(OlySocket* s) {
                                ready = true;
                                break;
                        case COMMAND_APC_STOP:
-                               // Clear error log so no text appears on console and exit
                                logg->logMessage("Received apc stop request before apc start request");
-                               logg->logError(__FILE__, __LINE__, "");
-                               handleException();
+                               exit(0);
                                break;
                        case COMMAND_DISCONNECT:
-                               // Clear error log so no text appears on console and exit
                                logg->logMessage("Received disconnect command");
-                               logg->logError(__FILE__, __LINE__, "");
-                               handleException();
+                               exit(0);
                                break;
                        case COMMAND_PING:
                                logg->logMessage("Received ping command");
@@ -95,7 +91,7 @@ char* StreamlineSetup::readCommand(int* command) {
        response = socket->receiveNBytes(&type, sizeof(type));
 
        // After receiving a single byte, we are no longer waiting on a command
-       gSessionData.mWaitingOnCommand = false;
+       gSessionData->mWaitingOnCommand = false;
 
        if (response < 0) {
                logg->logError(__FILE__, __LINE__, "Target error: Unexpected socket disconnect");
@@ -196,7 +192,7 @@ void StreamlineSetup::handleDeliver(char* xml) {
                        break;
                case SESSION_XML:
                        // Parse the session xml
-                       gSessionData.parseSessionXML(xml);
+                       gSessionData->parseSessionXML(xml);
 
                        // Save xml
                        mSessionXML = strdup(xml);
@@ -307,13 +303,19 @@ void StreamlineSetup::sendCounters() {
 void StreamlineSetup::writeConfiguration(char* xml) {
        char* path = (char*)malloc(PATH_MAX);
 
-       util->getApplicationFullPath(path, PATH_MAX);
-       strncat(path, "configuration.xml", PATH_MAX - strlen(path) - 1);
+       if (gSessionData->configurationXMLPath) {
+               strncpy(path, gSessionData->configurationXMLPath, PATH_MAX);
+       } else {
+               util->getApplicationFullPath(path, PATH_MAX);
+               strncat(path, "configuration.xml", PATH_MAX - strlen(path) - 1);
+       }
+
        if (util->writeToDisk(path, xml) < 0) {
                logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify write permissions to this path.", path);
                handleException();
        }
 
+       // Re-populate gSessionData with the configuration, as it has now changed
        new ConfigurationXML();
        free(path);
 }
index c090afb222dc606b99a7cbbdc49a6a6131102225..10327e00bc7f2874e45d2cf662ad6577aefb652b 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 647e799a9aa779b33bf4980458d525c2c13c3c9c..c194fc0042d3d7d7a3d94cee686fb60ebd645ef4 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 479cfa95e81b03a714df23e7301f0e77aae63e36..3af253dbe83663efc9211b80cbc60e7d22622058 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 45231edd8373a447283d209ac5f91fb719bd56f6..77c76e29d73dda9a5718991601af0c623b3573ce 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 55f655b8306b434c72badfd547c985de6ccf6705..ac0098add0a83e370a69019dcc3b89d250c4728f 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
index 48a614ee6239b5b497eb2155194a9244cde2f7e9..5742271c29b89d9482e1856baf667c763479384f 100644 (file)
@@ -1,43 +1,43 @@
-  <counter_set name="ARM_ARM11_cntX">
-    <counter name="ARM_ARM11_cnt0"/>
-    <counter name="ARM_ARM11_cnt1"/>
-    <counter name="ARM_ARM11_cnt2"/>
-  </counter_set>
-  <category name="ARM11" counter_set="ARM_ARM11_cntX" per_cpu="yes">
-    <event counter="ARM_ARM11_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>
-    <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>
-    <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>
-    <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>
-    <event event="0x03" title="Cache" name="Inst micro TLB miss" description="Instruction MicroTLB miss (unused on ARM1156)"/>
-    <event event="0x04" title="Cache" name="Data micro TLB miss" description="Data MicroTLB miss (unused on ARM1156)"/>
-    <event event="0x05" title="Branch" name="Instruction executed" description="Branch instruction executed, branch might or might not have changed program flow"/>
-    <event event="0x06" title="Branch" name="Mispredicted" description="Branch mis-predicted"/>
-    <event event="0x07" title="Instruction" name="Executed" description="Instructions executed"/>
-    <event event="0x09" title="Cache" name="Data access" description="Data cache access, not including Cache operations"/>
-    <event event="0x0a" title="Cache" name="Data all access" description="Data cache access, not including Cache Operations regardless of whether or not the location is cacheable"/>
-    <event event="0x0b" title="Cache" name="Data miss" description="Data cache miss, not including Cache Operations"/>
-    <event event="0x0c" title="Cache" name="Write-back" description="Data cache write-back"/>
-    <event event="0x0d" title="Program Counter" name="SW change" description="Software changed the PC"/>
-    <event event="0x0f" title="Cache " name="TLB miss" description="Main TLB miss (unused on ARM1156)"/>
-    <event event="0x10" title="External" name="Access" description="Explicit external data or peripheral access"/>
-    <event event="0x11" title="Cache" name="Data miss" description="Stall because of Load Store Unit request queue being full"/>
-    <event event="0x12" title="Write Buffer" name="Drains" description="The number of times the Write Buffer was drained because of a Data Synchronization Barrier command or Strongly Ordered operation"/>
-    <event event="0x13" title="Disable Interrupts" name="FIQ" description="The number of cycles which FIQ interrupts are disabled (ARM1156 only)"/>
-    <event event="0x14" title="Disable Interrupts" name="IRQ" description="The number of cycles which IRQ interrupts are disabled (ARM1156 only)"/>
-    <event event="0x20" title="ETM" name="ETMEXTOUT[0]" description="ETMEXTOUT[0] signal was asserted for a cycle"/>
-    <event event="0x21" title="ETM" name="ETMEXTOUT[1]" description="ETMEXTOUT[1] signal was asserted for a cycle"/>
-    <event event="0x22" title="ETM" name="ETMEXTOUT[0,1]" description="ETMEXTOUT[0] or ETMEXTOUT[1] was asserted"/>
-    <event event="0x23" title="Procedure" name="Calls" description="Procedure call instruction executed"/>
-    <event event="0x24" title="Procedure" name="Returns" description="Procedure return instruction executed"/>
-    <event event="0x25" title="Procedure" name="Return and predicted" description="Procedure return instruction executed and return address predicted"/>
-    <event event="0x26" title="Procedure" name="Return and mispredicted" description="Procedure return instruction executed and return address predicted incorrectly"/>
-    <event event="0x30" title="Cache" name="Inst tag or parity error" description="Instruction cache Tag or Valid RAM parity error (ARM1156 only)"/>
-    <event event="0x31" title="Cache" name="Inst parity error" description="Instruction cache RAM parity error (ARM1156 only)"/>
-    <event event="0x32" title="Cache" name="Data tag or parity error" description="Data cache Tag or Valid RAM parity error (ARM1156 only)"/>
-    <event event="0x33" title="Cache" name="Data parity error" description="Data cache RAM parity error (ARM1156 only)"/>
-    <event event="0x34" title="ITCM" name="Error" description="ITCM error (ARM1156 only)"/>
-    <event event="0x35" title="DTCM" name="Error" description="DTCM error (ARM1156 only)"/>
-    <event event="0x36" title="Procedure" name="Return address pop" description="Procedure return address popped off the return stack (ARM1156 only)"/>
-    <event event="0x37" title="Procedure" name="Return address misprediction" description="Procedure return address popped off the return stack has been incorrectly predicted by the PFU (ARM1156 only)"/>
-    <event event="0x38" title="Cache" name="Data dirty parity error" description="Data cache Dirty RAM parity error (ARM1156 only)"/>
-  </category>
+  <counter_set name="ARM_ARM11_cntX">\r
+    <counter name="ARM_ARM11_cnt0"/>\r
+    <counter name="ARM_ARM11_cnt1"/>\r
+    <counter name="ARM_ARM11_cnt2"/>\r
+  </counter_set>\r
+  <category name="ARM11" counter_set="ARM_ARM11_cntX" per_cpu="yes">\r
+    <event counter="ARM_ARM11_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>\r
+    <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>\r
+    <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>\r
+    <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>\r
+    <event event="0x03" title="Cache" name="Inst micro TLB miss" description="Instruction MicroTLB miss (unused on ARM1156)"/>\r
+    <event event="0x04" title="Cache" name="Data micro TLB miss" description="Data MicroTLB miss (unused on ARM1156)"/>\r
+    <event event="0x05" title="Branch" name="Instruction executed" description="Branch instruction executed, branch might or might not have changed program flow"/>\r
+    <event event="0x06" title="Branch" name="Mispredicted" description="Branch mis-predicted"/>\r
+    <event event="0x07" title="Instruction" name="Executed" description="Instructions executed"/>\r
+    <event event="0x09" title="Cache" name="Data access" description="Data cache access, not including Cache operations"/>\r
+    <event event="0x0a" title="Cache" name="Data all access" description="Data cache access, not including Cache Operations regardless of whether or not the location is cacheable"/>\r
+    <event event="0x0b" title="Cache" name="Data miss" description="Data cache miss, not including Cache Operations"/>\r
+    <event event="0x0c" title="Cache" name="Write-back" description="Data cache write-back"/>\r
+    <event event="0x0d" title="Program Counter" name="SW change" description="Software changed the PC"/>\r
+    <event event="0x0f" title="Cache " name="TLB miss" description="Main TLB miss (unused on ARM1156)"/>\r
+    <event event="0x10" title="External" name="Access" description="Explicit external data or peripheral access"/>\r
+    <event event="0x11" title="Cache" name="Data miss" description="Stall because of Load Store Unit request queue being full"/>\r
+    <event event="0x12" title="Write Buffer" name="Drains" description="The number of times the Write Buffer was drained because of a Data Synchronization Barrier command or Strongly Ordered operation"/>\r
+    <event event="0x13" title="Disable Interrupts" name="FIQ" description="The number of cycles which FIQ interrupts are disabled (ARM1156 only)"/>\r
+    <event event="0x14" title="Disable Interrupts" name="IRQ" description="The number of cycles which IRQ interrupts are disabled (ARM1156 only)"/>\r
+    <event event="0x20" title="ETM" name="ETMEXTOUT[0]" description="ETMEXTOUT[0] signal was asserted for a cycle"/>\r
+    <event event="0x21" title="ETM" name="ETMEXTOUT[1]" description="ETMEXTOUT[1] signal was asserted for a cycle"/>\r
+    <event event="0x22" title="ETM" name="ETMEXTOUT[0,1]" description="ETMEXTOUT[0] or ETMEXTOUT[1] was asserted"/>\r
+    <event event="0x23" title="Procedure" name="Calls" description="Procedure call instruction executed"/>\r
+    <event event="0x24" title="Procedure" name="Returns" description="Procedure return instruction executed"/>\r
+    <event event="0x25" title="Procedure" name="Return and predicted" description="Procedure return instruction executed and return address predicted"/>\r
+    <event event="0x26" title="Procedure" name="Return and mispredicted" description="Procedure return instruction executed and return address predicted incorrectly"/>\r
+    <event event="0x30" title="Cache" name="Inst tag or parity error" description="Instruction cache Tag or Valid RAM parity error (ARM1156 only)"/>\r
+    <event event="0x31" title="Cache" name="Inst parity error" description="Instruction cache RAM parity error (ARM1156 only)"/>\r
+    <event event="0x32" title="Cache" name="Data tag or parity error" description="Data cache Tag or Valid RAM parity error (ARM1156 only)"/>\r
+    <event event="0x33" title="Cache" name="Data parity error" description="Data cache RAM parity error (ARM1156 only)"/>\r
+    <event event="0x34" title="ITCM" name="Error" description="ITCM error (ARM1156 only)"/>\r
+    <event event="0x35" title="DTCM" name="Error" description="DTCM error (ARM1156 only)"/>\r
+    <event event="0x36" title="Procedure" name="Return address pop" description="Procedure return address popped off the return stack (ARM1156 only)"/>\r
+    <event event="0x37" title="Procedure" name="Return address misprediction" description="Procedure return address popped off the return stack has been incorrectly predicted by the PFU (ARM1156 only)"/>\r
+    <event event="0x38" title="Cache" name="Data dirty parity error" description="Data cache Dirty RAM parity error (ARM1156 only)"/>\r
+  </category>\r
index 78a4b176c3a742938c5bdc29fa50f8daf1645aa6..86a3d17e9d8b0fb42e54d83e4a4a9efbb33f7976 100644 (file)
@@ -1,77 +1,77 @@
-  <counter_set name="ARM_Cortex-A15_cntX">
-    <counter name="ARM_Cortex-A15_cnt0"/>
-    <counter name="ARM_Cortex-A15_cnt1"/>
-    <counter name="ARM_Cortex-A15_cnt2"/>
-    <counter name="ARM_Cortex-A15_cnt3"/>
-    <counter name="ARM_Cortex-A15_cnt4"/>
-    <counter name="ARM_Cortex-A15_cnt5"/>
-  </counter_set>
-  <category name="Cortex-A15" counter_set="ARM_Cortex-A15_cntX" per_cpu="yes" event_based_sampling="yes">
-    <event counter="ARM_Cortex-A15_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>
-    <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>
-    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
-    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
-    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
-    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
-    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
-    <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
-    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
-    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
-    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
-    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
-       <event event="0x11" title="Cycle" name="Cycle" description=""/>
-    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
-    <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
-    <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>
-    <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
-       <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
-       <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
-       <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
-       <event event="0x19" title="Bus" name="Access" description=""/>
-       <event event="0x1a" title="Memory" name="Error" description="Local memory error"/>
-       <event event="0x1b" title="Instruction" name="Speculative" description="Instruction speculatively executed"/>
-       <event event="0x1c" title="Memory" name="Translation table" description="Write to translation table base architecturally executed"/>
-       <event event="0x1d" title="Bus" name="Cycle" description=""/>
-    <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
-    <event event="0x41" title="Cache" name="L1 data write" description="Level 1 data cache access - Write"/>
-    <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
-    <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
-    <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-Back - Victim"/>
-    <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-Back - Cleaning and coherency"/>
-    <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
-    <event event="0x4c" title="TLB" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
-    <event event="0x4d" title="TLB" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
-    <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
-    <event event="0x51" title="Cache" name="L2 data write" description="Level 2 data cache access - Write"/>
-    <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
-    <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
-    <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-Back - Victim"/>
-    <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-Back - Cleaning and coherency"/>
-    <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
-    <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
-    <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
-    <event event="0x64" title="Bus" name="Access" description="Bus access - Normal"/>
-    <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
-    <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
-    <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
-    <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
-    <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
-       <event event="0x6a" title="Memory" name="Unaligned" description="Unaligned access"/>
-       <event event="0x6c" title="Intrinsic" name="LDREX" description="Exclusive instruction speculatively executed - LDREX"/>
-       <event event="0x6d" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
-       <event event="0x6e" title="Intrinsic" name="STREX fail" description="Exclusive instruction speculatively executed - STREX fail"/>
-    <event event="0x70" title="Instructions" name="Load" description="Instruction speculatively executed - Load"/>
-    <event event="0x71" title="Instructions" name="Store" description="Instruction speculatively executed - Store"/>
-    <event event="0x72" title="Instructions" name="Load/Store" description="Instruction speculatively executed - Load or store"/>
-    <event event="0x73" title="Instructions" name="Integer" description="Instruction speculatively executed - Integer data processing"/>
-    <event event="0x74" title="Instructions" name="Advanced SIMD" description="Instruction speculatively executed - Advanced SIMD"/>
-    <event event="0x75" title="Instructions" name="VFP" description="Instruction speculatively executed - VFP"/>
-    <event event="0x76" title="Instructions" name="Software change" description="Instruction speculatively executed - Software change of the PC"/>
-    <event event="0x78" title="Instructions" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
-    <event event="0x79" title="Instructions" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
-    <event event="0x7a" title="Instructions" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
-    <event event="0x7c" title="Instructions" name="ISB" description="Barrier speculatively executed - ISB"/>
-    <event event="0x7d" title="Instructions" name="DSB" description="Barrier speculatively executed - DSB"/>
-    <event event="0x7e" title="Instructions" name="DMB" description="Barrier speculatively executed - DMB"/>
-  </category>  
+  <counter_set name="ARM_Cortex-A15_cntX">\r
+    <counter name="ARM_Cortex-A15_cnt0"/>\r
+    <counter name="ARM_Cortex-A15_cnt1"/>\r
+    <counter name="ARM_Cortex-A15_cnt2"/>\r
+    <counter name="ARM_Cortex-A15_cnt3"/>\r
+    <counter name="ARM_Cortex-A15_cnt4"/>\r
+    <counter name="ARM_Cortex-A15_cnt5"/>\r
+  </counter_set>\r
+  <category name="Cortex-A15" counter_set="ARM_Cortex-A15_cntX" per_cpu="yes" event_based_sampling="yes">\r
+    <event counter="ARM_Cortex-A15_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>\r
+    <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>\r
+    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>\r
+    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>\r
+    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>\r
+    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>\r
+    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>\r
+    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>\r
+       <event event="0x11" title="Cycle" name="Cycle" description=""/>\r
+    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>\r
+    <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>\r
+    <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>\r
+    <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>\r
+       <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>\r
+       <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>\r
+       <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>\r
+       <event event="0x19" title="Bus" name="Access" description=""/>\r
+       <event event="0x1a" title="Memory" name="Error" description="Local memory error"/>\r
+       <event event="0x1b" title="Instruction" name="Speculative" description="Instruction speculatively executed"/>\r
+       <event event="0x1c" title="Memory" name="Translation table" description="Write to translation table base architecturally executed"/>\r
+       <event event="0x1d" title="Bus" name="Cycle" description=""/>\r
+    <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>\r
+    <event event="0x41" title="Cache" name="L1 data write" description="Level 1 data cache access - Write"/>\r
+    <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>\r
+    <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>\r
+    <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-Back - Victim"/>\r
+    <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-Back - Cleaning and coherency"/>\r
+    <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>\r
+    <event event="0x4c" title="TLB" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>\r
+    <event event="0x4d" title="TLB" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>\r
+    <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>\r
+    <event event="0x51" title="Cache" name="L2 data write" description="Level 2 data cache access - Write"/>\r
+    <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>\r
+    <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>\r
+    <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-Back - Victim"/>\r
+    <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-Back - Cleaning and coherency"/>\r
+    <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>\r
+    <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>\r
+    <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>\r
+    <event event="0x64" title="Bus" name="Access" description="Bus access - Normal"/>\r
+    <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>\r
+    <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>\r
+    <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>\r
+    <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>\r
+    <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>\r
+       <event event="0x6a" title="Memory" name="Unaligned" description="Unaligned access"/>\r
+       <event event="0x6c" title="Intrinsic" name="LDREX" description="Exclusive instruction speculatively executed - LDREX"/>\r
+       <event event="0x6d" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>\r
+       <event event="0x6e" title="Intrinsic" name="STREX fail" description="Exclusive instruction speculatively executed - STREX fail"/>\r
+    <event event="0x70" title="Instructions" name="Load" description="Instruction speculatively executed - Load"/>\r
+    <event event="0x71" title="Instructions" name="Store" description="Instruction speculatively executed - Store"/>\r
+    <event event="0x72" title="Instructions" name="Load/Store" description="Instruction speculatively executed - Load or store"/>\r
+    <event event="0x73" title="Instructions" name="Integer" description="Instruction speculatively executed - Integer data processing"/>\r
+    <event event="0x74" title="Instructions" name="Advanced SIMD" description="Instruction speculatively executed - Advanced SIMD"/>\r
+    <event event="0x75" title="Instructions" name="VFP" description="Instruction speculatively executed - VFP"/>\r
+    <event event="0x76" title="Instructions" name="Software change" description="Instruction speculatively executed - Software change of the PC"/>\r
+    <event event="0x78" title="Instructions" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>\r
+    <event event="0x79" title="Instructions" name="Procedure return" description="Branch speculatively executed - Procedure return"/>\r
+    <event event="0x7a" title="Instructions" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>\r
+    <event event="0x7c" title="Instructions" name="ISB" description="Barrier speculatively executed - ISB"/>\r
+    <event event="0x7d" title="Instructions" name="DSB" description="Barrier speculatively executed - DSB"/>\r
+    <event event="0x7e" title="Instructions" name="DMB" description="Barrier speculatively executed - DMB"/>\r
+  </category>  \r
   
\ No newline at end of file
index 3e2f5b27516505a19bab4ac4b69990d4b22018a1..3683947cbe565c659a0d14673f256c6b795c4ec4 100644 (file)
@@ -1,39 +1,39 @@
-  <counter_set name="ARM_Cortex-A5_cntX">
-    <counter name="ARM_Cortex-A5_cnt0"/>
-    <counter name="ARM_Cortex-A5_cnt1"/>
-  </counter_set>
-  <category name="Cortex-A5" counter_set="ARM_Cortex-A5_cntX" per_cpu="yes" event_based_sampling="yes">
-    <event counter="ARM_Cortex-A5_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>
-    <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
-    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
-    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
-    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
-    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
-    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
-    <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
-    <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
-    <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
-    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
-    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
-    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
-    <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
-    <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
-    <event event="0x0e" title="Procedure" name="Return" description="Procedure return, other than exception return, architecturally executed"/>
-    <event event="0x0f" title="Fault" name="Unaligned access" description="Unaligned access architecturally executed"/>
-    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
-    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
-    <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
-    <event event="0x14" title="Cache" name="Instruction access" description="Instruction cache access"/>
-    <event event="0x15" title="Cache" name="Data eviction" description="Data cache eviction"/>
-    <event event="0x86" title="Interrupts" name="IRQ" description="IRQ exception taken"/>
-    <event event="0x87" title="Interrupts" name="FIQ" description="FIQ exception taken"/>
-    <event event="0xC0" title="Memory" name="External request" description="External memory request"/>
-    <event event="0xC1" title="Memory" name="Non-cacheable ext req" description="Non-cacheable external memory request"/>
-    <event event="0xC2" title="Cache" name="Linefill" description="Linefill because of prefetch"/>
-    <event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/>
-    <event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/>
-    <event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/>
-    <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description=""/>
-    <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description=""/>
-    <event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/>
-  </category>
+  <counter_set name="ARM_Cortex-A5_cntX">\r
+    <counter name="ARM_Cortex-A5_cnt0"/>\r
+    <counter name="ARM_Cortex-A5_cnt1"/>\r
+  </counter_set>\r
+  <category name="Cortex-A5" counter_set="ARM_Cortex-A5_cntX" per_cpu="yes" event_based_sampling="yes">\r
+    <event counter="ARM_Cortex-A5_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>\r
+    <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>\r
+    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>\r
+    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>\r
+    <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>\r
+    <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>\r
+    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>\r
+    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>\r
+    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>\r
+    <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>\r
+    <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>\r
+    <event event="0x0e" title="Procedure" name="Return" description="Procedure return, other than exception return, architecturally executed"/>\r
+    <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>\r
+    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>\r
+    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>\r
+    <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>\r
+    <event event="0x14" title="Cache" name="Instruction access" description="Instruction cache access"/>\r
+    <event event="0x15" title="Cache" name="Data eviction" description="Data cache eviction"/>\r
+    <event event="0x86" title="Interrupts" name="IRQ" description="IRQ exception taken"/>\r
+    <event event="0x87" title="Interrupts" name="FIQ" description="FIQ exception taken"/>\r
+    <event event="0xC0" title="Memory" name="External request" description="External memory request"/>\r
+    <event event="0xC1" title="Memory" name="Non-cacheable ext req" description="Non-cacheable external memory request"/>\r
+    <event event="0xC2" title="Cache" name="Linefill" description="Linefill because of prefetch"/>\r
+    <event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/>\r
+    <event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/>\r
+    <event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/>\r
+    <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description=""/>\r
+    <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description=""/>\r
+    <event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/>\r
+  </category>\r
diff --git a/daemon/events-Cortex-A7.xml b/daemon/events-Cortex-A7.xml
new file mode 100644 (file)
index 0000000..db9f180
--- /dev/null
@@ -0,0 +1,50 @@
+  <counter_set name="ARM_Cortex-A7_cntX">\r
+    <counter name="ARM_Cortex-A7_cnt0"/>\r
+    <counter name="ARM_Cortex-A7_cnt1"/>\r
+    <counter name="ARM_Cortex-A7_cnt2"/>\r
+    <counter name="ARM_Cortex-A7_cnt3"/>\r
+  </counter_set>\r
+  <category name="Cortex-A7" counter_set="ARM_Cortex-A7_cntX" per_cpu="yes" event_based_sampling="yes">\r
+    <event counter="ARM_Cortex-A7_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>\r
+    <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>\r
+    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>\r
+    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x06" title="Memory" name="Data Read" description="Data read architecturally executed"/>\r
+    <event event="0x07" title="Memory" name="Data Write" description="Data write architecturally executed"/>\r
+       <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>\r
+    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>\r
+    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>\r
+    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>\r
+    <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>\r
+    <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>\r
+    <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>\r
+    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>\r
+       <event event="0x11" title="Cycle" name="Counter" description=""/>\r
+    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>\r
+    <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>\r
+    <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>\r
+    <event event="0x15" title="Cache" name="L1 data eviction" description="Level 1 data cache eviction"/>\r
+       <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>\r
+       <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>\r
+       <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>\r
+       <event event="0x19" title="Bus" name="Access" description=""/>\r
+       <event event="0x1d" title="Bus" name="Cycle" description=""/>\r
+    <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>\r
+    <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>\r
+       <event event="0x86" title="Exception" name="IRQ" description="IRQ exception taken"/>\r
+       <event event="0x87" title="Exception" name="FIQ" description="FIQ exception taken"/>\r
+    <event event="0xC0" title="Memory" name="External request" description="External memory request"/>\r
+    <event event="0xC1" title="Memory" name="Non-cacheable ext req" description="Non-cacheable external memory request"/>\r
+    <event event="0xC2" title="Cache" name="Linefill" description="Linefill because of prefetch"/>\r
+    <event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/>\r
+    <event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/>\r
+    <event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/>\r
+    <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description=""/>\r
+    <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description=""/>\r
+    <event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/>\r
+    <event event="0xCA" title="Memory" name="Snoop" description="Data snooped from other processor. This event counts memory-read operations that read data from another processor within the local cluster, rather than accessing the L2 cache or issuing an external read."/>\r
+  </category>  \r
+  
\ No newline at end of file
index 1f78b0c9986ef5d0639824b999c90206ca96a3e3..f3396b71144103bc941e884731cf6de312ea4a16 100644 (file)
@@ -1,58 +1,58 @@
-  <counter_set name="ARM_Cortex-A8_cntX">
-    <counter name="ARM_Cortex-A8_cnt0"/>
-    <counter name="ARM_Cortex-A8_cnt1"/>
-    <counter name="ARM_Cortex-A8_cnt2"/>
-    <counter name="ARM_Cortex-A8_cnt3"/>
-  </counter_set>
-  <category name="Cortex-A8" counter_set="ARM_Cortex-A8_cntX" per_cpu="yes" event_based_sampling="yes">
-    <event counter="ARM_Cortex-A8_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>
-    <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
-    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
-    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
-    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
-    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
-    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
-    <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
-    <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
-    <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
-    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
-    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
-    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
-    <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
-    <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
-    <event event="0x0e" title="Procedure" name="Return" description="Procedure return, other than exception return, architecturally executed"/>
-    <event event="0x0f" title="Fault" name="Unaligned access" description="Unaligned access architecturally executed"/>
-    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
-    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
-    <event event="0x40" title="Cache" name="Write buffer full" description="Any write buffer full cycle"/>
-    <event event="0x41" title="Cache" name="L2 store" description="Any store that is merged in the L2 memory system"/>
-    <event event="0x42" title="Cache" name="Bufferable transaction" description="Any bufferable store transaction from load/store to L2 cache, excluding eviction or cast out data"/>
-    <event event="0x43" title="Cache" name="L1 miss" description="Any accesses to the L2 cache"/>
-    <event event="0x44" title="Cache" name="L2 miss" description="Any cacheable miss in the L2 cache"/>
-    <event event="0x45" title="AXI" name="Read" description="The number of AXI read data transfers"/>
-    <event event="0x46" title="AXI" name="Write" description="The number of AXI write data transfers"/>
-    <event event="0x47" title="Memory" name="Replay event" description="Any replay event in the memory system"/>
-    <event event="0x48" title="Memory" name="Unaligned access" description="Any unaligned memory access that results in a replay"/>
-    <event event="0x49" title="Cache" name="L1 data miss" description="Any L1 data memory access that misses in the cache as a result of the hashing algorithm"/>
-    <event event="0x4a" title="Cache" name="L1 inst miss" description="Any L1 instruction memory access that misses in the cache as a result of the hashing algorithm"/>
-    <event event="0x4b" title="Cache" name="L1 page coloring" description="Any L1 data memory access in which a page coloring alias occurs"/>
-    <event event="0x4c" title="NEON" name="L1 cache hit" description="Any NEON access that hits in the L1 data cache"/>
-    <event event="0x4d" title="NEON" name="L1 cache access" description="Any NEON cacheable data accesses for L1 data cache"/>
-    <event event="0x4e" title="NEON" name="L2 cache access" description="Any L2 cache accesses as a result of a NEON memory access"/>
-    <event event="0x4f" title="NEON" name="L2 cache hit" description="Any NEON hit in the L2 cache"/>
-    <event event="0x50" title="Cache" name="L1 inst access" description="Any L1 instruction cache access, excluding CP15 cache accesses"/>
-    <event event="0x51" title="Branch" name="Return stack misprediction" description="Any return stack misprediction because of incorrect target address for a taken return stack pop"/>
-    <event event="0x52" title="Branch" name="Direction misprediction" description="Branch direction misprediction"/>
-    <event event="0x53" title="Branch" name="Taken prediction" description="Any predictable branch that is predicted to be taken"/>
-    <event event="0x54" title="Branch" name="Executed and taken prediction" description="Any predictable branch that is executed and taken"/>
-    <event event="0x55" title="Core" name="Operations issued" description="Number of operations issued, where an operation is either: an instruction or one operation in a sequence of operations that make up a multi-cycle instruction"/>
-    <event event="0x56" title="Core" name="No issue cycles" description="Increment for every cycle that no instructions are available for issue"/>
-    <event event="0x57" title="Core" name="Issue cycles" description="For every cycle, this event counts the number of instructions issued in that cycle. Multi-cycle instructions are only counted once"/>
-    <event event="0x58" title="NEON" name="MRC data wait" description="Number of cycles the processor stalls waiting on MRC data from NEON"/>
-    <event event="0x59" title="NEON" name="Full queue" description="Number of cycles that the processor stalls as a result of a full NEON instruction queue or NEON load queue"/>
-    <event event="0x5a" title="NEON" name="Idle" description="Number of cycles that NEON and integer processors are both not idle"/>
-    <event event="0x70" title="External" name="PMUEXTIN[0]" description="Counts any event from external input source PMUEXTIN[0]"/>
-    <event event="0x71" title="External" name="PMUEXTIN[1]" description="Counts any event from external input source PMUEXTIN[1]"/>
-    <event event="0x72" title="External" name="PMUEXTIN[0,1]" description="Counts any event from both external input sources PMUEXTIN[0] and PMUEXTIN[1]"/>
-  </category>
+  <counter_set name="ARM_Cortex-A8_cntX">\r
+    <counter name="ARM_Cortex-A8_cnt0"/>\r
+    <counter name="ARM_Cortex-A8_cnt1"/>\r
+    <counter name="ARM_Cortex-A8_cnt2"/>\r
+    <counter name="ARM_Cortex-A8_cnt3"/>\r
+  </counter_set>\r
+  <category name="Cortex-A8" counter_set="ARM_Cortex-A8_cntX" per_cpu="yes" event_based_sampling="yes">\r
+    <event counter="ARM_Cortex-A8_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>\r
+    <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>\r
+    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>\r
+    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>\r
+    <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>\r
+    <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>\r
+    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>\r
+    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>\r
+    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>\r
+    <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>\r
+    <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>\r
+    <event event="0x0e" title="Procedure" name="Return" description="Procedure return, other than exception return, architecturally executed"/>\r
+    <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>\r
+    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>\r
+    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>\r
+    <event event="0x40" title="Cache" name="Write buffer full" description="Any write buffer full cycle"/>\r
+    <event event="0x41" title="Cache" name="L2 store" description="Any store that is merged in the L2 memory system"/>\r
+    <event event="0x42" title="Cache" name="Bufferable transaction" description="Any bufferable store transaction from load/store to L2 cache, excluding eviction or cast out data"/>\r
+    <event event="0x43" title="Cache" name="L1 miss" description="Any accesses to the L2 cache"/>\r
+    <event event="0x44" title="Cache" name="L2 miss" description="Any cacheable miss in the L2 cache"/>\r
+    <event event="0x45" title="AXI" name="Read" description="The number of AXI read data transfers"/>\r
+    <event event="0x46" title="AXI" name="Write" description="The number of AXI write data transfers"/>\r
+    <event event="0x47" title="Memory" name="Replay event" description="Any replay event in the memory system"/>\r
+    <event event="0x48" title="Memory" name="Unaligned access" description="Any unaligned memory access that results in a replay"/>\r
+    <event event="0x49" title="Cache" name="L1 data hash miss" description="Any L1 data memory access that misses in the cache as a result of the hashing algorithm"/>\r
+    <event event="0x4a" title="Cache" name="L1 inst hash miss" description="Any L1 instruction memory access that misses in the cache as a result of the hashing algorithm"/>\r
+    <event event="0x4b" title="Cache" name="L1 page coloring" description="Any L1 data memory access in which a page coloring alias occurs"/>\r
+    <event event="0x4c" title="NEON" name="L1 cache hit" description="Any NEON access that hits in the L1 data cache"/>\r
+    <event event="0x4d" title="NEON" name="L1 cache access" description="Any NEON cacheable data accesses for L1 data cache"/>\r
+    <event event="0x4e" title="NEON" name="L2 cache access" description="Any L2 cache accesses as a result of a NEON memory access"/>\r
+    <event event="0x4f" title="NEON" name="L2 cache hit" description="Any NEON hit in the L2 cache"/>\r
+    <event event="0x50" title="Cache" name="L1 inst access" description="Any L1 instruction cache access, excluding CP15 cache accesses"/>\r
+    <event event="0x51" title="Branch" name="Return stack misprediction" description="Any return stack misprediction because of incorrect target address for a taken return stack pop"/>\r
+    <event event="0x52" title="Branch" name="Direction misprediction" description="Branch direction misprediction"/>\r
+    <event event="0x53" title="Branch" name="Taken prediction" description="Any predictable branch that is predicted to be taken"/>\r
+    <event event="0x54" title="Branch" name="Executed and taken prediction" description="Any predictable branch that is executed and taken"/>\r
+    <event event="0x55" title="Core" name="Operations issued" description="Number of operations issued, where an operation is either: an instruction or one operation in a sequence of operations that make up a multi-cycle instruction"/>\r
+    <event event="0x56" title="Core" name="No issue cycles" description="Increment for every cycle that no instructions are available for issue"/>\r
+    <event event="0x57" title="Core" name="Issue cycles" description="For every cycle, this event counts the number of instructions issued in that cycle. Multi-cycle instructions are only counted once"/>\r
+    <event event="0x58" title="NEON" name="MRC data wait" description="Number of cycles the processor stalls waiting on MRC data from NEON"/>\r
+    <event event="0x59" title="NEON" name="Full queue" description="Number of cycles that the processor stalls as a result of a full NEON instruction queue or NEON load queue"/>\r
+    <event event="0x5a" title="NEON" name="Idle" description="Number of cycles that NEON and integer processors are both not idle"/>\r
+    <event event="0x70" title="External" name="PMUEXTIN[0]" description="Counts any event from external input source PMUEXTIN[0]"/>\r
+    <event event="0x71" title="External" name="PMUEXTIN[1]" description="Counts any event from external input source PMUEXTIN[1]"/>\r
+    <event event="0x72" title="External" name="PMUEXTIN[0,1]" description="Counts any event from both external input sources PMUEXTIN[0] and PMUEXTIN[1]"/>\r
+  </category>\r
   
\ No newline at end of file
index 7bc2f212f030b34d14197dc7570d758a1d23ac60..1edb54a935934cfc81d36faa568e01e0ce7a36f2 100644 (file)
@@ -1,67 +1,67 @@
-  <counter_set name="ARM_Cortex-A9_cntX">
-    <counter name="ARM_Cortex-A9_cnt0"/>
-    <counter name="ARM_Cortex-A9_cnt1"/>
-    <counter name="ARM_Cortex-A9_cnt2"/>
-    <counter name="ARM_Cortex-A9_cnt3"/>
-    <counter name="ARM_Cortex-A9_cnt4"/>
-    <counter name="ARM_Cortex-A9_cnt5"/>
-  </counter_set>
-  <category name="Cortex-A9" counter_set="ARM_Cortex-A9_cntX" per_cpu="yes" event_based_sampling="yes">
-    <event counter="ARM_Cortex-A9_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>
-    <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
-    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
-    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
-    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
-    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
-    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
-    <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
-    <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
-    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
-    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
-    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
-    <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
-    <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
-    <event event="0x0f" title="Fault" name="Unaligned access" description="Unaligned access architecturally executed"/>
-    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
-    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
-    <event event="0x40" title="Java" name="Bytecode execute" description="Counts the number of Java bytecodes being decoded, including speculative ones"/>
-    <event event="0x41" title="Java" name="SW bytecode execute" description="Counts the number of software java bytecodes being decoded, including speculative ones"/>
-    <event event="0x42" title="Jazelle" name="Backward branch execute" description="Counts the number of Jazelle taken branches being executed"/>
-    <event event="0x50" title="Cache" name="Coherency miss" description="Counts the number of coherent linefill requests performed by the Cortex-A9 processor which also miss in all the other Cortex-A9 processors, meaning that the request is sent to the external memory"/>
-    <event event="0x51" title="Cache" name="Coherency hit" description="Counts the number of coherent linefill requests performed by the Cortex-A9 processor which hit in another Cortex-A9 processor, meaning that the linefill data is fetched directly from the relevant Cortex-A9 cache"/>
-    <event event="0x60" title="Cache" name="Inst dependent stall" description="Counts the number of cycles where the processor is ready to accept new instructions, but does not receive any because of the instruction side not being able to provide any and the instruction cache is currently performing at least one linefill"/>
-    <event event="0x61" title="Cache" name="Data dependent stall" description="Counts the number of cycles where the core has some instructions that it cannot issue to any pipeline, and the Load Store unit has at least one pending linefill request, and no pending TLB requests"/>
-    <event event="0x62" title="Cache" name="TLB stall" description="Counts the number of cycles where the processor is stalled waiting for the completion of translation table walks from the main TLB"/>
-    <event event="0x63" title="Intrinsic" name="STREX pass" description="Counts the number of STREX instructions architecturally executed and passed"/>
-    <event event="0x64" title="Intrinsic" name="STREX fail" description="Counts the number of STREX instructions architecturally executed and failed"/>
-    <event event="0x65" title="Cache" name="Data eviction" description="Counts the number of eviction requests because of a linefill in the data cache"/>
-    <event event="0x66" title="Pipeline" name="Issue stage no dispatch" description="Counts the number of cycles where the issue stage does not dispatch any instruction because it is empty or cannot dispatch any instructions"/>
-    <event event="0x67" title="Pipeline" name="Issue stage empty" description="Counts the number of cycles where the issue stage is empty"/>
-    <event event="0x68" title="Instruction" name="Executed" description="Counts the number of instructions going through the Register Renaming stage. This number is an approximate number of the total number of instructions speculatively executed, and even more approximate of the total number of instructions architecturally executed"/>
-    <event event="0x6E" title="Core" name="Functions" description="Counts the number of procedure returns whose condition codes do not fail, excluding all returns from exception"/>
-    <event event="0x70" title="Instructions" name="Main execution unit" description="Counts the number of instructions being executed in the main execution pipeline of the processor, the multiply pipeline and arithmetic logic unit pipeline"/>
-    <event event="0x71" title="Instructions" name="Second execution unit" description="Counts the number of instructions being executed in the processor second execution pipeline (ALU)"/>
-    <event event="0x72" title="Instructions" name="Load/Store" description="Counts the number of instructions being executed in the Load/Store unit"/>
-    <event event="0x73" title="Instructions" name="Floating point" description="Counts the number of Floating-point instructions going through the Register Rename stage"/>
-    <event event="0x74" title="Instructions" name="NEON" description="Counts the number of NEON instructions going through the Register Rename stage"/>
-    <event event="0x80" title="Stalls" name="PLD" description="Counts the number of cycles where the processor is stalled because PLD slots are all full"/>
-    <event event="0x81" title="Stalls" name="Memory write" description="Counts the number of cycles when the processor is stalled and the data side is stalled too because it is full and executing writes to the external memory"/>
-    <event event="0x82" title="Stalls" name="Inst main TLB miss" description="Counts the number of stall cycles because of main TLB misses on requests issued by the instruction side"/>
-    <event event="0x83" title="Stalls" name="Data main TLB miss" description="Counts the number of stall cycles because of main TLB misses on requests issued by the data side"/>
-    <event event="0x84" title="Stalls" name="Inst micro TLB miss" description="Counts the number of stall cycles because of micro TLB misses on the instruction side"/>
-    <event event="0x85" title="Stalls" name="Data micro TLB miss" description="Counts the number of stall cycles because of micro TLB misses on the data side"/>
-    <event event="0x86" title="Stalls" name="DMB" description="Counts the number of stall cycles because of the execution of a DMB memory barrier"/>
-    <event event="0x8A" title="Clock" name="Integer core" description="Counts the number of cycles during which the integer core clock is enabled"/>
-    <event event="0x8B" title="Clock" name="Data engine" description="Counts the number of cycles during which the Data Engine clock is enabled"/>
-    <event event="0x90" title="Instructions" name="ISB" description="Counts the number of ISB instructions architecturally executed"/>
-    <event event="0x91" title="Instructions" name="DSB" description="Counts the number of DSB instructions architecturally executed"/>
-    <event event="0x92" title="Instructions" name="DMB" description="Counts the number of DMB instructions speculatively executed"/>
-    <event event="0x93" title="External" name="Interrupts" description="Counts the number of external interrupts executed by the processor"/>
-    <event event="0xA0" title="PLE" name="Cache line rq completed" description="Counts the number of PLE cache line requests completed"/>
-    <event event="0xA1" title="PLE" name="Cache line rq skipped" description="Counts the number of PLE cache line requests skipped"/>
-    <event event="0xA2" title="PLE" name="FIFO flush" description="Counts the number of PLE FIFO flush requests"/>
-    <event event="0xA3" title="PLE" name="Request completed" description="Counts the number of PLE FIFO flush completed"/>
-    <event event="0xA4" title="PLE" name="FIFO overflow" description="Counts the number of PLE FIFO flush overflowed"/>
-    <event event="0xA5" title="PLE" name="Request programmed" description="Counts the number of PLE FIFO flush program requests"/>
-  </category>
+  <counter_set name="ARM_Cortex-A9_cntX">\r
+    <counter name="ARM_Cortex-A9_cnt0"/>\r
+    <counter name="ARM_Cortex-A9_cnt1"/>\r
+    <counter name="ARM_Cortex-A9_cnt2"/>\r
+    <counter name="ARM_Cortex-A9_cnt3"/>\r
+    <counter name="ARM_Cortex-A9_cnt4"/>\r
+    <counter name="ARM_Cortex-A9_cnt5"/>\r
+  </counter_set>\r
+  <category name="Cortex-A9" counter_set="ARM_Cortex-A9_cntX" per_cpu="yes" event_based_sampling="yes">\r
+    <event counter="ARM_Cortex-A9_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>\r
+    <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>\r
+    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>\r
+    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>\r
+    <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>\r
+    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>\r
+    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>\r
+    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>\r
+    <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>\r
+    <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>\r
+    <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>\r
+    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>\r
+    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>\r
+    <event event="0x40" title="Java" name="Bytecode execute" description="Counts the number of Java bytecodes being decoded, including speculative ones"/>\r
+    <event event="0x41" title="Java" name="SW bytecode execute" description="Counts the number of software java bytecodes being decoded, including speculative ones"/>\r
+    <event event="0x42" title="Jazelle" name="Backward branch execute" description="Counts the number of Jazelle taken branches being executed"/>\r
+    <event event="0x50" title="Cache" name="Coherency miss" description="Counts the number of coherent linefill requests performed by the Cortex-A9 processor which also miss in all the other Cortex-A9 processors, meaning that the request is sent to the external memory"/>\r
+    <event event="0x51" title="Cache" name="Coherency hit" description="Counts the number of coherent linefill requests performed by the Cortex-A9 processor which hit in another Cortex-A9 processor, meaning that the linefill data is fetched directly from the relevant Cortex-A9 cache"/>\r
+    <event event="0x60" title="Cache" name="Inst dependent stall" description="Counts the number of cycles where the processor is ready to accept new instructions, but does not receive any because of the instruction side not being able to provide any and the instruction cache is currently performing at least one linefill"/>\r
+    <event event="0x61" title="Cache" name="Data dependent stall" description="Counts the number of cycles where the core has some instructions that it cannot issue to any pipeline, and the Load Store unit has at least one pending linefill request, and no pending TLB requests"/>\r
+    <event event="0x62" title="Cache" name="TLB stall" description="Counts the number of cycles where the processor is stalled waiting for the completion of translation table walks from the main TLB"/>\r
+    <event event="0x63" title="Intrinsic" name="STREX pass" description="Counts the number of STREX instructions architecturally executed and passed"/>\r
+    <event event="0x64" title="Intrinsic" name="STREX fail" description="Counts the number of STREX instructions architecturally executed and failed"/>\r
+    <event event="0x65" title="Cache" name="Data eviction" description="Counts the number of eviction requests because of a linefill in the data cache"/>\r
+    <event event="0x66" title="Pipeline" name="Issue stage no dispatch" description="Counts the number of cycles where the issue stage does not dispatch any instruction because it is empty or cannot dispatch any instructions"/>\r
+    <event event="0x67" title="Pipeline" name="Issue stage empty" description="Counts the number of cycles where the issue stage is empty"/>\r
+    <event event="0x68" title="Instruction" name="Executed" description="Counts the number of instructions going through the Register Renaming stage. This number is an approximate number of the total number of instructions speculatively executed, and even more approximate of the total number of instructions architecturally executed"/>\r
+    <event event="0x6E" title="Core" name="Functions" description="Counts the number of procedure returns whose condition codes do not fail, excluding all returns from exception"/>\r
+    <event event="0x70" title="Instructions" name="Main execution unit" description="Counts the number of instructions being executed in the main execution pipeline of the processor, the multiply pipeline and arithmetic logic unit pipeline"/>\r
+    <event event="0x71" title="Instructions" name="Second execution unit" description="Counts the number of instructions being executed in the processor second execution pipeline (ALU)"/>\r
+    <event event="0x72" title="Instructions" name="Load/Store" description="Counts the number of instructions being executed in the Load/Store unit"/>\r
+    <event event="0x73" title="Instructions" name="Floating point" description="Counts the number of Floating-point instructions going through the Register Rename stage"/>\r
+    <event event="0x74" title="Instructions" name="NEON" description="Counts the number of NEON instructions going through the Register Rename stage"/>\r
+    <event event="0x80" title="Stalls" name="PLD" description="Counts the number of cycles where the processor is stalled because PLD slots are all full"/>\r
+    <event event="0x81" title="Stalls" name="Memory write" description="Counts the number of cycles when the processor is stalled and the data side is stalled too because it is full and executing writes to the external memory"/>\r
+    <event event="0x82" title="Stalls" name="Inst main TLB miss" description="Counts the number of stall cycles because of main TLB misses on requests issued by the instruction side"/>\r
+    <event event="0x83" title="Stalls" name="Data main TLB miss" description="Counts the number of stall cycles because of main TLB misses on requests issued by the data side"/>\r
+    <event event="0x84" title="Stalls" name="Inst micro TLB miss" description="Counts the number of stall cycles because of micro TLB misses on the instruction side"/>\r
+    <event event="0x85" title="Stalls" name="Data micro TLB miss" description="Counts the number of stall cycles because of micro TLB misses on the data side"/>\r
+    <event event="0x86" title="Stalls" name="DMB" description="Counts the number of stall cycles because of the execution of a DMB memory barrier"/>\r
+    <event event="0x8A" title="Clock" name="Integer core" description="Counts the number of cycles during which the integer core clock is enabled"/>\r
+    <event event="0x8B" title="Clock" name="Data engine" description="Counts the number of cycles during which the Data Engine clock is enabled"/>\r
+    <event event="0x90" title="Instructions" name="ISB" description="Counts the number of ISB instructions architecturally executed"/>\r
+    <event event="0x91" title="Instructions" name="DSB" description="Counts the number of DSB instructions architecturally executed"/>\r
+    <event event="0x92" title="Instructions" name="DMB" description="Counts the number of DMB instructions speculatively executed"/>\r
+    <event event="0x93" title="External" name="Interrupts" description="Counts the number of external interrupts executed by the processor"/>\r
+    <event event="0xA0" title="PLE" name="Cache line rq completed" description="Counts the number of PLE cache line requests completed"/>\r
+    <event event="0xA1" title="PLE" name="Cache line rq skipped" description="Counts the number of PLE cache line requests skipped"/>\r
+    <event event="0xA2" title="PLE" name="FIFO flush" description="Counts the number of PLE FIFO flush requests"/>\r
+    <event event="0xA3" title="PLE" name="Request completed" description="Counts the number of PLE FIFO flush completed"/>\r
+    <event event="0xA4" title="PLE" name="FIFO overflow" description="Counts the number of PLE FIFO flush overflowed"/>\r
+    <event event="0xA5" title="PLE" name="Request programmed" description="Counts the number of PLE FIFO flush program requests"/>\r
+  </category>\r
   
\ No newline at end of file
diff --git a/daemon/events-Krait-architected.xml b/daemon/events-Krait-architected.xml
new file mode 100644 (file)
index 0000000..46d6a61
--- /dev/null
@@ -0,0 +1,28 @@
+  <counter_set name="Krait_cntX">\r
+    <counter name="Krait_cnt0"/>\r
+    <counter name="Krait_cnt1"/>\r
+    <counter name="Krait_cnt2"/>\r
+    <counter name="Krait_cnt3"/>\r
+  </counter_set>\r
+  <category name="Krait" counter_set="Krait_cntX" per_cpu="yes">\r
+    <event counter="Krait_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>\r
+    <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>\r
+    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>\r
+    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>\r
+    <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>\r
+       <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>\r
+    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>\r
+    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>\r
+    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>\r
+    <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>\r
+    <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>\r
+    <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/>\r
+    <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>\r
+    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>\r
+    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>\r
+  </category>\r
+  
\ No newline at end of file
index 100f10974f0023617ff477492d03efd97098bfbb..b1cd8dff5b50603325c550ec568b45a667c4fa24 100644 (file)
@@ -1,21 +1,21 @@
-  <counter_set name="L2C-310_cntX">
-    <counter name="L2C-310_cnt0"/>
-    <counter name="L2C-310_cnt1"/>
-  </counter_set>
-  <category name="L2C-310" counter_set="L2C-310_cntX" per_cpu="no">
-    <event event="0x1" title="L2Cache" name="CO" description="Eviction, CastOut, of a line from the L2 cache"/>
-    <event event="0x2" title="L2Cache" name="DRH" description="Data read hit"/>
-    <event event="0x3" title="L2Cache" name="DRREQ" description="Data read request"/>
-    <event event="0x4" title="L2Cache" name="DWHIT" description="Data write hit"/>
-    <event event="0x5" title="L2Cache" name="DWREQ" description="Data write request"/>
-    <event event="0x6" title="L2Cache" name="DWTREQ" description="Data write request with write-through attribute"/>
-    <event event="0x7" title="L2Cache" name="IRHIT" description="Instruction read hit"/>
-    <event event="0x8" title="L2Cache" name="IRREQ" description="Instruction read request"/>
-    <event event="0x9" title="L2Cache" name="WA" description="Write allocate"/>
-    <event event="0xa" title="L2Cache" name="IPFALLOC" description="Allocation of a prefetch generated by L2C-310 into the L2 cache"/>
-    <event event="0xb" title="L2Cache" name="EPFHIT" description="Prefetch hint hits in the L2 cache"/>
-    <event event="0xc" title="L2Cache" name="EPFALLOC" description="Prefetch hint allocated into the L2 cache"/>
-    <event event="0xd" title="L2Cache" name="SRRCVD" description="Speculative read received"/>
-    <event event="0xe" title="L2Cache" name="SRCONF" description="Speculative read confirmed"/>
-    <event event="0xf" title="L2Cache" name="EPFRCVD" description="Prefetch hint received"/>
-  </category>
+  <counter_set name="L2C-310_cntX">\r
+    <counter name="L2C-310_cnt0"/>\r
+    <counter name="L2C-310_cnt1"/>\r
+  </counter_set>\r
+  <category name="L2C-310" counter_set="L2C-310_cntX" per_cpu="no">\r
+    <event event="0x1" title="L2Cache" name="CO" description="Eviction, CastOut, of a line from the L2 cache"/>\r
+    <event event="0x2" title="L2Cache" name="DRH" description="Data read hit"/>\r
+    <event event="0x3" title="L2Cache" name="DRREQ" description="Data read request"/>\r
+    <event event="0x4" title="L2Cache" name="DWHIT" description="Data write hit"/>\r
+    <event event="0x5" title="L2Cache" name="DWREQ" description="Data write request"/>\r
+    <event event="0x6" title="L2Cache" name="DWTREQ" description="Data write request with write-through attribute"/>\r
+    <event event="0x7" title="L2Cache" name="IRHIT" description="Instruction read hit"/>\r
+    <event event="0x8" title="L2Cache" name="IRREQ" description="Instruction read request"/>\r
+    <event event="0x9" title="L2Cache" name="WA" description="Write allocate"/>\r
+    <event event="0xa" title="L2Cache" name="IPFALLOC" description="Allocation of a prefetch generated by L2C-310 into the L2 cache"/>\r
+    <event event="0xb" title="L2Cache" name="EPFHIT" description="Prefetch hint hits in the L2 cache"/>\r
+    <event event="0xc" title="L2Cache" name="EPFALLOC" description="Prefetch hint allocated into the L2 cache"/>\r
+    <event event="0xd" title="L2Cache" name="SRRCVD" description="Speculative read received"/>\r
+    <event event="0xe" title="L2Cache" name="SRCONF" description="Speculative read confirmed"/>\r
+    <event event="0xf" title="L2Cache" name="EPFRCVD" description="Prefetch hint received"/>\r
+  </category>\r
index ed50429056034a68acb01dda6db3b1b1a89c5719..338e1605506873c79620d39781745f07604aca93 100644 (file)
@@ -1,16 +1,16 @@
-  <category name="Linux">
-    <event counter="Linux_cpuload_user" title="CPU Load" name="User" per_cpu="yes" description="Scheduler CPU Load of User Application" operation="percentage"/>
-    <event counter="Linux_cpuload_system" title="CPU Load" name="System" per_cpu="yes" description="Scheduler CPU Load of System Behavior" operation="percentage"/>
-    <event counter="Linux_irq_softirq" title="Interrupts" name="SoftIRQ" per_cpu="yes" description="Linux SoftIRQ taken"/>
-    <event counter="Linux_irq_irq" title="Interrupts" name="IRQ" per_cpu="yes" description="Linux IRQ taken"/>
-    <event counter="Linux_block_rq_wr" title="Disk IO" name="Write" description="Disk IO Bytes Written"/>
-    <event counter="Linux_block_rq_rd" title="Disk IO" name="Read" description="Disk IO Bytes Read"/>
-    <event counter="Linux_meminfo_memused" title="Memory" name="Used" description="Total used memory size" operation="maximum"/>
-    <event counter="Linux_meminfo_memfree" title="Memory" name="Free" description="Available memory size" operation="maximum"/>
-    <event counter="Linux_meminfo_bufferram" title="Memory" name="Buffer" description="Memory used by buffers" operation="maximum"/>
-    <event counter="Linux_net_drv" title="Network" name="Gator" description="Network traffic from Gator driver"/>
-    <event counter="Linux_net_rx" title="Network" name="Receive" description="Receive network traffic, excluding effect from Streamline"/>
-    <event counter="Linux_net_tx" title="Network" name="Transmit" description="Transmit network traffic, excluding effect from Streamline"/>
-    <event counter="Linux_sched_switch" title="Scheduler" name="Switch" description="Context switch events"/>
-  </category>
-  
\ No newline at end of file
+  <category name="Linux">\r
+    <event counter="Linux_cpuload_user" title="CPU Load" name="User" per_cpu="yes" description="Scheduler CPU Load of User Application" operation="percentage"/>\r
+    <event counter="Linux_cpuload_system" title="CPU Load" name="System" per_cpu="yes" description="Scheduler CPU Load of System Behavior" operation="percentage"/>\r
+    <event counter="Linux_irq_softirq" title="Interrupts" name="SoftIRQ" per_cpu="yes" description="Linux SoftIRQ taken"/>\r
+    <event counter="Linux_irq_irq" title="Interrupts" name="IRQ" per_cpu="yes" description="Linux IRQ taken"/>\r
+    <event counter="Linux_block_rq_wr" title="Disk IO" name="Write" description="Disk IO Bytes Written"/>\r
+    <event counter="Linux_block_rq_rd" title="Disk IO" name="Read" description="Disk IO Bytes Read"/>\r
+    <event counter="Linux_meminfo_memused" title="Memory" name="Used" description="Total used memory size" operation="maximum"/>\r
+    <event counter="Linux_meminfo_memfree" title="Memory" name="Free" description="Available memory size" operation="maximum"/>\r
+    <event counter="Linux_meminfo_bufferram" title="Memory" name="Buffer" description="Memory used by buffers" operation="maximum"/>\r
+    <event counter="Linux_net_rx" title="Network" name="Receive" description="Receive network traffic, excluding effect from Streamline"/>\r
+    <event counter="Linux_net_tx" title="Network" name="Transmit" description="Transmit network traffic, excluding effect from Streamline"/>\r
+    <event counter="Linux_sched_switch" title="Scheduler" name="Switch" description="Context switch events"/>\r
+    <event counter="Linux_power_cpu_freq" title="Clock" name="Frequency" per_cpu="yes" description="Target frequency of the CPU" operation="frequency"/>\r
+  </category>\r
+  \r
diff --git a/daemon/events-Mali-400.xml b/daemon/events-Mali-400.xml
new file mode 100644 (file)
index 0000000..f64fec8
--- /dev/null
@@ -0,0 +1,395 @@
+  <counter_set name="ARM_Mali-400_VP_cntX">\r
+    <counter name="ARM_Mali-400_VP_cnt0"/>\r
+    <counter name="ARM_Mali-400_VP_cnt1"/>\r
+  </counter_set>\r
+  <counter_set name="ARM_Mali-400_FP0_cntX">\r
+    <counter name="ARM_Mali-400_FP0_cnt0"/>\r
+    <counter name="ARM_Mali-400_FP0_cnt1"/>\r
+  </counter_set>\r
+  <counter_set name="ARM_Mali-400_FP1_cntX">\r
+    <counter name="ARM_Mali-400_FP1_cnt0"/>\r
+    <counter name="ARM_Mali-400_FP1_cnt1"/>\r
+  </counter_set>  \r
+  <counter_set name="ARM_Mali-400_FP2_cntX">\r
+    <counter name="ARM_Mali-400_FP2_cnt0"/>\r
+    <counter name="ARM_Mali-400_FP2_cnt1"/>\r
+  </counter_set>\r
+  <counter_set name="ARM_Mali-400_FP3_cntX">\r
+    <counter name="ARM_Mali-400_FP3_cnt0"/>\r
+    <counter name="ARM_Mali-400_FP3_cnt1"/>\r
+  </counter_set>\r
+  <counter_set name="ARM_Mali-400_L2_cntX">\r
+    <counter name="ARM_Mali-400_L2_cnt0"/>\r
+    <counter name="ARM_Mali-400_L2_cnt1"/>\r
+  </counter_set>\r
+  <counter_set name="ARM_Mali-400_SW_cntX">\r
+  </counter_set>  \r
+  <counter_set name="ARM_Mali-400_Filmstrip_cntX">\r
+       <counter name="ARM_Mali-400_Filmstrip"/>\r
+  </counter_set>  \r
+  <category name="Mali-400-VP" counter_set="ARM_Mali-400_VP_cntX" per_cpu="no">\r
+    <event event="0x01" title="Mali GPU Vertex Processor" name="Active cycles" description="Number of cycles per frame the MaliGP2 was active"/>\r
+    <event event="0x02" title="Mali GPU Vertex Processor" name="Active cycles, vertex shader" description="Number of cycles per frame the vertex shader unit was active"/>\r
+    <event event="0x03" title="Mali GPU Vertex Processor" name="Active cycles, vertex storer" description="Number of cycles per frame the vertex storer unit was active"/>\r
+    <event event="0x04" title="Mali GPU Vertex Processor" name="Active cycles, vertex loader" description="Number of cycles per frame the vertex loader unit was active"/>\r
+    <event event="0x05" title="Mali GPU Vertex Processor" name="Cycles vertex loader waiting for vertex shader" description="Number of cycles per frame the vertex loader was idle while waiting on the vertex shader"/>\r
+    <event event="0x06" title="Mali GPU Vertex Processor" name="Words read, system bus" description="Total number of 64 bit words read by the GP2 from the system bus per frame"/>\r
+    <event event="0x07" title="Mali GPU Vertex Processor" name="Words written, system bus" description="Total number of 64 bit words written by the GP2 to the system bus per frame"/>\r
+    <event event="0x08" title="Mali GPU Vertex Processor" name="Read bursts, system bus" description="Number of read bursts by the GP2 from the system bus per frame"/>\r
+    <event event="0x09" title="Mali GPU Vertex Processor" name="Write bursts, system bus" description="Number of write bursts from the MaliGP2 to the system bus per frame"/>\r
+    <event event="0x0a" title="Mali GPU Vertex Processor" name="Vertices processed" description="Number of vertices processed by the MaliGP2 per frame"/>\r
+    <event event="0x0b" title="Mali GPU Vertex Processor" name="Vertices fetched" description="Number of vertices fetched by the MaliGP2 per frame"/>\r
+    <event event="0x0c" title="Mali GPU Vertex Processor" name="Primitives fetched" description="Number of graphics primitives fetched by the MaliGP2 per frame"/>\r
+    <event event="0x0e" title="Mali GPU Vertex Processor" name="Primitives culled" description="Number of graphics primitives discarded per frame, because they were seen from the back or were offscreen"/>\r
+    <event event="0x0f" title="Mali GPU Vertex Processor" name="Commands written to tiles" description="Number of commands (8 Bytes, mainly primitives) written by GP2 to the PP input data structure per frame"/>\r
+    <event event="0x10" title="Mali GPU Vertex Processor" name="Memory blocks allocated" description="Number of overflow data blocks needed for outputting the PP input data structure per frame "/>\r
+    <event event="0x13" title="Mali GPU Vertex Processor" name="Vertex loader cache misses" description="Number of cache misses for the vertex shader's vertex input unit per frame"/>\r
+    <event event="0x16" title="Mali GPU Vertex Processor" name="Active cycles, vertex shader command processor" description="Number of cycles per frame the GP2 vertex shader command processor was active. This includes time waiting for semaphores."/>\r
+    <event event="0x17" title="Mali GPU Vertex Processor" name="Active cycles, PLBU command processor" description="Number of cycles per frame the MaliGP2 PLBU command processor was active. This includes time waiting for semaphores"/>\r
+    <event event="0x18" title="Mali GPU Vertex Processor" name="Number of cycles per frame the MaliGP2 PLBU output unit was active (Writing the Mali200 input data structure). This includes time spent waiting on the bus" description="MALI_CINSTR_GP_ACTIVE_CYCLES_PLBU_LIST_WRITER"/>\r
+    <event event="0x19" title="Mali GPU Vertex Processor" name="Active cycles, PLBU geometry processing" description="Number of cycles per frame the MaliGP2 PLBU was active, excepting final data output. In other words: active cycles through the prepare list commands. This includes time spent waiting on the bus"/>\r
+    <event event="0x1b" title="Mali GPU Vertex Processor" name="Active cycles, PLBU primitive assembly" description="Number of active cycles per frame spent by the MaliGP2 PLBU doing primitive assembly. This does not include scissoring or final output. This includes time spent waiting on the bus"/>\r
+    <event event="0x1c" title="Mali GPU Vertex Processor" name="Active cycles, PLBU vertex fetcher" description="Number of active cycles per frame spent by the MaliGP2 PLBU fetching vertex data. This includes time spent waiting on the bus"/>\r
+    <event event="0x1e" title="Mali GPU Vertex Processor" name="Active cycles, Bounding-box and command generator" description="Number of active cycles per frame spent by the MaliGP2 PLBU setting up bounding boxes and commands (mainly graphics primitives). This includes time spent waiting on the bus"/>\r
+    <event event="0x20" title="Mali GPU Vertex Processor" name="Active cycles, Scissor tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over tiles to perform scissoringi. This includes time spent waiting on the bus"/>\r
+    <event event="0x21" title="Mali GPU Vertex Processor" name="Active cycles, PLBU tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over the tiles in the bounding box generating commands (mainly graphics primitives). This includes time spent waiting on the bus"/>\r
+  </category>\r
+  <category name="Mali-400-FP0" counter_set="ARM_Mali-400_FP0_cntX" per_cpu="no">\r
+    <event event="0x00" title="Mali GPU Fragment Processor 0" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ"/>\r
+    <event event="0x02" title="Mali GPU Fragment Processor 0" name="Total bus reads" description="Total number of 64-bit words read from the bus"/>\r
+    <event event="0x03" title="Mali GPU Fragment Processor 0" name="Total bus writes" description="Total number of 64-bit words written to the bus"/>\r
+    <event event="0x04" title="Mali GPU Fragment Processor 0" name="Bus read request cycles" description="MALI_CINSTR_PP_BUS_READ_REQUEST_CYCLES_COUNT"/>\r
+    <event event="0x05" title="Mali GPU Fragment Processor 0" name="Bus write request cycles" description="MALI_CINSTR_PP_BUS_WRITE_REQUEST_CYCLES_COUNT"/>\r
+    <event event="0x06" title="Mali GPU Fragment Processor 0" name="Bus read transactions count" description="Number of read requests accepted by the bus"/>\r
+    <event event="0x07" title="Mali GPU Fragment Processor 0" name="Bus write transactions" description="Number of write requests accepted by the bus"/>\r
+    <event event="0x09" title="Mali GPU Fragment Processor 0" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit"/>\r
+    <event event="0x0a" title="Mali GPU Fragment Processor 0" name="Store unit writes" description="64-bit words written to the bus by the store unit"/>\r
+    <event event="0x0d" title="Mali GPU Fragment Processor 0" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache"/>\r
+    <event event="0x0e" title="Mali GPU Fragment Processor 0" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader"/>\r
+    <event event="0x0f" title="Mali GPU Fragment Processor 0" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register"/>\r
+    <event event="0x10" title="Mali GPU Fragment Processor 0" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache"/>\r
+    <event event="0x11" title="Mali GPU Fragment Processor 0" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table"/>\r
+    <event event="0x12" title="Mali GPU Fragment Processor 0" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache"/>\r
+    <event event="0x13" title="Mali GPU Fragment Processor 0" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus"/>\r
+    <event event="0x14" title="Mali GPU Fragment Processor 0" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus"/>\r
+    <event event="0x15" title="Mali GPU Fragment Processor 0" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table"/>\r
+    <event event="0x17" title="Mali GPU Fragment Processor 0" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction"/>\r
+    <event event="0x18" title="Mali GPU Fragment Processor 0" name="Polygon count" description="Number of triangles read from the polygon list"/>\r
+    <event event="0x19" title="Mali GPU Fragment Processor 0" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list"/>\r
+    <event event="0x1a" title="Mali GPU Fragment Processor 0" name="Lines count" description="Number of lines read from the polygon list"/>\r
+    <event event="0x1b" title="Mali GPU Fragment Processor 0" name="Points count" description="Number of points read from the polygon list"/>\r
+    <event event="0x1c" title="Mali GPU Fragment Processor 0" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected"/>\r
+    <event event="0x1d" title="Mali GPU Fragment Processor 0" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input"/>\r
+    <event event="0x1e" title="Mali GPU Fragment Processor 0" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer"/>\r
+    <event event="0x1f" title="Mali GPU Fragment Processor 0" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad"/>\r
+    <event event="0x20" title="Mali GPU Fragment Processor 0" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed"/>\r
+    <event event="0x21" title="Mali GPU Fragment Processor 0" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill"/>\r
+    <event event="0x22" title="Mali GPU Fragment Processor 0" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test"/>\r
+    <event event="0x23" title="Mali GPU Fragment Processor 0" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels"/>\r
+    <event event="0x24" title="Mali GPU Fragment Processor 0" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection"/>\r
+    <event event="0x25" title="Mali GPU Fragment Processor 0" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs"/>\r
+    <event event="0x26" title="Mali GPU Fragment Processor 0" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous"/>\r
+    <event event="0x27" title="Mali GPU Fragment Processor 0" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation"/>\r
+    <event event="0x28" title="Mali GPU Fragment Processor 0" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation"/>\r
+    <event event="0x29" title="Mali GPU Fragment Processor 0" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation"/>\r
+    <event event="0x2a" title="Mali GPU Fragment Processor 0" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer"/>\r
+    <event event="0x2b" title="Mali GPU Fragment Processor 0" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation"/>\r
+    <event event="0x2c" title="Mali GPU Fragment Processor 0" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported"/>\r
+    <event event="0x2d" title="Mali GPU Fragment Processor 0" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active"/>\r
+    <event event="0x2e" title="Mali GPU Fragment Processor 0" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed"/>\r
+    <event event="0x2f" title="Mali GPU Fragment Processor 0" name="Texture mapper cycle count" description="Number of texture operation cycles"/>\r
+    <event event="0x30" title="Mali GPU Fragment Processor 0" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)"/>\r
+    <event event="0x31" title="Mali GPU Fragment Processor 0" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)"/>\r
+    <event event="0x32" title="Mali GPU Fragment Processor 0" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)"/>\r
+    <event event="0x33" title="Mali GPU Fragment Processor 0" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)"/>\r
+    <event event="0x34" title="Mali GPU Fragment Processor 0" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/>\r
+    <event event="0x35" title="Mali GPU Fragment Processor 0" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)"/>\r
+    <event event="0x36" title="Mali GPU Fragment Processor 0" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)"/>\r
+    <event event="0x37" title="Mali GPU Fragment Processor 0" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/>\r
+    <event event="0x38" title="Mali GPU Fragment Processor 0" name="(Mali200)Palette cache hit count; (Mali400)Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/>\r
+    <event event="0x39" title="Mali GPU Fragment Processor 0" name="(Mali200)Palette cache miss count; (Mali400)Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/>\r
+    <event event="0x3a" title="Mali GPU Fragment Processor 0" name="Load/Store cache hit count" description="Number of hits in the load/store cache"/>\r
+    <event event="0x3b" title="Mali GPU Fragment Processor 0" name="Load/Store cache miss count" description="Number of misses in the load/store cache"/>\r
+    <event event="0x3c" title="Mali GPU Fragment Processor 0" name="Program cache hit count" description="Number of hits in the program cache"/>\r
+    <event event="0x3d" title="Mali GPU Fragment Processor 0" name="Program cache miss count" description="Number of misses in the program cache"/>\r
+  </category>\r
+  <category name="Mali-400-FP1" counter_set="ARM_Mali-400_FP1_cntX" per_cpu="no">\r
+    <event event="0x00" title="Mali GPU Fragment Processor 1" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ"/>\r
+    <event event="0x02" title="Mali GPU Fragment Processor 1" name="Total bus reads" description="Total number of 64-bit words read from the bus"/>\r
+    <event event="0x03" title="Mali GPU Fragment Processor 1" name="Total bus writes" description="Total number of 64-bit words written to the bus"/>\r
+    <event event="0x04" title="Mali GPU Fragment Processor 1" name="Bus read request cycles" description="MALI_CINSTR_PP_BUS_READ_REQUEST_CYCLES_COUNT"/>\r
+    <event event="0x05" title="Mali GPU Fragment Processor 1" name="Bus write request cycles" description="MALI_CINSTR_PP_BUS_WRITE_REQUEST_CYCLES_COUNT"/>\r
+    <event event="0x06" title="Mali GPU Fragment Processor 1" name="Bus read transactions count" description="Number of read requests accepted by the bus"/>\r
+    <event event="0x07" title="Mali GPU Fragment Processor 1" name="Bus write transactions" description="Number of write requests accepted by the bus"/>\r
+    <event event="0x09" title="Mali GPU Fragment Processor 1" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit"/>\r
+    <event event="0x0a" title="Mali GPU Fragment Processor 1" name="Store unit writes" description="64-bit words written to the bus by the store unit"/>\r
+    <event event="0x0d" title="Mali GPU Fragment Processor 1" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache"/>\r
+    <event event="0x0e" title="Mali GPU Fragment Processor 1" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader"/>\r
+    <event event="0x0f" title="Mali GPU Fragment Processor 1" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register"/>\r
+    <event event="0x10" title="Mali GPU Fragment Processor 1" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache"/>\r
+    <event event="0x11" title="Mali GPU Fragment Processor 1" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table"/>\r
+    <event event="0x12" title="Mali GPU Fragment Processor 1" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache"/>\r
+    <event event="0x13" title="Mali GPU Fragment Processor 1" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus"/>\r
+    <event event="0x14" title="Mali GPU Fragment Processor 1" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus"/>\r
+    <event event="0x15" title="Mali GPU Fragment Processor 1" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table"/>\r
+    <event event="0x17" title="Mali GPU Fragment Processor 1" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction"/>\r
+    <event event="0x18" title="Mali GPU Fragment Processor 1" name="Polygon count" description="Number of triangles read from the polygon list"/>\r
+    <event event="0x19" title="Mali GPU Fragment Processor 1" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list"/>\r
+    <event event="0x1a" title="Mali GPU Fragment Processor 1" name="Lines count" description="Number of lines read from the polygon list"/>\r
+    <event event="0x1b" title="Mali GPU Fragment Processor 1" name="Points count" description="Number of points read from the polygon list"/>\r
+    <event event="0x1c" title="Mali GPU Fragment Processor 1" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected"/>\r
+    <event event="0x1d" title="Mali GPU Fragment Processor 1" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input"/>\r
+    <event event="0x1e" title="Mali GPU Fragment Processor 1" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer"/>\r
+    <event event="0x1f" title="Mali GPU Fragment Processor 1" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad"/>\r
+    <event event="0x20" title="Mali GPU Fragment Processor 1" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed"/>\r
+    <event event="0x21" title="Mali GPU Fragment Processor 1" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill"/>\r
+    <event event="0x22" title="Mali GPU Fragment Processor 1" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test"/>\r
+    <event event="0x23" title="Mali GPU Fragment Processor 1" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels"/>\r
+    <event event="0x24" title="Mali GPU Fragment Processor 1" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection"/>\r
+    <event event="0x25" title="Mali GPU Fragment Processor 1" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs"/>\r
+    <event event="0x26" title="Mali GPU Fragment Processor 1" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous"/>\r
+    <event event="0x27" title="Mali GPU Fragment Processor 1" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation"/>\r
+    <event event="0x28" title="Mali GPU Fragment Processor 1" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation"/>\r
+    <event event="0x29" title="Mali GPU Fragment Processor 1" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation"/>\r
+    <event event="0x2a" title="Mali GPU Fragment Processor 1" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer"/>\r
+    <event event="0x2b" title="Mali GPU Fragment Processor 1" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation"/>\r
+    <event event="0x2c" title="Mali GPU Fragment Processor 1" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported"/>\r
+    <event event="0x2d" title="Mali GPU Fragment Processor 1" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active"/>\r
+    <event event="0x2e" title="Mali GPU Fragment Processor 1" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed"/>\r
+    <event event="0x2f" title="Mali GPU Fragment Processor 1" name="Texture mapper cycle count" description="Number of texture operation cycles"/>\r
+    <event event="0x30" title="Mali GPU Fragment Processor 1" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)"/>\r
+    <event event="0x31" title="Mali GPU Fragment Processor 1" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)"/>\r
+    <event event="0x32" title="Mali GPU Fragment Processor 1" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)"/>\r
+    <event event="0x33" title="Mali GPU Fragment Processor 1" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)"/>\r
+    <event event="0x34" title="Mali GPU Fragment Processor 1" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/>\r
+    <event event="0x35" title="Mali GPU Fragment Processor 1" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)"/>\r
+    <event event="0x36" title="Mali GPU Fragment Processor 1" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)"/>\r
+    <event event="0x37" title="Mali GPU Fragment Processor 1" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/>\r
+    <event event="0x38" title="Mali GPU Fragment Processor 1" name="(Mali200)Palette cache hit count; (Mali400)Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/>\r
+    <event event="0x39" title="Mali GPU Fragment Processor 1" name="(Mali200)Palette cache miss count; (Mali400)Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/>\r
+    <event event="0x3a" title="Mali GPU Fragment Processor 1" name="Load/Store cache hit count" description="Number of hits in the load/store cache"/>\r
+    <event event="0x3b" title="Mali GPU Fragment Processor 1" name="Load/Store cache miss count" description="Number of misses in the load/store cache"/>\r
+    <event event="0x3c" title="Mali GPU Fragment Processor 1" name="Program cache hit count" description="Number of hits in the program cache"/>\r
+    <event event="0x3d" title="Mali GPU Fragment Processor 1" name="Program cache miss count" description="Number of misses in the program cache"/>\r
+  </category>\r
+  <category name="Mali-400-FP2" counter_set="ARM_Mali-400_FP2_cntX" per_cpu="no">\r
+    <event event="0x00" title="Mali GPU Fragment Processor 2" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ"/>\r
+    <event event="0x02" title="Mali GPU Fragment Processor 2" name="Total bus reads" description="Total number of 64-bit words read from the bus"/>\r
+    <event event="0x03" title="Mali GPU Fragment Processor 2" name="Total bus writes" description="Total number of 64-bit words written to the bus"/>\r
+    <event event="0x04" title="Mali GPU Fragment Processor 2" name="Bus read request cycles" description="MALI_CINSTR_PP_BUS_READ_REQUEST_CYCLES_COUNT"/>\r
+    <event event="0x05" title="Mali GPU Fragment Processor 2" name="Bus write request cycles" description="MALI_CINSTR_PP_BUS_WRITE_REQUEST_CYCLES_COUNT"/>\r
+    <event event="0x06" title="Mali GPU Fragment Processor 2" name="Bus read transactions count" description="Number of read requests accepted by the bus"/>\r
+    <event event="0x07" title="Mali GPU Fragment Processor 2" name="Bus write transactions" description="Number of write requests accepted by the bus"/>\r
+    <event event="0x09" title="Mali GPU Fragment Processor 2" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit"/>\r
+    <event event="0x0a" title="Mali GPU Fragment Processor 2" name="Store unit writes" description="64-bit words written to the bus by the store unit"/>\r
+    <event event="0x0d" title="Mali GPU Fragment Processor 2" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache"/>\r
+    <event event="0x0e" title="Mali GPU Fragment Processor 2" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader"/>\r
+    <event event="0x0f" title="Mali GPU Fragment Processor 2" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register"/>\r
+    <event event="0x10" title="Mali GPU Fragment Processor 2" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache"/>\r
+    <event event="0x11" title="Mali GPU Fragment Processor 2" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table"/>\r
+    <event event="0x12" title="Mali GPU Fragment Processor 2" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache"/>\r
+    <event event="0x13" title="Mali GPU Fragment Processor 2" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus"/>\r
+    <event event="0x14" title="Mali GPU Fragment Processor 2" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus"/>\r
+    <event event="0x15" title="Mali GPU Fragment Processor 2" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table"/>\r
+    <event event="0x17" title="Mali GPU Fragment Processor 2" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction"/>\r
+    <event event="0x18" title="Mali GPU Fragment Processor 2" name="Polygon count" description="Number of triangles read from the polygon list"/>\r
+    <event event="0x19" title="Mali GPU Fragment Processor 2" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list"/>\r
+    <event event="0x1a" title="Mali GPU Fragment Processor 2" name="Lines count" description="Number of lines read from the polygon list"/>\r
+    <event event="0x1b" title="Mali GPU Fragment Processor 2" name="Points count" description="Number of points read from the polygon list"/>\r
+    <event event="0x1c" title="Mali GPU Fragment Processor 2" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected"/>\r
+    <event event="0x1d" title="Mali GPU Fragment Processor 2" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input"/>\r
+    <event event="0x1e" title="Mali GPU Fragment Processor 2" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer"/>\r
+    <event event="0x1f" title="Mali GPU Fragment Processor 2" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad"/>\r
+    <event event="0x20" title="Mali GPU Fragment Processor 2" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed"/>\r
+    <event event="0x21" title="Mali GPU Fragment Processor 2" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill"/>\r
+    <event event="0x22" title="Mali GPU Fragment Processor 2" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test"/>\r
+    <event event="0x23" title="Mali GPU Fragment Processor 2" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels"/>\r
+    <event event="0x24" title="Mali GPU Fragment Processor 2" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection"/>\r
+    <event event="0x25" title="Mali GPU Fragment Processor 2" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs"/>\r
+    <event event="0x26" title="Mali GPU Fragment Processor 2" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous"/>\r
+    <event event="0x27" title="Mali GPU Fragment Processor 2" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation"/>\r
+    <event event="0x28" title="Mali GPU Fragment Processor 2" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation"/>\r
+    <event event="0x29" title="Mali GPU Fragment Processor 2" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation"/>\r
+    <event event="0x2a" title="Mali GPU Fragment Processor 2" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer"/>\r
+    <event event="0x2b" title="Mali GPU Fragment Processor 2" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation"/>\r
+    <event event="0x2c" title="Mali GPU Fragment Processor 2" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported"/>\r
+    <event event="0x2d" title="Mali GPU Fragment Processor 2" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active"/>\r
+    <event event="0x2e" title="Mali GPU Fragment Processor 2" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed"/>\r
+    <event event="0x2f" title="Mali GPU Fragment Processor 2" name="Texture mapper cycle count" description="Number of texture operation cycles"/>\r
+    <event event="0x30" title="Mali GPU Fragment Processor 2" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)"/>\r
+    <event event="0x31" title="Mali GPU Fragment Processor 2" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)"/>\r
+    <event event="0x32" title="Mali GPU Fragment Processor 2" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)"/>\r
+    <event event="0x33" title="Mali GPU Fragment Processor 2" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)"/>\r
+    <event event="0x34" title="Mali GPU Fragment Processor 2" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/>\r
+    <event event="0x35" title="Mali GPU Fragment Processor 2" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)"/>\r
+    <event event="0x36" title="Mali GPU Fragment Processor 2" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)"/>\r
+    <event event="0x37" title="Mali GPU Fragment Processor 2" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/>\r
+    <event event="0x38" title="Mali GPU Fragment Processor 2" name="(Mali200)Palette cache hit count; (Mali400)Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/>\r
+    <event event="0x39" title="Mali GPU Fragment Processor 2" name="(Mali200)Palette cache miss count; (Mali400)Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/>\r
+    <event event="0x3a" title="Mali GPU Fragment Processor 2" name="Load/Store cache hit count" description="Number of hits in the load/store cache"/>\r
+    <event event="0x3b" title="Mali GPU Fragment Processor 2" name="Load/Store cache miss count" description="Number of misses in the load/store cache"/>\r
+    <event event="0x3c" title="Mali GPU Fragment Processor 2" name="Program cache hit count" description="Number of hits in the program cache"/>\r
+    <event event="0x3d" title="Mali GPU Fragment Processor 2" name="Program cache miss count" description="Number of misses in the program cache"/>\r
+  </category>\r
+  <category name="Mali-400-FP3" counter_set="ARM_Mali-400_FP3_cntX" per_cpu="no">\r
+    <event event="0x00" title="Mali GPU Fragment Processor 3" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ"/>\r
+    <event event="0x02" title="Mali GPU Fragment Processor 3" name="Total bus reads" description="Total number of 64-bit words read from the bus"/>\r
+    <event event="0x03" title="Mali GPU Fragment Processor 3" name="Total bus writes" description="Total number of 64-bit words written to the bus"/>\r
+    <event event="0x04" title="Mali GPU Fragment Processor 3" name="Bus read request cycles" description="MALI_CINSTR_PP_BUS_READ_REQUEST_CYCLES_COUNT"/>\r
+    <event event="0x05" title="Mali GPU Fragment Processor 3" name="Bus write request cycles" description="MALI_CINSTR_PP_BUS_WRITE_REQUEST_CYCLES_COUNT"/>\r
+    <event event="0x06" title="Mali GPU Fragment Processor 3" name="Bus read transactions count" description="Number of read requests accepted by the bus"/>\r
+    <event event="0x07" title="Mali GPU Fragment Processor 3" name="Bus write transactions" description="Number of write requests accepted by the bus"/>\r
+    <event event="0x09" title="Mali GPU Fragment Processor 3" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit"/>\r
+    <event event="0x0a" title="Mali GPU Fragment Processor 3" name="Store unit writes" description="64-bit words written to the bus by the store unit"/>\r
+    <event event="0x0d" title="Mali GPU Fragment Processor 3" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache"/>\r
+    <event event="0x0e" title="Mali GPU Fragment Processor 3" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader"/>\r
+    <event event="0x0f" title="Mali GPU Fragment Processor 3" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register"/>\r
+    <event event="0x10" title="Mali GPU Fragment Processor 3" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache"/>\r
+    <event event="0x11" title="Mali GPU Fragment Processor 3" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table"/>\r
+    <event event="0x12" title="Mali GPU Fragment Processor 3" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache"/>\r
+    <event event="0x13" title="Mali GPU Fragment Processor 3" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus"/>\r
+    <event event="0x14" title="Mali GPU Fragment Processor 3" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus"/>\r
+    <event event="0x15" title="Mali GPU Fragment Processor 3" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table"/>\r
+    <event event="0x17" title="Mali GPU Fragment Processor 3" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction"/>\r
+    <event event="0x18" title="Mali GPU Fragment Processor 3" name="Polygon count" description="Number of triangles read from the polygon list"/>\r
+    <event event="0x19" title="Mali GPU Fragment Processor 3" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list"/>\r
+    <event event="0x1a" title="Mali GPU Fragment Processor 3" name="Lines count" description="Number of lines read from the polygon list"/>\r
+    <event event="0x1b" title="Mali GPU Fragment Processor 3" name="Points count" description="Number of points read from the polygon list"/>\r
+    <event event="0x1c" title="Mali GPU Fragment Processor 3" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected"/>\r
+    <event event="0x1d" title="Mali GPU Fragment Processor 3" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input"/>\r
+    <event event="0x1e" title="Mali GPU Fragment Processor 3" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer"/>\r
+    <event event="0x1f" title="Mali GPU Fragment Processor 3" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad"/>\r
+    <event event="0x20" title="Mali GPU Fragment Processor 3" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed"/>\r
+    <event event="0x21" title="Mali GPU Fragment Processor 3" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill"/>\r
+    <event event="0x22" title="Mali GPU Fragment Processor 3" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test"/>\r
+    <event event="0x23" title="Mali GPU Fragment Processor 3" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels"/>\r
+    <event event="0x24" title="Mali GPU Fragment Processor 3" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection"/>\r
+    <event event="0x25" title="Mali GPU Fragment Processor 3" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs"/>\r
+    <event event="0x26" title="Mali GPU Fragment Processor 3" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous"/>\r
+    <event event="0x27" title="Mali GPU Fragment Processor 3" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation"/>\r
+    <event event="0x28" title="Mali GPU Fragment Processor 3" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation"/>\r
+    <event event="0x29" title="Mali GPU Fragment Processor 3" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation"/>\r
+    <event event="0x2a" title="Mali GPU Fragment Processor 3" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer"/>\r
+    <event event="0x2b" title="Mali GPU Fragment Processor 3" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation"/>\r
+    <event event="0x2c" title="Mali GPU Fragment Processor 3" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported"/>\r
+    <event event="0x2d" title="Mali GPU Fragment Processor 3" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active"/>\r
+    <event event="0x2e" title="Mali GPU Fragment Processor 3" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed"/>\r
+    <event event="0x2f" title="Mali GPU Fragment Processor 3" name="Texture mapper cycle count" description="Number of texture operation cycles"/>\r
+    <event event="0x30" title="Mali GPU Fragment Processor 3" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)"/>\r
+    <event event="0x31" title="Mali GPU Fragment Processor 3" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)"/>\r
+    <event event="0x32" title="Mali GPU Fragment Processor 3" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)"/>\r
+    <event event="0x33" title="Mali GPU Fragment Processor 3" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)"/>\r
+    <event event="0x34" title="Mali GPU Fragment Processor 3" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/>\r
+    <event event="0x35" title="Mali GPU Fragment Processor 3" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)"/>\r
+    <event event="0x36" title="Mali GPU Fragment Processor 3" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)"/>\r
+    <event event="0x37" title="Mali GPU Fragment Processor 3" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache"/>\r
+    <event event="0x38" title="Mali GPU Fragment Processor 3" name="(Mali200)Palette cache hit count; (Mali400)Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/>\r
+    <event event="0x39" title="Mali GPU Fragment Processor 3" name="(Mali200)Palette cache miss count; (Mali400)Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/>\r
+    <event event="0x3a" title="Mali GPU Fragment Processor 3" name="Load/Store cache hit count" description="Number of hits in the load/store cache"/>\r
+    <event event="0x3b" title="Mali GPU Fragment Processor 3" name="Load/Store cache miss count" description="Number of misses in the load/store cache"/>\r
+    <event event="0x3c" title="Mali GPU Fragment Processor 3" name="Program cache hit count" description="Number of hits in the program cache"/>\r
+    <event event="0x3d" title="Mali GPU Fragment Processor 3" name="Program cache miss count" description="Number of misses in the program cache"/>\r
+  </category>\r
+  <category name="Mali-400-L2" counter_set="ARM_Mali-400_L2_cntX" per_cpu="no">\r
+    <event event="0x01" title="Mali L2 Cache" name="Total clock cycles" description="Total clock cycles"/>\r
+    <event event="0x02" title="Mali L2 Cache" name="Active clock cycles" description="Active clock cycles" />\r
+    <event event="0x08" title="Mali L2 Cache" name="Read transactions, master" description="Read transactions, master" />\r
+    <event event="0x09" title="Mali L2 Cache" name="Write transactions, master" description="Write transactions, master" />\r
+    <event event="0x0a" title="Mali L2 Cache" name="Words read, master" description="Words read, master" />\r
+    <event event="0x0b" title="Mali L2 Cache" name="Words written, master" description="Words written, master" />\r
+    <event event="0x10" title="Mali L2 Cache" name="Read transactions, all slaves" description="Read transactions, all slaves" />\r
+    <event event="0x11" title="Mali L2 Cache" name="Write transactions, all slaves" description="Write transactions, all slaves" />\r
+    <event event="0x12" title="Mali L2 Cache" name="Words read, all slaves" description="Words read, all slaves" />\r
+    <event event="0x13" title="Mali L2 Cache" name="Words written, all slaves" description="Words written, all slaves" />\r
+    <event event="0x14" title="Mali L2 Cache" name="Read hits, all slaves" description="Read hits, all slaves" />\r
+    <event event="0x15" title="Mali L2 Cache" name="Read misses, all slaves" description="Read misses, all slaves" />\r
+    <event event="0x16" title="Mali L2 Cache" name="Write invalidates, all slaves" description="Write invalidates, all slaves" />\r
+    <event event="0x17" title="Mali L2 Cache" name="Read invalidates, all slaves" description="Read invalidates, all slaves" />\r
+    <event event="0x18" title="Mali L2 Cache" name="Cacheable read transactions, all slaves" description="Cacheable read transactions, all slaves" />\r
+    <event event="0x20" title="Mali L2 Cache" name="Read transactions, slave 0" description="Read transactions, slave 0" />\r
+    <event event="0x21" title="Mali L2 Cache" name="Write transactions, slave 0" description="Write transactions, slave 0" />\r
+    <event event="0x22" title="Mali L2 Cache" name="Words read, slave 0" description="Words read, slave 0" />\r
+    <event event="0x23" title="Mali L2 Cache" name="Words written, slave 0" description="Words written, slave 0" />\r
+    <event event="0x24" title="Mali L2 Cache" name="Read hits, slave 0" description="Read hits, slave 0" />\r
+    <event event="0x25" title="Mali L2 Cache" name="Read misses, slave 0" description="Read misses, slave 0" />\r
+    <event event="0x26" title="Mali L2 Cache" name="Write invalidates, slave 0" description="Write invalidates, slave 0" />\r
+    <event event="0x27" title="Mali L2 Cache" name="Read invalidates, slave 0" description="Read invalidates, slave 0" />\r
+    <event event="0x28" title="Mali L2 Cache" name="Cacheable read transactions, slave 0" description="Cacheable read transactions, slave 0" />\r
+    <event event="0x30" title="Mali L2 Cache" name="Read transactions, slave 1" description="Read transactions, slave 1" />\r
+    <event event="0x31" title="Mali L2 Cache" name="Write transactions, slave 1" description="Write transactions, slave 1" />\r
+    <event event="0x32" title="Mali L2 Cache" name="Words read, slave 1" description="Words read, slave 1" />\r
+    <event event="0x33" title="Mali L2 Cache" name="Words written, slave 1" description="Words written, slave 1" />\r
+    <event event="0x34" title="Mali L2 Cache" name="Read hits, slave 1" description="Read hits, slave 1" />\r
+    <event event="0x35" title="Mali L2 Cache" name="Read misses, slave 1" description="Read misses, slave 1" />\r
+    <event event="0x36" title="Mali L2 Cache" name="Write invalidates, slave 1" description="Write invalidates, slave 1" />\r
+    <event event="0x37" title="Mali L2 Cache" name="Read invalidates, slave 1" description="Read invalidates, slave 1" />\r
+    <event event="0x38" title="Mali L2 Cache" name="Cacheable read transactions, slave 1" description="Cacheable read transactions, slave 1" />\r
+    <event event="0x40" title="Mali L2 Cache" name="Read transactions, slave 2" description="Read transactions, slave 2" />\r
+    <event event="0x41" title="Mali L2 Cache" name="Write transactions, slave 2" description="Write transactions, slave 2" />\r
+    <event event="0x42" title="Mali L2 Cache" name="Words read, slave 2" description="Words read, slave 2" />\r
+    <event event="0x43" title="Mali L2 Cache" name="Words written, slave 2" description="Words written, slave 2" />\r
+    <event event="0x44" title="Mali L2 Cache" name="Read hits, slave 2" description="Read hits, slave 2" />\r
+    <event event="0x45" title="Mali L2 Cache" name="Read misses, slave 2" description="Read misses, slave 2" />\r
+    <event event="0x46" title="Mali L2 Cache" name="Write invalidates, slave 2" description="Write invalidates, slave 2" />\r
+    <event event="0x47" title="Mali L2 Cache" name="Read invalidates, slave 2" description="Read invalidates, slave 2" />\r
+    <event event="0x48" title="Mali L2 Cache" name="Cacheable read transactions, slave 2" description="Cacheable read transactions, slave 2" />\r
+    <event event="0x50" title="Mali L2 Cache" name="Read transactions, slave 3" description="Read transactions, slave 3" />\r
+    <event event="0x51" title="Mali L2 Cache" name="Write transactions, slave 3" description="Write transactions, slave 3" />\r
+    <event event="0x52" title="Mali L2 Cache" name="Words read, slave 3" description="Words read, slave 3" />\r
+    <event event="0x53" title="Mali L2 Cache" name="Words written, slave 3" description="Words written, slave 3" />\r
+    <event event="0x54" title="Mali L2 Cache" name="Read hits, slave 3" description="Read hits, slave 3" />\r
+    <event event="0x55" title="Mali L2 Cache" name="Read misses, slave 3" description="Read misses, slave 3" />\r
+    <event event="0x56" title="Mali L2 Cache" name="Write invalidates, slave 3" description="Write invalidates, slave 3" />\r
+    <event event="0x57" title="Mali L2 Cache" name="Read invalidates, slave 3" description="Read invalidates, slave 3" />\r
+    <event event="0x58" title="Mali L2 Cache" name="Cacheable read transactions, slave 3" description="Cacheable read transactions, slave 3" />\r
+    <event event="0x60" title="Mali L2 Cache" name="Read transactions, slave 4" description="Read transactions, slave 4" />\r
+    <event event="0x61" title="Mali L2 Cache" name="Write transactions, slave 4" description="Write transactions, slave 4" />\r
+    <event event="0x62" title="Mali L2 Cache" name="Words read, slave 4" description="Words read, slave 4" />\r
+    <event event="0x63" title="Mali L2 Cache" name="Words written, slave 4" description="Words written, slave 4" />\r
+    <event event="0x64" title="Mali L2 Cache" name="Read hits, slave 4" description="Read hits, slave 4" />\r
+    <event event="0x65" title="Mali L2 Cache" name="Read misses, slave 4" description="Read misses, slave 4" />\r
+    <event event="0x66" title="Mali L2 Cache" name="Write invalidates, slave 4" description="Write invalidates, slave 4" />\r
+    <event event="0x67" title="Mali L2 Cache" name="Read invalidates, slave 4" description="Read invalidates, slave 4" />\r
+    <event event="0x68" title="Mali L2 Cache" name="Cacheable read transactions, slave 4" description="Cacheable read transactions, slave 4" />\r
+  </category>\r
+  <category name="ARM_Mali-400_Filmstrip" counter_set="ARM_Mali-400_Filmstrip_cntX" per_cpu="no">\r
+    <event event="0x040a" title="ARM_Mali-400_Filmstrip" name="Size 1:4, freq 1:10" description="Scaled framebuffer captures every 10th frame" />\r
+  </category>\r
+  <category name="Mali-400-SW" counter_set="ARM_Mali-400_SW_cntX" per_cpu="no">\r
+    <!-- EGL Counters -->\r
+    <event counter="ARM_Mali-400_SW_17" title="Mali EGL Software Counters" name="Blit Time" description="Time spent blitting the the framebuffer from video memory to framebuffer"/>\r
+    <!-- glDrawElements Counters -->\r
+    <event counter="ARM_Mali-400_SW_18" title="glDrawElements Statistics" name="Calls to glDrawElements" description="Number of calls to glDrawElements"/>\r
+    <event counter="ARM_Mali-400_SW_19" title="glDrawElements Statistics" name="Indices to glDrawElements" description="Number of indicies to glDrawElements"/>\r
+    <event counter="ARM_Mali-400_SW_20" title="glDrawElements Statistics" name="Transformed by glDrawElements" description="Number of vertices transformed by glDrawElements"/>\r
+    <!-- glDrawArrays Counters -->\r
+    <event counter="ARM_Mali-400_SW_21" title="glDrawArrays Statistics" name="Calls to glDrawArrays" description="Number of calls to glDrawArrays"/>\r
+    <event counter="ARM_Mali-400_SW_22" title="glDrawArrays Statistics" name="Transformed by glDrawArrays" description="Number of vertices transformed by glDrawArrays"/>\r
+    <!-- Draw Call Counters -->\r
+    <event counter="ARM_Mali-400_SW_23" title="Drawcall Statistics" name="Points" description="Number of calls to glDraw* with parameter GL_POINTS"/>\r
+    <event counter="ARM_Mali-400_SW_24" title="Drawcall Statistics" name="Lines" description="Number of calls to glDraw* with parameter GL_LINES"/>\r
+    <event counter="ARM_Mali-400_SW_25" title="Drawcall Statistics" name="Lineloop" description="Number of calls to glDraw* with parameter GL_LINE_LOOP"/>\r
+    <event counter="ARM_Mali-400_SW_26" title="Drawcall Statistics" name="Linestrip" description="Number of calls to glDraw* with parameter GL_LINE_STRIP"/>\r
+    <event counter="ARM_Mali-400_SW_27" title="Drawcall Statistics" name="Triangles" description="Number of calls to glDraw* with parameter GL_TRIANGLES"/>\r
+    <event counter="ARM_Mali-400_SW_28" title="Drawcall Statistics" name="Trianglestrip" description="Number of calls to glDraw* with parameter GL_TRIANGLE_STRIP"/>\r
+    <event counter="ARM_Mali-400_SW_29" title="Drawcall Statistics" name="Trianglefan" description="Number of calls to glDraw* with parameter GL_TRIANGLE_FAN"/>\r
+    <event counter="ARM_Mali-400_SW_30" title="Drawcall Statistics" name="Vertex Upload Time (us)" description="Time spent uploading vertex attributes and faceindex data not present in a VBO"/>\r
+    <event counter="ARM_Mali-400_SW_31" title="Drawcall Statistics" name="Uniform Bytes Copied (bytes)" description="Number of bytes copied to Mali memory as a result of uniforms update"/>\r
+    <!-- Buffer Profiling Counters -->\r
+    <event counter="ARM_Mali-400_SW_32" title="Buffer Profiling" name="Texture Upload Time (ms)" description="Time spent uploading textures"/>\r
+    <event counter="ARM_Mali-400_SW_33" title="Buffer Profiling" name="VBO Upload Time (ms)" description="Time spent uploading vertex buffer objects"/>\r
+    <event counter="ARM_Mali-400_SW_34" title="Buffer Profiling" name="FBO Flushes" description="Number of flushed on framebuffer attachement"/>\r
+    <!-- OpenGL ES 1.1 Emulation -->\r
+    <event counter="ARM_Mali-400_SW_35" title="Fixed-function Emulation" name="# Vertex Shaders Generated" description="Number of vertex shaders generated"/>\r
+    <event counter="ARM_Mali-400_SW_36" title="Fixed-function Emulation" name="# Fragment Shaders Generated" description="Number of fragment shaders generated"/>\r
+    <!-- Geometry Statistics -->\r
+    <event counter="ARM_Mali-400_SW_50" title="Geometry Statistics" name="Triangles" description="The total number of triangles passed to GLES per-frame"/>\r
+    <event counter="ARM_Mali-400_SW_51" title="Geometry Statistics" name="Independent Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLES"/>\r
+    <event counter="ARM_Mali-400_SW_52" title="Geometry Statistics" name="Strip Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLE_STRIP"/>\r
+    <event counter="ARM_Mali-400_SW_53" title="Geometry Statistics" name="Fan Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLE_FAN"/>\r
+    <event counter="ARM_Mali-400_SW_54" title="Geometry Statistics" name="Lines" description="Number of lines passed to GLES per-frame"/>\r
+    <event counter="ARM_Mali-400_SW_55" title="Geometry Statistics" name="Independent Lines" description="Number of lines passed to GLES using the mode GL_LINES"/>\r
+    <event counter="ARM_Mali-400_SW_56" title="Geometry Statistics" name="Strip Lines" description="Number of lines passed to GLES using the mode GL_LINE_STRIP"/>\r
+    <event counter="ARM_Mali-400_SW_57" title="Geometry Statistics" name="Loop Lines" description="Number of lines passed to GLES using the mode GL_LINE_LOOP"/>\r
+  </category>\r
+\r
index 212bfeda3b01f3c123b378237109bc72c4752114..8ad196a2dbfa05b70a10805a6a7f3d76963dc665 100644 (file)
-  <counter_set name="Scorpion_cntX">
-    <counter name="Scorpion_cnt0"/>
-    <counter name="Scorpion_cnt1"/>
-    <counter name="Scorpion_cnt2"/>
-    <counter name="Scorpion_cnt3"/>
-  </counter_set>
-  <category name="Scorpion" counter_set="Scorpion_cntX" per_cpu="yes">
-    <event counter="Scorpion_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>
-    <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
-    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
-    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
-    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
-    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
-    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
-    <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
-    <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
-       <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
-    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
-    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
-    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
-    <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>
-    <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
-    <event event="0x0f" title="Fault" name="Unaligned access" description="Unaligned access architecturally executed"/>
-    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
-       <event event="0x11" title="Cycle" name="Cycle" description=""/>
-    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
-       <event event="0x4c" title="Scorpion" name="ICACHE_EXPL_INV" description=""/>
-       <event event="0x4d" title="Scorpion" name="ICACHE_MISS" description=""/>
-       <event event="0x4e" title="Scorpion" name="ICACHE_ACCESS" description=""/>
-       <event event="0x4f" title="Scorpion" name="ICACHE_CACHEREQ_L2" description=""/>
-       <event event="0x50" title="Scorpion" name="ICACHE_NOCACHE_L2" description=""/>
-       <event event="0x51" title="Scorpion" name="HIQUP_NOPED" description=""/>
-       <event event="0x52" title="Scorpion" name="DATA_ABORT" description=""/>
-       <event event="0x53" title="Scorpion" name="IRQ" description=""/>
-       <event event="0x54" title="Scorpion" name="FIQ" description=""/>
-       <event event="0x55" title="Scorpion" name="ALL_EXCPT" description=""/>
-       <event event="0x56" title="Scorpion" name="UNDEF" description=""/>
-       <event event="0x57" title="Scorpion" name="SVC" description=""/>
-       <event event="0x58" title="Scorpion" name="SMC" description=""/>
-       <event event="0x59" title="Scorpion" name="PREFETCH_ABORT" description=""/>
-       <event event="0x5a" title="Scorpion" name="INDEX_CHECK" description=""/>
-       <event event="0x5b" title="Scorpion" name="NULL_CHECK" description=""/>
-       <event event="0x5c" title="Scorpion" name="EXPL_ICIALLU" description=""/>
-       <event event="0x5d" title="Scorpion" name="IMPL_ICIALLU" description=""/>
-       <event event="0x5e" title="Scorpion" name="NONICIALLU_BTAC_INV" description=""/>
-       <event event="0x5f" title="Scorpion" name="ICIMVAU_IMPL_ICIALLU" description=""/>
-       <event event="0x60" title="Scorpion" name="SPIPE_ONLY_CYCLES" description=""/>
-       <event event="0x61" title="Scorpion" name="XPIPE_ONLY_CYCLES" description=""/>
-       <event event="0x62" title="Scorpion" name="DUAL_CYCLES" description=""/>
-       <event event="0x63" title="Scorpion" name="DISPATCH_ANY_CYCLES" description=""/>
-       <event event="0x64" title="Scorpion" name="FIFO_FULLBLK_CMT" description=""/>
-       <event event="0x65" title="Scorpion" name="FAIL_COND_INST" description=""/>
-       <event event="0x66" title="Scorpion" name="PASS_COND_INST" description=""/>
-       <event event="0x67" title="Scorpion" name="ALLOW_VU_CLK" description=""/>
-       <event event="0x68" title="Scorpion" name="VU_IDLE" description=""/>
-       <event event="0x69" title="Scorpion" name="ALLOW_L2_CLK" description=""/>
-       <event event="0x6a" title="Scorpion" name="L2_IDLE" description=""/>
-       <event event="0x6b" title="Scorpion" name="DTLB_IMPL_INV_SCTLR_DACR" description=""/>
-       <event event="0x6c" title="Scorpion" name="DTLB_EXPL_INV" description=""/>
-       <event event="0x6d" title="Scorpion" name="DTLB_MISS" description=""/>
-       <event event="0x6e" title="Scorpion" name="DTLB_ACCESS" description=""/>
-       <event event="0x6f" title="Scorpion" name="ITLB_MISS" description=""/>
-       <event event="0x70" title="Scorpion" name="ITLB_IMPL_INV" description=""/>
-       <event event="0x71" title="Scorpion" name="ITLB_EXPL_INV" description=""/>
-       <event event="0x72" title="Scorpion" name="UTLB_D_MISS" description=""/>
-       <event event="0x73" title="Scorpion" name="UTLB_D_ACCESS" description=""/>
-       <event event="0x74" title="Scorpion" name="UTLB_I_MISS" description=""/>
-       <event event="0x75" title="Scorpion" name="UTLB_I_ACCESS" description=""/>
-       <event event="0x76" title="Scorpion" name="UTLB_INV_ASID" description=""/>
-       <event event="0x77" title="Scorpion" name="UTLB_INV_MVA" description=""/>
-       <event event="0x78" title="Scorpion" name="UTLB_INV_ALL" description=""/>
-       <event event="0x79" title="Scorpion" name="S2_HOLD_RDQ_UNAVAIL" description=""/>
-       <event event="0x7a" title="Scorpion" name="S2_HOLD" description=""/>
-       <event event="0x7b" title="Scorpion" name="S2_HOLD_DEV_OP" description=""/>
-       <event event="0x7c" title="Scorpion" name="S2_HOLD_ORDER" description=""/>
-       <event event="0x7d" title="Scorpion" name="S2_HOLD_BARRIER" description=""/>
-       <event event="0x7e" title="Scorpion" name="VIU_DUAL_CYCLE" description=""/>
-       <event event="0x7f" title="Scorpion" name="VIU_SINGLE_CYCLE" description=""/>
-       <event event="0x80" title="Scorpion" name="VX_PIPE_WAR_STALL_CYCLES" description=""/>
-       <event event="0x81" title="Scorpion" name="VX_PIPE_WAW_STALL_CYCLES" description=""/>
-       <event event="0x82" title="Scorpion" name="VX_PIPE_RAW_STALL_CYCLES" description=""/>
-       <event event="0x83" title="Scorpion" name="VX_PIPE_LOAD_USE_STALL" description=""/>
-       <event event="0x84" title="Scorpion" name="VS_PIPE_WAR_STALL_CYCLES" description=""/>
-       <event event="0x85" title="Scorpion" name="VS_PIPE_WAW_STALL_CYCLES" description=""/>
-       <event event="0x86" title="Scorpion" name="VS_PIPE_RAW_STALL_CYCLES" description=""/>
-       <event event="0x87" title="Scorpion" name="EXCEPTIONS_INV_OPERATION" description=""/>
-       <event event="0x88" title="Scorpion" name="EXCEPTIONS_DIV_BY_ZERO" description=""/>
-       <event event="0x89" title="Scorpion" name="COND_INST_FAIL_VX_PIPE" description=""/>
-       <event event="0x8a" title="Scorpion" name="COND_INST_FAIL_VS_PIPE" description=""/>
-       <event event="0x8b" title="Scorpion" name="EXCEPTIONS_OVERFLOW" description=""/>
-       <event event="0x8c" title="Scorpion" name="EXCEPTIONS_UNDERFLOW" description=""/>
-       <event event="0x8d" title="Scorpion" name="EXCEPTIONS_DENORM" description=""/>
-       <event event="0x8e" title="Scorpion" name="BANK_AB_HIT" description=""/>
-       <event event="0x8f" title="Scorpion" name="BANK_AB_ACCESS" description=""/>
-       <event event="0x90" title="Scorpion" name="BANK_CD_HIT" description=""/>
-       <event event="0x91" title="Scorpion" name="BANK_CD_ACCESS" description=""/>
-       <event event="0x92" title="Scorpion" name="BANK_AB_DSIDE_HIT" description=""/>
-       <event event="0x93" title="Scorpion" name="BANK_AB_DSIDE_ACCESS" description=""/>
-       <event event="0x94" title="Scorpion" name="BANK_CD_DSIDE_HIT" description=""/>
-       <event event="0x95" title="Scorpion" name="BANK_CD_DSIDE_ACCESS" description=""/>
-       <event event="0x96" title="Scorpion" name="BANK_AB_ISIDE_HIT" description=""/>
-       <event event="0x97" title="Scorpion" name="BANK_AB_ISIDE_ACCESS" description=""/>
-       <event event="0x98" title="Scorpion" name="BANK_CD_ISIDE_HIT" description=""/>
-       <event event="0x99" title="Scorpion" name="BANK_CD_ISIDE_ACCESS" description=""/>
-       <event event="0x9a" title="Scorpion" name="ISIDE_RD_WAIT" description=""/>
-       <event event="0x9b" title="Scorpion" name="DSIDE_RD_WAIT" description=""/>
-       <event event="0x9c" title="Scorpion" name="BANK_BYPASS_WRITE" description=""/>
-       <event event="0x9d" title="Scorpion" name="BANK_AB_NON_CASTOUT" description=""/>
-       <event event="0x9e" title="Scorpion" name="BANK_AB_L2_CASTOUT" description=""/>
-       <event event="0x9f" title="Scorpion" name="BANK_CD_NON_CASTOUT" description=""/>
-       <event event="0xa0" title="Scorpion" name="BANK_CD_L2_CASTOUT" description=""/>
-  </category>
+  <counter_set name="Scorpion_cntX">\r
+    <counter name="Scorpion_cnt0"/>\r
+    <counter name="Scorpion_cnt1"/>\r
+    <counter name="Scorpion_cnt2"/>\r
+    <counter name="Scorpion_cnt3"/>\r
+  </counter_set>\r
+  <category name="Scorpion" counter_set="Scorpion_cntX" per_cpu="yes">\r
+    <event counter="Scorpion_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>\r
+    <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>\r
+    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>\r
+    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>\r
+    <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>\r
+       <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>\r
+    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>\r
+    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>\r
+    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>\r
+    <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>\r
+    <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>\r
+    <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/>\r
+    <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>\r
+    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>\r
+    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>\r
+       <event event="0x4c" title="Scorpion" name="ICACHE_EXPL_INV" description="I-cache explicit invalidates"/>\r
+       <event event="0x4d" title="Scorpion" name="ICACHE_MISS" description="I-cache misses"/>\r
+       <event event="0x4e" title="Scorpion" name="ICACHE_ACCESS" description="I-cache accesses"/>\r
+       <event event="0x4f" title="Scorpion" name="ICACHE_CACHEREQ_L2" description="I-cache cacheable requests to L2"/>\r
+       <event event="0x50" title="Scorpion" name="ICACHE_NOCACHE_L2" description="I-cache non-cacheable requests to L2"/>\r
+       <event event="0x51" title="Scorpion" name="HIQUP_NOPED" description="Conditional instructions HIQUPs NOPed"/>\r
+       <event event="0x52" title="Scorpion" name="DATA_ABORT" description="Interrupts and Exceptions Data Abort"/>\r
+       <event event="0x53" title="Scorpion" name="IRQ" description="Interrupts and Exceptions IRQ"/>\r
+       <event event="0x54" title="Scorpion" name="FIQ" description="Interrupts and Exceptions FIQ"/>\r
+       <event event="0x55" title="Scorpion" name="ALL_EXCPT" description="Interrupts and Exceptions All interrupts"/>\r
+       <event event="0x56" title="Scorpion" name="UNDEF" description="Interrupts and Exceptions Undefined"/>\r
+       <event event="0x57" title="Scorpion" name="SVC" description="Interrupts and Exceptions SVC"/>\r
+       <event event="0x58" title="Scorpion" name="SMC" description="Interrupts and Exceptions SMC"/>\r
+       <event event="0x59" title="Scorpion" name="PREFETCH_ABORT" description="Interrupts and Exceptions Prefetch Abort"/>\r
+       <event event="0x5a" title="Scorpion" name="INDEX_CHECK" description="Interrupts and Exceptions Index Check"/>\r
+       <event event="0x5b" title="Scorpion" name="NULL_CHECK" description="Interrupts and Exceptions Null Check"/>\r
+       <event event="0x5c" title="Scorpion" name="EXPL_ICIALLU" description="I-cache and BTAC Invalidates Explicit ICIALLU"/>\r
+       <event event="0x5d" title="Scorpion" name="IMPL_ICIALLU" description="I-cache and BTAC Invalidates Implicit ICIALLU"/>\r
+       <event event="0x5e" title="Scorpion" name="NONICIALLU_BTAC_INV" description="I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate"/>\r
+       <event event="0x5f" title="Scorpion" name="ICIMVAU_IMPL_ICIALLU" description="I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU"/>\r
+       <event event="0x60" title="Scorpion" name="SPIPE_ONLY_CYCLES" description="Issue S-pipe only issue cycles"/>\r
+       <event event="0x61" title="Scorpion" name="XPIPE_ONLY_CYCLES" description="Issue X-pipe only issue cycles"/>\r
+       <event event="0x62" title="Scorpion" name="DUAL_CYCLES" description="Issue dual issue cycles"/>\r
+       <event event="0x63" title="Scorpion" name="DISPATCH_ANY_CYCLES" description="Dispatch any dispatch cycles"/>\r
+       <event event="0x64" title="Scorpion" name="FIFO_FULLBLK_CMT" description="Commits Trace FIFO full Blk CMT"/>\r
+       <event event="0x65" title="Scorpion" name="FAIL_COND_INST" description="Conditional instructions failing conditional instrs (excluding branches)"/>\r
+       <event event="0x66" title="Scorpion" name="PASS_COND_INST" description="Conditional instructions passing conditional instrs (excluding branches)"/>\r
+       <event event="0x67" title="Scorpion" name="ALLOW_VU_CLK" description="Unit Clock Gating Allow VU Clks"/>\r
+       <event event="0x68" title="Scorpion" name="VU_IDLE" description="Unit Clock Gating VU Idle"/>\r
+       <event event="0x69" title="Scorpion" name="ALLOW_L2_CLK" description="Unit Clock Gating Allow L2 Clks"/>\r
+       <event event="0x6a" title="Scorpion" name="L2_IDLE" description="Unit Clock Gating L2 Idle"/>\r
+       <event event="0x6b" title="Scorpion" name="DTLB_IMPL_INV_SCTLR_DACR" description="DTLB implicit invalidates writes to SCTLR and DACR"/>\r
+       <event event="0x6c" title="Scorpion" name="DTLB_EXPL_INV" description="DTLB explicit invalidates"/>\r
+       <event event="0x6d" title="Scorpion" name="DTLB_MISS" description="DTLB misses"/>\r
+       <event event="0x6e" title="Scorpion" name="DTLB_ACCESS" description="DTLB accesses"/>\r
+       <event event="0x6f" title="Scorpion" name="ITLB_MISS" description="ITLB misses"/>\r
+       <event event="0x70" title="Scorpion" name="ITLB_IMPL_INV" description="ITLB implicit ITLB invalidates"/>\r
+       <event event="0x71" title="Scorpion" name="ITLB_EXPL_INV" description="ITLB explicit ITLB invalidates"/>\r
+       <event event="0x72" title="Scorpion" name="UTLB_D_MISS" description="UTLB d-side misses"/>\r
+       <event event="0x73" title="Scorpion" name="UTLB_D_ACCESS" description="UTLB d-side accesses"/>\r
+       <event event="0x74" title="Scorpion" name="UTLB_I_MISS" description="UTLB i-side misses"/>\r
+       <event event="0x75" title="Scorpion" name="UTLB_I_ACCESS" description="UTLB i-side accesses"/>\r
+       <event event="0x76" title="Scorpion" name="UTLB_INV_ASID" description="UTLB invalidate by ASID"/>\r
+       <event event="0x77" title="Scorpion" name="UTLB_INV_MVA" description="UTLB invalidate by MVA"/>\r
+       <event event="0x78" title="Scorpion" name="UTLB_INV_ALL" description="UTLB invalidate all"/>\r
+       <event event="0x79" title="Scorpion" name="S2_HOLD_RDQ_UNAVAIL" description="S2 hold RDQ unavail"/>\r
+       <event event="0x7a" title="Scorpion" name="S2_HOLD" description="S2 hold"/>\r
+       <event event="0x7b" title="Scorpion" name="S2_HOLD_DEV_OP" description="S2 hold device op"/>\r
+       <event event="0x7c" title="Scorpion" name="S2_HOLD_ORDER" description="S2 hold strongly ordered op"/>\r
+       <event event="0x7d" title="Scorpion" name="S2_HOLD_BARRIER" description="S2 hold barrier"/>\r
+       <event event="0x7e" title="Scorpion" name="VIU_DUAL_CYCLE" description="Scorpion VIU dual cycle"/>\r
+       <event event="0x7f" title="Scorpion" name="VIU_SINGLE_CYCLE" description="Scorpion VIU single cycle"/>\r
+       <event event="0x80" title="Scorpion" name="VX_PIPE_WAR_STALL_CYCLES" description="Scorpion VX pipe WAR cycles"/>\r
+       <event event="0x81" title="Scorpion" name="VX_PIPE_WAW_STALL_CYCLES" description="Scorpion VX pipe WAW cycles"/>\r
+       <event event="0x82" title="Scorpion" name="VX_PIPE_RAW_STALL_CYCLES" description="Scorpion VX pipe RAW cycles"/>\r
+       <event event="0x83" title="Scorpion" name="VX_PIPE_LOAD_USE_STALL" description="Scorpion VX pipe load use stall"/>\r
+       <event event="0x84" title="Scorpion" name="VS_PIPE_WAR_STALL_CYCLES" description="Scorpion VS pipe WAR stall cycles"/>\r
+       <event event="0x85" title="Scorpion" name="VS_PIPE_WAW_STALL_CYCLES" description="Scorpion VS pipe WAW stall cycles"/>\r
+       <event event="0x86" title="Scorpion" name="VS_PIPE_RAW_STALL_CYCLES" description="Scorpion VS pipe RAW stall cycles"/>\r
+       <event event="0x87" title="Scorpion" name="EXCEPTIONS_INV_OPERATION" description="Scorpion invalid operation exceptions"/>\r
+       <event event="0x88" title="Scorpion" name="EXCEPTIONS_DIV_BY_ZERO" description="Scorpion divide by zero exceptions"/>\r
+       <event event="0x89" title="Scorpion" name="COND_INST_FAIL_VX_PIPE" description="Scorpion conditional instruction fail VX pipe"/>\r
+       <event event="0x8a" title="Scorpion" name="COND_INST_FAIL_VS_PIPE" description="Scorpion conditional instruction fail VS pipe"/>\r
+       <event event="0x8b" title="Scorpion" name="EXCEPTIONS_OVERFLOW" description="Scorpion overflow exceptions"/>\r
+       <event event="0x8c" title="Scorpion" name="EXCEPTIONS_UNDERFLOW" description="Scorpion underflow exceptions"/>\r
+       <event event="0x8d" title="Scorpion" name="EXCEPTIONS_DENORM" description="Scorpion denorm exceptions"/>\r
+       <event event="0x8e" title="Scorpion" name="BANK_AB_HIT" description="L2 hit rates bank A/B hits"/>\r
+       <event event="0x8f" title="Scorpion" name="BANK_AB_ACCESS" description="L2 hit rates bank A/B accesses"/>\r
+       <event event="0x90" title="Scorpion" name="BANK_CD_HIT" description="L2 hit rates bank C/D hits"/>\r
+       <event event="0x91" title="Scorpion" name="BANK_CD_ACCESS" description="L2 hit rates bank C/D accesses"/>\r
+       <event event="0x92" title="Scorpion" name="BANK_AB_DSIDE_HIT" description="L2 hit rates bank A/B d-side hits"/>\r
+       <event event="0x93" title="Scorpion" name="BANK_AB_DSIDE_ACCESS" description="L2 hit rates bank A/B d-side accesses"/>\r
+       <event event="0x94" title="Scorpion" name="BANK_CD_DSIDE_HIT" description="L2 hit rates bank C/D d-side hits"/>\r
+       <event event="0x95" title="Scorpion" name="BANK_CD_DSIDE_ACCESS" description="L2 hit rates bank C/D d-side accesses"/>\r
+       <event event="0x96" title="Scorpion" name="BANK_AB_ISIDE_HIT" description="L2 hit rates bank A/B i-side hits"/>\r
+       <event event="0x97" title="Scorpion" name="BANK_AB_ISIDE_ACCESS" description="L2 hit rates bank A/B i-side accesses"/>\r
+       <event event="0x98" title="Scorpion" name="BANK_CD_ISIDE_HIT" description="L2 hit rates bank C/D i-side hits"/>\r
+       <event event="0x99" title="Scorpion" name="BANK_CD_ISIDE_ACCESS" description="L2 hit rates bank C/D i-side accesses"/>\r
+       <event event="0x9a" title="Scorpion" name="ISIDE_RD_WAIT" description="fills and castouts cycles that i-side RD requests wait on data from bus"/>\r
+       <event event="0x9b" title="Scorpion" name="DSIDE_RD_WAIT" description="fills and castouts cycles that d-side RD requests wait on data from bus"/>\r
+       <event event="0x9c" title="Scorpion" name="BANK_BYPASS_WRITE" description="fills and castouts bank bypass writes"/>\r
+       <event event="0x9d" title="Scorpion" name="BANK_AB_NON_CASTOUT" description="fills and castouts bank A/B non-castout writes to bus"/>\r
+       <event event="0x9e" title="Scorpion" name="BANK_AB_L2_CASTOUT" description="fills and castouts bank A/B L2 castouts (granules)"/>\r
+       <event event="0x9f" title="Scorpion" name="BANK_CD_NON_CASTOUT" description="fills and castouts bank C/D non-castout writes to bus"/>\r
+       <event event="0xa0" title="Scorpion" name="BANK_CD_L2_CASTOUT" description="fills and castouts bank C/D L2 castouts (granules)"/>\r
+  </category>\r
   
\ No newline at end of file
index 22c93a01e5d5c87c7fa7726757c8cf75162c57cd..bd13b8a9b3a09e0f05e70d95463dba935ac4256d 100644 (file)
@@ -1,96 +1,96 @@
-  <counter_set name="ScorpionMP_cntX">
-    <counter name="ScorpionMP_cnt0"/>
-    <counter name="ScorpionMP_cnt1"/>
-    <counter name="ScorpionMP_cnt2"/>
-    <counter name="ScorpionMP_cnt3"/>
-  </counter_set>
-  <category name="ScorpionMP" counter_set="ScorpionMP_cntX" per_cpu="yes">
-    <event counter="ScorpionMP_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>
-    <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
-    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
-    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
-    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
-    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
-    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
-    <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
-    <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
-       <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
-    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
-    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
-    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
-    <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>
-    <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
-    <event event="0x0f" title="Fault" name="Unaligned access" description="Unaligned access architecturally executed"/>
-    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
-       <event event="0x11" title="Cycle" name="Cycle" description=""/>
-    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
-       <event event="0x4c" title="Scorpion" name="ICACHE_EXPL_INV" description=""/>
-       <event event="0x4d" title="Scorpion" name="ICACHE_MISS" description=""/>
-       <event event="0x4e" title="Scorpion" name="ICACHE_ACCESS" description=""/>
-       <event event="0x4f" title="Scorpion" name="ICACHE_CACHEREQ_L2" description=""/>
-       <event event="0x50" title="Scorpion" name="ICACHE_NOCACHE_L2" description=""/>
-       <event event="0x51" title="Scorpion" name="HIQUP_NOPED" description=""/>
-       <event event="0x52" title="Scorpion" name="DATA_ABORT" description=""/>
-       <event event="0x53" title="Scorpion" name="IRQ" description=""/>
-       <event event="0x54" title="Scorpion" name="FIQ" description=""/>
-       <event event="0x55" title="Scorpion" name="ALL_EXCPT" description=""/>
-       <event event="0x56" title="Scorpion" name="UNDEF" description=""/>
-       <event event="0x57" title="Scorpion" name="SVC" description=""/>
-       <event event="0x58" title="Scorpion" name="SMC" description=""/>
-       <event event="0x59" title="Scorpion" name="PREFETCH_ABORT" description=""/>
-       <event event="0x5a" title="Scorpion" name="INDEX_CHECK" description=""/>
-       <event event="0x5b" title="Scorpion" name="NULL_CHECK" description=""/>
-       <event event="0x5c" title="Scorpion" name="EXPL_ICIALLU" description=""/>
-       <event event="0x5d" title="Scorpion" name="IMPL_ICIALLU" description=""/>
-       <event event="0x5e" title="Scorpion" name="NONICIALLU_BTAC_INV" description=""/>
-       <event event="0x5f" title="Scorpion" name="ICIMVAU_IMPL_ICIALLU" description=""/>
-       <event event="0x60" title="Scorpion" name="SPIPE_ONLY_CYCLES" description=""/>
-       <event event="0x61" title="Scorpion" name="XPIPE_ONLY_CYCLES" description=""/>
-       <event event="0x62" title="Scorpion" name="DUAL_CYCLES" description=""/>
-       <event event="0x63" title="Scorpion" name="DISPATCH_ANY_CYCLES" description=""/>
-       <event event="0x64" title="Scorpion" name="FIFO_FULLBLK_CMT" description=""/>
-       <event event="0x65" title="Scorpion" name="FAIL_COND_INST" description=""/>
-       <event event="0x66" title="Scorpion" name="PASS_COND_INST" description=""/>
-       <event event="0x67" title="Scorpion" name="ALLOW_VU_CLK" description=""/>
-       <event event="0x68" title="Scorpion" name="VU_IDLE" description=""/>
-       <event event="0x69" title="Scorpion" name="ALLOW_L2_CLK" description=""/>
-       <event event="0x6a" title="Scorpion" name="L2_IDLE" description=""/>
-       <event event="0x6b" title="Scorpion" name="DTLB_IMPL_INV_SCTLR_DACR" description=""/>
-       <event event="0x6c" title="Scorpion" name="DTLB_EXPL_INV" description=""/>
-       <event event="0x6d" title="Scorpion" name="DTLB_MISS" description=""/>
-       <event event="0x6e" title="Scorpion" name="DTLB_ACCESS" description=""/>
-       <event event="0x6f" title="Scorpion" name="ITLB_MISS" description=""/>
-       <event event="0x70" title="Scorpion" name="ITLB_IMPL_INV" description=""/>
-       <event event="0x71" title="Scorpion" name="ITLB_EXPL_INV" description=""/>
-       <event event="0x72" title="Scorpion" name="UTLB_D_MISS" description=""/>
-       <event event="0x73" title="Scorpion" name="UTLB_D_ACCESS" description=""/>
-       <event event="0x74" title="Scorpion" name="UTLB_I_MISS" description=""/>
-       <event event="0x75" title="Scorpion" name="UTLB_I_ACCESS" description=""/>
-       <event event="0x76" title="Scorpion" name="UTLB_INV_ASID" description=""/>
-       <event event="0x77" title="Scorpion" name="UTLB_INV_MVA" description=""/>
-       <event event="0x78" title="Scorpion" name="UTLB_INV_ALL" description=""/>
-       <event event="0x79" title="Scorpion" name="S2_HOLD_RDQ_UNAVAIL" description=""/>
-       <event event="0x7a" title="Scorpion" name="S2_HOLD" description=""/>
-       <event event="0x7b" title="Scorpion" name="S2_HOLD_DEV_OP" description=""/>
-       <event event="0x7c" title="Scorpion" name="S2_HOLD_ORDER" description=""/>
-       <event event="0x7d" title="Scorpion" name="S2_HOLD_BARRIER" description=""/>
-       <event event="0x7e" title="Scorpion" name="VIU_DUAL_CYCLE" description=""/>
-       <event event="0x7f" title="Scorpion" name="VIU_SINGLE_CYCLE" description=""/>
-       <event event="0x80" title="Scorpion" name="VX_PIPE_WAR_STALL_CYCLES" description=""/>
-       <event event="0x81" title="Scorpion" name="VX_PIPE_WAW_STALL_CYCLES" description=""/>
-       <event event="0x82" title="Scorpion" name="VX_PIPE_RAW_STALL_CYCLES" description=""/>
-       <event event="0x83" title="Scorpion" name="VX_PIPE_LOAD_USE_STALL" description=""/>
-       <event event="0x84" title="Scorpion" name="VS_PIPE_WAR_STALL_CYCLES" description=""/>
-       <event event="0x85" title="Scorpion" name="VS_PIPE_WAW_STALL_CYCLES" description=""/>
-       <event event="0x86" title="Scorpion" name="VS_PIPE_RAW_STALL_CYCLES" description=""/>
-       <event event="0x87" title="Scorpion" name="EXCEPTIONS_INV_OPERATION" description=""/>
-       <event event="0x88" title="Scorpion" name="EXCEPTIONS_DIV_BY_ZERO" description=""/>
-       <event event="0x89" title="Scorpion" name="COND_INST_FAIL_VX_PIPE" description=""/>
-       <event event="0x8a" title="Scorpion" name="COND_INST_FAIL_VS_PIPE" description=""/>
-       <event event="0x8b" title="Scorpion" name="EXCEPTIONS_OVERFLOW" description=""/>
-       <event event="0x8c" title="Scorpion" name="EXCEPTIONS_UNDERFLOW" description=""/>
-       <event event="0x8d" title="Scorpion" name="EXCEPTIONS_DENORM" description=""/>
-       <event event="0x8e" title="ScorpionMP" name="NUM_BARRIERS" description=""/>
-       <event event="0x8f" title="ScorpionMP" name="BARRIER_CYCLES" description=""/>
-  </category>  
+  <counter_set name="ScorpionMP_cntX">\r
+    <counter name="ScorpionMP_cnt0"/>\r
+    <counter name="ScorpionMP_cnt1"/>\r
+    <counter name="ScorpionMP_cnt2"/>\r
+    <counter name="ScorpionMP_cnt3"/>\r
+  </counter_set>\r
+  <category name="ScorpionMP" counter_set="ScorpionMP_cntX" per_cpu="yes">\r
+    <event counter="ScorpionMP_ccnt" title="Clock" name="Cycles" description="The number of core clock cycles"/>\r
+    <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>\r
+    <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>\r
+    <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>\r
+    <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>\r
+    <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>\r
+    <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>\r
+       <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>\r
+    <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>\r
+    <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>\r
+    <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>\r
+    <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>\r
+    <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>\r
+    <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/>\r
+    <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>\r
+    <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>\r
+    <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>\r
+       <event event="0x4c" title="Scorpion" name="ICACHE_EXPL_INV" description="I-cache explicit invalidates"/>\r
+       <event event="0x4d" title="Scorpion" name="ICACHE_MISS" description="I-cache misses"/>\r
+       <event event="0x4e" title="Scorpion" name="ICACHE_ACCESS" description="I-cache accesses"/>\r
+       <event event="0x4f" title="Scorpion" name="ICACHE_CACHEREQ_L2" description="I-cache cacheable requests to L2"/>\r
+       <event event="0x50" title="Scorpion" name="ICACHE_NOCACHE_L2" description="I-cache non-cacheable requests to L2"/>\r
+       <event event="0x51" title="Scorpion" name="HIQUP_NOPED" description="Conditional instructions HIQUPs NOPed"/>\r
+       <event event="0x52" title="Scorpion" name="DATA_ABORT" description="Interrupts and Exceptions Data Abort"/>\r
+       <event event="0x53" title="Scorpion" name="IRQ" description="Interrupts and Exceptions IRQ"/>\r
+       <event event="0x54" title="Scorpion" name="FIQ" description="Interrupts and Exceptions FIQ"/>\r
+       <event event="0x55" title="Scorpion" name="ALL_EXCPT" description="Interrupts and Exceptions All interrupts"/>\r
+       <event event="0x56" title="Scorpion" name="UNDEF" description="Interrupts and Exceptions Undefined"/>\r
+       <event event="0x57" title="Scorpion" name="SVC" description="Interrupts and Exceptions SVC"/>\r
+       <event event="0x58" title="Scorpion" name="SMC" description="Interrupts and Exceptions SMC"/>\r
+       <event event="0x59" title="Scorpion" name="PREFETCH_ABORT" description="Interrupts and Exceptions Prefetch Abort"/>\r
+       <event event="0x5a" title="Scorpion" name="INDEX_CHECK" description="Interrupts and Exceptions Index Check"/>\r
+       <event event="0x5b" title="Scorpion" name="NULL_CHECK" description="Interrupts and Exceptions Null Check"/>\r
+       <event event="0x5c" title="Scorpion" name="EXPL_ICIALLU" description="I-cache and BTAC Invalidates Explicit ICIALLU"/>\r
+       <event event="0x5d" title="Scorpion" name="IMPL_ICIALLU" description="I-cache and BTAC Invalidates Implicit ICIALLU"/>\r
+       <event event="0x5e" title="Scorpion" name="NONICIALLU_BTAC_INV" description="I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate"/>\r
+       <event event="0x5f" title="Scorpion" name="ICIMVAU_IMPL_ICIALLU" description="I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU"/>\r
+       <event event="0x60" title="Scorpion" name="SPIPE_ONLY_CYCLES" description="Issue S-pipe only issue cycles"/>\r
+       <event event="0x61" title="Scorpion" name="XPIPE_ONLY_CYCLES" description="Issue X-pipe only issue cycles"/>\r
+       <event event="0x62" title="Scorpion" name="DUAL_CYCLES" description="Issue dual issue cycles"/>\r
+       <event event="0x63" title="Scorpion" name="DISPATCH_ANY_CYCLES" description="Dispatch any dispatch cycles"/>\r
+       <event event="0x64" title="Scorpion" name="FIFO_FULLBLK_CMT" description="Commits Trace FIFO full Blk CMT"/>\r
+       <event event="0x65" title="Scorpion" name="FAIL_COND_INST" description="Conditional instructions failing conditional instrs (excluding branches)"/>\r
+       <event event="0x66" title="Scorpion" name="PASS_COND_INST" description="Conditional instructions passing conditional instrs (excluding branches)"/>\r
+       <event event="0x67" title="Scorpion" name="ALLOW_VU_CLK" description="Unit Clock Gating Allow VU Clks"/>\r
+       <event event="0x68" title="Scorpion" name="VU_IDLE" description="Unit Clock Gating VU Idle"/>\r
+       <event event="0x69" title="Scorpion" name="ALLOW_L2_CLK" description="Unit Clock Gating Allow L2 Clks"/>\r
+       <event event="0x6a" title="Scorpion" name="L2_IDLE" description="Unit Clock Gating L2 Idle"/>\r
+       <event event="0x6b" title="Scorpion" name="DTLB_IMPL_INV_SCTLR_DACR" description="DTLB implicit invalidates writes to SCTLR and DACR"/>\r
+       <event event="0x6c" title="Scorpion" name="DTLB_EXPL_INV" description="DTLB explicit invalidates"/>\r
+       <event event="0x6d" title="Scorpion" name="DTLB_MISS" description="DTLB misses"/>\r
+       <event event="0x6e" title="Scorpion" name="DTLB_ACCESS" description="DTLB accesses"/>\r
+       <event event="0x6f" title="Scorpion" name="ITLB_MISS" description="ITLB misses"/>\r
+       <event event="0x70" title="Scorpion" name="ITLB_IMPL_INV" description="ITLB implicit ITLB invalidates"/>\r
+       <event event="0x71" title="Scorpion" name="ITLB_EXPL_INV" description="ITLB explicit ITLB invalidates"/>\r
+       <event event="0x72" title="Scorpion" name="UTLB_D_MISS" description="UTLB d-side misses"/>\r
+       <event event="0x73" title="Scorpion" name="UTLB_D_ACCESS" description="UTLB d-side accesses"/>\r
+       <event event="0x74" title="Scorpion" name="UTLB_I_MISS" description="UTLB i-side misses"/>\r
+       <event event="0x75" title="Scorpion" name="UTLB_I_ACCESS" description="UTLB i-side accesses"/>\r
+       <event event="0x76" title="Scorpion" name="UTLB_INV_ASID" description="UTLB invalidate by ASID"/>\r
+       <event event="0x77" title="Scorpion" name="UTLB_INV_MVA" description="UTLB invalidate by MVA"/>\r
+       <event event="0x78" title="Scorpion" name="UTLB_INV_ALL" description="UTLB invalidate all"/>\r
+       <event event="0x79" title="Scorpion" name="S2_HOLD_RDQ_UNAVAIL" description="S2 hold RDQ unavail"/>\r
+       <event event="0x7a" title="Scorpion" name="S2_HOLD" description="S2 hold"/>\r
+       <event event="0x7b" title="Scorpion" name="S2_HOLD_DEV_OP" description="S2 hold device op"/>\r
+       <event event="0x7c" title="Scorpion" name="S2_HOLD_ORDER" description="S2 hold strongly ordered op"/>\r
+       <event event="0x7d" title="Scorpion" name="S2_HOLD_BARRIER" description="S2 hold barrier"/>\r
+       <event event="0x7e" title="Scorpion" name="VIU_DUAL_CYCLE" description="Scorpion VIU dual cycle"/>\r
+       <event event="0x7f" title="Scorpion" name="VIU_SINGLE_CYCLE" description="Scorpion VIU single cycle"/>\r
+       <event event="0x80" title="Scorpion" name="VX_PIPE_WAR_STALL_CYCLES" description="Scorpion VX pipe WAR cycles"/>\r
+       <event event="0x81" title="Scorpion" name="VX_PIPE_WAW_STALL_CYCLES" description="Scorpion VX pipe WAW cycles"/>\r
+       <event event="0x82" title="Scorpion" name="VX_PIPE_RAW_STALL_CYCLES" description="Scorpion VX pipe RAW cycles"/>\r
+       <event event="0x83" title="Scorpion" name="VX_PIPE_LOAD_USE_STALL" description="Scorpion VX pipe load use stall"/>\r
+       <event event="0x84" title="Scorpion" name="VS_PIPE_WAR_STALL_CYCLES" description="Scorpion VS pipe WAR stall cycles"/>\r
+       <event event="0x85" title="Scorpion" name="VS_PIPE_WAW_STALL_CYCLES" description="Scorpion VS pipe WAW stall cycles"/>\r
+       <event event="0x86" title="Scorpion" name="VS_PIPE_RAW_STALL_CYCLES" description="Scorpion VS pipe RAW stall cycles"/>\r
+       <event event="0x87" title="Scorpion" name="EXCEPTIONS_INV_OPERATION" description="Scorpion invalid operation exceptions"/>\r
+       <event event="0x88" title="Scorpion" name="EXCEPTIONS_DIV_BY_ZERO" description="Scorpion divide by zero exceptions"/>\r
+       <event event="0x89" title="Scorpion" name="COND_INST_FAIL_VX_PIPE" description="Scorpion conditional instruction fail VX pipe"/>\r
+       <event event="0x8a" title="Scorpion" name="COND_INST_FAIL_VS_PIPE" description="Scorpion conditional instruction fail VS pipe"/>\r
+       <event event="0x8b" title="Scorpion" name="EXCEPTIONS_OVERFLOW" description="Scorpion overflow exceptions"/>\r
+       <event event="0x8c" title="Scorpion" name="EXCEPTIONS_UNDERFLOW" description="Scorpion underflow exceptions"/>\r
+       <event event="0x8d" title="Scorpion" name="EXCEPTIONS_DENORM" description="Scorpion denorm exceptions"/>\r
+       <event event="0x8e" title="ScorpionMP" name="NUM_BARRIERS" description="Barriers"/>\r
+       <event event="0x8f" title="ScorpionMP" name="BARRIER_CYCLES" description="Barrier cycles"/>\r
+  </category>  \r
   
\ No newline at end of file
index cf28bfc703af9e9283dff658cfa78ee730570f3f..51237cbcf758d9699a8a72c16ce086add4c8856e 100644 (file)
@@ -1,5 +1,5 @@
 /**
- * Copyright (C) ARM Limited 2010-2011. All rights reserved.
+ * Copyright (C) ARM Limited 2010-2012. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -101,7 +101,7 @@ void child_exit(int signum) {
 // retval: -1 = failure; 0 = was already mounted; 1 = successfully mounted
 int mountGatorFS() {
        // If already mounted,
-       if (access("/dev/gator/buffer", F_OK) != -1)
+       if (access("/dev/gator/buffer", F_OK) == 0)
                return 0;
 
        // else, mount the filesystem
@@ -176,28 +176,34 @@ struct cmdline_t parseCommandLine(int argc, char** argv) {
        struct cmdline_t cmdline;
        cmdline.port = 8080;
        cmdline.sessionXML = NULL;
-
-       for (int i = 1; i < argc; i++) {
-               // Is the argument a number?
-               if (strtol(argv[i], NULL, 10) > 0) {
-                       cmdline.port = strtol(argv[i], NULL, 10);
-                       continue;
-               }
-
-               if (strcmp(argv[i], "-h") == 0 || strcmp(argv[i], "-?") == 0 || strcmp(argv[i], "--help") == 0) {
-                       logg->logError(__FILE__, __LINE__,
-                               "Streamline gatord version %d. All parameters are optional:\n"
-                               "port_number\tport upon which the server listens; default is 8080\n"
-                               "session_xml\tfilename of a session xml used for local capture\n"
-                               "-v/--version\tversion information\n"
-                               "-h/--help\tthis help page\n", PROTOCOL_VERSION);
-                       handleException();
-               } else if (strcmp(argv[i], "-v") == 0 || strcmp(argv[i], "--version") == 0) {
-                       logg->logError(__FILE__, __LINE__, "Streamline gatord version %d", PROTOCOL_VERSION);
-                       handleException();
-               } else {
-                       // Assume it is an .xml file
-                       cmdline.sessionXML = argv[i];
+       int c;
+
+       while ((c = getopt (argc, argv, "hvp:s:c:")) != -1) {
+               switch(c) {
+                       case 'p':
+                               cmdline.port = strtol(optarg, NULL, 10);
+                               break;
+                       case 's':
+                               cmdline.sessionXML = optarg;
+                               break;
+                       case 'c':
+                               gSessionData->configurationXMLPath = optarg;
+                               break;
+                       case 'h':
+                       case '?':
+                               logg->logError(__FILE__, __LINE__,
+                                       "Streamline gatord version %d. All parameters are optional:\n"
+                                       "-p port_number\tport upon which the server listens; default is 8080\n"
+                                       "-s session_xml\tpath and filename of a session xml used for local capture\n"
+                                       "-c config_xml\tpath and filename of the configuration.xml to use\n"
+                                       "-v\t\tversion information\n"
+                                       "-h\t\tthis help page\n", PROTOCOL_VERSION);
+                               handleException();
+                               break;
+                       case 'v':
+                               logg->logError(__FILE__, __LINE__, "Streamline gatord version %d", PROTOCOL_VERSION);
+                               handleException();
+                               break;
                }
        }
 
@@ -207,11 +213,17 @@ struct cmdline_t parseCommandLine(int argc, char** argv) {
                handleException();
        }
 
+       if (optind < argc) {
+               logg->logError(__FILE__, __LINE__, "Unknown argument: %s. Use '-h' for help.", argv[optind]);
+               handleException();
+       }
+
        return cmdline;
 }
 
 // Gator data flow: collector -> collector fifo -> sender
 int main(int argc, char** argv, char *envp[]) {
+       gSessionData = new SessionData(); // Global data class
        logg = new Logging(DEBUG);  // Set up global thread-safe logging
        util = new OlyUtility();        // Set up global utility class
 
@@ -223,10 +235,11 @@ int main(int argc, char** argv, char *envp[]) {
        signal(SIGABRT, handler);
 
        // Set to high priority
-       setpriority(PRIO_PROCESS, syscall(__NR_gettid), -19);
+       if (setpriority(PRIO_PROCESS, syscall(__NR_gettid), -19) == -1)
+               logg->logMessage("setpriority() failed");
 
        // Initialize session data
-       gSessionData.initialize();
+       gSessionData->initialize();
 
        // Parse the command line parameters
        struct cmdline_t cmdline = parseCommandLine(argc, argv);