jacinto6: sgx: update DDK version to 1.12/2701748
[android-sdk/device-ti-proprietary-open.git] / jacinto6 / sgx_src / eurasia_km / include4 / sgxapi_km.h
1 /*************************************************************************/ /*!
2 @Title          SGX KM API Header
3 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
4 @Description    Exported SGX API details
5 @License        Dual MIT/GPLv2
7 The contents of this file are subject to the MIT license as set out below.
9 Permission is hereby granted, free of charge, to any person obtaining a copy
10 of this software and associated documentation files (the "Software"), to deal
11 in the Software without restriction, including without limitation the rights
12 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 copies of the Software, and to permit persons to whom the Software is
14 furnished to do so, subject to the following conditions:
16 The above copyright notice and this permission notice shall be included in
17 all copies or substantial portions of the Software.
19 Alternatively, the contents of this file may be used under the terms of
20 the GNU General Public License Version 2 ("GPL") in which case the provisions
21 of GPL are applicable instead of those above.
23 If you wish to allow use of your version of this file only under the terms of
24 GPL, and not to allow others to use your version of this file under the terms
25 of the MIT license, indicate your decision by deleting the provisions above
26 and replace them with the notice and other provisions required by GPL as set
27 out in the file called "GPL-COPYING" included in this distribution. If you do
28 not delete the provisions above, a recipient may use your version of this file
29 under the terms of either the MIT license or GPL.
31 This License is also included in this distribution in the file called
32 "MIT-COPYING".
34 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
35 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
36 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
37 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
38 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
39 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
40 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
41 */ /**************************************************************************/
43 #ifndef __SGXAPI_KM_H__
44 #define __SGXAPI_KM_H__
46 #if defined (__cplusplus)
47 extern "C" {
48 #endif
50 #include "sgxdefs.h"
52 #if (defined(__linux__) || defined(__QNXNTO__)) && !defined(USE_CODE)
53         #if defined(__KERNEL__)
54                 #include <asm/unistd.h>
55         #else
56                 #include <unistd.h>
57         #endif
58 #endif
60 /******************************************************************************
61  Some defines...
62 ******************************************************************************/
64 /* SGX Heap IDs, note: not all heaps are available to clients */
65 #define SGX_UNDEFINED_HEAP_ID                                   (~0LU)
66 #define SGX_GENERAL_HEAP_ID                                             0
67 #define SGX_TADATA_HEAP_ID                                              1
68 #define SGX_KERNEL_CODE_HEAP_ID                                 2
69 #define SGX_KERNEL_DATA_HEAP_ID                                 3
70 #define SGX_PIXELSHADER_HEAP_ID                                 4
71 #define SGX_VERTEXSHADER_HEAP_ID                                5
72 #define SGX_PDSPIXEL_CODEDATA_HEAP_ID                   6
73 #define SGX_PDSVERTEX_CODEDATA_HEAP_ID                  7
74 #define SGX_SYNCINFO_HEAP_ID                                    8
75 #define SGX_SHARED_3DPARAMETERS_HEAP_ID                         9
76 #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_ID                     10
77 #if defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP)
78 #define SGX_GENERAL_MAPPING_HEAP_ID                             11
79 #endif
80 #if defined(SGX_FEATURE_2D_HARDWARE)
81 #define SGX_2D_HEAP_ID                                                  12
82 #endif
83 #if defined(SUPPORT_MEMORY_TILING)
84 #define SGX_VPB_TILED_HEAP_ID                   14
85 #endif
87 #define SGX_MAX_HEAP_ID                                                 15
89 /*
90  * Keep SGX_3DPARAMETERS_HEAP_ID as TQ full custom
91  * shaders need it to select which heap to write
92  * their ISP controll stream to.
93  */
94 #if (defined(SUPPORT_PERCONTEXT_PB) || defined(SUPPORT_HYBRID_PB))
95 #define SGX_3DPARAMETERS_HEAP_ID                        SGX_PERCONTEXT_3DPARAMETERS_HEAP_ID     
96 #else
97 #define SGX_3DPARAMETERS_HEAP_ID                        SGX_SHARED_3DPARAMETERS_HEAP_ID
98 #endif
99 /* Define for number of bytes between consecutive code base registers */
100 #if defined(SGX543) || defined(SGX544) || defined(SGX554)
101 #define SGX_USE_CODE_SEGMENT_RANGE_BITS         23
102 #else
103 #define SGX_USE_CODE_SEGMENT_RANGE_BITS         19
104 #endif
106 #define SGX_MAX_TA_STATUS_VALS  32
107 #define SGX_MAX_3D_STATUS_VALS  4
109 #if defined(SUPPORT_SGX_GENERALISED_SYNCOBJECTS)
110 /* sync info structure array size */
111 #define SGX_MAX_TA_DST_SYNCS                    1
112 #define SGX_MAX_TA_SRC_SYNCS                    1
113 #define SGX_MAX_3D_SRC_SYNCS                    4
114 /* note: there is implicitly 1 3D Dst Sync */
115 #else
116 /* sync info structure array size */
117 #define SGX_MAX_SRC_SYNCS_TA                            32
118 #define SGX_MAX_DST_SYNCS_TA                            1
119 /* note: only one dst sync is supported by the 2D paths */
120 #define SGX_MAX_SRC_SYNCS_TQ                            6
121 #define SGX_MAX_DST_SYNCS_TQ                            2
122 #endif
125 #if defined(SGX_FEATURE_EXTENDED_PERF_COUNTERS)
126 #define PVRSRV_SGX_HWPERF_NUM_COUNTERS  8
127 #define PVRSRV_SGX_HWPERF_NUM_MISC_COUNTERS 11
128 #else
129 #define PVRSRV_SGX_HWPERF_NUM_COUNTERS  9
130 #define PVRSRV_SGX_HWPERF_NUM_MISC_COUNTERS 8
131 #endif /* SGX543 */
133 #define PVRSRV_SGX_HWPERF_INVALID                                       0x1
135 #define PVRSRV_SGX_HWPERF_TRANSFER                                      0x2
136 #define PVRSRV_SGX_HWPERF_TA                                            0x3
137 #define PVRSRV_SGX_HWPERF_3D                                            0x4
138 #define PVRSRV_SGX_HWPERF_2D                                            0x5
139 #define PVRSRV_SGX_HWPERF_POWER                                         0x6
140 #define PVRSRV_SGX_HWPERF_PERIODIC                                      0x7
141 #define PVRSRV_SGX_HWPERF_3DSPM                                         0x8
142 #define PVRSRV_SGX_HWPERF_TA_OCL                                        0x9
143 #define PVRSRV_SGX_HWPERF_3D_OCL                                        0xA
144 #define PVRSRV_SGX_HWPERF_3DSPM_OCL                                     0xB
146 #define PVRSRV_SGX_HWPERF_MK_EVENT                                      0x101
147 #define PVRSRV_SGX_HWPERF_MK_TA                                         0x102
148 #define PVRSRV_SGX_HWPERF_MK_3D                                         0x103
149 #define PVRSRV_SGX_HWPERF_MK_2D                                         0x104
150 #define PVRSRV_SGX_HWPERF_MK_TRANSFER_DUMMY                             0x105
151 #define PVRSRV_SGX_HWPERF_MK_TA_DUMMY                                   0x106
152 #define PVRSRV_SGX_HWPERF_MK_3D_DUMMY                                   0x107
153 #define PVRSRV_SGX_HWPERF_MK_2D_DUMMY                                   0x108
154 #define PVRSRV_SGX_HWPERF_MK_TA_LOCKUP                                  0x109
155 #define PVRSRV_SGX_HWPERF_MK_3D_LOCKUP                                  0x10A
156 #define PVRSRV_SGX_HWPERF_MK_2D_LOCKUP                                  0x10B
157 #define PVRSRV_SGX_HWPERF_MK_HK                                         0x10C
159 #define PVRSRV_SGX_HWPERF_TYPE_STARTEND_BIT                     28
160 #define PVRSRV_SGX_HWPERF_TYPE_OP_MASK                          ((1UL << PVRSRV_SGX_HWPERF_TYPE_STARTEND_BIT) - 1)
161 #define PVRSRV_SGX_HWPERF_TYPE_OP_START                         (0UL << PVRSRV_SGX_HWPERF_TYPE_STARTEND_BIT)
162 #define PVRSRV_SGX_HWPERF_TYPE_OP_END                           (1Ul << PVRSRV_SGX_HWPERF_TYPE_STARTEND_BIT)
164 #define PVRSRV_SGX_HWPERF_TYPE_TRANSFER_START           (PVRSRV_SGX_HWPERF_TRANSFER | PVRSRV_SGX_HWPERF_TYPE_OP_START)
165 #define PVRSRV_SGX_HWPERF_TYPE_TRANSFER_END                     (PVRSRV_SGX_HWPERF_TRANSFER | PVRSRV_SGX_HWPERF_TYPE_OP_END)
166 #define PVRSRV_SGX_HWPERF_TYPE_TA_START                         (PVRSRV_SGX_HWPERF_TA | PVRSRV_SGX_HWPERF_TYPE_OP_START)
167 #define PVRSRV_SGX_HWPERF_TYPE_TA_END                           (PVRSRV_SGX_HWPERF_TA | PVRSRV_SGX_HWPERF_TYPE_OP_END)
168 #define PVRSRV_SGX_HWPERF_TYPE_3D_START                         (PVRSRV_SGX_HWPERF_3D | PVRSRV_SGX_HWPERF_TYPE_OP_START)
169 #define PVRSRV_SGX_HWPERF_TYPE_3D_END                           (PVRSRV_SGX_HWPERF_3D | PVRSRV_SGX_HWPERF_TYPE_OP_END)
170 #define PVRSRV_SGX_HWPERF_TYPE_2D_START                         (PVRSRV_SGX_HWPERF_2D | PVRSRV_SGX_HWPERF_TYPE_OP_START)
171 #define PVRSRV_SGX_HWPERF_TYPE_2D_END                           (PVRSRV_SGX_HWPERF_2D | PVRSRV_SGX_HWPERF_TYPE_OP_END)
172 #define PVRSRV_SGX_HWPERF_TYPE_POWER_START                      (PVRSRV_SGX_HWPERF_POWER | PVRSRV_SGX_HWPERF_TYPE_OP_START)
173 #define PVRSRV_SGX_HWPERF_TYPE_POWER_END                        (PVRSRV_SGX_HWPERF_POWER | PVRSRV_SGX_HWPERF_TYPE_OP_END)
174 #define PVRSRV_SGX_HWPERF_TYPE_PERIODIC                         (PVRSRV_SGX_HWPERF_PERIODIC)
175 #define PVRSRV_SGX_HWPERF_TYPE_3DSPM_START                      (PVRSRV_SGX_HWPERF_3DSPM | PVRSRV_SGX_HWPERF_TYPE_OP_START)
176 #define PVRSRV_SGX_HWPERF_TYPE_3DSPM_END                        (PVRSRV_SGX_HWPERF_3DSPM | PVRSRV_SGX_HWPERF_TYPE_OP_END)
177 #define PVRSRV_SGX_HWPERF_TYPE_3DSPM_OCL_START                  (PVRSRV_SGX_HWPERF_3DSPM_OCL | PVRSRV_SGX_HWPERF_TYPE_OP_START)
178 #define PVRSRV_SGX_HWPERF_TYPE_3DSPM_OCL_END                    (PVRSRV_SGX_HWPERF_3DSPM_OCL | PVRSRV_SGX_HWPERF_TYPE_OP_END)
179 #define PVRSRV_SGX_HWPERF_TYPE_TA_OCL_START                     (PVRSRV_SGX_HWPERF_TA_OCL | PVRSRV_SGX_HWPERF_TYPE_OP_START)
180 #define PVRSRV_SGX_HWPERF_TYPE_TA_OCL_END                       (PVRSRV_SGX_HWPERF_TA_OCL | PVRSRV_SGX_HWPERF_TYPE_OP_END)
181 #define PVRSRV_SGX_HWPERF_TYPE_3D_OCL_START                     (PVRSRV_SGX_HWPERF_3D_OCL | PVRSRV_SGX_HWPERF_TYPE_OP_START)
182 #define PVRSRV_SGX_HWPERF_TYPE_3D_OCL_END                       (PVRSRV_SGX_HWPERF_3D_OCL | PVRSRV_SGX_HWPERF_TYPE_OP_END)
183 #define PVRSRV_SGX_HWPERF_TYPE_MK_TRANSFER_DUMMY_START          (PVRSRV_SGX_HWPERF_MK_TRANSFER_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_START)
184 #define PVRSRV_SGX_HWPERF_TYPE_MK_TRANSFER_DUMMY_END            (PVRSRV_SGX_HWPERF_MK_TRANSFER_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_END)
185 #define PVRSRV_SGX_HWPERF_TYPE_MK_TA_DUMMY_START                (PVRSRV_SGX_HWPERF_MK_TA_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_START)
186 #define PVRSRV_SGX_HWPERF_TYPE_MK_TA_DUMMY_END                  (PVRSRV_SGX_HWPERF_MK_TA_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_END)
187 #define PVRSRV_SGX_HWPERF_TYPE_MK_3D_DUMMY_START                (PVRSRV_SGX_HWPERF_MK_3D_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_START)
188 #define PVRSRV_SGX_HWPERF_TYPE_MK_3D_DUMMY_END                  (PVRSRV_SGX_HWPERF_MK_3D_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_END)
189 #define PVRSRV_SGX_HWPERF_TYPE_MK_2D_DUMMY_START                (PVRSRV_SGX_HWPERF_MK_2D_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_START)
190 #define PVRSRV_SGX_HWPERF_TYPE_MK_2D_DUMMY_END                  (PVRSRV_SGX_HWPERF_MK_2D_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_END)
191 #define PVRSRV_SGX_HWPERF_TYPE_MK_TA_LOCKUP                     (PVRSRV_SGX_HWPERF_MK_TA_LOCKUP)
192 #define PVRSRV_SGX_HWPERF_TYPE_MK_3D_LOCKUP                     (PVRSRV_SGX_HWPERF_MK_3D_LOCKUP)
193 #define PVRSRV_SGX_HWPERF_TYPE_MK_2D_LOCKUP                     (PVRSRV_SGX_HWPERF_MK_2D_LOCKUP)
195 #define PVRSRV_SGX_HWPERF_TYPE_MK_EVENT_START           (PVRSRV_SGX_HWPERF_MK_EVENT | PVRSRV_SGX_HWPERF_TYPE_OP_START)
196 #define PVRSRV_SGX_HWPERF_TYPE_MK_EVENT_END                     (PVRSRV_SGX_HWPERF_MK_EVENT | PVRSRV_SGX_HWPERF_TYPE_OP_END)
197 #define PVRSRV_SGX_HWPERF_TYPE_MK_TA_START                      (PVRSRV_SGX_HWPERF_MK_TA | PVRSRV_SGX_HWPERF_TYPE_OP_START)
198 #define PVRSRV_SGX_HWPERF_TYPE_MK_TA_END                        (PVRSRV_SGX_HWPERF_MK_TA | PVRSRV_SGX_HWPERF_TYPE_OP_END)
199 #define PVRSRV_SGX_HWPERF_TYPE_MK_3D_START                      (PVRSRV_SGX_HWPERF_MK_3D | PVRSRV_SGX_HWPERF_TYPE_OP_START)
200 #define PVRSRV_SGX_HWPERF_TYPE_MK_3D_END                        (PVRSRV_SGX_HWPERF_MK_3D | PVRSRV_SGX_HWPERF_TYPE_OP_END)
201 #define PVRSRV_SGX_HWPERF_TYPE_MK_2D_START                      (PVRSRV_SGX_HWPERF_MK_2D | PVRSRV_SGX_HWPERF_TYPE_OP_START)
202 #define PVRSRV_SGX_HWPERF_TYPE_MK_2D_END                        (PVRSRV_SGX_HWPERF_MK_2D | PVRSRV_SGX_HWPERF_TYPE_OP_END)
203 #define PVRSRV_SGX_HWPERF_TYPE_MK_HK_START                      (PVRSRV_SGX_HWPERF_MK_HK | PVRSRV_SGX_HWPERF_TYPE_OP_START)
204 #define PVRSRV_SGX_HWPERF_TYPE_MK_HK_END                        (PVRSRV_SGX_HWPERF_MK_HK | PVRSRV_SGX_HWPERF_TYPE_OP_END)
207 #define PVRSRV_SGX_HWPERF_STATUS_OFF                            (0x0)
208 #define PVRSRV_SGX_HWPERF_STATUS_RESET_COUNTERS         (1UL << 0)
209 #define PVRSRV_SGX_HWPERF_STATUS_GRAPHICS_ON            (1UL << 1)
210 #define PVRSRV_SGX_HWPERF_STATUS_PERIODIC_ON            (1UL << 2)
211 #define PVRSRV_SGX_HWPERF_STATUS_MK_EXECUTION_ON        (1UL << 3)
214 /*!
215  *****************************************************************************
216  * One entry in the HWPerf Circular Buffer. 
217  *****************************************************************************/
218 typedef struct _PVRSRV_SGX_HWPERF_CB_ENTRY_
220         IMG_UINT32      ui32FrameNo;
221         IMG_UINT32      ui32PID;
222         IMG_UINT32      ui32RTData;
223         IMG_UINT32      ui32Type;
224         IMG_UINT32      ui32Ordinal;
225         IMG_UINT32      ui32Info;
226         IMG_UINT32      ui32Clocksx16;
227         /* NOTE: There should always be at least as many 3D cores as TA cores. */       
228         IMG_UINT32      ui32Counters[SGX_FEATURE_MP_CORE_COUNT_3D][PVRSRV_SGX_HWPERF_NUM_COUNTERS];
229         IMG_UINT32      ui32MiscCounters[SGX_FEATURE_MP_CORE_COUNT_3D][PVRSRV_SGX_HWPERF_NUM_MISC_COUNTERS];
230 } PVRSRV_SGX_HWPERF_CB_ENTRY;
233 /*
234         Status values control structure
235 */
236 typedef struct _CTL_STATUS_
238         IMG_DEV_VIRTADDR        sStatusDevAddr;
239         IMG_UINT32                      ui32StatusValue;
240 } CTL_STATUS;
243 /*!
244         List of possible requests/commands to SGXGetMiscInfo()
245 */
246 typedef enum _SGX_MISC_INFO_REQUEST_
248         SGX_MISC_INFO_REQUEST_CLOCKSPEED = 0,
249         SGX_MISC_INFO_REQUEST_CLOCKSPEED_SLCSIZE,
250         SGX_MISC_INFO_REQUEST_SGXREV,
251         SGX_MISC_INFO_REQUEST_DRIVER_SGXREV,
252 #if defined(SUPPORT_SGX_EDM_MEMORY_DEBUG)
253         SGX_MISC_INFO_REQUEST_MEMREAD,
254         SGX_MISC_INFO_REQUEST_MEMCOPY,
255 #endif /* SUPPORT_SGX_EDM_MEMORY_DEBUG */
256         SGX_MISC_INFO_REQUEST_SET_HWPERF_STATUS,
257 #if defined(SGX_FEATURE_DATA_BREAKPOINTS)
258         SGX_MISC_INFO_REQUEST_SET_BREAKPOINT,
259         SGX_MISC_INFO_REQUEST_POLL_BREAKPOINT,
260         SGX_MISC_INFO_REQUEST_RESUME_BREAKPOINT,
261 #endif /* SGX_FEATURE_DATA_BREAKPOINTS */
262         SGX_MISC_INFO_DUMP_DEBUG_INFO,
263         SGX_MISC_INFO_DUMP_DEBUG_INFO_FORCE_REGS,
264         SGX_MISC_INFO_PANIC,
265         SGX_MISC_INFO_REQUEST_SPM,
266         SGX_MISC_INFO_REQUEST_ACTIVEPOWER,
267         SGX_MISC_INFO_REQUEST_LOCKUPS,
268 #if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
269         SGX_MISC_INFO_REQUEST_EDM_STATUS_BUFFER_INFO,
270 #endif
271         SGX_MISC_INFO_REQUEST_FORCE_I16                                 =  0x7fff
272 } SGX_MISC_INFO_REQUEST;
275 /******************************************************************************
276  * Struct for passing SGX core rev/features from ukernel to driver.
277  * This is accessed from the kernel part of the driver and microkernel; it is
278  * only accessed in user space during buffer allocation in srvinit.
279  ******************************************************************************/
280 typedef struct _PVRSRV_SGX_MISCINFO_FEATURES
282         IMG_UINT32                      ui32CoreRev;    /*!< SGX Core revision from HW register */
283         IMG_UINT32                      ui32CoreID;             /*!< SGX Core ID from HW register */
284         IMG_UINT32                      ui32DDKVersion; /*!< software DDK version */
285         IMG_UINT32                      ui32DDKBuild;   /*!< software DDK build no. */
286         IMG_UINT32                      ui32CoreIdSW;   /*!< software core version (ID), e.g. SGX535, SGX540 */
287         IMG_UINT32                      ui32CoreRevSW;  /*!< software core revision */
288         IMG_UINT32                      ui32BuildOptions;       /*!< build options bit-field */
289 #if defined(SUPPORT_SGX_EDM_MEMORY_DEBUG)
290         IMG_UINT32                      ui32DeviceMemValue;             /*!< device mem value read from ukernel */
291 #endif
292 } PVRSRV_SGX_MISCINFO_FEATURES;
294 typedef struct _PVRSRV_SGX_MISCINFO_QUERY_CLOCKSPEED_SLCSIZE
296         IMG_UINT32                      ui32SGXClockSpeed;
297         IMG_UINT32                      ui32SGXSLCSize;
298 } PVRSRV_SGX_MISCINFO_QUERY_CLOCKSPEED_SLCSIZE;
300 #if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
301 /******************************************************************************
302  * Struct for getting access to the EDM Status Buffer
303  ******************************************************************************/
304 typedef struct _PVRSRV_SGX_MISCINFO_EDM_STATUS_BUFFER_INFO
306         IMG_DEV_VIRTADDR        sDevVAEDMStatusBuffer;  /*!< DevVAddr of the EDM status buffer */
307         IMG_PVOID                       pvEDMStatusBuffer;              /*!< CPUVAddr of the EDM status buffer */
308 } PVRSRV_SGX_MISCINFO_EDM_STATUS_BUFFER_INFO;
309 #endif
312 /******************************************************************************
313  * Struct for getting lock-up stats from the kernel driver
314  ******************************************************************************/
315 typedef struct _PVRSRV_SGX_MISCINFO_LOCKUPS
317         IMG_UINT32                      ui32HostDetectedLockups; /*!< Host timer detected lockups */
318         IMG_UINT32                      ui32uKernelDetectedLockups; /*!< Microkernel detected lockups */
319 } PVRSRV_SGX_MISCINFO_LOCKUPS;
322 /******************************************************************************
323  * Struct for getting lock-up stats from the kernel driver
324  ******************************************************************************/
325 typedef struct _PVRSRV_SGX_MISCINFO_ACTIVEPOWER
327         IMG_UINT32                      ui32NumActivePowerEvents; /*!< active power events */
328 } PVRSRV_SGX_MISCINFO_ACTIVEPOWER;
331 /******************************************************************************
332  * Struct for getting SPM stats fro the kernel driver
333  ******************************************************************************/
334 typedef struct _PVRSRV_SGX_MISCINFO_SPM
336         IMG_HANDLE                      hRTDataSet;                             /*!< render target data set handle returned from SGXAddRenderTarget */
337         IMG_UINT32                      ui32NumOutOfMemSignals; /*!< Number of Out of Mem Signals */
338         IMG_UINT32                      ui32NumSPMRenders;      /*!< Number of SPM renders */
339 } PVRSRV_SGX_MISCINFO_SPM;
342 #if defined(SGX_FEATURE_DATA_BREAKPOINTS)
343 /*!
344  ******************************************************************************
345  * Structure for SGX break points control
346  *****************************************************************************/
347 typedef struct _SGX_BREAKPOINT_INFO
349         /* set/clear BP boolean */
350         IMG_BOOL                                        bBPEnable;
351         /* Index of BP to set */
352         IMG_UINT32                                      ui32BPIndex;
353         /* On which DataMaster(s) should the breakpoint fire? */
354         IMG_UINT32                  ui32DataMasterMask;
355         /* DevVAddr of BP to set */
356         IMG_DEV_VIRTADDR                        sBPDevVAddr, sBPDevVAddrEnd;
357         /* Whether or not the desired breakpoint will be trapped */
358         IMG_BOOL                    bTrapped;
359         /* Will the requested breakpoint fire for reads? */
360         IMG_BOOL                    bRead;
361         /* Will the requested breakpoint fire for writes? */
362         IMG_BOOL                    bWrite;
363         /* Has a breakpoint been trapped? */
364         IMG_BOOL                    bTrappedBP;
365         /* Extra information recorded about a trapped breakpoint */
366         IMG_UINT32                  ui32CoreNum;
367         IMG_DEV_VIRTADDR            sTrappedBPDevVAddr;
368         IMG_UINT32                  ui32TrappedBPBurstLength;
369         IMG_BOOL                    bTrappedBPRead;
370         IMG_UINT32                  ui32TrappedBPDataMaster;
371         IMG_UINT32                  ui32TrappedBPTag;
372 } SGX_BREAKPOINT_INFO;
373 #endif /* SGX_FEATURE_DATA_BREAKPOINTS */
376 /*!
377  ******************************************************************************
378  * Structure for setting the hardware performance status
379  *****************************************************************************/
380 typedef struct _PVRSRV_SGX_MISCINFO_SET_HWPERF_STATUS
382         /* See PVRSRV_SGX_HWPERF_STATUS_* */
383         IMG_UINT32      ui32NewHWPerfStatus;
384         
385         #if defined(SGX_FEATURE_EXTENDED_PERF_COUNTERS)
386         /* Specifies the HW's active group selectors */
387         IMG_UINT32      aui32PerfGroup[PVRSRV_SGX_HWPERF_NUM_COUNTERS];
388         /* Specifies the HW's active bit selectors */
389         IMG_UINT32      aui32PerfBit[PVRSRV_SGX_HWPERF_NUM_COUNTERS];
390         /* Specifies the HW's counter bit selectors */
391         IMG_UINT32      ui32PerfCounterBitSelect;
392         /* Specifies the HW's sum_mux selectors */
393         IMG_UINT32      ui32PerfSumMux;
394         #else
395         /* Specifies the HW's active group */
396         IMG_UINT32      ui32PerfGroup;
397         #endif /* SGX_FEATURE_EXTENDED_PERF_COUNTERS */
398 } PVRSRV_SGX_MISCINFO_SET_HWPERF_STATUS;
401 /*!
402  ******************************************************************************
403  * Structure for misc SGX commands in services
404  *****************************************************************************/
405 typedef struct _SGX_MISC_INFO_
407         SGX_MISC_INFO_REQUEST   eRequest;       /*!< Command request to SGXGetMiscInfo() */
408         IMG_UINT32                              ui32Padding;
409 #if defined(SUPPORT_SGX_EDM_MEMORY_DEBUG)
410         IMG_DEV_VIRTADDR                        sDevVAddrSrc;           /*!< dev virtual addr for mem read */
411         IMG_DEV_VIRTADDR                        sDevVAddrDest;          /*!< dev virtual addr for mem write */
412         IMG_HANDLE                                      hDevMemContext;         /*!< device memory context for mem debug */
413 #endif
414         union
415         {
416                 IMG_UINT32      reserved;       /*!< Unused: ensures valid code in the case everything else is compiled out */
417                 PVRSRV_SGX_MISCINFO_FEATURES                                            sSGXFeatures;
418                 IMG_UINT32                                                                                      ui32SGXClockSpeed;
419                 PVRSRV_SGX_MISCINFO_QUERY_CLOCKSPEED_SLCSIZE                            sQueryClockSpeedSLCSize;
420                 PVRSRV_SGX_MISCINFO_ACTIVEPOWER                                         sActivePower;
421                 PVRSRV_SGX_MISCINFO_LOCKUPS                                                     sLockups;
422                 PVRSRV_SGX_MISCINFO_SPM                                                         sSPM;
423 #if defined(SGX_FEATURE_DATA_BREAKPOINTS)
424                 SGX_BREAKPOINT_INFO                                                                     sSGXBreakpointInfo;
425 #endif
426                 PVRSRV_SGX_MISCINFO_SET_HWPERF_STATUS                           sSetHWPerfStatus;
428 #if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
429                 PVRSRV_SGX_MISCINFO_EDM_STATUS_BUFFER_INFO                      sEDMStatusBufferInfo;
430 #endif
431         } uData;
432 } SGX_MISC_INFO;
434 #if defined(SGX_FEATURE_2D_HARDWARE)
435 /*
436  * The largest number of source sync objects that can be associated with a blit
437  * command.  Allows for src, pattern, and mask
438  */
439 #define PVRSRV_MAX_BLT_SRC_SYNCS                3
440 #endif
443 #define SGX_KICKTA_DUMPBITMAP_MAX_NAME_LENGTH           256
445 /*
446         Structure for dumping bitmaps
447 */
448 typedef struct _SGX_KICKTA_DUMPBITMAP_
450         IMG_DEV_VIRTADDR        sDevBaseAddr;
451         IMG_UINT32                      ui32Flags;
452         IMG_UINT32                      ui32Width;
453         IMG_UINT32                      ui32Height;
454         IMG_UINT32                      ui32Stride;
455         IMG_UINT32                      ui32PDUMPFormat;
456         IMG_UINT32                      ui32BytesPP;
457         IMG_CHAR                        pszName[SGX_KICKTA_DUMPBITMAP_MAX_NAME_LENGTH];
458 } SGX_KICKTA_DUMPBITMAP, *PSGX_KICKTA_DUMPBITMAP;
460 #define PVRSRV_SGX_PDUMP_CONTEXT_MAX_BITMAP_ARRAY_SIZE  (16)
462 /*!
463  ******************************************************************************
464  * Data required only when dumping parameters
465  *****************************************************************************/
466 typedef struct _PVRSRV_SGX_PDUMP_CONTEXT_
468         /* cache control word for micro kernel cache flush/invalidates */
469         IMG_UINT32                                              ui32CacheControl;
471 } PVRSRV_SGX_PDUMP_CONTEXT;
474 typedef struct _SGX_KICKTA_DUMP_ROFF_
476         IMG_HANDLE                      hKernelMemInfo;                                         /*< Buffer handle */
477         IMG_UINT32                      uiAllocIndex;                                           /*< Alloc index for LDDM */
478         IMG_UINT32                      ui32Offset;                                                     /*< Byte offset to value to dump */
479         IMG_UINT32                      ui32Value;                                                      /*< Actual value to dump */
480         IMG_PCHAR                       pszName;                                                        /*< Name of buffer */
481 } SGX_KICKTA_DUMP_ROFF, *PSGX_KICKTA_DUMP_ROFF;
483 typedef struct _SGX_KICKTA_DUMP_BUFFER_
485         IMG_UINT32                      ui32SpaceUsed;
486         IMG_UINT32                      ui32Start;                                                      /*< Byte offset of start to dump */
487         IMG_UINT32                      ui32End;                                                        /*< Byte offset of end of dump (non-inclusive) */
488         IMG_UINT32                      ui32BufferSize;                                         /*< Size of buffer */
489         IMG_UINT32                      ui32BackEndLength;                                      /*< Size of back end portion, if End < Start */
490         IMG_UINT32                      uiAllocIndex;
491         IMG_HANDLE                      hKernelMemInfo;                                         /*< MemInfo handle for the circular buffer */
492         IMG_PVOID                       pvLinAddr;
493 #if defined(SUPPORT_SGX_NEW_STATUS_VALS)
494         IMG_HANDLE                      hCtrlKernelMemInfo;                                     /*< MemInfo handle for the control structure of the
495                                                                                                                                 circular buffer */
496         IMG_DEV_VIRTADDR        sCtrlDevVAddr;                                          /*< Device virtual address of the memory in the 
497                                                                                                                                 control structure to be checked */
498 #endif
499         IMG_PCHAR                       pszName;                                                        /*< Name of buffer */
501 #if defined (__QNXNTO__)
502         IMG_UINT32          ui32NameLength;                     /*< Number of characters in buffer name */
503 #endif
504 } SGX_KICKTA_DUMP_BUFFER, *PSGX_KICKTA_DUMP_BUFFER;
506 #ifdef PDUMP
507 /*
508         PDUMP version of above kick structure
509 */
510 typedef struct _SGX_KICKTA_PDUMP_
512         // Bitmaps to dump
513         PSGX_KICKTA_DUMPBITMAP          psPDumpBitmapArray;
514         IMG_UINT32                                              ui32PDumpBitmapSize;
516         // Misc buffers to dump (e.g. TA, PDS etc..)
517         PSGX_KICKTA_DUMP_BUFFER psBufferArray;
518         IMG_UINT32                                              ui32BufferArraySize;
520         // Roffs to dump
521         PSGX_KICKTA_DUMP_ROFF           psROffArray;
522         IMG_UINT32                                              ui32ROffArraySize;
523 } SGX_KICKTA_PDUMP, *PSGX_KICKTA_PDUMP;
524 #endif  /* PDUMP */
526 #if defined(TRANSFER_QUEUE)
527 #if defined(SGX_FEATURE_2D_HARDWARE)
528 /* Maximum size of ctrl stream for 2d blit command (in 32 bit words) */
529 #define SGX_MAX_2D_BLIT_CMD_SIZE                26
530 #define SGX_MAX_2D_SRC_SYNC_OPS                 3
531 #endif
532 #define SGX_MAX_TRANSFER_STATUS_VALS    2
533 #define SGX_MAX_TRANSFER_SYNC_OPS       5
534 #endif
536 #if defined (__cplusplus)
538 #endif
540 #endif /* __SGXAPI_KM_H__ */
542 /******************************************************************************
543  End of file (sgxapi_km.h)
544 ******************************************************************************/