[android-sdk/device-ti-proprietary-open.git] / jacinto6 / sgx_src / eurasia_km / services4 / srvkm / devices / sgx / sgxreset.c
1 /*************************************************************************/ /*!
2 @Title Device specific reset routines
3 @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
4 @License Dual MIT/GPLv2
6 The contents of this file are subject to the MIT license as set out below.
8 Permission is hereby granted, free of charge, to any person obtaining a copy
9 of this software and associated documentation files (the "Software"), to deal
10 in the Software without restriction, including without limitation the rights
11 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 copies of the Software, and to permit persons to whom the Software is
13 furnished to do so, subject to the following conditions:
15 The above copyright notice and this permission notice shall be included in
16 all copies or substantial portions of the Software.
18 Alternatively, the contents of this file may be used under the terms of
19 the GNU General Public License Version 2 ("GPL") in which case the provisions
20 of GPL are applicable instead of those above.
22 If you wish to allow use of your version of this file only under the terms of
23 GPL, and not to allow others to use your version of this file under the terms
24 of the MIT license, indicate your decision by deleting the provisions above
25 and replace them with the notice and other provisions required by GPL as set
26 out in the file called "GPL-COPYING" included in this distribution. If you do
27 not delete the provisions above, a recipient may use your version of this file
28 under the terms of either the MIT license or GPL.
30 This License is also included in this distribution in the file called
31 "MIT-COPYING".
33 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
34 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
35 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
36 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
37 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
38 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
39 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
40 */ /**************************************************************************/
42 #include "sgxdefs.h"
43 #include "sgxmmu.h"
44 #include "services_headers.h"
45 #include "sgxinfokm.h"
46 #include "sgxconfig.h"
47 #include "sgxutils.h"
49 #include "pdump_km.h"
52 /*!
53 *******************************************************************************
55 @Function SGXInitClocks
57 @Description
58 Initialise the SGX clocks
60 @Input psDevInfo - device info. structure
61 @Input ui32PDUMPFlags - flags to control PDUMP output
63 @Return IMG_VOID
65 ******************************************************************************/
66 IMG_VOID SGXInitClocks(PVRSRV_SGXDEV_INFO *psDevInfo,
67 IMG_UINT32 ui32PDUMPFlags)
68 {
69 IMG_UINT32 ui32RegVal;
71 #if !defined(PDUMP)
72 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
73 #endif /* PDUMP */
75 ui32RegVal = psDevInfo->ui32ClkGateCtl;
76 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_CLKGATECTL, ui32RegVal);
77 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_CLKGATECTL, ui32RegVal, ui32PDUMPFlags);
79 #if defined(EUR_CR_CLKGATECTL2)
80 ui32RegVal = psDevInfo->ui32ClkGateCtl2;
81 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_CLKGATECTL2, ui32RegVal);
82 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_CLKGATECTL2, ui32RegVal, ui32PDUMPFlags);
83 #endif
84 }
87 /*!
88 *******************************************************************************
90 @Function SGXResetInitBIFContexts
92 @Description
93 Initialise the BIF memory contexts
95 @Input psDevInfo - SGX Device Info
97 @Return IMG_VOID
99 ******************************************************************************/
100 static IMG_VOID SGXResetInitBIFContexts(PVRSRV_SGXDEV_INFO *psDevInfo,
101 IMG_UINT32 ui32PDUMPFlags)
102 {
103 IMG_UINT32 ui32RegVal;
105 #if !defined(PDUMP)
106 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
107 #endif /* PDUMP */
109 ui32RegVal = 0;
110 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
111 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
113 #if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
114 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the BIF bank settings\r\n");
115 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK_SET, ui32RegVal);
116 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK_SET, ui32RegVal, ui32PDUMPFlags);
117 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
118 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
119 #endif /* SGX_FEATURE_MULTIPLE_MEM_CONTEXTS */
121 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the BIF directory list\r\n");
122 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
123 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal, ui32PDUMPFlags);
125 #if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
126 {
127 IMG_UINT32 ui32DirList, ui32DirListReg;
129 for (ui32DirList = 1;
130 ui32DirList < SGX_FEATURE_BIF_NUM_DIRLISTS;
131 ui32DirList++)
132 {
133 ui32DirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (ui32DirList - 1);
134 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32DirListReg, ui32RegVal);
135 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, ui32DirListReg, ui32RegVal, ui32PDUMPFlags);
136 }
137 }
138 #endif /* SGX_FEATURE_MULTIPLE_MEM_CONTEXTS */
139 }
142 /*!
143 *******************************************************************************
145 @Function SGXResetSetupBIFContexts
147 @Description
148 Configure the BIF for the EDM context
150 @Input psDevInfo - SGX Device Info
152 @Return IMG_VOID
154 ******************************************************************************/
155 static IMG_VOID SGXResetSetupBIFContexts(PVRSRV_SGXDEV_INFO *psDevInfo,
156 IMG_UINT32 ui32PDUMPFlags)
157 {
158 IMG_UINT32 ui32RegVal;
160 #if !defined(PDUMP)
161 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
162 #endif /* PDUMP */
164 #if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
165 /* Set up EDM for bank 0 to point at kernel context */
166 ui32RegVal = (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT);
168 #if defined(SGX_FEATURE_2D_HARDWARE) && !defined(SGX_FEATURE_PTLA)
169 /* Set up 2D core for bank 0 to point at kernel context */
170 ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_2D_SHIFT);
171 #endif /* SGX_FEATURE_2D_HARDWARE */
173 #if defined(FIX_HW_BRN_23410)
174 /* Set up TA core for bank 0 to point at kernel context to guarantee it is a valid context */
175 ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_TA_SHIFT);
176 #endif /* FIX_HW_BRN_23410 */
178 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
179 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Set up EDM requestor page table in BIF\r\n");
180 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
181 #endif /* defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS) */
183 {
184 IMG_UINT32 ui32EDMDirListReg;
186 /* Set up EDM context with kernel page directory */
187 #if (SGX_BIF_DIR_LIST_INDEX_EDM == 0)
188 ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE0;
189 #else
190 /* Bases 0 and 1 are not necessarily contiguous */
191 ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (SGX_BIF_DIR_LIST_INDEX_EDM - 1);
192 #endif /* SGX_BIF_DIR_LIST_INDEX_EDM */
194 ui32RegVal = (IMG_UINT32)(psDevInfo->sKernelPDDevPAddr.uiAddr >> SGX_MMU_PDE_ADDR_ALIGNSHIFT);
196 #if defined(FIX_HW_BRN_28011)
197 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
198 PDUMPPDREGWITHFLAGS(&psDevInfo->sMMUAttrib, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
199 #endif
201 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32EDMDirListReg, ui32RegVal);
202 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the EDM's directory list base\r\n");
203 PDUMPPDREGWITHFLAGS(&psDevInfo->sMMUAttrib, ui32EDMDirListReg, ui32RegVal, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
204 }
205 }
208 /*!
209 *******************************************************************************
211 @Function SGXResetSleep
213 @Description
215 Sleep for a short time to allow reset register writes to complete.
216 Required because no status registers are available to poll on.
218 @Input psDevInfo - SGX Device Info
219 @Input ui32PDUMPFlags - flags to control PDUMP output
220 @Input bPDump - Pdump the sleep
222 @Return Nothing
224 ******************************************************************************/
225 static IMG_VOID SGXResetSleep(PVRSRV_SGXDEV_INFO *psDevInfo,
226 IMG_UINT32 ui32PDUMPFlags,
227 IMG_BOOL bPDump)
228 {
229 #if defined(PDUMP) || defined(EMULATOR)
230 IMG_UINT32 ui32ReadRegister;
232 #if defined(SGX_FEATURE_MP)
233 ui32ReadRegister = EUR_CR_MASTER_SOFT_RESET;
234 #else
235 ui32ReadRegister = EUR_CR_SOFT_RESET;
236 #endif /* SGX_FEATURE_MP */
237 #endif
239 #if !defined(PDUMP)
240 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
241 #endif /* PDUMP */
243 /* Sleep for 100 SGX clocks */
244 SGXWaitClocks(psDevInfo, 100);
245 if (bPDump)
246 {
247 PDUMPIDLWITHFLAGS(30, ui32PDUMPFlags);
248 #if defined(PDUMP)
249 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Read back to flush the register writes\r\n");
250 PDumpRegRead(SGX_PDUMPREG_NAME, ui32ReadRegister, ui32PDUMPFlags);
251 #endif
252 }
254 #if defined(EMULATOR)
255 /*
256 Read a register to make sure we wait long enough on the emulator...
257 */
258 OSReadHWReg(psDevInfo->pvRegsBaseKM, ui32ReadRegister);
259 #endif
260 }
263 #if !defined(SGX_FEATURE_MP)
264 /*!
265 *******************************************************************************
267 @Function SGXResetSoftReset
269 @Description
271 Write to the SGX soft reset register.
273 @Input psDevInfo - SGX Device Info
274 @Input bResetBIF - Include the BIF in the soft reset
275 @Input ui32PDUMPFlags - flags to control PDUMP output
276 @Input bPDump - Pdump the sleep
278 @Return Nothing
280 ******************************************************************************/
281 static IMG_VOID SGXResetSoftReset(PVRSRV_SGXDEV_INFO *psDevInfo,
282 IMG_BOOL bResetBIF,
283 IMG_UINT32 ui32PDUMPFlags,
284 IMG_BOOL bPDump)
285 {
286 IMG_UINT32 ui32SoftResetRegVal;
288 ui32SoftResetRegVal =
289 /* add common reset bits: */
290 EUR_CR_SOFT_RESET_DPM_RESET_MASK |
291 EUR_CR_SOFT_RESET_TA_RESET_MASK |
292 EUR_CR_SOFT_RESET_USE_RESET_MASK |
293 EUR_CR_SOFT_RESET_ISP_RESET_MASK |
294 EUR_CR_SOFT_RESET_TSP_RESET_MASK;
296 /* add conditional reset bits: */
297 #ifdef EUR_CR_SOFT_RESET_TWOD_RESET_MASK
298 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_TWOD_RESET_MASK;
299 #endif
300 #if defined(EUR_CR_SOFT_RESET_TE_RESET_MASK)
301 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_TE_RESET_MASK;
302 #endif
303 #if defined(EUR_CR_SOFT_RESET_MTE_RESET_MASK)
304 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_MTE_RESET_MASK;
305 #endif
306 #if defined(EUR_CR_SOFT_RESET_ISP2_RESET_MASK)
307 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_ISP2_RESET_MASK;
308 #endif
309 #if defined(EUR_CR_SOFT_RESET_PDS_RESET_MASK)
310 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_PDS_RESET_MASK;
311 #endif
312 #if defined(EUR_CR_SOFT_RESET_PBE_RESET_MASK)
313 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_PBE_RESET_MASK;
314 #endif
315 #if defined(EUR_CR_SOFT_RESET_CACHEL2_RESET_MASK)
316 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_CACHEL2_RESET_MASK;
317 #endif
318 #if defined(EUR_CR_SOFT_RESET_TCU_L2_RESET_MASK)
319 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_TCU_L2_RESET_MASK;
320 #endif
321 #if defined(EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK)
322 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK;
323 #endif
324 #if defined(EUR_CR_SOFT_RESET_MADD_RESET_MASK)
325 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_MADD_RESET_MASK;
326 #endif
327 #if defined(EUR_CR_SOFT_RESET_ITR_RESET_MASK)
328 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_ITR_RESET_MASK;
329 #endif
330 #if defined(EUR_CR_SOFT_RESET_TEX_RESET_MASK)
331 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_TEX_RESET_MASK;
332 #endif
333 #if defined(EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK)
334 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK;
335 #endif
336 #if defined(EUR_CR_SOFT_RESET_VDM_RESET_MASK)
337 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_VDM_RESET_MASK;
338 #endif
339 #if defined(EUR_CR_SOFT_RESET_DCU_L2_RESET_MASK)
340 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_DCU_L2_RESET_MASK;
341 #endif
342 #if defined(EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK)
343 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK;
344 #endif
346 #if !defined(PDUMP)
347 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
348 #endif /* PDUMP */
350 if (bResetBIF)
351 {
352 ui32SoftResetRegVal |= EUR_CR_SOFT_RESET_BIF_RESET_MASK;
353 }
355 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_SOFT_RESET, ui32SoftResetRegVal);
356 if (bPDump)
357 {
358 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_SOFT_RESET, ui32SoftResetRegVal, ui32PDUMPFlags);
359 }
360 }
363 /*!
364 *******************************************************************************
366 @Function SGXResetInvalDC
368 @Description
370 Invalidate the BIF Directory Cache and wait for the operation to complete.
372 @Input psDevInfo - SGX Device Info
373 @Input ui32PDUMPFlags - flags to control PDUMP output
375 @Return Nothing
377 ******************************************************************************/
378 static IMG_VOID SGXResetInvalDC(PVRSRV_SGXDEV_INFO *psDevInfo,
379 IMG_UINT32 ui32PDUMPFlags,
380 IMG_BOOL bPDump)
381 {
382 IMG_UINT32 ui32RegVal;
384 /* Invalidate BIF Directory cache. */
385 #if defined(EUR_CR_BIF_CTRL_INVAL)
386 ui32RegVal = EUR_CR_BIF_CTRL_INVAL_ALL_MASK;
387 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL_INVAL, ui32RegVal);
388 if (bPDump)
389 {
390 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL_INVAL, ui32RegVal, ui32PDUMPFlags);
391 }
392 #else
393 ui32RegVal = EUR_CR_BIF_CTRL_INVALDC_MASK;
394 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
395 if (bPDump)
396 {
397 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
398 }
400 ui32RegVal = 0;
401 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
402 if (bPDump)
403 {
404 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
405 }
406 #endif
407 SGXResetSleep(psDevInfo, ui32PDUMPFlags, bPDump);
409 #if !defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
410 {
411 /*
412 Wait for the DC invalidate to complete - indicated by
413 outstanding reads reaching zero.
414 */
415 if (PollForValueKM((IMG_UINT32 *)((IMG_UINT8*)psDevInfo->pvRegsBaseKM + EUR_CR_BIF_MEM_REQ_STAT),
416 0,
417 EUR_CR_BIF_MEM_REQ_STAT_READS_MASK,
418 MAX_HW_TIME_US,
419 MAX_HW_TIME_US/WAIT_TRY_COUNT,
420 IMG_FALSE) != PVRSRV_OK)
421 {
422 PVR_DPF((PVR_DBG_ERROR,"Wait for DC invalidate failed."));
423 PVR_DBG_BREAK;
424 }
426 if (bPDump)
427 {
428 PDUMPREGPOLWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_MEM_REQ_STAT, 0, EUR_CR_BIF_MEM_REQ_STAT_READS_MASK, ui32PDUMPFlags, PDUMP_POLL_OPERATOR_EQUAL);
429 }
430 }
431 #endif /* SGX_FEATURE_MULTIPLE_MEM_CONTEXTS */
432 }
433 #endif /* SGX_FEATURE_MP */
436 /*!
437 *******************************************************************************
439 @Function SGXReset
441 @Description
443 Reset chip
445 @Input psDevInfo - device info. structure
446 @Input bHardwareRecovery - true if recovering powered hardware,
447 false if powering up
448 @Input ui32PDUMPFlags - flags to control PDUMP output
450 @Return IMG_VOID
452 ******************************************************************************/
453 IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
454 IMG_BOOL bHardwareRecovery,
455 IMG_UINT32 ui32PDUMPFlags)
456 #if !defined(SGX_FEATURE_MP)
457 {
458 IMG_UINT32 ui32RegVal;
459 #if defined(EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK)
460 const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK;
461 #else
462 const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_MASK;
463 #endif
465 #if !defined(PDUMP)
466 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
467 #endif /* PDUMP */
469 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Start of SGX reset sequence\r\n");
471 #if defined(FIX_HW_BRN_23944)
472 /* Pause the BIF. */
473 ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
474 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
475 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
477 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
479 ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
480 if (ui32RegVal & ui32BifFaultMask)
481 {
482 /* Page fault needs to be cleared before resetting the BIF. */
483 ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK | EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK;
484 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
485 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
487 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
489 ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
490 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
491 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
493 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
494 }
495 #endif /* defined(FIX_HW_BRN_23944) */
497 /* Reset all including BIF */
498 SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_TRUE);
500 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
502 /*
503 Initialise the BIF state.
504 */
505 #if defined(SGX_FEATURE_36BIT_MMU)
506 /* enable 36bit addressing mode if the MMU supports it*/
507 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK);
508 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK, ui32PDUMPFlags);
509 #else
510 #if defined(EUR_CR_BIF_36BIT_ADDRESSING)
511 OSWriteHWReg(psDevInfo->pvRegsBaseKM,
512 EUR_CR_BIF_36BIT_ADDRESSING,
513 0);
514 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME,
515 EUR_CR_BIF_36BIT_ADDRESSING,
516 0,
517 ui32PDUMPFlags);
518 #endif
519 #endif
521 SGXResetInitBIFContexts(psDevInfo, ui32PDUMPFlags);
523 #if defined(EUR_CR_BIF_MEM_ARB_CONFIG)
524 /*
525 Initialise the memory arbiter to its default state
526 */
527 ui32RegVal = (12UL << EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_SHIFT) |
528 (7UL << EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_SHIFT) |
529 (12UL << EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_SHIFT);
530 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_MEM_ARB_CONFIG, ui32RegVal);
531 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_MEM_ARB_CONFIG, ui32RegVal, ui32PDUMPFlags);
532 #endif /* EUR_CR_BIF_MEM_ARB_CONFIG */
534 #if defined(SGX_FEATURE_SYSTEM_CACHE)
535 #if defined(SGX_BYPASS_SYSTEM_CACHE)
536 /* set the SLC to bypass all accesses */
537 ui32RegVal = MNE_CR_CTRL_BYPASS_ALL_MASK;
538 #else
539 #if defined(FIX_HW_BRN_26620)
540 ui32RegVal = 0;
541 #else
542 /* set the SLC to bypass cache-coherent accesses */
543 ui32RegVal = MNE_CR_CTRL_BYP_CC_MASK;
544 #endif
545 #if defined(FIX_HW_BRN_34028)
546 /* Bypass the MNE for the USEC requester */
547 ui32RegVal |= (8 << MNE_CR_CTRL_BYPASS_SHIFT);
548 #endif
549 #endif /* SGX_BYPASS_SYSTEM_CACHE */
550 OSWriteHWReg(psDevInfo->pvRegsBaseKM, MNE_CR_CTRL, ui32RegVal);
551 PDUMPREG(SGX_PDUMPREG_NAME, MNE_CR_CTRL, ui32RegVal);
552 #endif /* SGX_FEATURE_SYSTEM_CACHE */
554 if (bHardwareRecovery)
555 {
556 /*
557 Set all requestors to the dummy PD which forces all memory
558 accesses to page fault.
559 This enables us to flush out BIF requests from parts of SGX
560 which do not have their own soft reset.
561 Note: sBIFResetPDDevPAddr.uiAddr is a relative address (2GB max)
562 MSB is the bus master flag; 1 == enabled
563 */
564 ui32RegVal = (IMG_UINT32)psDevInfo->sBIFResetPDDevPAddr.uiAddr;
565 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
567 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
569 /* Bring BIF out of reset. */
570 SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_TRUE);
571 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
573 SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
575 /*
576 Check for a page fault from parts of SGX which do not have a reset.
577 */
578 for (;;)
579 {
580 IMG_UINT32 ui32BifIntStat = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
581 IMG_DEV_VIRTADDR sBifFault;
582 IMG_UINT32 ui32PDIndex, ui32PTIndex;
584 if ((ui32BifIntStat & ui32BifFaultMask) == 0)
585 {
586 break;
587 }
589 /*
590 There is a page fault, so reset the BIF again, map in the dummy page,
591 bring the BIF up and invalidate the Directory Cache.
592 */
593 sBifFault.uiAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_FAULT);
594 PVR_DPF((PVR_DBG_WARNING, "SGXReset: Page fault 0x%x/0x%x", ui32BifIntStat, sBifFault.uiAddr));
595 ui32PDIndex = sBifFault.uiAddr >> (SGX_MMU_PAGE_SHIFT + SGX_MMU_PT_SHIFT);
596 ui32PTIndex = (sBifFault.uiAddr & SGX_MMU_PT_MASK) >> SGX_MMU_PAGE_SHIFT;
598 /* Put the BIF into reset. */
599 SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_FALSE);
601 /* Map in the dummy page. */
602 psDevInfo->pui32BIFResetPD[ui32PDIndex] = (IMG_UINT32)(psDevInfo->sBIFResetPTDevPAddr.uiAddr
603 >>SGX_MMU_PDE_ADDR_ALIGNSHIFT)
604 | SGX_MMU_PDE_PAGE_SIZE_4K
605 | SGX_MMU_PDE_VALID;
606 psDevInfo->pui32BIFResetPT[ui32PTIndex] = (IMG_UINT32)(psDevInfo->sBIFResetPageDevPAddr.uiAddr
607 >>SGX_MMU_PTE_ADDR_ALIGNSHIFT)
608 | SGX_MMU_PTE_VALID;
610 /* Clear outstanding events. */
611 ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
612 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32RegVal);
613 ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2);
614 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32RegVal);
616 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
618 /* Bring the BIF out of reset. */
619 SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_FALSE);
620 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
622 /* Invalidate Directory Cache. */
623 SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
625 /* Unmap the dummy page and try again. */
626 psDevInfo->pui32BIFResetPD[ui32PDIndex] = 0;
627 psDevInfo->pui32BIFResetPT[ui32PTIndex] = 0;
628 }
629 }
630 else
631 {
632 /* Bring BIF out of reset. */
633 SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_TRUE);
634 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
635 }
637 /*
638 Initialise the BIF memory contexts before bringing the rest of SGX out of reset.
639 */
640 SGXResetSetupBIFContexts(psDevInfo, ui32PDUMPFlags);
642 #if defined(SGX_FEATURE_2D_HARDWARE) && !defined(SGX_FEATURE_PTLA)
643 /* check that the heap base has the right alignment (1Mb) */
644 #if ((SGX_2D_HEAP_BASE & ~EUR_CR_BIF_TWOD_REQ_BASE_ADDR_MASK) != 0)
645 #error "SGXReset: SGX_2D_HEAP_BASE doesn't match EUR_CR_BIF_TWOD_REQ_BASE_ADDR_MASK alignment"
646 #endif
647 /* Set up 2D requestor base */
648 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_TWOD_REQ_BASE, SGX_2D_HEAP_BASE);
649 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_TWOD_REQ_BASE, SGX_2D_HEAP_BASE, ui32PDUMPFlags);
650 #endif
652 /* Invalidate BIF Directory cache. */
653 SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
655 PVR_DPF((PVR_DBG_MESSAGE,"Soft Reset of SGX"));
657 /* Take chip out of reset */
658 ui32RegVal = 0;
659 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_SOFT_RESET, ui32RegVal);
660 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
662 /* wait a bit */
663 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
665 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "End of SGX reset sequence\r\n");
666 }
668 #else
670 {
671 IMG_UINT32 ui32RegVal;
673 PVR_UNREFERENCED_PARAMETER(bHardwareRecovery);
675 #if !defined(PDUMP)
676 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
677 #endif /* PDUMP */
679 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Start of SGX MP reset sequence\r\n");
681 /* Put hydra into soft reset */
682 ui32RegVal = EUR_CR_MASTER_SOFT_RESET_BIF_RESET_MASK |
683 EUR_CR_MASTER_SOFT_RESET_IPF_RESET_MASK |
684 EUR_CR_MASTER_SOFT_RESET_DPM_RESET_MASK |
685 EUR_CR_MASTER_SOFT_RESET_VDM_RESET_MASK;
687 if (bHardwareRecovery)
688 {
689 ui32RegVal |= EUR_CR_MASTER_SOFT_RESET_MCI_RESET_MASK;
690 }
692 #if defined(SGX_FEATURE_PTLA)
693 ui32RegVal |= EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_MASK;
694 #endif
695 #if defined(SGX_FEATURE_SYSTEM_CACHE)
696 ui32RegVal |= EUR_CR_MASTER_SOFT_RESET_SLC_RESET_MASK;
697 #endif
699 /* Hard reset the slave cores */
700 ui32RegVal |= EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(0) |
701 EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(1) |
702 EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(2) |
703 EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(3);
705 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SOFT_RESET, ui32RegVal);
706 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Soft reset hydra partition, hard reset the cores\r\n");
707 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
709 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
711 ui32RegVal = 0;
712 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BIF_CTRL, ui32RegVal);
713 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the hydra BIF control\r\n");
714 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
716 #if defined(SGX_FEATURE_SYSTEM_CACHE)
717 #if defined(SGX_BYPASS_SYSTEM_CACHE)
718 ui32RegVal = EUR_CR_MASTER_SLC_CTRL_BYPASS_ALL_MASK;
719 #else
720 ui32RegVal = EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_MASK |
721 #if defined(FIX_HW_BRN_30954)
722 EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_MASK |
723 #endif
724 #if defined(PVR_SLC_8KB_ADDRESS_MODE)
725 (4 << EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SHIFT) |
726 #endif
727 #if defined(FIX_HW_BRN_33809)
728 (1 << EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SHIFT) |
729 #endif
730 (0xC << EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SHIFT);
731 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
732 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the hydra SLC control\r\n");
733 PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
735 ui32RegVal = EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_MASK;
736 #if defined(FIX_HW_BRN_31620)
737 ui32RegVal |= EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_MMU_MASK;
738 #endif
739 #if defined(FIX_HW_BRN_31195)
740 ui32RegVal |= EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_MASK |
741 EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_MASK |
742 EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_MASK |
743 EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_MASK |
744 EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_MASK;
745 #endif
746 #endif /* SGX_BYPASS_SYSTEM_CACHE */
747 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
748 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the hydra SLC bypass control\r\n");
749 PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
750 #endif /* SGX_FEATURE_SYSTEM_CACHE */
752 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
754 /* Remove the resets */
755 ui32RegVal = 0;
756 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SOFT_RESET, ui32RegVal);
757 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Remove the resets from all of SGX\r\n");
758 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
760 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
762 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Turn on the slave cores' clock gating\r\n");
763 SGXInitClocks(psDevInfo, ui32PDUMPFlags);
765 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
767 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the slave BIFs\r\n");
769 #if defined(FIX_HW_BRN_31278) || defined(FIX_HW_BRN_31620) || defined(FIX_HW_BRN_31671) || defined(FIX_HW_BRN_32085)
770 #if defined(FIX_HW_BRN_31278) || defined(FIX_HW_BRN_32085)
771 /* disable prefetch */
772 ui32RegVal = (1<<EUR_CR_MASTER_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT);
773 #else
774 ui32RegVal = (1<<EUR_CR_MASTER_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT) | EUR_CR_MASTER_BIF_MMU_CTRL_PREFETCHING_ON_MASK;
775 #endif
776 #if !defined(FIX_HW_BRN_31620) && !defined(FIX_HW_BRN_31671)
777 /* enable the DC TLB */
778 ui32RegVal |= EUR_CR_MASTER_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK;
779 #endif
781 /* Master bank */
782 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BIF_MMU_CTRL, ui32RegVal);
783 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_BIF_MMU_CTRL, ui32RegVal, ui32PDUMPFlags);
785 #if defined(FIX_HW_BRN_31278) || defined(FIX_HW_BRN_32085)
786 /* disable prefetch */
787 ui32RegVal = (1<<EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT);
788 #else
789 ui32RegVal = (1<<EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT) | EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK;
790 #endif
791 #if !defined(FIX_HW_BRN_31620) && !defined(FIX_HW_BRN_31671)
792 /* enable the DC TLB */
793 ui32RegVal |= EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK;
794 #endif
796 /* Per-core */
797 {
798 IMG_UINT32 ui32Core;
800 for (ui32Core=0;ui32Core<SGX_FEATURE_MP_CORE_COUNT;ui32Core++)
801 {
802 OSWriteHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BIF_MMU_CTRL, ui32Core), ui32RegVal);
803 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, SGX_MP_CORE_SELECT(EUR_CR_BIF_MMU_CTRL, ui32Core), ui32RegVal, ui32PDUMPFlags);
804 }
805 }
806 #endif
808 SGXResetInitBIFContexts(psDevInfo, ui32PDUMPFlags);
809 SGXResetSetupBIFContexts(psDevInfo, ui32PDUMPFlags);
811 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "End of SGX MP reset sequence\r\n");
812 }
813 #endif /* SGX_FEATURE_MP */
816 /******************************************************************************
817 End of file (sgxreset.c)
818 ******************************************************************************/