drm/radeon: properly lock disp in mc_stop/resume for r5xx-r7xx

commit 2f86e2ede39a98650c2d465857405ef1c51372b1 upstream.

Need to wait for the new addresses to take affect before
re-enabling the MC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index ec576aaafb7347b74f5f223f31a0273ffb8215fe..6ada4e4e73017e5e6dc68f89c0b739de5aabb2fa 100644 (file)
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -357,6 +357,7 @@
 #define AVIVO_D1CRTC_FRAME_COUNT                                0x60a4
 #define AVIVO_D1CRTC_STEREO_CONTROL                             0x60c4
 
+#define AVIVO_D1MODE_MASTER_UPDATE_LOCK                         0x60e0
 #define AVIVO_D1MODE_MASTER_UPDATE_MODE                         0x60e4
 
 /* master controls */

diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 5e1ba16c7a77b0de744c60e6ea1fc059c78cab18..6a1e5dd5b5eec17c3e6f299ba934b385fe0cc5b3 100644 (file)
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -338,6 +338,22 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
        }
        /* wait for the MC to settle */
        udelay(100);
+
+       /* lock double buffered regs */
+       for (i = 0; i < rdev->num_crtc; i++) {
+               if (save->crtc_enabled[i]) {
+                       tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
+                       if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
+                               tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
+                               WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
+                       }
+                       tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
+                       if (!(tmp & 1)) {
+                               tmp |= 1;
+                               WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
+                       }
+               }
+       }
 }
 
 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
@@ -367,6 +383,33 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
        }
        WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
 
+       /* unlock regs and wait for update */
+       for (i = 0; i < rdev->num_crtc; i++) {
+               if (save->crtc_enabled[i]) {
+                       tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
+                       if ((tmp & 0x3) != 0) {
+                               tmp &= ~0x3;
+                               WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
+                       }
+                       tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
+                       if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
+                               tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
+                               WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
+                       }
+                       tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
+                       if (tmp & 1) {
+                               tmp &= ~1;
+                               WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
+                       }
+                       for (j = 0; j < rdev->usec_timeout; j++) {
+                               tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
+                               if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
+                                       break;
+                               udelay(1);
+                       }
+               }
+       }
+
        if (rdev->family >= CHIP_R600) {
                /* unblackout the MC */
                if (rdev->family >= CHIP_RV770)