e1dcf5424406581b93343deebd3c3f7bba38e424
1 config ARM
2 bool
3 default y
4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_PCI_IOMAP
16 select GENERIC_SMP_IDLE_THREAD
17 select GENERIC_STRNCPY_FROM_USER
18 select GENERIC_STRNLEN_USER
19 select HARDIRQS_SW_RESEND
20 select HAVE_AOUT
21 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
22 select HAVE_ARCH_KGDB
23 select HAVE_ARCH_SECCOMP_FILTER
24 select HAVE_ARCH_TRACEHOOK
25 select HAVE_BPF_JIT
26 select HAVE_C_RECORDMCOUNT
27 select HAVE_DEBUG_KMEMLEAK
28 select HAVE_DMA_API_DEBUG
29 select HAVE_DMA_ATTRS
30 select HAVE_DMA_CONTIGUOUS if MMU
31 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
32 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
33 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
34 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
35 select HAVE_GENERIC_DMA_COHERENT
36 select HAVE_GENERIC_HARDIRQS
37 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
38 select HAVE_IDE if PCI || ISA || PCMCIA
39 select HAVE_IRQ_WORK
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
43 select HAVE_KERNEL_XZ
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
46 select HAVE_MEMBLOCK
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
51 select HAVE_UID16
52 select KTIME_SCALAR
53 select PERF_USE_VMALLOC
54 select RTC_LIB
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 select CLONE_BACKWARDS
59 help
60 The ARM series is a line of low-power-consumption RISC chip designs
61 licensed by ARM Ltd and targeted at embedded applications and
62 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
63 manufactured, but legacy ARM-based PC hardware remains popular in
64 Europe. There is an ARM Linux project with a web page at
65 <http://www.arm.linux.org.uk/>.
67 config ARM_HAS_SG_CHAIN
68 bool
70 config NEED_SG_DMA_LENGTH
71 bool
73 config ARM_DMA_USE_IOMMU
74 bool
75 select ARM_HAS_SG_CHAIN
76 select NEED_SG_DMA_LENGTH
78 config HAVE_PWM
79 bool
81 config MIGHT_HAVE_PCI
82 bool
84 config SYS_SUPPORTS_APM_EMULATION
85 bool
87 config GENERIC_GPIO
88 bool
90 config HAVE_TCM
91 bool
92 select GENERIC_ALLOCATOR
94 config HAVE_PROC_CPU
95 bool
97 config NO_IOPORT
98 bool
100 config EISA
101 bool
102 ---help---
103 The Extended Industry Standard Architecture (EISA) bus was
104 developed as an open alternative to the IBM MicroChannel bus.
106 The EISA bus provided some of the features of the IBM MicroChannel
107 bus while maintaining backward compatibility with cards made for
108 the older ISA bus. The EISA bus saw limited use between 1988 and
109 1995 when it was made obsolete by the PCI bus.
111 Say Y here if you are building a kernel for an EISA-based machine.
113 Otherwise, say N.
115 config SBUS
116 bool
118 config STACKTRACE_SUPPORT
119 bool
120 default y
122 config HAVE_LATENCYTOP_SUPPORT
123 bool
124 depends on !SMP
125 default y
127 config LOCKDEP_SUPPORT
128 bool
129 default y
131 config TRACE_IRQFLAGS_SUPPORT
132 bool
133 default y
135 config RWSEM_GENERIC_SPINLOCK
136 bool
137 default y
139 config RWSEM_XCHGADD_ALGORITHM
140 bool
142 config ARCH_HAS_ILOG2_U32
143 bool
145 config ARCH_HAS_ILOG2_U64
146 bool
148 config ARCH_HAS_CPUFREQ
149 bool
150 help
151 Internal node to signify that the ARCH has CPUFREQ support
152 and that the relevant menu configurations are displayed for
153 it.
155 config GENERIC_HWEIGHT
156 bool
157 default y
159 config GENERIC_CALIBRATE_DELAY
160 bool
161 default y
163 config ARCH_MAY_HAVE_PC_FDC
164 bool
166 config ZONE_DMA
167 bool
169 config NEED_DMA_MAP_STATE
170 def_bool y
172 config ARCH_HAS_DMA_SET_COHERENT_MASK
173 bool
175 config GENERIC_ISA_DMA
176 bool
178 config FIQ
179 bool
181 config NEED_RET_TO_USER
182 bool
184 config ARCH_MTD_XIP
185 bool
187 config VECTORS_BASE
188 hex
189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190 default DRAM_BASE if REMAP_VECTORS_TO_RAM
191 default 0x00000000
192 help
193 The base address of exception vectors.
195 config ARM_PATCH_PHYS_VIRT
196 bool "Patch physical to virtual translations at runtime" if EMBEDDED
197 default y
198 depends on !XIP_KERNEL && MMU
199 depends on !ARCH_REALVIEW || !SPARSEMEM
200 help
201 Patch phys-to-virt and virt-to-phys translation functions at
202 boot and module load time according to the position of the
203 kernel in system memory.
205 This can only be used with non-XIP MMU kernels where the base
206 of physical memory is at a 16MB boundary.
208 Only disable this option if you know that you do not require
209 this feature (eg, building a kernel for a single machine) and
210 you need to shrink the kernel to the minimal size.
212 config NEED_MACH_GPIO_H
213 bool
214 help
215 Select this when mach/gpio.h is required to provide special
216 definitions for this platform. The need for mach/gpio.h should
217 be avoided when possible.
219 config NEED_MACH_IO_H
220 bool
221 help
222 Select this when mach/io.h is required to provide special
223 definitions for this platform. The need for mach/io.h should
224 be avoided when possible.
226 config NEED_MACH_MEMORY_H
227 bool
228 help
229 Select this when mach/memory.h is required to provide special
230 definitions for this platform. The need for mach/memory.h should
231 be avoided when possible.
233 config PHYS_OFFSET
234 hex "Physical address of main memory" if MMU
235 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
236 default DRAM_BASE if !MMU
237 help
238 Please provide the physical address corresponding to the
239 location of main memory in your system.
241 config GENERIC_BUG
242 def_bool y
243 depends on BUG
245 source "init/Kconfig"
247 source "kernel/Kconfig.freezer"
249 menu "System Type"
251 config MMU
252 bool "MMU-based Paged Memory Management Support"
253 default y
254 help
255 Select if you want MMU-based virtualised addressing space
256 support by paged memory management. If unsure, say 'Y'.
258 #
259 # The "ARM system type" choice list is ordered alphabetically by option
260 # text. Please add new entries in the option alphabetic order.
261 #
262 choice
263 prompt "ARM system type"
264 default ARCH_MULTIPLATFORM
266 config ARCH_MULTIPLATFORM
267 bool "Allow multiple platforms to be selected"
268 depends on MMU
269 select ARM_PATCH_PHYS_VIRT
270 select AUTO_ZRELADDR
271 select COMMON_CLK
272 select MULTI_IRQ_HANDLER
273 select SPARSE_IRQ
274 select USE_OF
276 config ARCH_INTEGRATOR
277 bool "ARM Ltd. Integrator family"
278 select ARCH_HAS_CPUFREQ
279 select ARM_AMBA
280 select COMMON_CLK
281 select COMMON_CLK_VERSATILE
282 select GENERIC_CLOCKEVENTS
283 select HAVE_TCM
284 select ICST
285 select MULTI_IRQ_HANDLER
286 select NEED_MACH_MEMORY_H
287 select PLAT_VERSATILE
288 select SPARSE_IRQ
289 select VERSATILE_FPGA_IRQ
290 help
291 Support for ARM's Integrator platform.
293 config ARCH_REALVIEW
294 bool "ARM Ltd. RealView family"
295 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select ARM_AMBA
297 select ARM_TIMER_SP804
298 select COMMON_CLK
299 select COMMON_CLK_VERSATILE
300 select GENERIC_CLOCKEVENTS
301 select GPIO_PL061 if GPIOLIB
302 select ICST
303 select NEED_MACH_MEMORY_H
304 select PLAT_VERSATILE
305 select PLAT_VERSATILE_CLCD
306 help
307 This enables support for ARM Ltd RealView boards.
309 config ARCH_VERSATILE
310 bool "ARM Ltd. Versatile family"
311 select ARCH_WANT_OPTIONAL_GPIOLIB
312 select ARM_AMBA
313 select ARM_TIMER_SP804
314 select ARM_VIC
315 select CLKDEV_LOOKUP
316 select GENERIC_CLOCKEVENTS
317 select HAVE_MACH_CLKDEV
318 select ICST
319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLCD
321 select PLAT_VERSATILE_CLOCK
322 select VERSATILE_FPGA_IRQ
323 help
324 This enables support for ARM Ltd Versatile board.
326 config ARCH_AT91
327 bool "Atmel AT91"
328 select ARCH_REQUIRE_GPIOLIB
329 select CLKDEV_LOOKUP
330 select HAVE_CLK
331 select IRQ_DOMAIN
332 select NEED_MACH_GPIO_H
333 select NEED_MACH_IO_H if PCCARD
334 select PINCTRL
335 select PINCTRL_AT91 if USE_OF
336 help
337 This enables support for systems based on Atmel
338 AT91RM9200 and AT91SAM9* processors.
340 config ARCH_BCM2835
341 bool "Broadcom BCM2835 family"
342 select ARCH_REQUIRE_GPIOLIB
343 select ARM_AMBA
344 select ARM_ERRATA_411920
345 select ARM_TIMER_SP804
346 select CLKDEV_LOOKUP
347 select COMMON_CLK
348 select CPU_V6
349 select GENERIC_CLOCKEVENTS
350 select GENERIC_GPIO
351 select MULTI_IRQ_HANDLER
352 select PINCTRL
353 select PINCTRL_BCM2835
354 select SPARSE_IRQ
355 select USE_OF
356 help
357 This enables support for the Broadcom BCM2835 SoC. This SoC is
358 use in the Raspberry Pi, and Roku 2 devices.
360 config ARCH_CNS3XXX
361 bool "Cavium Networks CNS3XXX family"
362 select ARM_GIC
363 select CPU_V6K
364 select GENERIC_CLOCKEVENTS
365 select MIGHT_HAVE_CACHE_L2X0
366 select MIGHT_HAVE_PCI
367 select PCI_DOMAINS if PCI
368 help
369 Support for Cavium Networks CNS3XXX platform.
371 config ARCH_CLPS711X
372 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
373 select ARCH_REQUIRE_GPIOLIB
374 select AUTO_ZRELADDR
375 select CLKDEV_LOOKUP
376 select COMMON_CLK
377 select CPU_ARM720T
378 select GENERIC_CLOCKEVENTS
379 select MULTI_IRQ_HANDLER
380 select NEED_MACH_MEMORY_H
381 select SPARSE_IRQ
382 help
383 Support for Cirrus Logic 711x/721x/731x based boards.
385 config ARCH_GEMINI
386 bool "Cortina Systems Gemini"
387 select ARCH_REQUIRE_GPIOLIB
388 select ARCH_USES_GETTIMEOFFSET
389 select CPU_FA526
390 help
391 Support for the Cortina Systems Gemini family SoCs
393 config ARCH_SIRF
394 bool "CSR SiRF"
395 select ARCH_REQUIRE_GPIOLIB
396 select COMMON_CLK
397 select GENERIC_CLOCKEVENTS
398 select GENERIC_IRQ_CHIP
399 select MIGHT_HAVE_CACHE_L2X0
400 select NO_IOPORT
401 select PINCTRL
402 select PINCTRL_SIRF
403 select USE_OF
404 help
405 Support for CSR SiRFprimaII/Marco/Polo platforms
407 config ARCH_EBSA110
408 bool "EBSA-110"
409 select ARCH_USES_GETTIMEOFFSET
410 select CPU_SA110
411 select ISA
412 select NEED_MACH_IO_H
413 select NEED_MACH_MEMORY_H
414 select NO_IOPORT
415 help
416 This is an evaluation board for the StrongARM processor available
417 from Digital. It has limited hardware on-board, including an
418 Ethernet interface, two PCMCIA sockets, two serial ports and a
419 parallel port.
421 config ARCH_EP93XX
422 bool "EP93xx-based"
423 select ARCH_HAS_HOLES_MEMORYMODEL
424 select ARCH_REQUIRE_GPIOLIB
425 select ARCH_USES_GETTIMEOFFSET
426 select ARM_AMBA
427 select ARM_VIC
428 select CLKDEV_LOOKUP
429 select CPU_ARM920T
430 select NEED_MACH_MEMORY_H
431 help
432 This enables support for the Cirrus EP93xx series of CPUs.
434 config ARCH_FOOTBRIDGE
435 bool "FootBridge"
436 select CPU_SA110
437 select FOOTBRIDGE
438 select GENERIC_CLOCKEVENTS
439 select HAVE_IDE
440 select NEED_MACH_IO_H if !MMU
441 select NEED_MACH_MEMORY_H
442 help
443 Support for systems based on the DC21285 companion chip
444 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
446 config ARCH_MXS
447 bool "Freescale MXS-based"
448 select ARCH_REQUIRE_GPIOLIB
449 select CLKDEV_LOOKUP
450 select CLKSRC_MMIO
451 select COMMON_CLK
452 select GENERIC_CLOCKEVENTS
453 select HAVE_CLK_PREPARE
454 select MULTI_IRQ_HANDLER
455 select PINCTRL
456 select SPARSE_IRQ
457 select USE_OF
458 help
459 Support for Freescale MXS-based family of processors
461 config ARCH_NETX
462 bool "Hilscher NetX based"
463 select ARM_VIC
464 select CLKSRC_MMIO
465 select CPU_ARM926T
466 select GENERIC_CLOCKEVENTS
467 help
468 This enables support for systems based on the Hilscher NetX Soc
470 config ARCH_H720X
471 bool "Hynix HMS720x-based"
472 select ARCH_USES_GETTIMEOFFSET
473 select CPU_ARM720T
474 select ISA_DMA_API
475 help
476 This enables support for systems based on the Hynix HMS720x
478 config ARCH_IOP13XX
479 bool "IOP13xx-based"
480 depends on MMU
481 select ARCH_SUPPORTS_MSI
482 select CPU_XSC3
483 select NEED_MACH_MEMORY_H
484 select NEED_RET_TO_USER
485 select PCI
486 select PLAT_IOP
487 select VMSPLIT_1G
488 help
489 Support for Intel's IOP13XX (XScale) family of processors.
491 config ARCH_IOP32X
492 bool "IOP32x-based"
493 depends on MMU
494 select ARCH_REQUIRE_GPIOLIB
495 select CPU_XSCALE
496 select NEED_MACH_GPIO_H
497 select NEED_RET_TO_USER
498 select PCI
499 select PLAT_IOP
500 help
501 Support for Intel's 80219 and IOP32X (XScale) family of
502 processors.
504 config ARCH_IOP33X
505 bool "IOP33x-based"
506 depends on MMU
507 select ARCH_REQUIRE_GPIOLIB
508 select CPU_XSCALE
509 select NEED_MACH_GPIO_H
510 select NEED_RET_TO_USER
511 select PCI
512 select PLAT_IOP
513 help
514 Support for Intel's IOP33X (XScale) family of processors.
516 config ARCH_IXP4XX
517 bool "IXP4xx-based"
518 depends on MMU
519 select ARCH_HAS_DMA_SET_COHERENT_MASK
520 select ARCH_REQUIRE_GPIOLIB
521 select CLKSRC_MMIO
522 select CPU_XSCALE
523 select DMABOUNCE if PCI
524 select GENERIC_CLOCKEVENTS
525 select MIGHT_HAVE_PCI
526 select NEED_MACH_IO_H
527 help
528 Support for Intel's IXP4XX (XScale) family of processors.
530 config ARCH_DOVE
531 bool "Marvell Dove"
532 select ARCH_REQUIRE_GPIOLIB
533 select COMMON_CLK_DOVE
534 select CPU_V7
535 select GENERIC_CLOCKEVENTS
536 select MIGHT_HAVE_PCI
537 select PINCTRL
538 select PINCTRL_DOVE
539 select PLAT_ORION_LEGACY
540 select USB_ARCH_HAS_EHCI
541 help
542 Support for the Marvell Dove SoC 88AP510
544 config ARCH_KIRKWOOD
545 bool "Marvell Kirkwood"
546 select ARCH_REQUIRE_GPIOLIB
547 select CPU_FEROCEON
548 select GENERIC_CLOCKEVENTS
549 select PCI
550 select PCI_QUIRKS
551 select PINCTRL
552 select PINCTRL_KIRKWOOD
553 select PLAT_ORION_LEGACY
554 help
555 Support for the following Marvell Kirkwood series SoCs:
556 88F6180, 88F6192 and 88F6281.
558 config ARCH_MV78XX0
559 bool "Marvell MV78xx0"
560 select ARCH_REQUIRE_GPIOLIB
561 select CPU_FEROCEON
562 select GENERIC_CLOCKEVENTS
563 select PCI
564 select PLAT_ORION_LEGACY
565 help
566 Support for the following Marvell MV78xx0 series SoCs:
567 MV781x0, MV782x0.
569 config ARCH_ORION5X
570 bool "Marvell Orion"
571 depends on MMU
572 select ARCH_REQUIRE_GPIOLIB
573 select CPU_FEROCEON
574 select GENERIC_CLOCKEVENTS
575 select PCI
576 select PLAT_ORION_LEGACY
577 help
578 Support for the following Marvell Orion 5x series SoCs:
579 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
580 Orion-2 (5281), Orion-1-90 (6183).
582 config ARCH_MMP
583 bool "Marvell PXA168/910/MMP2"
584 depends on MMU
585 select ARCH_REQUIRE_GPIOLIB
586 select CLKDEV_LOOKUP
587 select GENERIC_ALLOCATOR
588 select GENERIC_CLOCKEVENTS
589 select GPIO_PXA
590 select IRQ_DOMAIN
591 select NEED_MACH_GPIO_H
592 select PINCTRL
593 select PLAT_PXA
594 select SPARSE_IRQ
595 help
596 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
598 config ARCH_KS8695
599 bool "Micrel/Kendin KS8695"
600 select ARCH_REQUIRE_GPIOLIB
601 select CLKSRC_MMIO
602 select CPU_ARM922T
603 select GENERIC_CLOCKEVENTS
604 select NEED_MACH_MEMORY_H
605 help
606 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
607 System-on-Chip devices.
609 config ARCH_W90X900
610 bool "Nuvoton W90X900 CPU"
611 select ARCH_REQUIRE_GPIOLIB
612 select CLKDEV_LOOKUP
613 select CLKSRC_MMIO
614 select CPU_ARM926T
615 select GENERIC_CLOCKEVENTS
616 help
617 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
618 At present, the w90x900 has been renamed nuc900, regarding
619 the ARM series product line, you can login the following
620 link address to know more.
622 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
623 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
625 config ARCH_LPC32XX
626 bool "NXP LPC32XX"
627 select ARCH_REQUIRE_GPIOLIB
628 select ARM_AMBA
629 select CLKDEV_LOOKUP
630 select CLKSRC_MMIO
631 select CPU_ARM926T
632 select GENERIC_CLOCKEVENTS
633 select HAVE_IDE
634 select HAVE_PWM
635 select USB_ARCH_HAS_OHCI
636 select USE_OF
637 help
638 Support for the NXP LPC32XX family of processors
640 config ARCH_TEGRA
641 bool "NVIDIA Tegra"
642 select ARCH_HAS_CPUFREQ
643 select CLKDEV_LOOKUP
644 select CLKSRC_MMIO
645 select COMMON_CLK
646 select GENERIC_CLOCKEVENTS
647 select GENERIC_GPIO
648 select HAVE_CLK
649 select HAVE_SMP
650 select MIGHT_HAVE_CACHE_L2X0
651 select SPARSE_IRQ
652 select USE_OF
653 help
654 This enables support for NVIDIA Tegra based systems (Tegra APX,
655 Tegra 6xx and Tegra 2 series).
657 config ARCH_PXA
658 bool "PXA2xx/PXA3xx-based"
659 depends on MMU
660 select ARCH_HAS_CPUFREQ
661 select ARCH_MTD_XIP
662 select ARCH_REQUIRE_GPIOLIB
663 select ARM_CPU_SUSPEND if PM
664 select AUTO_ZRELADDR
665 select CLKDEV_LOOKUP
666 select CLKSRC_MMIO
667 select GENERIC_CLOCKEVENTS
668 select GPIO_PXA
669 select HAVE_IDE
670 select MULTI_IRQ_HANDLER
671 select NEED_MACH_GPIO_H
672 select PLAT_PXA
673 select SPARSE_IRQ
674 help
675 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
677 config ARCH_MSM
678 bool "Qualcomm MSM"
679 select ARCH_REQUIRE_GPIOLIB
680 select CLKDEV_LOOKUP
681 select GENERIC_CLOCKEVENTS
682 select HAVE_CLK
683 help
684 Support for Qualcomm MSM/QSD based systems. This runs on the
685 apps processor of the MSM/QSD and depends on a shared memory
686 interface to the modem processor which runs the baseband
687 stack and controls some vital subsystems
688 (clock and power control, etc).
690 config ARCH_SHMOBILE
691 bool "Renesas SH-Mobile / R-Mobile"
692 select CLKDEV_LOOKUP
693 select GENERIC_CLOCKEVENTS
694 select HAVE_CLK
695 select HAVE_MACH_CLKDEV
696 select HAVE_SMP
697 select MIGHT_HAVE_CACHE_L2X0
698 select MULTI_IRQ_HANDLER
699 select NEED_MACH_MEMORY_H
700 select NO_IOPORT
701 select PM_GENERIC_DOMAINS if PM
702 select SPARSE_IRQ
703 help
704 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
706 config ARCH_RPC
707 bool "RiscPC"
708 select ARCH_ACORN
709 select ARCH_MAY_HAVE_PC_FDC
710 select ARCH_SPARSEMEM_ENABLE
711 select ARCH_USES_GETTIMEOFFSET
712 select FIQ
713 select HAVE_IDE
714 select HAVE_PATA_PLATFORM
715 select ISA_DMA_API
716 select NEED_MACH_IO_H
717 select NEED_MACH_MEMORY_H
718 select NO_IOPORT
719 help
720 On the Acorn Risc-PC, Linux can support the internal IDE disk and
721 CD-ROM interface, serial and parallel port, and the floppy drive.
723 config ARCH_SA1100
724 bool "SA1100-based"
725 select ARCH_HAS_CPUFREQ
726 select ARCH_MTD_XIP
727 select ARCH_REQUIRE_GPIOLIB
728 select ARCH_SPARSEMEM_ENABLE
729 select CLKDEV_LOOKUP
730 select CLKSRC_MMIO
731 select CPU_FREQ
732 select CPU_SA1100
733 select GENERIC_CLOCKEVENTS
734 select HAVE_IDE
735 select ISA
736 select NEED_MACH_GPIO_H
737 select NEED_MACH_MEMORY_H
738 select SPARSE_IRQ
739 help
740 Support for StrongARM 11x0 based boards.
742 config ARCH_S3C24XX
743 bool "Samsung S3C24XX SoCs"
744 select ARCH_HAS_CPUFREQ
745 select ARCH_USES_GETTIMEOFFSET
746 select CLKDEV_LOOKUP
747 select GENERIC_GPIO
748 select HAVE_CLK
749 select HAVE_S3C2410_I2C if I2C
750 select HAVE_S3C2410_WATCHDOG if WATCHDOG
751 select HAVE_S3C_RTC if RTC_CLASS
752 select NEED_MACH_GPIO_H
753 select NEED_MACH_IO_H
754 help
755 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
756 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
757 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
758 Samsung SMDK2410 development board (and derivatives).
760 config ARCH_S3C64XX
761 bool "Samsung S3C64XX"
762 select ARCH_HAS_CPUFREQ
763 select ARCH_REQUIRE_GPIOLIB
764 select ARCH_USES_GETTIMEOFFSET
765 select ARM_VIC
766 select CLKDEV_LOOKUP
767 select CPU_V6
768 select HAVE_CLK
769 select HAVE_S3C2410_I2C if I2C
770 select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 select HAVE_TCM
772 select NEED_MACH_GPIO_H
773 select NO_IOPORT
774 select PLAT_SAMSUNG
775 select S3C_DEV_NAND
776 select S3C_GPIO_TRACK
777 select SAMSUNG_CLKSRC
778 select SAMSUNG_GPIOLIB_4BIT
779 select SAMSUNG_IRQ_VIC_TIMER
780 select USB_ARCH_HAS_OHCI
781 help
782 Samsung S3C64XX series based systems
784 config ARCH_S5P64X0
785 bool "Samsung S5P6440 S5P6450"
786 select CLKDEV_LOOKUP
787 select CLKSRC_MMIO
788 select CPU_V6
789 select GENERIC_CLOCKEVENTS
790 select GENERIC_GPIO
791 select HAVE_CLK
792 select HAVE_S3C2410_I2C if I2C
793 select HAVE_S3C2410_WATCHDOG if WATCHDOG
794 select HAVE_S3C_RTC if RTC_CLASS
795 select NEED_MACH_GPIO_H
796 help
797 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
798 SMDK6450.
800 config ARCH_S5PC100
801 bool "Samsung S5PC100"
802 select ARCH_USES_GETTIMEOFFSET
803 select CLKDEV_LOOKUP
804 select CPU_V7
805 select GENERIC_GPIO
806 select HAVE_CLK
807 select HAVE_S3C2410_I2C if I2C
808 select HAVE_S3C2410_WATCHDOG if WATCHDOG
809 select HAVE_S3C_RTC if RTC_CLASS
810 select NEED_MACH_GPIO_H
811 help
812 Samsung S5PC100 series based systems
814 config ARCH_S5PV210
815 bool "Samsung S5PV210/S5PC110"
816 select ARCH_HAS_CPUFREQ
817 select ARCH_HAS_HOLES_MEMORYMODEL
818 select ARCH_SPARSEMEM_ENABLE
819 select CLKDEV_LOOKUP
820 select CLKSRC_MMIO
821 select CPU_V7
822 select GENERIC_CLOCKEVENTS
823 select GENERIC_GPIO
824 select HAVE_CLK
825 select HAVE_S3C2410_I2C if I2C
826 select HAVE_S3C2410_WATCHDOG if WATCHDOG
827 select HAVE_S3C_RTC if RTC_CLASS
828 select NEED_MACH_GPIO_H
829 select NEED_MACH_MEMORY_H
830 help
831 Samsung S5PV210/S5PC110 series based systems
833 config ARCH_EXYNOS
834 bool "Samsung EXYNOS"
835 select ARCH_HAS_CPUFREQ
836 select ARCH_HAS_HOLES_MEMORYMODEL
837 select ARCH_SPARSEMEM_ENABLE
838 select CLKDEV_LOOKUP
839 select CPU_V7
840 select GENERIC_CLOCKEVENTS
841 select GENERIC_GPIO
842 select HAVE_CLK
843 select HAVE_S3C2410_I2C if I2C
844 select HAVE_S3C2410_WATCHDOG if WATCHDOG
845 select HAVE_S3C_RTC if RTC_CLASS
846 select NEED_MACH_GPIO_H
847 select NEED_MACH_MEMORY_H
848 help
849 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
851 config ARCH_SHARK
852 bool "Shark"
853 select ARCH_USES_GETTIMEOFFSET
854 select CPU_SA110
855 select ISA
856 select ISA_DMA
857 select NEED_MACH_MEMORY_H
858 select PCI
859 select ZONE_DMA
860 help
861 Support for the StrongARM based Digital DNARD machine, also known
862 as "Shark" (<http://www.shark-linux.de/shark.html>).
864 config ARCH_U300
865 bool "ST-Ericsson U300 Series"
866 depends on MMU
867 select ARCH_REQUIRE_GPIOLIB
868 select ARM_AMBA
869 select ARM_PATCH_PHYS_VIRT
870 select ARM_VIC
871 select CLKDEV_LOOKUP
872 select CLKSRC_MMIO
873 select COMMON_CLK
874 select CPU_ARM926T
875 select GENERIC_CLOCKEVENTS
876 select GENERIC_GPIO
877 select HAVE_TCM
878 select SPARSE_IRQ
879 help
880 Support for ST-Ericsson U300 series mobile platforms.
882 config ARCH_U8500
883 bool "ST-Ericsson U8500 Series"
884 depends on MMU
885 select ARCH_HAS_CPUFREQ
886 select ARCH_REQUIRE_GPIOLIB
887 select ARM_AMBA
888 select CLKDEV_LOOKUP
889 select CPU_V7
890 select GENERIC_CLOCKEVENTS
891 select HAVE_SMP
892 select MIGHT_HAVE_CACHE_L2X0
893 select SPARSE_IRQ
894 help
895 Support for ST-Ericsson's Ux500 architecture
897 config ARCH_NOMADIK
898 bool "STMicroelectronics Nomadik"
899 select ARCH_REQUIRE_GPIOLIB
900 select ARM_AMBA
901 select ARM_VIC
902 select COMMON_CLK
903 select CPU_ARM926T
904 select GENERIC_CLOCKEVENTS
905 select MIGHT_HAVE_CACHE_L2X0
906 select PINCTRL
907 select PINCTRL_STN8815
908 select SPARSE_IRQ
909 help
910 Support for the Nomadik platform by ST-Ericsson
912 config PLAT_SPEAR
913 bool "ST SPEAr"
914 select ARCH_HAS_CPUFREQ
915 select ARCH_REQUIRE_GPIOLIB
916 select ARM_AMBA
917 select CLKDEV_LOOKUP
918 select CLKSRC_MMIO
919 select COMMON_CLK
920 select GENERIC_CLOCKEVENTS
921 select HAVE_CLK
922 help
923 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
925 config ARCH_DAVINCI
926 bool "TI DaVinci"
927 select ARCH_HAS_HOLES_MEMORYMODEL
928 select ARCH_REQUIRE_GPIOLIB
929 select CLKDEV_LOOKUP
930 select GENERIC_ALLOCATOR
931 select GENERIC_CLOCKEVENTS
932 select GENERIC_IRQ_CHIP
933 select HAVE_IDE
934 select NEED_MACH_GPIO_H
935 select TI_PRIV_EDMA
936 select USE_OF
937 select ZONE_DMA
938 help
939 Support for TI's DaVinci platform.
941 config ARCH_OMAP
942 bool "TI OMAP"
943 depends on MMU
944 select ARCH_HAS_CPUFREQ
945 select ARCH_HAS_HOLES_MEMORYMODEL
946 select ARCH_REQUIRE_GPIOLIB
947 select CLKSRC_MMIO
948 select GENERIC_CLOCKEVENTS
949 select HAVE_CLK
950 help
951 Support for TI's OMAP platform (OMAP1/2/3/4).
953 config ARCH_VT8500_SINGLE
954 bool "VIA/WonderMedia 85xx"
955 select ARCH_HAS_CPUFREQ
956 select ARCH_REQUIRE_GPIOLIB
957 select CLKDEV_LOOKUP
958 select COMMON_CLK
959 select CPU_ARM926T
960 select GENERIC_CLOCKEVENTS
961 select GENERIC_GPIO
962 select HAVE_CLK
963 select MULTI_IRQ_HANDLER
964 select SPARSE_IRQ
965 select USE_OF
966 help
967 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
969 endchoice
971 menu "Multiple platform selection"
972 depends on ARCH_MULTIPLATFORM
974 comment "CPU Core family selection"
976 config ARCH_MULTI_V4
977 bool "ARMv4 based platforms (FA526, StrongARM)"
978 depends on !ARCH_MULTI_V6_V7
979 select ARCH_MULTI_V4_V5
981 config ARCH_MULTI_V4T
982 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
983 depends on !ARCH_MULTI_V6_V7
984 select ARCH_MULTI_V4_V5
986 config ARCH_MULTI_V5
987 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
988 depends on !ARCH_MULTI_V6_V7
989 select ARCH_MULTI_V4_V5
991 config ARCH_MULTI_V4_V5
992 bool
994 config ARCH_MULTI_V6
995 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
996 select ARCH_MULTI_V6_V7
997 select CPU_V6
999 config ARCH_MULTI_V7
1000 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1001 default y
1002 select ARCH_MULTI_V6_V7
1003 select ARCH_VEXPRESS
1004 select CPU_V7
1006 config ARCH_MULTI_V6_V7
1007 bool
1009 config ARCH_MULTI_CPU_AUTO
1010 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1011 select ARCH_MULTI_V5
1013 endmenu
1015 #
1016 # This is sorted alphabetically by mach-* pathname. However, plat-*
1017 # Kconfigs may be included either alphabetically (according to the
1018 # plat- suffix) or along side the corresponding mach-* source.
1019 #
1020 source "arch/arm/mach-mvebu/Kconfig"
1022 source "arch/arm/mach-at91/Kconfig"
1024 source "arch/arm/mach-bcm/Kconfig"
1026 source "arch/arm/mach-clps711x/Kconfig"
1028 source "arch/arm/mach-cns3xxx/Kconfig"
1030 source "arch/arm/mach-davinci/Kconfig"
1032 source "arch/arm/mach-dove/Kconfig"
1034 source "arch/arm/mach-ep93xx/Kconfig"
1036 source "arch/arm/mach-footbridge/Kconfig"
1038 source "arch/arm/mach-gemini/Kconfig"
1040 source "arch/arm/mach-h720x/Kconfig"
1042 source "arch/arm/mach-highbank/Kconfig"
1044 source "arch/arm/mach-integrator/Kconfig"
1046 source "arch/arm/mach-iop32x/Kconfig"
1048 source "arch/arm/mach-iop33x/Kconfig"
1050 source "arch/arm/mach-iop13xx/Kconfig"
1052 source "arch/arm/mach-ixp4xx/Kconfig"
1054 source "arch/arm/mach-kirkwood/Kconfig"
1056 source "arch/arm/mach-ks8695/Kconfig"
1058 source "arch/arm/mach-msm/Kconfig"
1060 source "arch/arm/mach-mv78xx0/Kconfig"
1062 source "arch/arm/mach-imx/Kconfig"
1064 source "arch/arm/mach-mxs/Kconfig"
1066 source "arch/arm/mach-netx/Kconfig"
1068 source "arch/arm/mach-nomadik/Kconfig"
1070 source "arch/arm/plat-omap/Kconfig"
1072 source "arch/arm/mach-omap1/Kconfig"
1074 source "arch/arm/mach-omap2/Kconfig"
1076 source "arch/arm/mach-orion5x/Kconfig"
1078 source "arch/arm/mach-picoxcell/Kconfig"
1080 source "arch/arm/mach-pxa/Kconfig"
1081 source "arch/arm/plat-pxa/Kconfig"
1083 source "arch/arm/mach-mmp/Kconfig"
1085 source "arch/arm/mach-realview/Kconfig"
1087 source "arch/arm/mach-sa1100/Kconfig"
1089 source "arch/arm/plat-samsung/Kconfig"
1090 source "arch/arm/plat-s3c24xx/Kconfig"
1092 source "arch/arm/mach-socfpga/Kconfig"
1094 source "arch/arm/plat-spear/Kconfig"
1096 source "arch/arm/mach-s3c24xx/Kconfig"
1097 if ARCH_S3C24XX
1098 source "arch/arm/mach-s3c2412/Kconfig"
1099 source "arch/arm/mach-s3c2440/Kconfig"
1100 endif
1102 if ARCH_S3C64XX
1103 source "arch/arm/mach-s3c64xx/Kconfig"
1104 endif
1106 source "arch/arm/mach-s5p64x0/Kconfig"
1108 source "arch/arm/mach-s5pc100/Kconfig"
1110 source "arch/arm/mach-s5pv210/Kconfig"
1112 source "arch/arm/mach-exynos/Kconfig"
1114 source "arch/arm/mach-shmobile/Kconfig"
1116 source "arch/arm/mach-sunxi/Kconfig"
1118 source "arch/arm/mach-prima2/Kconfig"
1120 source "arch/arm/mach-tegra/Kconfig"
1122 source "arch/arm/mach-u300/Kconfig"
1124 source "arch/arm/mach-ux500/Kconfig"
1126 source "arch/arm/mach-versatile/Kconfig"
1128 source "arch/arm/mach-vexpress/Kconfig"
1129 source "arch/arm/plat-versatile/Kconfig"
1131 source "arch/arm/mach-vt8500/Kconfig"
1133 source "arch/arm/mach-w90x900/Kconfig"
1135 source "arch/arm/mach-zynq/Kconfig"
1137 # Definitions to make life easier
1138 config ARCH_ACORN
1139 bool
1141 config PLAT_IOP
1142 bool
1143 select GENERIC_CLOCKEVENTS
1145 config PLAT_ORION
1146 bool
1147 select CLKSRC_MMIO
1148 select COMMON_CLK
1149 select GENERIC_IRQ_CHIP
1150 select IRQ_DOMAIN
1152 config PLAT_ORION_LEGACY
1153 bool
1154 select PLAT_ORION
1156 config PLAT_PXA
1157 bool
1159 config PLAT_VERSATILE
1160 bool
1162 config ARM_TIMER_SP804
1163 bool
1164 select CLKSRC_MMIO
1165 select HAVE_SCHED_CLOCK
1167 source arch/arm/mm/Kconfig
1169 config ARM_NR_BANKS
1170 int
1171 default 16 if ARCH_EP93XX
1172 default 8
1174 config IWMMXT
1175 bool "Enable iWMMXt support"
1176 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1177 default y if PXA27x || PXA3xx || ARCH_MMP
1178 help
1179 Enable support for iWMMXt context switching at run time if
1180 running on a CPU that supports it.
1182 config XSCALE_PMU
1183 bool
1184 depends on CPU_XSCALE
1185 default y
1187 config MULTI_IRQ_HANDLER
1188 bool
1189 help
1190 Allow each machine to specify it's own IRQ handler at run time.
1192 if !MMU
1193 source "arch/arm/Kconfig-nommu"
1194 endif
1196 config ARM_ERRATA_326103
1197 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1198 depends on CPU_V6
1199 help
1200 Executing a SWP instruction to read-only memory does not set bit 11
1201 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1202 treat the access as a read, preventing a COW from occurring and
1203 causing the faulting task to livelock.
1205 config ARM_ERRATA_411920
1206 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1207 depends on CPU_V6 || CPU_V6K
1208 help
1209 Invalidation of the Instruction Cache operation can
1210 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1211 It does not affect the MPCore. This option enables the ARM Ltd.
1212 recommended workaround.
1214 config ARM_ERRATA_430973
1215 bool "ARM errata: Stale prediction on replaced interworking branch"
1216 depends on CPU_V7
1217 help
1218 This option enables the workaround for the 430973 Cortex-A8
1219 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1220 interworking branch is replaced with another code sequence at the
1221 same virtual address, whether due to self-modifying code or virtual
1222 to physical address re-mapping, Cortex-A8 does not recover from the
1223 stale interworking branch prediction. This results in Cortex-A8
1224 executing the new code sequence in the incorrect ARM or Thumb state.
1225 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1226 and also flushes the branch target cache at every context switch.
1227 Note that setting specific bits in the ACTLR register may not be
1228 available in non-secure mode.
1230 config ARM_ERRATA_458693
1231 bool "ARM errata: Processor deadlock when a false hazard is created"
1232 depends on CPU_V7
1233 depends on !ARCH_MULTIPLATFORM
1234 help
1235 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1236 erratum. For very specific sequences of memory operations, it is
1237 possible for a hazard condition intended for a cache line to instead
1238 be incorrectly associated with a different cache line. This false
1239 hazard might then cause a processor deadlock. The workaround enables
1240 the L1 caching of the NEON accesses and disables the PLD instruction
1241 in the ACTLR register. Note that setting specific bits in the ACTLR
1242 register may not be available in non-secure mode.
1244 config ARM_ERRATA_460075
1245 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1246 depends on CPU_V7
1247 depends on !ARCH_MULTIPLATFORM
1248 help
1249 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1250 erratum. Any asynchronous access to the L2 cache may encounter a
1251 situation in which recent store transactions to the L2 cache are lost
1252 and overwritten with stale memory contents from external memory. The
1253 workaround disables the write-allocate mode for the L2 cache via the
1254 ACTLR register. Note that setting specific bits in the ACTLR register
1255 may not be available in non-secure mode.
1257 config ARM_ERRATA_742230
1258 bool "ARM errata: DMB operation may be faulty"
1259 depends on CPU_V7 && SMP
1260 depends on !ARCH_MULTIPLATFORM
1261 help
1262 This option enables the workaround for the 742230 Cortex-A9
1263 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1264 between two write operations may not ensure the correct visibility
1265 ordering of the two writes. This workaround sets a specific bit in
1266 the diagnostic register of the Cortex-A9 which causes the DMB
1267 instruction to behave as a DSB, ensuring the correct behaviour of
1268 the two writes.
1270 config ARM_ERRATA_742231
1271 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1272 depends on CPU_V7 && SMP
1273 depends on !ARCH_MULTIPLATFORM
1274 help
1275 This option enables the workaround for the 742231 Cortex-A9
1276 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1277 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1278 accessing some data located in the same cache line, may get corrupted
1279 data due to bad handling of the address hazard when the line gets
1280 replaced from one of the CPUs at the same time as another CPU is
1281 accessing it. This workaround sets specific bits in the diagnostic
1282 register of the Cortex-A9 which reduces the linefill issuing
1283 capabilities of the processor.
1285 config PL310_ERRATA_588369
1286 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1287 depends on CACHE_L2X0
1288 help
1289 The PL310 L2 cache controller implements three types of Clean &
1290 Invalidate maintenance operations: by Physical Address
1291 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1292 They are architecturally defined to behave as the execution of a
1293 clean operation followed immediately by an invalidate operation,
1294 both performing to the same memory location. This functionality
1295 is not correctly implemented in PL310 as clean lines are not
1296 invalidated as a result of these operations.
1298 config ARM_ERRATA_720789
1299 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1300 depends on CPU_V7
1301 help
1302 This option enables the workaround for the 720789 Cortex-A9 (prior to
1303 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1304 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1305 As a consequence of this erratum, some TLB entries which should be
1306 invalidated are not, resulting in an incoherency in the system page
1307 tables. The workaround changes the TLB flushing routines to invalidate
1308 entries regardless of the ASID.
1310 config PL310_ERRATA_727915
1311 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1312 depends on CACHE_L2X0
1313 help
1314 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1315 operation (offset 0x7FC). This operation runs in background so that
1316 PL310 can handle normal accesses while it is in progress. Under very
1317 rare circumstances, due to this erratum, write data can be lost when
1318 PL310 treats a cacheable write transaction during a Clean &
1319 Invalidate by Way operation.
1321 config ARM_ERRATA_743622
1322 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1323 depends on CPU_V7
1324 depends on !ARCH_MULTIPLATFORM
1325 help
1326 This option enables the workaround for the 743622 Cortex-A9
1327 (r2p*) erratum. Under very rare conditions, a faulty
1328 optimisation in the Cortex-A9 Store Buffer may lead to data
1329 corruption. This workaround sets a specific bit in the diagnostic
1330 register of the Cortex-A9 which disables the Store Buffer
1331 optimisation, preventing the defect from occurring. This has no
1332 visible impact on the overall performance or power consumption of the
1333 processor.
1335 config ARM_ERRATA_751472
1336 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1337 depends on CPU_V7
1338 depends on !ARCH_MULTIPLATFORM
1339 help
1340 This option enables the workaround for the 751472 Cortex-A9 (prior
1341 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1342 completion of a following broadcasted operation if the second
1343 operation is received by a CPU before the ICIALLUIS has completed,
1344 potentially leading to corrupted entries in the cache or TLB.
1346 config PL310_ERRATA_753970
1347 bool "PL310 errata: cache sync operation may be faulty"
1348 depends on CACHE_PL310
1349 help
1350 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1352 Under some condition the effect of cache sync operation on
1353 the store buffer still remains when the operation completes.
1354 This means that the store buffer is always asked to drain and
1355 this prevents it from merging any further writes. The workaround
1356 is to replace the normal offset of cache sync operation (0x730)
1357 by another offset targeting an unmapped PL310 register 0x740.
1358 This has the same effect as the cache sync operation: store buffer
1359 drain and waiting for all buffers empty.
1361 config ARM_ERRATA_754322
1362 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1363 depends on CPU_V7
1364 help
1365 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1366 r3p*) erratum. A speculative memory access may cause a page table walk
1367 which starts prior to an ASID switch but completes afterwards. This
1368 can populate the micro-TLB with a stale entry which may be hit with
1369 the new ASID. This workaround places two dsb instructions in the mm
1370 switching code so that no page table walks can cross the ASID switch.
1372 config ARM_ERRATA_754327
1373 bool "ARM errata: no automatic Store Buffer drain"
1374 depends on CPU_V7 && SMP
1375 help
1376 This option enables the workaround for the 754327 Cortex-A9 (prior to
1377 r2p0) erratum. The Store Buffer does not have any automatic draining
1378 mechanism and therefore a livelock may occur if an external agent
1379 continuously polls a memory location waiting to observe an update.
1380 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1381 written polling loops from denying visibility of updates to memory.
1383 config ARM_ERRATA_364296
1384 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1385 depends on CPU_V6 && !SMP
1386 help
1387 This options enables the workaround for the 364296 ARM1136
1388 r0p2 erratum (possible cache data corruption with
1389 hit-under-miss enabled). It sets the undocumented bit 31 in
1390 the auxiliary control register and the FI bit in the control
1391 register, thus disabling hit-under-miss without putting the
1392 processor into full low interrupt latency mode. ARM11MPCore
1393 is not affected.
1395 config ARM_ERRATA_764369
1396 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1397 depends on CPU_V7 && SMP
1398 help
1399 This option enables the workaround for erratum 764369
1400 affecting Cortex-A9 MPCore with two or more processors (all
1401 current revisions). Under certain timing circumstances, a data
1402 cache line maintenance operation by MVA targeting an Inner
1403 Shareable memory region may fail to proceed up to either the
1404 Point of Coherency or to the Point of Unification of the
1405 system. This workaround adds a DSB instruction before the
1406 relevant cache maintenance functions and sets a specific bit
1407 in the diagnostic control register of the SCU.
1409 config PL310_ERRATA_769419
1410 bool "PL310 errata: no automatic Store Buffer drain"
1411 depends on CACHE_L2X0
1412 help
1413 On revisions of the PL310 prior to r3p2, the Store Buffer does
1414 not automatically drain. This can cause normal, non-cacheable
1415 writes to be retained when the memory system is idle, leading
1416 to suboptimal I/O performance for drivers using coherent DMA.
1417 This option adds a write barrier to the cpu_idle loop so that,
1418 on systems with an outer cache, the store buffer is drained
1419 explicitly.
1421 config ARM_ERRATA_775420
1422 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1423 depends on CPU_V7
1424 help
1425 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1426 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1427 operation aborts with MMU exception, it might cause the processor
1428 to deadlock. This workaround puts DSB before executing ISB if
1429 an abort may occur on cache maintenance.
1431 endmenu
1433 source "arch/arm/common/Kconfig"
1435 menu "Bus support"
1437 config ARM_AMBA
1438 bool
1440 config ISA
1441 bool
1442 help
1443 Find out whether you have ISA slots on your motherboard. ISA is the
1444 name of a bus system, i.e. the way the CPU talks to the other stuff
1445 inside your box. Other bus systems are PCI, EISA, MicroChannel
1446 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1447 newer boards don't support it. If you have ISA, say Y, otherwise N.
1449 # Select ISA DMA controller support
1450 config ISA_DMA
1451 bool
1452 select ISA_DMA_API
1454 # Select ISA DMA interface
1455 config ISA_DMA_API
1456 bool
1458 config PCI
1459 bool "PCI support" if MIGHT_HAVE_PCI
1460 help
1461 Find out whether you have a PCI motherboard. PCI is the name of a
1462 bus system, i.e. the way the CPU talks to the other stuff inside
1463 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1464 VESA. If you have PCI, say Y, otherwise N.
1466 config PCI_DOMAINS
1467 bool
1468 depends on PCI
1470 config PCI_NANOENGINE
1471 bool "BSE nanoEngine PCI support"
1472 depends on SA1100_NANOENGINE
1473 help
1474 Enable PCI on the BSE nanoEngine board.
1476 config PCI_SYSCALL
1477 def_bool PCI
1479 # Select the host bridge type
1480 config PCI_HOST_VIA82C505
1481 bool
1482 depends on PCI && ARCH_SHARK
1483 default y
1485 config PCI_HOST_ITE8152
1486 bool
1487 depends on PCI && MACH_ARMCORE
1488 default y
1489 select DMABOUNCE
1491 source "drivers/pci/Kconfig"
1493 source "drivers/pcmcia/Kconfig"
1495 endmenu
1497 menu "Kernel Features"
1499 config HAVE_SMP
1500 bool
1501 help
1502 This option should be selected by machines which have an SMP-
1503 capable CPU.
1505 The only effect of this option is to make the SMP-related
1506 options available to the user for configuration.
1508 config SMP
1509 bool "Symmetric Multi-Processing"
1510 depends on CPU_V6K || CPU_V7
1511 depends on GENERIC_CLOCKEVENTS
1512 depends on HAVE_SMP
1513 depends on MMU
1514 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1515 select USE_GENERIC_SMP_HELPERS
1516 help
1517 This enables support for systems with more than one CPU. If you have
1518 a system with only one CPU, like most personal computers, say N. If
1519 you have a system with more than one CPU, say Y.
1521 If you say N here, the kernel will run on single and multiprocessor
1522 machines, but will use only one CPU of a multiprocessor machine. If
1523 you say Y here, the kernel will run on many, but not all, single
1524 processor machines. On a single processor machine, the kernel will
1525 run faster if you say N here.
1527 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1528 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1529 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1531 If you don't know what to do here, say N.
1533 config SMP_ON_UP
1534 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1535 depends on EXPERIMENTAL
1536 depends on SMP && !XIP_KERNEL
1537 default y
1538 help
1539 SMP kernels contain instructions which fail on non-SMP processors.
1540 Enabling this option allows the kernel to modify itself to make
1541 these instructions safe. Disabling it allows about 1K of space
1542 savings.
1544 If you don't know what to do here, say Y.
1546 config ARM_CPU_TOPOLOGY
1547 bool "Support cpu topology definition"
1548 depends on SMP && CPU_V7
1549 default y
1550 help
1551 Support ARM cpu topology definition. The MPIDR register defines
1552 affinity between processors which is then used to describe the cpu
1553 topology of an ARM System.
1555 config SCHED_MC
1556 bool "Multi-core scheduler support"
1557 depends on ARM_CPU_TOPOLOGY
1558 help
1559 Multi-core scheduler support improves the CPU scheduler's decision
1560 making when dealing with multi-core CPU chips at a cost of slightly
1561 increased overhead in some places. If unsure say N here.
1563 config SCHED_SMT
1564 bool "SMT scheduler support"
1565 depends on ARM_CPU_TOPOLOGY
1566 help
1567 Improves the CPU scheduler's decision making when dealing with
1568 MultiThreading at a cost of slightly increased overhead in some
1569 places. If unsure say N here.
1571 config HAVE_ARM_SCU
1572 bool
1573 help
1574 This option enables support for the ARM system coherency unit
1576 config ARM_ARCH_TIMER
1577 bool "Architected timer support"
1578 depends on CPU_V7
1579 help
1580 This option enables support for the ARM architected timer
1582 config HAVE_ARM_TWD
1583 bool
1584 depends on SMP
1585 help
1586 This options enables support for the ARM timer and watchdog unit
1588 choice
1589 prompt "Memory split"
1590 default VMSPLIT_3G
1591 help
1592 Select the desired split between kernel and user memory.
1594 If you are not absolutely sure what you are doing, leave this
1595 option alone!
1597 config VMSPLIT_3G
1598 bool "3G/1G user/kernel split"
1599 config VMSPLIT_2G
1600 bool "2G/2G user/kernel split"
1601 config VMSPLIT_1G
1602 bool "1G/3G user/kernel split"
1603 endchoice
1605 config PAGE_OFFSET
1606 hex
1607 default 0x40000000 if VMSPLIT_1G
1608 default 0x80000000 if VMSPLIT_2G
1609 default 0xC0000000
1611 config NR_CPUS
1612 int "Maximum number of CPUs (2-32)"
1613 range 2 32
1614 depends on SMP
1615 default "4"
1617 config HOTPLUG_CPU
1618 bool "Support for hot-pluggable CPUs"
1619 depends on SMP && HOTPLUG
1620 help
1621 Say Y here to experiment with turning CPUs off and on. CPUs
1622 can be controlled through /sys/devices/system/cpu.
1624 config LOCAL_TIMERS
1625 bool "Use local timer interrupts"
1626 depends on SMP
1627 default y
1628 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1629 help
1630 Enable support for local timers on SMP platforms, rather then the
1631 legacy IPI broadcast method. Local timers allows the system
1632 accounting to be spread across the timer interval, preventing a
1633 "thundering herd" at every timer tick.
1635 config ARCH_NR_GPIO
1636 int
1637 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1638 default 355 if ARCH_U8500
1639 default 264 if MACH_H4700
1640 default 512 if SOC_OMAP5
1641 default 288 if ARCH_VT8500
1642 default 0
1643 help
1644 Maximum number of GPIOs in the system.
1646 If unsure, leave the default value.
1648 source kernel/Kconfig.preempt
1650 config HZ
1651 int
1652 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1653 ARCH_S5PV210 || ARCH_EXYNOS4
1654 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1655 default AT91_TIMER_HZ if ARCH_AT91
1656 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1657 default 100
1659 config THUMB2_KERNEL
1660 bool "Compile the kernel in Thumb-2 mode"
1661 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1662 select AEABI
1663 select ARM_ASM_UNIFIED
1664 select ARM_UNWIND
1665 help
1666 By enabling this option, the kernel will be compiled in
1667 Thumb-2 mode. A compiler/assembler that understand the unified
1668 ARM-Thumb syntax is needed.
1670 If unsure, say N.
1672 config THUMB2_AVOID_R_ARM_THM_JUMP11
1673 bool "Work around buggy Thumb-2 short branch relocations in gas"
1674 depends on THUMB2_KERNEL && MODULES
1675 default y
1676 help
1677 Various binutils versions can resolve Thumb-2 branches to
1678 locally-defined, preemptible global symbols as short-range "b.n"
1679 branch instructions.
1681 This is a problem, because there's no guarantee the final
1682 destination of the symbol, or any candidate locations for a
1683 trampoline, are within range of the branch. For this reason, the
1684 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1685 relocation in modules at all, and it makes little sense to add
1686 support.
1688 The symptom is that the kernel fails with an "unsupported
1689 relocation" error when loading some modules.
1691 Until fixed tools are available, passing
1692 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1693 code which hits this problem, at the cost of a bit of extra runtime
1694 stack usage in some cases.
1696 The problem is described in more detail at:
1697 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1699 Only Thumb-2 kernels are affected.
1701 Unless you are sure your tools don't have this problem, say Y.
1703 config ARM_ASM_UNIFIED
1704 bool
1706 config AEABI
1707 bool "Use the ARM EABI to compile the kernel"
1708 help
1709 This option allows for the kernel to be compiled using the latest
1710 ARM ABI (aka EABI). This is only useful if you are using a user
1711 space environment that is also compiled with EABI.
1713 Since there are major incompatibilities between the legacy ABI and
1714 EABI, especially with regard to structure member alignment, this
1715 option also changes the kernel syscall calling convention to
1716 disambiguate both ABIs and allow for backward compatibility support
1717 (selected with CONFIG_OABI_COMPAT).
1719 To use this you need GCC version 4.0.0 or later.
1721 config OABI_COMPAT
1722 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1723 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1724 default y
1725 help
1726 This option preserves the old syscall interface along with the
1727 new (ARM EABI) one. It also provides a compatibility layer to
1728 intercept syscalls that have structure arguments which layout
1729 in memory differs between the legacy ABI and the new ARM EABI
1730 (only for non "thumb" binaries). This option adds a tiny
1731 overhead to all syscalls and produces a slightly larger kernel.
1732 If you know you'll be using only pure EABI user space then you
1733 can say N here. If this option is not selected and you attempt
1734 to execute a legacy ABI binary then the result will be
1735 UNPREDICTABLE (in fact it can be predicted that it won't work
1736 at all). If in doubt say Y.
1738 config ARCH_HAS_HOLES_MEMORYMODEL
1739 bool
1741 config ARCH_SPARSEMEM_ENABLE
1742 bool
1744 config ARCH_SPARSEMEM_DEFAULT
1745 def_bool ARCH_SPARSEMEM_ENABLE
1747 config ARCH_SELECT_MEMORY_MODEL
1748 def_bool ARCH_SPARSEMEM_ENABLE
1750 config HAVE_ARCH_PFN_VALID
1751 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1753 config HIGHMEM
1754 bool "High Memory Support"
1755 depends on MMU
1756 help
1757 The address space of ARM processors is only 4 Gigabytes large
1758 and it has to accommodate user address space, kernel address
1759 space as well as some memory mapped IO. That means that, if you
1760 have a large amount of physical memory and/or IO, not all of the
1761 memory can be "permanently mapped" by the kernel. The physical
1762 memory that is not permanently mapped is called "high memory".
1764 Depending on the selected kernel/user memory split, minimum
1765 vmalloc space and actual amount of RAM, you may not need this
1766 option which should result in a slightly faster kernel.
1768 If unsure, say n.
1770 config HIGHPTE
1771 bool "Allocate 2nd-level pagetables from highmem"
1772 depends on HIGHMEM
1774 config HW_PERF_EVENTS
1775 bool "Enable hardware performance counter support for perf events"
1776 depends on PERF_EVENTS
1777 default y
1778 help
1779 Enable hardware performance counter support for perf events. If
1780 disabled, perf events will use software events only.
1782 source "mm/Kconfig"
1784 config FORCE_MAX_ZONEORDER
1785 int "Maximum zone order" if ARCH_SHMOBILE
1786 range 11 64 if ARCH_SHMOBILE
1787 default "12" if SOC_AM33XX
1788 default "9" if SA1111
1789 default "11"
1790 help
1791 The kernel memory allocator divides physically contiguous memory
1792 blocks into "zones", where each zone is a power of two number of
1793 pages. This option selects the largest power of two that the kernel
1794 keeps in the memory allocator. If you need to allocate very large
1795 blocks of physically contiguous memory, then you may need to
1796 increase this value.
1798 This config option is actually maximum order plus one. For example,
1799 a value of 11 means that the largest free memory block is 2^10 pages.
1801 config ALIGNMENT_TRAP
1802 bool
1803 depends on CPU_CP15_MMU
1804 default y if !ARCH_EBSA110
1805 select HAVE_PROC_CPU if PROC_FS
1806 help
1807 ARM processors cannot fetch/store information which is not
1808 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1809 address divisible by 4. On 32-bit ARM processors, these non-aligned
1810 fetch/store instructions will be emulated in software if you say
1811 here, which has a severe performance impact. This is necessary for
1812 correct operation of some network protocols. With an IP-only
1813 configuration it is safe to say N, otherwise say Y.
1815 config UACCESS_WITH_MEMCPY
1816 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1817 depends on MMU
1818 default y if CPU_FEROCEON
1819 help
1820 Implement faster copy_to_user and clear_user methods for CPU
1821 cores where a 8-word STM instruction give significantly higher
1822 memory write throughput than a sequence of individual 32bit stores.
1824 A possible side effect is a slight increase in scheduling latency
1825 between threads sharing the same address space if they invoke
1826 such copy operations with large buffers.
1828 However, if the CPU data cache is using a write-allocate mode,
1829 this option is unlikely to provide any performance gain.
1831 config SECCOMP
1832 bool
1833 prompt "Enable seccomp to safely compute untrusted bytecode"
1834 ---help---
1835 This kernel feature is useful for number crunching applications
1836 that may need to compute untrusted bytecode during their
1837 execution. By using pipes or other transports made available to
1838 the process as file descriptors supporting the read/write
1839 syscalls, it's possible to isolate those applications in
1840 their own address space using seccomp. Once seccomp is
1841 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1842 and the task is only allowed to execute a few safe syscalls
1843 defined by each seccomp mode.
1845 config CC_STACKPROTECTOR
1846 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1847 depends on EXPERIMENTAL
1848 help
1849 This option turns on the -fstack-protector GCC feature. This
1850 feature puts, at the beginning of functions, a canary value on
1851 the stack just before the return address, and validates
1852 the value just before actually returning. Stack based buffer
1853 overflows (that need to overwrite this return address) now also
1854 overwrite the canary, which gets detected and the attack is then
1855 neutralized via a kernel panic.
1856 This feature requires gcc version 4.2 or above.
1858 config XEN_DOM0
1859 def_bool y
1860 depends on XEN
1862 config XEN
1863 bool "Xen guest support on ARM (EXPERIMENTAL)"
1864 depends on EXPERIMENTAL && ARM && OF
1865 depends on CPU_V7 && !CPU_V6
1866 help
1867 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1869 config ARM_FLUSH_CONSOLE_ON_RESTART
1870 bool "Force flush the console on restart"
1871 help
1872 If the console is locked while the system is rebooted, the messages
1873 in the temporary logbuffer would not have propogated to all the
1874 console drivers. This option forces the console lock to be
1875 released if it failed to be acquired, which will cause all the
1876 pending messages to be flushed.
1878 endmenu
1880 menu "Boot options"
1882 config USE_OF
1883 bool "Flattened Device Tree support"
1884 select IRQ_DOMAIN
1885 select OF
1886 select OF_EARLY_FLATTREE
1887 help
1888 Include support for flattened device tree machine descriptions.
1890 config ATAGS
1891 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1892 default y
1893 help
1894 This is the traditional way of passing data to the kernel at boot
1895 time. If you are solely relying on the flattened device tree (or
1896 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1897 to remove ATAGS support from your kernel binary. If unsure,
1898 leave this to y.
1900 config DEPRECATED_PARAM_STRUCT
1901 bool "Provide old way to pass kernel parameters"
1902 depends on ATAGS
1903 help
1904 This was deprecated in 2001 and announced to live on for 5 years.
1905 Some old boot loaders still use this way.
1907 # Compressed boot loader in ROM. Yes, we really want to ask about
1908 # TEXT and BSS so we preserve their values in the config files.
1909 config ZBOOT_ROM_TEXT
1910 hex "Compressed ROM boot loader base address"
1911 default "0"
1912 help
1913 The physical address at which the ROM-able zImage is to be
1914 placed in the target. Platforms which normally make use of
1915 ROM-able zImage formats normally set this to a suitable
1916 value in their defconfig file.
1918 If ZBOOT_ROM is not enabled, this has no effect.
1920 config ZBOOT_ROM_BSS
1921 hex "Compressed ROM boot loader BSS address"
1922 default "0"
1923 help
1924 The base address of an area of read/write memory in the target
1925 for the ROM-able zImage which must be available while the
1926 decompressor is running. It must be large enough to hold the
1927 entire decompressed kernel plus an additional 128 KiB.
1928 Platforms which normally make use of ROM-able zImage formats
1929 normally set this to a suitable value in their defconfig file.
1931 If ZBOOT_ROM is not enabled, this has no effect.
1933 config ZBOOT_ROM
1934 bool "Compressed boot loader in ROM/flash"
1935 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1936 help
1937 Say Y here if you intend to execute your compressed kernel image
1938 (zImage) directly from ROM or flash. If unsure, say N.
1940 choice
1941 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1942 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1943 default ZBOOT_ROM_NONE
1944 help
1945 Include experimental SD/MMC loading code in the ROM-able zImage.
1946 With this enabled it is possible to write the ROM-able zImage
1947 kernel image to an MMC or SD card and boot the kernel straight
1948 from the reset vector. At reset the processor Mask ROM will load
1949 the first part of the ROM-able zImage which in turn loads the
1950 rest the kernel image to RAM.
1952 config ZBOOT_ROM_NONE
1953 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1954 help
1955 Do not load image from SD or MMC
1957 config ZBOOT_ROM_MMCIF
1958 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1959 help
1960 Load image from MMCIF hardware block.
1962 config ZBOOT_ROM_SH_MOBILE_SDHI
1963 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1964 help
1965 Load image from SDHI hardware block
1967 endchoice
1969 config ARM_APPENDED_DTB
1970 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1971 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1972 help
1973 With this option, the boot code will look for a device tree binary
1974 (DTB) appended to zImage
1975 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1977 This is meant as a backward compatibility convenience for those
1978 systems with a bootloader that can't be upgraded to accommodate
1979 the documented boot protocol using a device tree.
1981 Beware that there is very little in terms of protection against
1982 this option being confused by leftover garbage in memory that might
1983 look like a DTB header after a reboot if no actual DTB is appended
1984 to zImage. Do not leave this option active in a production kernel
1985 if you don't intend to always append a DTB. Proper passing of the
1986 location into r2 of a bootloader provided DTB is always preferable
1987 to this option.
1989 config ARM_ATAG_DTB_COMPAT
1990 bool "Supplement the appended DTB with traditional ATAG information"
1991 depends on ARM_APPENDED_DTB
1992 help
1993 Some old bootloaders can't be updated to a DTB capable one, yet
1994 they provide ATAGs with memory configuration, the ramdisk address,
1995 the kernel cmdline string, etc. Such information is dynamically
1996 provided by the bootloader and can't always be stored in a static
1997 DTB. To allow a device tree enabled kernel to be used with such
1998 bootloaders, this option allows zImage to extract the information
1999 from the ATAG list and store it at run time into the appended DTB.
2001 choice
2002 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2003 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2005 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2006 bool "Use bootloader kernel arguments if available"
2007 help
2008 Uses the command-line options passed by the boot loader instead of
2009 the device tree bootargs property. If the boot loader doesn't provide
2010 any, the device tree bootargs property will be used.
2012 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2013 bool "Extend with bootloader kernel arguments"
2014 help
2015 The command-line arguments provided by the boot loader will be
2016 appended to the the device tree bootargs property.
2018 endchoice
2020 config CMDLINE
2021 string "Default kernel command string"
2022 default ""
2023 help
2024 On some architectures (EBSA110 and CATS), there is currently no way
2025 for the boot loader to pass arguments to the kernel. For these
2026 architectures, you should supply some command-line options at build
2027 time by entering them here. As a minimum, you should specify the
2028 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2030 choice
2031 prompt "Kernel command line type" if CMDLINE != ""
2032 default CMDLINE_FROM_BOOTLOADER
2033 depends on ATAGS
2035 config CMDLINE_FROM_BOOTLOADER
2036 bool "Use bootloader kernel arguments if available"
2037 help
2038 Uses the command-line options passed by the boot loader. If
2039 the boot loader doesn't provide any, the default kernel command
2040 string provided in CMDLINE will be used.
2042 config CMDLINE_EXTEND
2043 bool "Extend bootloader kernel arguments"
2044 help
2045 The command-line arguments provided by the boot loader will be
2046 appended to the default kernel command string.
2048 config CMDLINE_FORCE
2049 bool "Always use the default kernel command string"
2050 help
2051 Always use the default kernel command string, even if the boot
2052 loader passes other arguments to the kernel.
2053 This is useful if you cannot or don't want to change the
2054 command-line options your boot loader passes to the kernel.
2055 endchoice
2057 config XIP_KERNEL
2058 bool "Kernel Execute-In-Place from ROM"
2059 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2060 help
2061 Execute-In-Place allows the kernel to run from non-volatile storage
2062 directly addressable by the CPU, such as NOR flash. This saves RAM
2063 space since the text section of the kernel is not loaded from flash
2064 to RAM. Read-write sections, such as the data section and stack,
2065 are still copied to RAM. The XIP kernel is not compressed since
2066 it has to run directly from flash, so it will take more space to
2067 store it. The flash address used to link the kernel object files,
2068 and for storing it, is configuration dependent. Therefore, if you
2069 say Y here, you must know the proper physical address where to
2070 store the kernel image depending on your own flash memory usage.
2072 Also note that the make target becomes "make xipImage" rather than
2073 "make zImage" or "make Image". The final kernel binary to put in
2074 ROM memory will be arch/arm/boot/xipImage.
2076 If unsure, say N.
2078 config XIP_PHYS_ADDR
2079 hex "XIP Kernel Physical Location"
2080 depends on XIP_KERNEL
2081 default "0x00080000"
2082 help
2083 This is the physical address in your flash memory the kernel will
2084 be linked for and stored to. This address is dependent on your
2085 own flash usage.
2087 config KEXEC
2088 bool "Kexec system call (EXPERIMENTAL)"
2089 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2090 help
2091 kexec is a system call that implements the ability to shutdown your
2092 current kernel, and to start another kernel. It is like a reboot
2093 but it is independent of the system firmware. And like a reboot
2094 you can start any kernel with it, not just Linux.
2096 It is an ongoing process to be certain the hardware in a machine
2097 is properly shutdown, so do not be surprised if this code does not
2098 initially work for you. It may help to enable device hotplugging
2099 support.
2101 config ATAGS_PROC
2102 bool "Export atags in procfs"
2103 depends on ATAGS && KEXEC
2104 default y
2105 help
2106 Should the atags used to boot the kernel be exported in an "atags"
2107 file in procfs. Useful with kexec.
2109 config CRASH_DUMP
2110 bool "Build kdump crash kernel (EXPERIMENTAL)"
2111 depends on EXPERIMENTAL
2112 help
2113 Generate crash dump after being started by kexec. This should
2114 be normally only set in special crash dump kernels which are
2115 loaded in the main kernel with kexec-tools into a specially
2116 reserved region and then later executed after a crash by
2117 kdump/kexec. The crash dump kernel must be compiled to a
2118 memory address not used by the main kernel
2120 For more details see Documentation/kdump/kdump.txt
2122 config AUTO_ZRELADDR
2123 bool "Auto calculation of the decompressed kernel image address"
2124 depends on !ZBOOT_ROM && !ARCH_U300
2125 help
2126 ZRELADDR is the physical address where the decompressed kernel
2127 image will be placed. If AUTO_ZRELADDR is selected, the address
2128 will be determined at run-time by masking the current IP with
2129 0xf8000000. This assumes the zImage being placed in the first 128MB
2130 from start of memory.
2132 endmenu
2134 menu "CPU Power Management"
2136 if ARCH_HAS_CPUFREQ
2138 source "drivers/cpufreq/Kconfig"
2140 config CPU_FREQ_IMX
2141 tristate "CPUfreq driver for i.MX CPUs"
2142 depends on ARCH_MXC && CPU_FREQ
2143 select CPU_FREQ_TABLE
2144 help
2145 This enables the CPUfreq driver for i.MX CPUs.
2147 config CPU_FREQ_SA1100
2148 bool
2150 config CPU_FREQ_SA1110
2151 bool
2153 config CPU_FREQ_INTEGRATOR
2154 tristate "CPUfreq driver for ARM Integrator CPUs"
2155 depends on ARCH_INTEGRATOR && CPU_FREQ
2156 default y
2157 help
2158 This enables the CPUfreq driver for ARM Integrator CPUs.
2160 For details, take a look at <file:Documentation/cpu-freq>.
2162 If in doubt, say Y.
2164 config CPU_FREQ_PXA
2165 bool
2166 depends on CPU_FREQ && ARCH_PXA && PXA25x
2167 default y
2168 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2169 select CPU_FREQ_TABLE
2171 config CPU_FREQ_S3C
2172 bool
2173 help
2174 Internal configuration node for common cpufreq on Samsung SoC
2176 config CPU_FREQ_S3C24XX
2177 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2178 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2179 select CPU_FREQ_S3C
2180 help
2181 This enables the CPUfreq driver for the Samsung S3C24XX family
2182 of CPUs.
2184 For details, take a look at <file:Documentation/cpu-freq>.
2186 If in doubt, say N.
2188 config CPU_FREQ_S3C24XX_PLL
2189 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2190 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2191 help
2192 Compile in support for changing the PLL frequency from the
2193 S3C24XX series CPUfreq driver. The PLL takes time to settle
2194 after a frequency change, so by default it is not enabled.
2196 This also means that the PLL tables for the selected CPU(s) will
2197 be built which may increase the size of the kernel image.
2199 config CPU_FREQ_S3C24XX_DEBUG
2200 bool "Debug CPUfreq Samsung driver core"
2201 depends on CPU_FREQ_S3C24XX
2202 help
2203 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2205 config CPU_FREQ_S3C24XX_IODEBUG
2206 bool "Debug CPUfreq Samsung driver IO timing"
2207 depends on CPU_FREQ_S3C24XX
2208 help
2209 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2211 config CPU_FREQ_S3C24XX_DEBUGFS
2212 bool "Export debugfs for CPUFreq"
2213 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2214 help
2215 Export status information via debugfs.
2217 endif
2219 source "drivers/cpuidle/Kconfig"
2221 endmenu
2223 menu "Floating point emulation"
2225 comment "At least one emulation must be selected"
2227 config FPE_NWFPE
2228 bool "NWFPE math emulation"
2229 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2230 ---help---
2231 Say Y to include the NWFPE floating point emulator in the kernel.
2232 This is necessary to run most binaries. Linux does not currently
2233 support floating point hardware so you need to say Y here even if
2234 your machine has an FPA or floating point co-processor podule.
2236 You may say N here if you are going to load the Acorn FPEmulator
2237 early in the bootup.
2239 config FPE_NWFPE_XP
2240 bool "Support extended precision"
2241 depends on FPE_NWFPE
2242 help
2243 Say Y to include 80-bit support in the kernel floating-point
2244 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2245 Note that gcc does not generate 80-bit operations by default,
2246 so in most cases this option only enlarges the size of the
2247 floating point emulator without any good reason.
2249 You almost surely want to say N here.
2251 config FPE_FASTFPE
2252 bool "FastFPE math emulation (EXPERIMENTAL)"
2253 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2254 ---help---
2255 Say Y here to include the FAST floating point emulator in the kernel.
2256 This is an experimental much faster emulator which now also has full
2257 precision for the mantissa. It does not support any exceptions.
2258 It is very simple, and approximately 3-6 times faster than NWFPE.
2260 It should be sufficient for most programs. It may be not suitable
2261 for scientific calculations, but you have to check this for yourself.
2262 If you do not feel you need a faster FP emulation you should better
2263 choose NWFPE.
2265 config VFP
2266 bool "VFP-format floating point maths"
2267 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2268 help
2269 Say Y to include VFP support code in the kernel. This is needed
2270 if your hardware includes a VFP unit.
2272 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2273 release notes and additional status information.
2275 Say N if your target does not have VFP hardware.
2277 config VFPv3
2278 bool
2279 depends on VFP
2280 default y if CPU_V7
2282 config NEON
2283 bool "Advanced SIMD (NEON) Extension support"
2284 depends on VFPv3 && CPU_V7
2285 help
2286 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2287 Extension.
2289 endmenu
2291 menu "Userspace binary formats"
2293 source "fs/Kconfig.binfmt"
2295 config ARTHUR
2296 tristate "RISC OS personality"
2297 depends on !AEABI
2298 help
2299 Say Y here to include the kernel code necessary if you want to run
2300 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2301 experimental; if this sounds frightening, say N and sleep in peace.
2302 You can also say M here to compile this support as a module (which
2303 will be called arthur).
2305 endmenu
2307 menu "Power management options"
2309 source "kernel/power/Kconfig"
2311 config ARCH_SUSPEND_POSSIBLE
2312 depends on !ARCH_S5PC100
2313 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2314 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2315 def_bool y
2317 config ARM_CPU_SUSPEND
2318 def_bool PM_SLEEP
2320 endmenu
2322 source "net/Kconfig"
2324 source "drivers/Kconfig"
2326 source "fs/Kconfig"
2328 source "arch/arm/Kconfig.debug"
2330 source "security/Kconfig"
2332 source "crypto/Kconfig"
2334 source "lib/Kconfig"