1 /*
2 * linux/arch/arm/boot/compressed/head.S
3 *
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/linkage.h>
12 #include <asm/assembler.h>
14 /*
15 * Debugging stuff
16 *
17 * Note that these macros must not contain any code which is not
18 * 100% relocatable. Any attempt to do so will result in a crash.
19 * Please select one of the following when turning on debugging.
20 */
21 #ifdef DEBUG
23 #if defined(CONFIG_DEBUG_ICEDCC)
25 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
26 .macro loadsp, rb, tmp
27 .endm
28 .macro writeb, ch, rb
29 mcr p14, 0, \ch, c0, c5, 0
30 .endm
31 #elif defined(CONFIG_CPU_XSCALE)
32 .macro loadsp, rb, tmp
33 .endm
34 .macro writeb, ch, rb
35 mcr p14, 0, \ch, c8, c0, 0
36 .endm
37 #else
38 .macro loadsp, rb, tmp
39 .endm
40 .macro writeb, ch, rb
41 mcr p14, 0, \ch, c1, c0, 0
42 .endm
43 #endif
45 #else
47 #include CONFIG_DEBUG_LL_INCLUDE
49 .macro writeb, ch, rb
50 senduart \ch, \rb
51 .endm
53 #if defined(CONFIG_ARCH_SA1100)
54 .macro loadsp, rb, tmp
55 mov \rb, #0x80000000 @ physical base address
56 #ifdef CONFIG_DEBUG_LL_SER3
57 add \rb, \rb, #0x00050000 @ Ser3
58 #else
59 add \rb, \rb, #0x00010000 @ Ser1
60 #endif
61 .endm
62 #elif defined(CONFIG_ARCH_S3C24XX)
63 .macro loadsp, rb, tmp
64 mov \rb, #0x50000000
65 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
66 .endm
67 #else
68 .macro loadsp, rb, tmp
69 addruart \rb, \tmp
70 .endm
71 #endif
72 #endif
73 #endif
75 .macro kputc,val
76 mov r0, \val
77 bl putc
78 .endm
80 .macro kphex,val,len
81 mov r0, \val
82 mov r1, #\len
83 bl phex
84 .endm
86 .macro debug_reloc_start
87 #ifdef DEBUG
88 kputc #'\n'
89 kphex r6, 8 /* processor id */
90 kputc #':'
91 kphex r7, 8 /* architecture id */
92 #ifdef CONFIG_CPU_CP15
93 kputc #':'
94 mrc p15, 0, r0, c1, c0
95 kphex r0, 8 /* control reg */
96 #endif
97 kputc #'\n'
98 kphex r5, 8 /* decompressed kernel start */
99 kputc #'-'
100 kphex r9, 8 /* decompressed kernel end */
101 kputc #'>'
102 kphex r4, 8 /* kernel execution address */
103 kputc #'\n'
104 #endif
105 .endm
107 .macro debug_reloc_end
108 #ifdef DEBUG
109 kphex r5, 8 /* end of kernel */
110 kputc #'\n'
111 mov r0, r4
112 bl memdump /* dump 256 bytes at start of kernel */
113 #endif
114 .endm
116 .section ".start", #alloc, #execinstr
117 /*
118 * sort out different calling conventions
119 */
120 .align
121 .arm @ Always enter in ARM state
122 start:
123 .type start,#function
124 .rept 7
125 mov r0, r0
126 .endr
127 ARM( mov r0, r0 )
128 ARM( b 1f )
129 THUMB( adr r12, BSYM(1f) )
130 THUMB( bx r12 )
132 .word 0x016f2818 @ Magic numbers to help the loader
133 .word start @ absolute load/run zImage address
134 .word _edata @ zImage end address
135 THUMB( .thumb )
136 1:
137 mrs r9, cpsr
138 #ifdef CONFIG_ARM_VIRT_EXT
139 bl __hyp_stub_install @ get into SVC mode, reversibly
140 #endif
141 mov r7, r1 @ save architecture ID
142 mov r8, r2 @ save atags pointer
144 #ifndef __ARM_ARCH_2__
145 /*
146 * Booting from Angel - need to enter SVC mode and disable
147 * FIQs/IRQs (numeric definitions from angel arm.h source).
148 * We only do this if we were in user mode on entry.
149 */
150 mrs r2, cpsr @ get current mode
151 tst r2, #3 @ not user?
152 bne not_angel
153 mov r0, #0x17 @ angel_SWIreason_EnterSVC
154 ARM( swi 0x123456 ) @ angel_SWI_ARM
155 THUMB( svc 0xab ) @ angel_SWI_THUMB
156 not_angel:
157 safe_svcmode_maskall r0
158 msr spsr_cxsf, r9 @ Save the CPU boot mode in
159 @ SPSR
160 #else
161 teqp pc, #0x0c000003 @ turn off interrupts
162 #endif
164 /*
165 * Note that some cache flushing and other stuff may
166 * be needed here - is there an Angel SWI call for this?
167 */
169 /*
170 * some architecture specific code can be inserted
171 * by the linker here, but it should preserve r7, r8, and r9.
172 */
174 .text
176 #ifdef CONFIG_AUTO_ZRELADDR
177 @ determine final kernel image address
178 mov r4, pc
179 and r4, r4, #0xf8000000
180 add r4, r4, #TEXT_OFFSET
181 #else
182 ldr r4, =zreladdr
183 #endif
185 bl cache_on
187 restart: adr r0, LC0
188 ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
189 ldr sp, [r0, #28]
191 /*
192 * We might be running at a different address. We need
193 * to fix up various pointers.
194 */
195 sub r0, r0, r1 @ calculate the delta offset
196 add r6, r6, r0 @ _edata
197 add r10, r10, r0 @ inflated kernel size location
199 /*
200 * The kernel build system appends the size of the
201 * decompressed kernel at the end of the compressed data
202 * in little-endian form.
203 */
204 ldrb r9, [r10, #0]
205 ldrb lr, [r10, #1]
206 orr r9, r9, lr, lsl #8
207 ldrb lr, [r10, #2]
208 ldrb r10, [r10, #3]
209 orr r9, r9, lr, lsl #16
210 orr r9, r9, r10, lsl #24
212 #ifndef CONFIG_ZBOOT_ROM
213 /* malloc space is above the relocated stack (64k max) */
214 add sp, sp, r0
215 add r10, sp, #0x10000
216 #else
217 /*
218 * With ZBOOT_ROM the bss/stack is non relocatable,
219 * but someone could still run this code from RAM,
220 * in which case our reference is _edata.
221 */
222 mov r10, r6
223 #endif
225 mov r5, #0 @ init dtb size to 0
226 #ifdef CONFIG_ARM_APPENDED_DTB
227 /*
228 * r0 = delta
229 * r2 = BSS start
230 * r3 = BSS end
231 * r4 = final kernel address
232 * r5 = appended dtb size (still unknown)
233 * r6 = _edata
234 * r7 = architecture ID
235 * r8 = atags/device tree pointer
236 * r9 = size of decompressed image
237 * r10 = end of this image, including bss/stack/malloc space if non XIP
238 * r11 = GOT start
239 * r12 = GOT end
240 * sp = stack pointer
241 *
242 * if there are device trees (dtb) appended to zImage, advance r10 so that the
243 * dtb data will get relocated along with the kernel if necessary.
244 */
246 ldr lr, [r6, #0]
247 #ifndef __ARMEB__
248 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
249 #else
250 ldr r1, =0xd00dfeed
251 #endif
252 cmp lr, r1
253 bne dtb_check_done @ not found
255 #ifdef CONFIG_ARM_ATAG_DTB_COMPAT
256 /*
257 * OK... Let's do some funky business here.
258 * If we do have a DTB appended to zImage, and we do have
259 * an ATAG list around, we want the later to be translated
260 * and folded into the former here. To be on the safe side,
261 * let's temporarily move the stack away into the malloc
262 * area. No GOT fixup has occurred yet, but none of the
263 * code we're about to call uses any global variable.
264 */
265 add sp, sp, #0x10000
266 stmfd sp!, {r0-r3, ip, lr}
267 mov r0, r8
268 mov r1, r6
269 sub r2, sp, r6
270 bl atags_to_fdt
272 /*
273 * If returned value is 1, there is no ATAG at the location
274 * pointed by r8. Try the typical 0x100 offset from start
275 * of RAM and hope for the best.
276 */
277 cmp r0, #1
278 sub r0, r4, #TEXT_OFFSET
279 add r0, r0, #0x100
280 mov r1, r6
281 sub r2, sp, r6
282 bleq atags_to_fdt
284 ldmfd sp!, {r0-r3, ip, lr}
285 sub sp, sp, #0x10000
286 #endif
288 mov r8, r6 @ use the appended device tree
290 /*
291 * Make sure that the DTB doesn't end up in the final
292 * kernel's .bss area. To do so, we adjust the decompressed
293 * kernel size to compensate if that .bss size is larger
294 * than the relocated code.
295 */
296 ldr r5, =_kernel_bss_size
297 adr r1, wont_overwrite
298 sub r1, r6, r1
299 subs r1, r5, r1
300 addhi r9, r9, r1
302 /* Get the dtb's size */
303 ldr r5, [r6, #4]
304 #ifndef __ARMEB__
305 /* convert r5 (dtb size) to little endian */
306 eor r1, r5, r5, ror #16
307 bic r1, r1, #0x00ff0000
308 mov r5, r5, ror #8
309 eor r5, r5, r1, lsr #8
310 #endif
312 /* preserve 64-bit alignment */
313 add r5, r5, #7
314 bic r5, r5, #7
316 /* relocate some pointers past the appended dtb */
317 add r6, r6, r5
318 add r10, r10, r5
319 add sp, sp, r5
320 dtb_check_done:
321 #endif
323 /*
324 * Check to see if we will overwrite ourselves.
325 * r4 = final kernel address
326 * r9 = size of decompressed image
327 * r10 = end of this image, including bss/stack/malloc space if non XIP
328 * We basically want:
329 * r4 - 16k page directory >= r10 -> OK
330 * r4 + image length <= address of wont_overwrite -> OK
331 */
332 add r10, r10, #16384
333 cmp r4, r10
334 bhs wont_overwrite
335 add r10, r4, r9
336 adr r9, wont_overwrite
337 cmp r10, r9
338 bls wont_overwrite
340 /*
341 * Relocate ourselves past the end of the decompressed kernel.
342 * r6 = _edata
343 * r10 = end of the decompressed kernel
344 * Because we always copy ahead, we need to do it from the end and go
345 * backward in case the source and destination overlap.
346 */
347 /*
348 * Bump to the next 256-byte boundary with the size of
349 * the relocation code added. This avoids overwriting
350 * ourself when the offset is small.
351 */
352 add r10, r10, #((reloc_code_end - restart + 256) & ~255)
353 bic r10, r10, #255
355 /* Get start of code we want to copy and align it down. */
356 adr r5, restart
357 bic r5, r5, #31
359 /* Relocate the hyp vector base if necessary */
360 #ifdef CONFIG_ARM_VIRT_EXT
361 mrs r0, spsr
362 and r0, r0, #MODE_MASK
363 cmp r0, #HYP_MODE
364 bne 1f
366 bl __hyp_get_vectors
367 sub r0, r0, r5
368 add r0, r0, r10
369 bl __hyp_set_vectors
370 1:
371 #endif
373 sub r9, r6, r5 @ size to copy
374 add r9, r9, #31 @ rounded up to a multiple
375 bic r9, r9, #31 @ ... of 32 bytes
376 add r6, r9, r5
377 add r9, r9, r10
379 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
380 cmp r6, r5
381 stmdb r9!, {r0 - r3, r10 - r12, lr}
382 bhi 1b
384 /* Preserve offset to relocated code. */
385 sub r6, r9, r6
387 #ifndef CONFIG_ZBOOT_ROM
388 /* cache_clean_flush may use the stack, so relocate it */
389 add sp, sp, r6
390 #endif
392 bl cache_clean_flush
394 adr r0, BSYM(restart)
395 add r0, r0, r6
396 mov pc, r0
398 wont_overwrite:
399 /*
400 * If delta is zero, we are running at the address we were linked at.
401 * r0 = delta
402 * r2 = BSS start
403 * r3 = BSS end
404 * r4 = kernel execution address
405 * r5 = appended dtb size (0 if not present)
406 * r7 = architecture ID
407 * r8 = atags pointer
408 * r11 = GOT start
409 * r12 = GOT end
410 * sp = stack pointer
411 */
412 orrs r1, r0, r5
413 beq not_relocated
415 add r11, r11, r0
416 add r12, r12, r0
418 #ifndef CONFIG_ZBOOT_ROM
419 /*
420 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
421 * we need to fix up pointers into the BSS region.
422 * Note that the stack pointer has already been fixed up.
423 */
424 add r2, r2, r0
425 add r3, r3, r0
427 /*
428 * Relocate all entries in the GOT table.
429 * Bump bss entries to _edata + dtb size
430 */
431 1: ldr r1, [r11, #0] @ relocate entries in the GOT
432 add r1, r1, r0 @ This fixes up C references
433 cmp r1, r2 @ if entry >= bss_start &&
434 cmphs r3, r1 @ bss_end > entry
435 addhi r1, r1, r5 @ entry += dtb size
436 str r1, [r11], #4 @ next entry
437 cmp r11, r12
438 blo 1b
440 /* bump our bss pointers too */
441 add r2, r2, r5
442 add r3, r3, r5
444 #else
446 /*
447 * Relocate entries in the GOT table. We only relocate
448 * the entries that are outside the (relocated) BSS region.
449 */
450 1: ldr r1, [r11, #0] @ relocate entries in the GOT
451 cmp r1, r2 @ entry < bss_start ||
452 cmphs r3, r1 @ _end < entry
453 addlo r1, r1, r0 @ table. This fixes up the
454 str r1, [r11], #4 @ C references.
455 cmp r11, r12
456 blo 1b
457 #endif
459 not_relocated: mov r0, #0
460 1: str r0, [r2], #4 @ clear bss
461 str r0, [r2], #4
462 str r0, [r2], #4
463 str r0, [r2], #4
464 cmp r2, r3
465 blo 1b
467 /*
468 * The C runtime environment should now be setup sufficiently.
469 * Set up some pointers, and start decompressing.
470 * r4 = kernel execution address
471 * r7 = architecture ID
472 * r8 = atags pointer
473 */
474 mov r0, r4
475 mov r1, sp @ malloc space above stack
476 add r2, sp, #0x10000 @ 64k max
477 mov r3, r7
478 bl decompress_kernel
479 bl cache_clean_flush
480 bl cache_off
481 mov r1, r7 @ restore architecture number
482 mov r2, r8 @ restore atags pointer
484 #ifdef CONFIG_ARM_VIRT_EXT
485 mrs r0, spsr @ Get saved CPU boot mode
486 and r0, r0, #MODE_MASK
487 cmp r0, #HYP_MODE @ if not booted in HYP mode...
488 bne __enter_kernel @ boot kernel directly
490 adr r12, .L__hyp_reentry_vectors_offset
491 ldr r0, [r12]
492 add r0, r0, r12
494 bl __hyp_set_vectors
495 __HVC(0) @ otherwise bounce to hyp mode
497 b . @ should never be reached
499 .align 2
500 .L__hyp_reentry_vectors_offset: .long __hyp_reentry_vectors - .
501 #else
502 b __enter_kernel
503 #endif
505 .align 2
506 .type LC0, #object
507 LC0: .word LC0 @ r1
508 .word __bss_start @ r2
509 .word _end @ r3
510 .word _edata @ r6
511 .word input_data_end - 4 @ r10 (inflated size location)
512 .word _got_start @ r11
513 .word _got_end @ ip
514 .word .L_user_stack_end @ sp
515 .size LC0, . - LC0
517 #ifdef CONFIG_ARCH_RPC
518 .globl params
519 params: ldr r0, =0x10000100 @ params_phys for RPC
520 mov pc, lr
521 .ltorg
522 .align
523 #endif
525 /*
526 * Turn on the cache. We need to setup some page tables so that we
527 * can have both the I and D caches on.
528 *
529 * We place the page tables 16k down from the kernel execution address,
530 * and we hope that nothing else is using it. If we're using it, we
531 * will go pop!
532 *
533 * On entry,
534 * r4 = kernel execution address
535 * r7 = architecture number
536 * r8 = atags pointer
537 * On exit,
538 * r0, r1, r2, r3, r9, r10, r12 corrupted
539 * This routine must preserve:
540 * r4, r7, r8
541 */
542 .align 5
543 cache_on: mov r3, #8 @ cache_on function
544 b call_cache_fn
546 /*
547 * Initialize the highest priority protection region, PR7
548 * to cover all 32bit address and cacheable and bufferable.
549 */
550 __armv4_mpu_cache_on:
551 .arch armv4
552 mov r0, #0x3f @ 4G, the whole
553 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
554 mcr p15, 0, r0, c6, c7, 1
556 mov r0, #0x80 @ PR7
557 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
558 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
559 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
561 mov r0, #0xc000
562 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
563 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
565 mov r0, #0
566 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
567 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
568 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
569 mrc p15, 0, r0, c1, c0, 0 @ read control reg
570 @ ...I .... ..D. WC.M
571 orr r0, r0, #0x002d @ .... .... ..1. 11.1
572 orr r0, r0, #0x1000 @ ...1 .... .... ....
574 mcr p15, 0, r0, c1, c0, 0 @ write control reg
576 mov r0, #0
577 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
578 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
579 mov pc, lr
581 __armv3_mpu_cache_on:
582 mov r0, #0x3f @ 4G, the whole
583 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
585 mov r0, #0x80 @ PR7
586 mcr p15, 0, r0, c2, c0, 0 @ cache on
587 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
589 mov r0, #0xc000
590 mcr p15, 0, r0, c5, c0, 0 @ access permission
592 mov r0, #0
593 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
594 /*
595 * ?? ARMv3 MMU does not allow reading the control register,
596 * does this really work on ARMv3 MPU?
597 */
598 mrc p15, 0, r0, c1, c0, 0 @ read control reg
599 @ .... .... .... WC.M
600 orr r0, r0, #0x000d @ .... .... .... 11.1
601 /* ?? this overwrites the value constructed above? */
602 mov r0, #0
603 mcr p15, 0, r0, c1, c0, 0 @ write control reg
605 /* ?? invalidate for the second time? */
606 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
607 mov pc, lr
609 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
610 #define CB_BITS 0x08
611 #else
612 #define CB_BITS 0x0c
613 #endif
615 __setup_mmu: sub r3, r4, #16384 @ Page directory size
616 bic r3, r3, #0xff @ Align the pointer
617 bic r3, r3, #0x3f00
618 /*
619 * Initialise the page tables, turning on the cacheable and bufferable
620 * bits for the RAM area only.
621 */
622 mov r0, r3
623 mov r9, r0, lsr #18
624 mov r9, r9, lsl #18 @ start of RAM
625 add r10, r9, #0x10000000 @ a reasonable RAM size
626 mov r1, #0x12 @ XN|U + section mapping
627 orr r1, r1, #3 << 10 @ AP=11
628 add r2, r3, #16384
629 1: cmp r1, r9 @ if virt > start of RAM
630 cmphs r10, r1 @ && end of RAM > virt
631 bic r1, r1, #0x1c @ clear XN|U + C + B
632 orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
633 orrhs r1, r1, r6 @ set RAM section settings
634 str r1, [r0], #4 @ 1:1 mapping
635 add r1, r1, #1048576
636 teq r0, r2
637 bne 1b
638 /*
639 * If ever we are running from Flash, then we surely want the cache
640 * to be enabled also for our execution instance... We map 2MB of it
641 * so there is no map overlap problem for up to 1 MB compressed kernel.
642 * If the execution is in RAM then we would only be duplicating the above.
643 */
644 orr r1, r6, #0x04 @ ensure B is set for this
645 orr r1, r1, #3 << 10
646 mov r2, pc
647 mov r2, r2, lsr #20
648 orr r1, r1, r2, lsl #20
649 add r0, r3, r2, lsl #2
650 str r1, [r0], #4
651 add r1, r1, #1048576
652 str r1, [r0]
653 mov pc, lr
654 ENDPROC(__setup_mmu)
656 @ Enable unaligned access on v6, to allow better code generation
657 @ for the decompressor C code:
658 __armv6_mmu_cache_on:
659 .arch armv6
660 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
661 bic r0, r0, #2 @ A (no unaligned access fault)
662 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
663 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
664 b __armv4_mmu_cache_on
666 __arm926ejs_mmu_cache_on:
667 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
668 .arch armv5
669 mov r0, #4 @ put dcache in WT mode
670 mcr p15, 7, r0, c15, c0, 0
671 #endif
673 __armv4_mmu_cache_on:
674 .arch armv4
675 mov r12, lr
676 #ifdef CONFIG_MMU
677 mov r6, #CB_BITS | 0x12 @ U
678 bl __setup_mmu
679 mov r0, #0
680 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
681 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
682 mrc p15, 0, r0, c1, c0, 0 @ read control reg
683 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
684 orr r0, r0, #0x0030
685 #ifdef CONFIG_CPU_ENDIAN_BE8
686 orr r0, r0, #1 << 25 @ big-endian page tables
687 #endif
688 bl __common_mmu_cache_on
689 mov r0, #0
690 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
691 #endif
692 mov pc, r12
694 __armv7_mmu_cache_on:
695 .arch armv7-a
696 mov r12, lr
697 #ifdef CONFIG_MMU
698 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
699 tst r11, #0xf @ VMSA
700 movne r6, #CB_BITS | 0x02 @ !XN
701 blne __setup_mmu
702 mov r0, #0
703 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
704 tst r11, #0xf @ VMSA
705 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
706 #endif
707 mrc p15, 0, r0, c1, c0, 0 @ read control reg
708 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
709 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
710 orr r0, r0, #0x003c @ write buffer
711 bic r0, r0, #2 @ A (no unaligned access fault)
712 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
713 @ (needed for ARM1176)
714 #ifdef CONFIG_MMU
715 #ifdef CONFIG_CPU_ENDIAN_BE8
716 orr r0, r0, #1 << 25 @ big-endian page tables
717 #endif
718 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
719 orrne r0, r0, #1 @ MMU enabled
720 movne r1, #0xfffffffd @ domain 0 = client
721 bic r6, r6, #1 << 31 @ 32-bit translation system
722 bic r6, r6, #3 << 0 @ use only ttbr0
723 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
724 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
725 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
726 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
727 #endif
728 mcr p15, 0, r0, c7, c5, 4 @ ISB
729 mcr p15, 0, r0, c1, c0, 0 @ load control register
730 mrc p15, 0, r0, c1, c0, 0 @ and read it back
731 mov r0, #0
732 mcr p15, 0, r0, c7, c5, 4 @ ISB
733 mov pc, r12
735 __fa526_cache_on:
736 mov r12, lr
737 mov r6, #CB_BITS | 0x12 @ U
738 bl __setup_mmu
739 mov r0, #0
740 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
741 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
742 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
743 mrc p15, 0, r0, c1, c0, 0 @ read control reg
744 orr r0, r0, #0x1000 @ I-cache enable
745 bl __common_mmu_cache_on
746 mov r0, #0
747 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
748 mov pc, r12
750 __common_mmu_cache_on:
751 #ifndef CONFIG_THUMB2_KERNEL
752 #ifndef DEBUG
753 orr r0, r0, #0x000d @ Write buffer, mmu
754 #endif
755 mov r1, #-1
756 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
757 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
758 b 1f
759 .align 5 @ cache line aligned
760 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
761 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
762 sub pc, lr, r0, lsr #32 @ properly flush pipeline
763 #endif
765 #define PROC_ENTRY_SIZE (4*5)
767 /*
768 * Here follow the relocatable cache support functions for the
769 * various processors. This is a generic hook for locating an
770 * entry and jumping to an instruction at the specified offset
771 * from the start of the block. Please note this is all position
772 * independent code.
773 *
774 * r1 = corrupted
775 * r2 = corrupted
776 * r3 = block offset
777 * r9 = corrupted
778 * r12 = corrupted
779 */
781 call_cache_fn: adr r12, proc_types
782 #ifdef CONFIG_CPU_CP15
783 mrc p15, 0, r9, c0, c0 @ get processor ID
784 #else
785 ldr r9, =CONFIG_PROCESSOR_ID
786 #endif
787 1: ldr r1, [r12, #0] @ get value
788 ldr r2, [r12, #4] @ get mask
789 eor r1, r1, r9 @ (real ^ match)
790 tst r1, r2 @ & mask
791 ARM( addeq pc, r12, r3 ) @ call cache function
792 THUMB( addeq r12, r3 )
793 THUMB( moveq pc, r12 ) @ call cache function
794 add r12, r12, #PROC_ENTRY_SIZE
795 b 1b
797 /*
798 * Table for cache operations. This is basically:
799 * - CPU ID match
800 * - CPU ID mask
801 * - 'cache on' method instruction
802 * - 'cache off' method instruction
803 * - 'cache flush' method instruction
804 *
805 * We match an entry using: ((real_id ^ match) & mask) == 0
806 *
807 * Writethrough caches generally only need 'on' and 'off'
808 * methods. Writeback caches _must_ have the flush method
809 * defined.
810 */
811 .align 2
812 .type proc_types,#object
813 proc_types:
814 #if !defined(CONFIG_CPU_V7)
815 /* This collides with some V7 IDs, preventing correct detection */
816 .word 0x00000000 @ old ARM ID
817 .word 0x0000f000
818 mov pc, lr
819 THUMB( nop )
820 mov pc, lr
821 THUMB( nop )
822 mov pc, lr
823 THUMB( nop )
824 #endif
826 .word 0x41007000 @ ARM7/710
827 .word 0xfff8fe00
828 mov pc, lr
829 THUMB( nop )
830 mov pc, lr
831 THUMB( nop )
832 mov pc, lr
833 THUMB( nop )
835 .word 0x41807200 @ ARM720T (writethrough)
836 .word 0xffffff00
837 W(b) __armv4_mmu_cache_on
838 W(b) __armv4_mmu_cache_off
839 mov pc, lr
840 THUMB( nop )
842 .word 0x41007400 @ ARM74x
843 .word 0xff00ff00
844 W(b) __armv3_mpu_cache_on
845 W(b) __armv3_mpu_cache_off
846 W(b) __armv3_mpu_cache_flush
848 .word 0x41009400 @ ARM94x
849 .word 0xff00ff00
850 W(b) __armv4_mpu_cache_on
851 W(b) __armv4_mpu_cache_off
852 W(b) __armv4_mpu_cache_flush
854 .word 0x41069260 @ ARM926EJ-S (v5TEJ)
855 .word 0xff0ffff0
856 W(b) __arm926ejs_mmu_cache_on
857 W(b) __armv4_mmu_cache_off
858 W(b) __armv5tej_mmu_cache_flush
860 .word 0x00007000 @ ARM7 IDs
861 .word 0x0000f000
862 mov pc, lr
863 THUMB( nop )
864 mov pc, lr
865 THUMB( nop )
866 mov pc, lr
867 THUMB( nop )
869 @ Everything from here on will be the new ID system.
871 .word 0x4401a100 @ sa110 / sa1100
872 .word 0xffffffe0
873 W(b) __armv4_mmu_cache_on
874 W(b) __armv4_mmu_cache_off
875 W(b) __armv4_mmu_cache_flush
877 .word 0x6901b110 @ sa1110
878 .word 0xfffffff0
879 W(b) __armv4_mmu_cache_on
880 W(b) __armv4_mmu_cache_off
881 W(b) __armv4_mmu_cache_flush
883 .word 0x56056900
884 .word 0xffffff00 @ PXA9xx
885 W(b) __armv4_mmu_cache_on
886 W(b) __armv4_mmu_cache_off
887 W(b) __armv4_mmu_cache_flush
889 .word 0x56158000 @ PXA168
890 .word 0xfffff000
891 W(b) __armv4_mmu_cache_on
892 W(b) __armv4_mmu_cache_off
893 W(b) __armv5tej_mmu_cache_flush
895 .word 0x56050000 @ Feroceon
896 .word 0xff0f0000
897 W(b) __armv4_mmu_cache_on
898 W(b) __armv4_mmu_cache_off
899 W(b) __armv5tej_mmu_cache_flush
901 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
902 /* this conflicts with the standard ARMv5TE entry */
903 .long 0x41009260 @ Old Feroceon
904 .long 0xff00fff0
905 b __armv4_mmu_cache_on
906 b __armv4_mmu_cache_off
907 b __armv5tej_mmu_cache_flush
908 #endif
910 .word 0x66015261 @ FA526
911 .word 0xff01fff1
912 W(b) __fa526_cache_on
913 W(b) __armv4_mmu_cache_off
914 W(b) __fa526_cache_flush
916 @ These match on the architecture ID
918 .word 0x00020000 @ ARMv4T
919 .word 0x000f0000
920 W(b) __armv4_mmu_cache_on
921 W(b) __armv4_mmu_cache_off
922 W(b) __armv4_mmu_cache_flush
924 .word 0x00050000 @ ARMv5TE
925 .word 0x000f0000
926 W(b) __armv4_mmu_cache_on
927 W(b) __armv4_mmu_cache_off
928 W(b) __armv4_mmu_cache_flush
930 .word 0x00060000 @ ARMv5TEJ
931 .word 0x000f0000
932 W(b) __armv4_mmu_cache_on
933 W(b) __armv4_mmu_cache_off
934 W(b) __armv5tej_mmu_cache_flush
936 .word 0x0007b000 @ ARMv6
937 .word 0x000ff000
938 W(b) __armv6_mmu_cache_on
939 W(b) __armv4_mmu_cache_off
940 W(b) __armv6_mmu_cache_flush
942 .word 0x000f0000 @ new CPU Id
943 .word 0x000f0000
944 W(b) __armv7_mmu_cache_on
945 W(b) __armv7_mmu_cache_off
946 W(b) __armv7_mmu_cache_flush
948 .word 0 @ unrecognised type
949 .word 0
950 mov pc, lr
951 THUMB( nop )
952 mov pc, lr
953 THUMB( nop )
954 mov pc, lr
955 THUMB( nop )
957 .size proc_types, . - proc_types
959 /*
960 * If you get a "non-constant expression in ".if" statement"
961 * error from the assembler on this line, check that you have
962 * not accidentally written a "b" instruction where you should
963 * have written W(b).
964 */
965 .if (. - proc_types) % PROC_ENTRY_SIZE != 0
966 .error "The size of one or more proc_types entries is wrong."
967 .endif
969 /*
970 * Turn off the Cache and MMU. ARMv3 does not support
971 * reading the control register, but ARMv4 does.
972 *
973 * On exit,
974 * r0, r1, r2, r3, r9, r12 corrupted
975 * This routine must preserve:
976 * r4, r7, r8
977 */
978 .align 5
979 cache_off: mov r3, #12 @ cache_off function
980 b call_cache_fn
982 __armv4_mpu_cache_off:
983 mrc p15, 0, r0, c1, c0
984 bic r0, r0, #0x000d
985 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
986 mov r0, #0
987 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
988 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
989 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
990 mov pc, lr
992 __armv3_mpu_cache_off:
993 mrc p15, 0, r0, c1, c0
994 bic r0, r0, #0x000d
995 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
996 mov r0, #0
997 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
998 mov pc, lr
1000 __armv4_mmu_cache_off:
1001 #ifdef CONFIG_MMU
1002 mrc p15, 0, r0, c1, c0
1003 bic r0, r0, #0x000d
1004 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1005 mov r0, #0
1006 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1007 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1008 #endif
1009 mov pc, lr
1011 __armv7_mmu_cache_off:
1012 mrc p15, 0, r0, c1, c0
1013 #ifdef CONFIG_MMU
1014 bic r0, r0, #0x000d
1015 #else
1016 bic r0, r0, #0x000c
1017 #endif
1018 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1019 mov r12, lr
1020 bl __armv7_mmu_cache_flush
1021 mov r0, #0
1022 #ifdef CONFIG_MMU
1023 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1024 #endif
1025 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1026 mcr p15, 0, r0, c7, c10, 4 @ DSB
1027 mcr p15, 0, r0, c7, c5, 4 @ ISB
1028 mov pc, r12
1030 /*
1031 * Clean and flush the cache to maintain consistency.
1032 *
1033 * On exit,
1034 * r1, r2, r3, r9, r10, r11, r12 corrupted
1035 * This routine must preserve:
1036 * r4, r6, r7, r8
1037 */
1038 .align 5
1039 cache_clean_flush:
1040 mov r3, #16
1041 b call_cache_fn
1043 .arch armv4
1044 __armv4_mpu_cache_flush:
1045 mov r2, #1
1046 mov r3, #0
1047 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1048 mov r1, #7 << 5 @ 8 segments
1049 1: orr r3, r1, #63 << 26 @ 64 entries
1050 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1051 subs r3, r3, #1 << 26
1052 bcs 2b @ entries 63 to 0
1053 subs r1, r1, #1 << 5
1054 bcs 1b @ segments 7 to 0
1056 teq r2, #0
1057 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1058 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1059 mov pc, lr
1061 __fa526_cache_flush:
1062 mov r1, #0
1063 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1064 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1065 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1066 mov pc, lr
1068 __armv6_mmu_cache_flush:
1069 .arch armv6
1070 mov r1, #0
1071 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1072 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1073 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1074 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1075 mov pc, lr
1077 .arch armv7-a
1078 __armv7_mmu_cache_flush:
1079 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1080 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
1081 mov r10, #0
1082 beq hierarchical
1083 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1084 b iflush
1085 hierarchical:
1086 mcr p15, 0, r10, c7, c10, 5 @ DMB
1087 stmfd sp!, {r0-r7, r9-r11}
1088 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1089 ands r3, r0, #0x7000000 @ extract loc from clidr
1090 mov r3, r3, lsr #23 @ left align loc bit field
1091 beq finished @ if loc is 0, then no need to clean
1092 mov r10, #0 @ start clean at cache level 0
1093 loop1:
1094 add r2, r10, r10, lsr #1 @ work out 3x current cache level
1095 mov r1, r0, lsr r2 @ extract cache type bits from clidr
1096 and r1, r1, #7 @ mask of the bits for current cache only
1097 cmp r1, #2 @ see what cache we have at this level
1098 blt skip @ skip if no cache, or just i-cache
1099 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1100 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1101 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1102 and r2, r1, #7 @ extract the length of the cache lines
1103 add r2, r2, #4 @ add 4 (line length offset)
1104 ldr r4, =0x3ff
1105 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
1106 clz r5, r4 @ find bit position of way size increment
1107 ldr r7, =0x7fff
1108 ands r7, r7, r1, lsr #13 @ extract max number of the index size
1109 loop2:
1110 mov r9, r4 @ create working copy of max way size
1111 loop3:
1112 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
1113 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
1114 THUMB( lsl r6, r9, r5 )
1115 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
1116 THUMB( lsl r6, r7, r2 )
1117 THUMB( orr r11, r11, r6 ) @ factor index number into r11
1118 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1119 subs r9, r9, #1 @ decrement the way
1120 bge loop3
1121 subs r7, r7, #1 @ decrement the index
1122 bge loop2
1123 skip:
1124 add r10, r10, #2 @ increment cache number
1125 cmp r3, r10
1126 bgt loop1
1127 finished:
1128 ldmfd sp!, {r0-r7, r9-r11}
1129 mov r10, #0 @ swith back to cache level 0
1130 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1131 iflush:
1132 mcr p15, 0, r10, c7, c10, 4 @ DSB
1133 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1134 mcr p15, 0, r10, c7, c10, 4 @ DSB
1135 mcr p15, 0, r10, c7, c5, 4 @ ISB
1136 mov pc, lr
1138 .arch armv5
1139 __armv5tej_mmu_cache_flush:
1140 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1141 bne 1b
1142 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1143 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1144 mov pc, lr
1146 .arch armv4
1147 __armv4_mmu_cache_flush:
1148 mov r2, #64*1024 @ default: 32K dcache size (*2)
1149 mov r11, #32 @ default: 32 byte line size
1150 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1151 teq r3, r9 @ cache ID register present?
1152 beq no_cache_id
1153 mov r1, r3, lsr #18
1154 and r1, r1, #7
1155 mov r2, #1024
1156 mov r2, r2, lsl r1 @ base dcache size *2
1157 tst r3, #1 << 14 @ test M bit
1158 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1159 mov r3, r3, lsr #12
1160 and r3, r3, #3
1161 mov r11, #8
1162 mov r11, r11, lsl r3 @ cache line size in bytes
1163 no_cache_id:
1164 mov r1, pc
1165 bic r1, r1, #63 @ align to longest cache line
1166 add r2, r1, r2
1167 1:
1168 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1169 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1170 THUMB( add r1, r1, r11 )
1171 teq r1, r2
1172 bne 1b
1174 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1175 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1176 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1177 mov pc, lr
1179 __armv3_mmu_cache_flush:
1180 __armv3_mpu_cache_flush:
1181 mov r1, #0
1182 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1183 mov pc, lr
1185 .arch armv4
1187 /*
1188 * Various debugging routines for printing hex characters and
1189 * memory, which again must be relocatable.
1190 */
1191 #ifdef DEBUG
1192 .align 2
1193 .type phexbuf,#object
1194 phexbuf: .space 12
1195 .size phexbuf, . - phexbuf
1197 @ phex corrupts {r0, r1, r2, r3}
1198 phex: adr r3, phexbuf
1199 mov r2, #0
1200 strb r2, [r3, r1]
1201 1: subs r1, r1, #1
1202 movmi r0, r3
1203 bmi puts
1204 and r2, r0, #15
1205 mov r0, r0, lsr #4
1206 cmp r2, #10
1207 addge r2, r2, #7
1208 add r2, r2, #'0'
1209 strb r2, [r3, r1]
1210 b 1b
1212 @ puts corrupts {r0, r1, r2, r3}
1213 puts: loadsp r3, r1
1214 1: ldrb r2, [r0], #1
1215 teq r2, #0
1216 moveq pc, lr
1217 2: writeb r2, r3
1218 mov r1, #0x00020000
1219 3: subs r1, r1, #1
1220 bne 3b
1221 teq r2, #'\n'
1222 moveq r2, #'\r'
1223 beq 2b
1224 teq r0, #0
1225 bne 1b
1226 mov pc, lr
1227 @ putc corrupts {r0, r1, r2, r3}
1228 putc:
1229 mov r2, r0
1230 mov r0, #0
1231 loadsp r3, r1
1232 b 2b
1234 @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
1235 memdump: mov r12, r0
1236 mov r10, lr
1237 mov r11, #0
1238 2: mov r0, r11, lsl #2
1239 add r0, r0, r12
1240 mov r1, #8
1241 bl phex
1242 mov r0, #':'
1243 bl putc
1244 1: mov r0, #' '
1245 bl putc
1246 ldr r0, [r12, r11, lsl #2]
1247 mov r1, #8
1248 bl phex
1249 and r0, r11, #7
1250 teq r0, #3
1251 moveq r0, #' '
1252 bleq putc
1253 and r0, r11, #7
1254 add r11, r11, #1
1255 teq r0, #7
1256 bne 1b
1257 mov r0, #'\n'
1258 bl putc
1259 cmp r11, #64
1260 blt 2b
1261 mov pc, r10
1262 #endif
1264 .ltorg
1266 #ifdef CONFIG_ARM_VIRT_EXT
1267 .align 5
1268 __hyp_reentry_vectors:
1269 W(b) . @ reset
1270 W(b) . @ undef
1271 W(b) . @ svc
1272 W(b) . @ pabort
1273 W(b) . @ dabort
1274 W(b) __enter_kernel @ hyp
1275 W(b) . @ irq
1276 W(b) . @ fiq
1277 #endif /* CONFIG_ARM_VIRT_EXT */
1279 __enter_kernel:
1280 mov r0, #0 @ must be 0
1281 ARM( mov pc, r4 ) @ call kernel
1282 THUMB( bx r4 ) @ entry point is always ARM
1284 reloc_code_end:
1286 .align
1287 .section ".stack", "aw", %nobits
1288 .L_user_stack: .space 4096
1289 .L_user_stack_end: