1 /*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
11 /include/ "skeleton.dtsi"
13 / {
14 compatible = "ti,am33xx";
15 interrupt-parent = <&intc>;
17 aliases {
18 serial0 = &uart0;
19 serial1 = &uart1;
20 serial2 = &uart2;
21 serial3 = &uart3;
22 serial4 = &uart4;
23 serial5 = &uart5;
24 };
26 cpus {
27 cpu@0 {
28 compatible = "arm,cortex-a8";
30 /*
31 * To consider voltage drop between PMIC and SoC,
32 * tolerance value is reduced to 2% from 4% and
33 * voltage value is increased as a precaution.
34 */
35 operating-points = <
36 /* kHz uV */
37 720000 1285000
38 600000 1225000
39 500000 1125000
40 275000 1125000
41 >;
42 voltage-tolerance = <2>; /* 2 percentage */
43 clock-latency = <300000>; /* From omap-cpufreq driver */
44 };
45 };
47 /*
48 * The soc node represents the soc top level view. It is uses for IPs
49 * that are not memory mapped in the MPU view or for the MPU itself.
50 */
51 soc {
52 compatible = "ti,omap-infra";
53 mpu {
54 compatible = "ti,omap3-mpu";
55 ti,hwmods = "mpu";
56 };
57 };
59 am33xx_pinmux: pinmux@44e10800 {
60 compatible = "pinctrl-single";
61 reg = <0x44e10800 0x0238>;
62 #address-cells = <1>;
63 #size-cells = <0>;
64 pinctrl-single,register-width = <32>;
65 pinctrl-single,function-mask = <0x7f>;
66 };
68 /*
69 * XXX: Use a flat representation of the AM33XX interconnect.
70 * The real AM33XX interconnect network is quite complex.Since
71 * that will not bring real advantage to represent that in DT
72 * for the moment, just use a fake OCP bus entry to represent
73 * the whole bus hierarchy.
74 */
75 ocp {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80 ti,hwmods = "l3_main";
82 intc: interrupt-controller@48200000 {
83 compatible = "ti,omap2-intc";
84 interrupt-controller;
85 #interrupt-cells = <1>;
86 ti,intc-size = <128>;
87 reg = <0x48200000 0x1000>;
88 };
90 edma: edma@49000000 {
91 compatible = "ti,edma3";
92 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
93 reg = <0x49000000 0x10000>,
94 <0x44e10f90 0x10>;
95 interrupt-parent = <&intc>;
96 interrupts = <12 13 14>;
97 #dma-cells = <1>;
98 dma-channels = <64>;
99 ti,edma-regions = <4>;
100 ti,edma-slots = <256>;
101 ti,edma-queue-tc-map = <0 0
102 1 1
103 2 2>;
104 ti,edma-queue-priority-map = <0 0
105 1 1
106 2 2>;
107 ti,edma-default-queue = <0>;
108 };
110 gpio0: gpio@44e07000 {
111 compatible = "ti,omap4-gpio";
112 ti,hwmods = "gpio1";
113 gpio-controller;
114 #gpio-cells = <2>;
115 interrupt-controller;
116 #interrupt-cells = <1>;
117 reg = <0x44e07000 0x1000>;
118 interrupts = <96>;
119 };
121 gpio1: gpio@4804c000 {
122 compatible = "ti,omap4-gpio";
123 ti,hwmods = "gpio2";
124 gpio-controller;
125 #gpio-cells = <2>;
126 interrupt-controller;
127 #interrupt-cells = <1>;
128 reg = <0x4804c000 0x1000>;
129 interrupts = <98>;
130 };
132 gpio2: gpio@481ac000 {
133 compatible = "ti,omap4-gpio";
134 ti,hwmods = "gpio3";
135 gpio-controller;
136 #gpio-cells = <2>;
137 interrupt-controller;
138 #interrupt-cells = <1>;
139 reg = <0x481ac000 0x1000>;
140 interrupts = <32>;
141 };
143 gpio3: gpio@481ae000 {
144 compatible = "ti,omap4-gpio";
145 ti,hwmods = "gpio4";
146 gpio-controller;
147 #gpio-cells = <2>;
148 interrupt-controller;
149 #interrupt-cells = <1>;
150 reg = <0x481ae000 0x1000>;
151 interrupts = <62>;
152 };
154 uart0: serial@44e09000 {
155 compatible = "ti,omap3-uart";
156 ti,hwmods = "uart1";
157 clock-frequency = <48000000>;
158 reg = <0x44e09000 0x2000>;
159 interrupts = <72>;
160 status = "disabled";
161 };
163 uart1: serial@48022000 {
164 compatible = "ti,omap3-uart";
165 ti,hwmods = "uart2";
166 clock-frequency = <48000000>;
167 reg = <0x48022000 0x2000>;
168 interrupts = <73>;
169 status = "disabled";
170 };
172 uart2: serial@48024000 {
173 compatible = "ti,omap3-uart";
174 ti,hwmods = "uart3";
175 clock-frequency = <48000000>;
176 reg = <0x48024000 0x2000>;
177 interrupts = <74>;
178 status = "disabled";
179 };
181 uart3: serial@481a6000 {
182 compatible = "ti,omap3-uart";
183 ti,hwmods = "uart4";
184 clock-frequency = <48000000>;
185 reg = <0x481a6000 0x2000>;
186 interrupts = <44>;
187 status = "disabled";
188 };
190 uart4: serial@481a8000 {
191 compatible = "ti,omap3-uart";
192 ti,hwmods = "uart5";
193 clock-frequency = <48000000>;
194 reg = <0x481a8000 0x2000>;
195 interrupts = <45>;
196 status = "disabled";
197 };
199 uart5: serial@481aa000 {
200 compatible = "ti,omap3-uart";
201 ti,hwmods = "uart6";
202 clock-frequency = <48000000>;
203 reg = <0x481aa000 0x2000>;
204 interrupts = <46>;
205 status = "disabled";
206 };
208 i2c0: i2c@44e0b000 {
209 compatible = "ti,omap4-i2c";
210 #address-cells = <1>;
211 #size-cells = <0>;
212 ti,hwmods = "i2c1";
213 reg = <0x44e0b000 0x1000>;
214 interrupts = <70>;
215 status = "disabled";
216 };
218 i2c1: i2c@4802a000 {
219 compatible = "ti,omap4-i2c";
220 #address-cells = <1>;
221 #size-cells = <0>;
222 ti,hwmods = "i2c2";
223 reg = <0x4802a000 0x1000>;
224 interrupts = <71>;
225 status = "disabled";
226 };
228 i2c2: i2c@4819c000 {
229 compatible = "ti,omap4-i2c";
230 #address-cells = <1>;
231 #size-cells = <0>;
232 ti,hwmods = "i2c3";
233 reg = <0x4819c000 0x1000>;
234 interrupts = <30>;
235 status = "disabled";
236 };
238 mmc1: mmc@48060000 {
239 compatible = "ti,omap3-hsmmc";
240 ti,hwmods = "mmc1";
241 ti,dual-volt;
242 ti,needs-special-reset;
243 dmas = <&edma 24
244 &edma 25>;
245 dma-names = "tx", "rx";
246 status = "disabled";
247 };
249 mmc2: mmc@481d8000 {
250 compatible = "ti,omap3-hsmmc";
251 ti,hwmods = "mmc2";
252 ti,needs-special-reset;
253 dmas = <&edma 2
254 &edma 3>;
255 dma-names = "tx", "rx";
256 status = "disabled";
257 };
259 mmc3: mmc@47810000 {
260 compatible = "ti,omap3-hsmmc";
261 ti,hwmods = "mmc3";
262 ti,needs-special-reset;
263 status = "disabled";
264 };
266 wdt2: wdt@44e35000 {
267 compatible = "ti,omap3-wdt";
268 ti,hwmods = "wd_timer2";
269 reg = <0x44e35000 0x1000>;
270 interrupts = <91>;
271 };
273 dcan0: d_can@481cc000 {
274 compatible = "bosch,d_can";
275 ti,hwmods = "d_can0";
276 reg = <0x481cc000 0x2000>;
277 interrupts = <52>;
278 status = "disabled";
279 };
281 dcan1: d_can@481d0000 {
282 compatible = "bosch,d_can";
283 ti,hwmods = "d_can1";
284 reg = <0x481d0000 0x2000>;
285 interrupts = <55>;
286 status = "disabled";
287 };
289 timer1: timer@44e31000 {
290 compatible = "ti,omap2-timer";
291 reg = <0x44e31000 0x400>;
292 interrupts = <67>;
293 ti,hwmods = "timer1";
294 ti,timer-alwon;
295 };
297 timer2: timer@48040000 {
298 compatible = "ti,omap2-timer";
299 reg = <0x48040000 0x400>;
300 interrupts = <68>;
301 ti,hwmods = "timer2";
302 ti,timer-non-wkup;
303 };
305 timer3: timer@48042000 {
306 compatible = "ti,omap2-timer";
307 reg = <0x48042000 0x400>;
308 interrupts = <69>;
309 ti,hwmods = "timer3";
310 };
312 timer4: timer@48044000 {
313 compatible = "ti,omap2-timer";
314 reg = <0x48044000 0x400>;
315 interrupts = <92>;
316 ti,hwmods = "timer4";
317 ti,timer-pwm;
318 };
320 timer5: timer@48046000 {
321 compatible = "ti,omap2-timer";
322 reg = <0x48046000 0x400>;
323 interrupts = <93>;
324 ti,hwmods = "timer5";
325 ti,timer-pwm;
326 };
328 timer6: timer@48048000 {
329 compatible = "ti,omap2-timer";
330 reg = <0x48048000 0x400>;
331 interrupts = <94>;
332 ti,hwmods = "timer6";
333 ti,timer-pwm;
334 };
336 timer7: timer@4804a000 {
337 compatible = "ti,omap2-timer";
338 reg = <0x4804a000 0x400>;
339 interrupts = <95>;
340 ti,hwmods = "timer7";
341 ti,timer-pwm;
342 };
344 rtc@44e3e000 {
345 compatible = "ti,da830-rtc";
346 reg = <0x44e3e000 0x1000>;
347 interrupts = <75
348 76>;
349 ti,hwmods = "rtc";
350 };
352 spi0: spi@48030000 {
353 compatible = "ti,omap4-mcspi";
354 #address-cells = <1>;
355 #size-cells = <0>;
356 reg = <0x48030000 0x400>;
357 interrupt = <65>;
358 ti,spi-num-cs = <2>;
359 ti,hwmods = "spi0";
360 dmas = <&edma 16
361 &edma 17
362 &edma 18
363 &edma 19>;
364 dma-names = "tx0", "rx0", "tx1", "rx1";
365 status = "disabled";
366 };
368 spi1: spi@481a0000 {
369 compatible = "ti,omap4-mcspi";
370 #address-cells = <1>;
371 #size-cells = <0>;
372 reg = <0x481a0000 0x400>;
373 interrupt = <125>;
374 ti,spi-num-cs = <2>;
375 ti,hwmods = "spi1";
376 dmas = <&edma 42
377 &edma 43
378 &edma 44
379 &edma 45>;
380 dma-names = "tx0", "rx0", "tx1", "rx1";
381 status = "disabled";
382 };
384 usb@47400000 {
385 compatible = "ti,musb-am33xx";
386 reg = <0x47400000 0x1000 /* usbss */
387 0x47401000 0x800 /* musb instance 0 */
388 0x47401800 0x800 /* musb instance 1 */
389 0x47402000 0x6000>; /* cppi41 usbdma */
390 interrupts = <17 /* usbss */
391 18 /* musb instance 0 */
392 19>; /* musb instance 1 */
393 multipoint = <1>;
394 num-eps = <16>;
395 ram-bits = <12>;
396 port0-mode = <3>; /* 1: host only mode */
397 port1-mode = <3>; /* 2: device & 3:otg */
398 power = <250>;
399 ti,hwmods = "usb_otg_hs";
400 };
402 mac: ethernet@4a100000 {
403 compatible = "ti,cpsw";
404 ti,hwmods = "cpgmac0";
405 cpdma_channels = <8>;
406 ale_entries = <1024>;
407 bd_ram_size = <0x2000>;
408 no_bd_ram = <0>;
409 rx_descs = <64>;
410 mac_control = <0x20>;
411 slaves = <2>;
412 active_slave = <0>;
413 cpts_clock_mult = <0x80000000>;
414 cpts_clock_shift = <29>;
415 reg = <0x4a100000 0x800
416 0x4a101200 0x100>;
417 #address-cells = <1>;
418 #size-cells = <1>;
419 interrupt-parent = <&intc>;
420 /*
421 * c0_rx_thresh_pend
422 * c0_rx_pend
423 * c0_tx_pend
424 * c0_misc_pend
425 */
426 interrupts = <40 41 42 43>;
427 ranges;
429 davinci_mdio: mdio@4a101000 {
430 compatible = "ti,davinci_mdio";
431 #address-cells = <1>;
432 #size-cells = <0>;
433 ti,hwmods = "davinci_mdio";
434 bus_freq = <1000000>;
435 reg = <0x4a101000 0x100>;
436 };
438 cpsw_emac0: slave@4a100200 {
439 /* Filled in by U-Boot */
440 mac-address = [ 00 00 00 00 00 00 ];
441 };
443 cpsw_emac1: slave@4a100300 {
444 /* Filled in by U-Boot */
445 mac-address = [ 00 00 00 00 00 00 ];
446 };
447 };
449 wkup_m3: wkup_m3@44d00000 {
450 compatible = "ti,am3353-wkup-m3";
451 reg = <0x44d00000 0x4000 /* M3 UMEM */
452 0x44d80000 0x2000>; /* M3 DMEM */
453 interrupts = <78>;
454 ti,hwmods = "wkup_m3";
455 };
457 sham: sham@53100000 {
458 compatible = "ti,omap4-sham";
459 ti,hwmods = "sham";
460 #address-cells = <1>;
461 #size-cells = <0>;
462 reg = <0x53100000 0x200>;
463 interrupt-parent = <&intc>;
464 interrupts = <109>;
465 dmas = <&edma 36>;
466 dma-names = "rx";
467 };
469 aes: aes@53500000 {
470 compatible = "ti,omap4-aes";
471 ti,hwmods = "aes";
472 #address-cells = <1>;
473 #size-cells = <0>;
474 reg = <0x53500000 0xa0>;
475 interrupt-parent = <&intc>;
476 interrupts = <102>;
477 dmas = <&edma 6
478 &edma 5>;
479 dma-names = "tx", "rx";
480 };
481 };
482 };