1 /*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
12 /include/ "skeleton.dtsi"
14 / {
15 model = "Atmel AT91SAM9G45 family SoC";
16 compatible = "atmel,at91sam9g45";
17 interrupt-parent = <&aic>;
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 serial4 = &usart3;
25 gpio0 = &pioA;
26 gpio1 = &pioB;
27 gpio2 = &pioC;
28 gpio3 = &pioD;
29 gpio4 = &pioE;
30 tcb0 = &tcb0;
31 tcb1 = &tcb1;
32 i2c0 = &i2c0;
33 i2c1 = &i2c1;
34 ssc0 = &ssc0;
35 ssc1 = &ssc1;
36 };
37 cpus {
38 cpu@0 {
39 compatible = "arm,arm926ejs";
40 };
41 };
43 memory {
44 reg = <0x70000000 0x10000000>;
45 };
47 ahb {
48 compatible = "simple-bus";
49 #address-cells = <1>;
50 #size-cells = <1>;
51 ranges;
53 apb {
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
59 aic: interrupt-controller@fffff000 {
60 #interrupt-cells = <3>;
61 compatible = "atmel,at91rm9200-aic";
62 interrupt-controller;
63 reg = <0xfffff000 0x200>;
64 atmel,external-irqs = <31>;
65 };
67 ramc0: ramc@ffffe400 {
68 compatible = "atmel,at91sam9g45-ddramc";
69 reg = <0xffffe400 0x200
70 0xffffe600 0x200>;
71 };
73 pmc: pmc@fffffc00 {
74 compatible = "atmel,at91rm9200-pmc";
75 reg = <0xfffffc00 0x100>;
76 };
78 rstc@fffffd00 {
79 compatible = "atmel,at91sam9g45-rstc";
80 reg = <0xfffffd00 0x10>;
81 };
83 pit: timer@fffffd30 {
84 compatible = "atmel,at91sam9260-pit";
85 reg = <0xfffffd30 0xf>;
86 interrupts = <1 4 7>;
87 };
90 shdwc@fffffd10 {
91 compatible = "atmel,at91sam9rl-shdwc";
92 reg = <0xfffffd10 0x10>;
93 };
95 tcb0: timer@fff7c000 {
96 compatible = "atmel,at91rm9200-tcb";
97 reg = <0xfff7c000 0x100>;
98 interrupts = <18 4 0>;
99 };
101 tcb1: timer@fffd4000 {
102 compatible = "atmel,at91rm9200-tcb";
103 reg = <0xfffd4000 0x100>;
104 interrupts = <18 4 0>;
105 };
107 dma: dma-controller@ffffec00 {
108 compatible = "atmel,at91sam9g45-dma";
109 reg = <0xffffec00 0x200>;
110 interrupts = <21 4 0>;
111 };
113 pinctrl@fffff200 {
114 #address-cells = <1>;
115 #size-cells = <1>;
116 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
117 ranges = <0xfffff200 0xfffff200 0xa00>;
119 atmel,mux-mask = <
120 /* A B */
121 0xffffffff 0xffc003ff /* pioA */
122 0xffffffff 0x800f8f00 /* pioB */
123 0xffffffff 0x00000e00 /* pioC */
124 0xffffffff 0xff0c1381 /* pioD */
125 0xffffffff 0x81ffff81 /* pioE */
126 >;
128 /* shared pinctrl settings */
129 dbgu {
130 pinctrl_dbgu: dbgu-0 {
131 atmel,pins =
132 <1 12 0x1 0x0 /* PB12 periph A */
133 1 13 0x1 0x0>; /* PB13 periph A */
134 };
135 };
137 usart0 {
138 pinctrl_usart0: usart0-0 {
139 atmel,pins =
140 <1 19 0x1 0x1 /* PB19 periph A with pullup */
141 1 18 0x1 0x0>; /* PB18 periph A */
142 };
144 pinctrl_usart0_rts: usart0_rts-0 {
145 atmel,pins =
146 <1 17 0x2 0x0>; /* PB17 periph B */
147 };
149 pinctrl_usart0_cts: usart0_cts-0 {
150 atmel,pins =
151 <1 15 0x2 0x0>; /* PB15 periph B */
152 };
153 };
155 uart1 {
156 pinctrl_usart1: usart1-0 {
157 atmel,pins =
158 <1 4 0x1 0x1 /* PB4 periph A with pullup */
159 1 5 0x1 0x0>; /* PB5 periph A */
160 };
162 pinctrl_usart1_rts: usart1_rts-0 {
163 atmel,pins =
164 <3 16 0x1 0x0>; /* PD16 periph A */
165 };
167 pinctrl_usart1_cts: usart1_cts-0 {
168 atmel,pins =
169 <3 17 0x1 0x0>; /* PD17 periph A */
170 };
171 };
173 usart2 {
174 pinctrl_usart2: usart2-0 {
175 atmel,pins =
176 <1 6 0x1 0x1 /* PB6 periph A with pullup */
177 1 7 0x1 0x0>; /* PB7 periph A */
178 };
180 pinctrl_usart2_rts: usart2_rts-0 {
181 atmel,pins =
182 <2 9 0x2 0x0>; /* PC9 periph B */
183 };
185 pinctrl_usart2_cts: usart2_cts-0 {
186 atmel,pins =
187 <2 11 0x2 0x0>; /* PC11 periph B */
188 };
189 };
191 usart3 {
192 pinctrl_usart3: usart3-0 {
193 atmel,pins =
194 <1 8 0x1 0x1 /* PB9 periph A with pullup */
195 1 9 0x1 0x0>; /* PB8 periph A */
196 };
198 pinctrl_usart3_rts: usart3_rts-0 {
199 atmel,pins =
200 <0 23 0x2 0x0>; /* PA23 periph B */
201 };
203 pinctrl_usart3_cts: usart3_cts-0 {
204 atmel,pins =
205 <0 24 0x2 0x0>; /* PA24 periph B */
206 };
207 };
209 nand {
210 pinctrl_nand: nand-0 {
211 atmel,pins =
212 <2 8 0x0 0x1 /* PC8 gpio RDY pin pull_up*/
213 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
214 };
215 };
217 macb {
218 pinctrl_macb_rmii: macb_rmii-0 {
219 atmel,pins =
220 <0 10 0x1 0x0 /* PA10 periph A */
221 0 11 0x1 0x0 /* PA11 periph A */
222 0 12 0x1 0x0 /* PA12 periph A */
223 0 13 0x1 0x0 /* PA13 periph A */
224 0 14 0x1 0x0 /* PA14 periph A */
225 0 15 0x1 0x0 /* PA15 periph A */
226 0 16 0x1 0x0 /* PA16 periph A */
227 0 17 0x1 0x0 /* PA17 periph A */
228 0 18 0x1 0x0 /* PA18 periph A */
229 0 19 0x1 0x0>; /* PA19 periph A */
230 };
232 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
233 atmel,pins =
234 <0 6 0x2 0x0 /* PA6 periph B */
235 0 7 0x2 0x0 /* PA7 periph B */
236 0 8 0x2 0x0 /* PA8 periph B */
237 0 9 0x2 0x0 /* PA9 periph B */
238 0 27 0x2 0x0 /* PA27 periph B */
239 0 28 0x2 0x0 /* PA28 periph B */
240 0 29 0x2 0x0 /* PA29 periph B */
241 0 30 0x2 0x0>; /* PA30 periph B */
242 };
243 };
245 mmc0 {
246 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
247 atmel,pins =
248 <0 0 0x1 0x0 /* PA0 periph A */
249 0 1 0x1 0x1 /* PA1 periph A with pullup */
250 0 2 0x1 0x1>; /* PA2 periph A with pullup */
251 };
253 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
254 atmel,pins =
255 <0 3 0x1 0x1 /* PA3 periph A with pullup */
256 0 4 0x1 0x1 /* PA4 periph A with pullup */
257 0 5 0x1 0x1>; /* PA5 periph A with pullup */
258 };
260 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
261 atmel,pins =
262 <0 6 0x1 0x1 /* PA6 periph A with pullup */
263 0 7 0x1 0x1 /* PA7 periph A with pullup */
264 0 8 0x1 0x1 /* PA8 periph A with pullup */
265 0 9 0x1 0x1>; /* PA9 periph A with pullup */
266 };
267 };
269 mmc1 {
270 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
271 atmel,pins =
272 <0 31 0x1 0x0 /* PA31 periph A */
273 0 22 0x1 0x1 /* PA22 periph A with pullup */
274 0 23 0x1 0x1>; /* PA23 periph A with pullup */
275 };
277 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
278 atmel,pins =
279 <0 24 0x1 0x1 /* PA24 periph A with pullup */
280 0 25 0x1 0x1 /* PA25 periph A with pullup */
281 0 26 0x1 0x1>; /* PA26 periph A with pullup */
282 };
284 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
285 atmel,pins =
286 <0 27 0x1 0x1 /* PA27 periph A with pullup */
287 0 28 0x1 0x1 /* PA28 periph A with pullup */
288 0 29 0x1 0x1 /* PA29 periph A with pullup */
289 0 20 0x1 0x1>; /* PA30 periph A with pullup */
290 };
291 };
293 ssc0 {
294 pinctrl_ssc0_tx: ssc0_tx-0 {
295 atmel,pins =
296 <3 0 0x1 0x0 /* PD0 periph A */
297 3 1 0x1 0x0 /* PD1 periph A */
298 3 2 0x1 0x0>; /* PD2 periph A */
299 };
301 pinctrl_ssc0_rx: ssc0_rx-0 {
302 atmel,pins =
303 <3 3 0x1 0x0 /* PD3 periph A */
304 3 4 0x1 0x0 /* PD4 periph A */
305 3 5 0x1 0x0>; /* PD5 periph A */
306 };
307 };
309 ssc1 {
310 pinctrl_ssc1_tx: ssc1_tx-0 {
311 atmel,pins =
312 <3 10 0x1 0x0 /* PD10 periph A */
313 3 11 0x1 0x0 /* PD11 periph A */
314 3 12 0x1 0x0>; /* PD12 periph A */
315 };
317 pinctrl_ssc1_rx: ssc1_rx-0 {
318 atmel,pins =
319 <3 13 0x1 0x0 /* PD13 periph A */
320 3 14 0x1 0x0 /* PD14 periph A */
321 3 15 0x1 0x0>; /* PD15 periph A */
322 };
323 };
325 pioA: gpio@fffff200 {
326 compatible = "atmel,at91rm9200-gpio";
327 reg = <0xfffff200 0x200>;
328 interrupts = <2 4 1>;
329 #gpio-cells = <2>;
330 gpio-controller;
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 };
335 pioB: gpio@fffff400 {
336 compatible = "atmel,at91rm9200-gpio";
337 reg = <0xfffff400 0x200>;
338 interrupts = <3 4 1>;
339 #gpio-cells = <2>;
340 gpio-controller;
341 interrupt-controller;
342 #interrupt-cells = <2>;
343 };
345 pioC: gpio@fffff600 {
346 compatible = "atmel,at91rm9200-gpio";
347 reg = <0xfffff600 0x200>;
348 interrupts = <4 4 1>;
349 #gpio-cells = <2>;
350 gpio-controller;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 };
355 pioD: gpio@fffff800 {
356 compatible = "atmel,at91rm9200-gpio";
357 reg = <0xfffff800 0x200>;
358 interrupts = <5 4 1>;
359 #gpio-cells = <2>;
360 gpio-controller;
361 interrupt-controller;
362 #interrupt-cells = <2>;
363 };
365 pioE: gpio@fffffa00 {
366 compatible = "atmel,at91rm9200-gpio";
367 reg = <0xfffffa00 0x200>;
368 interrupts = <5 4 1>;
369 #gpio-cells = <2>;
370 gpio-controller;
371 interrupt-controller;
372 #interrupt-cells = <2>;
373 };
374 };
376 dbgu: serial@ffffee00 {
377 compatible = "atmel,at91sam9260-usart";
378 reg = <0xffffee00 0x200>;
379 interrupts = <1 4 7>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_dbgu>;
382 status = "disabled";
383 };
385 usart0: serial@fff8c000 {
386 compatible = "atmel,at91sam9260-usart";
387 reg = <0xfff8c000 0x200>;
388 interrupts = <7 4 5>;
389 atmel,use-dma-rx;
390 atmel,use-dma-tx;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_usart0>;
393 status = "disabled";
394 };
396 usart1: serial@fff90000 {
397 compatible = "atmel,at91sam9260-usart";
398 reg = <0xfff90000 0x200>;
399 interrupts = <8 4 5>;
400 atmel,use-dma-rx;
401 atmel,use-dma-tx;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_usart1>;
404 status = "disabled";
405 };
407 usart2: serial@fff94000 {
408 compatible = "atmel,at91sam9260-usart";
409 reg = <0xfff94000 0x200>;
410 interrupts = <9 4 5>;
411 atmel,use-dma-rx;
412 atmel,use-dma-tx;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_usart2>;
415 status = "disabled";
416 };
418 usart3: serial@fff98000 {
419 compatible = "atmel,at91sam9260-usart";
420 reg = <0xfff98000 0x200>;
421 interrupts = <10 4 5>;
422 atmel,use-dma-rx;
423 atmel,use-dma-tx;
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_usart3>;
426 status = "disabled";
427 };
429 macb0: ethernet@fffbc000 {
430 compatible = "cdns,at32ap7000-macb", "cdns,macb";
431 reg = <0xfffbc000 0x100>;
432 interrupts = <25 4 3>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_macb_rmii>;
435 status = "disabled";
436 };
438 i2c0: i2c@fff84000 {
439 compatible = "atmel,at91sam9g10-i2c";
440 reg = <0xfff84000 0x100>;
441 interrupts = <12 4 6>;
442 #address-cells = <1>;
443 #size-cells = <0>;
444 status = "disabled";
445 };
447 i2c1: i2c@fff88000 {
448 compatible = "atmel,at91sam9g10-i2c";
449 reg = <0xfff88000 0x100>;
450 interrupts = <13 4 6>;
451 #address-cells = <1>;
452 #size-cells = <0>;
453 status = "disabled";
454 };
456 ssc0: ssc@fff9c000 {
457 compatible = "atmel,at91sam9g45-ssc";
458 reg = <0xfff9c000 0x4000>;
459 interrupts = <16 4 5>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
462 status = "disabled";
463 };
465 ssc1: ssc@fffa0000 {
466 compatible = "atmel,at91sam9g45-ssc";
467 reg = <0xfffa0000 0x4000>;
468 interrupts = <17 4 5>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
471 status = "disabled";
472 };
474 adc0: adc@fffb0000 {
475 compatible = "atmel,at91sam9260-adc";
476 reg = <0xfffb0000 0x100>;
477 interrupts = <20 4 0>;
478 atmel,adc-use-external-triggers;
479 atmel,adc-channels-used = <0xff>;
480 atmel,adc-vref = <3300>;
481 atmel,adc-num-channels = <8>;
482 atmel,adc-startup-time = <40>;
483 atmel,adc-channel-base = <0x30>;
484 atmel,adc-drdy-mask = <0x10000>;
485 atmel,adc-status-register = <0x1c>;
486 atmel,adc-trigger-register = <0x08>;
488 trigger@0 {
489 trigger-name = "external-rising";
490 trigger-value = <0x1>;
491 trigger-external;
492 };
493 trigger@1 {
494 trigger-name = "external-falling";
495 trigger-value = <0x2>;
496 trigger-external;
497 };
499 trigger@2 {
500 trigger-name = "external-any";
501 trigger-value = <0x3>;
502 trigger-external;
503 };
505 trigger@3 {
506 trigger-name = "continuous";
507 trigger-value = <0x6>;
508 };
509 };
511 mmc0: mmc@fff80000 {
512 compatible = "atmel,hsmci";
513 reg = <0xfff80000 0x600>;
514 interrupts = <11 4 0>;
515 #address-cells = <1>;
516 #size-cells = <0>;
517 status = "disabled";
518 };
520 mmc1: mmc@fffd0000 {
521 compatible = "atmel,hsmci";
522 reg = <0xfffd0000 0x600>;
523 interrupts = <29 4 0>;
524 #address-cells = <1>;
525 #size-cells = <0>;
526 status = "disabled";
527 };
529 watchdog@fffffd40 {
530 compatible = "atmel,at91sam9260-wdt";
531 reg = <0xfffffd40 0x10>;
532 status = "disabled";
533 };
534 };
536 nand0: nand@40000000 {
537 compatible = "atmel,at91rm9200-nand";
538 #address-cells = <1>;
539 #size-cells = <1>;
540 reg = <0x40000000 0x10000000
541 0xffffe200 0x200
542 >;
543 atmel,nand-addr-offset = <21>;
544 atmel,nand-cmd-offset = <22>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_nand>;
547 gpios = <&pioC 8 0
548 &pioC 14 0
549 0
550 >;
551 status = "disabled";
552 };
554 usb0: ohci@00700000 {
555 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
556 reg = <0x00700000 0x100000>;
557 interrupts = <22 4 2>;
558 status = "disabled";
559 };
561 usb1: ehci@00800000 {
562 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
563 reg = <0x00800000 0x100000>;
564 interrupts = <22 4 2>;
565 status = "disabled";
566 };
567 };
569 i2c@0 {
570 compatible = "i2c-gpio";
571 gpios = <&pioA 20 0 /* sda */
572 &pioA 21 0 /* scl */
573 >;
574 i2c-gpio,sda-open-drain;
575 i2c-gpio,scl-open-drain;
576 i2c-gpio,delay-us = <5>; /* ~100 kHz */
577 #address-cells = <1>;
578 #size-cells = <0>;
579 status = "disabled";
580 };
581 };