Merge branch 'ti-linux-3.14.y' into p-ti-linux-3.14.y-common
[android-sdk/kernel-video.git] / arch / arm / boot / dts / dra7-evm.dts
1 /*
2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clk/ti-dra7-atl.h>
15 / {
16         model = "TI DRA742";
17         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
19         memory {
20                 device_type = "memory";
21                 reg = <0x80000000 0x60000000>; /* 1536 MB */
22         };
24         reserved-memory {
25                 #address-cells = <1>;
26                 #size-cells = <1>;
27                 ranges;
29                 ipu2_cma_pool: ipu2_cma@95800000 {
30                         compatible = "shared-dma-pool";
31                         reg = <0x95800000 0x3800000>;
32                         reusable;
33                         status = "okay";
34                 };
36                 dsp1_cma_pool: dsp1_cma@99000000 {
37                         compatible = "shared-dma-pool";
38                         reg = <0x99000000 0x4000000>;
39                         reusable;
40                         status = "okay";
41                 };
43                 ipu1_cma_pool: ipu1_cma@9d000000 {
44                         compatible = "shared-dma-pool";
45                         reg = <0x9d000000 0x2000000>;
46                         reusable;
47                         status = "okay";
48                 };
50                 dsp2_cma_pool: dsp2_cma@9f000000 {
51                         compatible = "shared-dma-pool";
52                         reg = <0x9f000000 0x800000>;
53                         reusable;
54                         status = "okay";
55                 };
57                 /* Required by cmem driver used by radio */
58                 cmem_radio: cmem@95400000 {
59                         reg = <0x95400000 0x400000>;
60                         no-map;
61                         status = "okay";
62                 };
63         };
65         extcon1: dra7x_usbid_extcon1 {
66                 compatible = "linux,extcon-gpio";
67                 gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_LOW>;
68                 cable-name = "USB-HOST";
69         };
71         extcon2: dra7x_usbid_extcon2 {
72                 compatible = "linux,extcon-gpio";
73                 gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_LOW>;
74                 cable-name = "USB-HOST";
75         };
77         evm_3v3_sd: fixedregulator-sd {
78                 compatible = "regulator-fixed";
79                 regulator-name = "evm_3v3_sd";
80                 regulator-min-microvolt = <3300000>;
81                 regulator-max-microvolt = <3300000>;
82                 enable-active-high;
83                 gpio = <&pcf_gpio_21 5 0>;
84         };
86         evm_3v3_sw: fixedregulator-evm_3v3_sw {
87                 compatible = "regulator-fixed";
88                 regulator-name = "evm_3v3_sw";
89                 vin-supply = <&sysen1>;
90                 regulator-min-microvolt = <3300000>;
91                 regulator-max-microvolt = <3300000>;
92         };
94         aic_dvdd: fixedregulator-aic_dvdd {
95                 /* TPS77018DBVT */
96                 compatible = "regulator-fixed";
97                 regulator-name = "aic_dvdd";
98                 vin-supply = <&evm_3v3_sw>;
99                 regulator-min-microvolt = <1800000>;
100                 regulator-max-microvolt = <1800000>;
101         };
103         vmmcwl_fixed: fixedregulator-mmcwl {
104                 compatible = "regulator-fixed";
105                 regulator-name = "vmmcwl_fixed";
106                 regulator-min-microvolt = <1800000>;
107                 regulator-max-microvolt = <1800000>;
108                 gpio = <&gpio5 8 0>;    /* gpio5_8 */
109                 startup-delay-us = <70000>;
110                 enable-active-high;
111         };
113         kim {
114                 compatible = "kim";
115                 nshutdown_gpio = <132>;
116                 dev_name = "/dev/ttyS2";
117                 flow_cntrl = <1>;
118                 baud_rate = <3686400>;
119         };
121         btwilink {
122                 compatible = "btwilink";
123         };
125         vtt_fixed: fixedregulator-vtt {
126                 compatible = "regulator-fixed";
127                 regulator-name = "vtt_fixed";
128                 regulator-min-microvolt = <1350000>;
129                 regulator-max-microvolt = <1350000>;
130                 regulator-always-on;
131                 regulator-boot-on;
132                 enable-active-high;
133                 vin-supply = <&sysen2>;
134                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
135         };
137         aliases {
138                 display0 = &hdmi0;
139                 sound0 = &primary_sound;
140                 sound1 = &hdmi;
141         };
143         hdmi0: connector@1 {
144                 compatible = "hdmi-connector";
145                 label = "hdmi";
147                 type = "a";
149                 port {
150                         hdmi_connector_in: endpoint {
151                                 remote-endpoint = <&tpd12s015_out>;
152                         };
153                 };
154         };
156         tpd12s015: encoder@1 {
157                 compatible = "ti,dra7evm-tpd12s015";
159                 gpios = <&pcf_hdmi 4 0>,        /* P4, CT CP HPD */
160                         <&pcf_hdmi 5 0>,        /* P5, LS OE */
161                         <&gpio7 12 0>;  /* gpio7_12/sp1_cs2, HPD */
163                 ports {
164                         #address-cells = <1>;
165                         #size-cells = <0>;
167                         port@0 {
168                                 reg = <0>;
170                                 tpd12s015_in: endpoint@0 {
171                                         remote-endpoint = <&hdmi_out>;
172                                 };
173                         };
175                         port@1 {
176                                 reg = <1>;
178                                 tpd12s015_out: endpoint@0 {
179                                         remote-endpoint = <&hdmi_connector_in>;
180                                 };
181                         };
182                 };
183         };
185     ocp {
186         gpu: gpu@0x56000000 {
187             gpu0-voltdm = <&voltdm_gpu>;
188         };
189     };
191         primary_sound: primary_sound {
192                 compatible = "ti,dra7xx-evm-audio";
193                 ti,model = "DRA7xx-EVM";
194                 ti,always-on;
195                 ti,audio-codec = <&tlv320aic3106>;
196                 ti,mcasp-controller = <&mcasp3>;
197                 ti,codec-clock-rate = <11289600>;
198                 clocks = <&atl_clkin2_ck>;
199                 clock-names = "mclk";
200                 ti,audio-routing =
201                         "Headphone Jack",       "HPLOUT",
202                         "Headphone Jack",       "HPROUT",
203                         "Line Out",             "LLOUT",
204                         "Line Out",             "RLOUT",
205                         "MIC3L",                "Mic Jack",
206                         "MIC3R",                "Mic Jack",
207                         "Mic Jack",             "Mic Bias",
208                         "LINE1L",               "Line In",
209                         "LINE1R",               "Line In";
210         };
212         radio {
213                 compatible = "ti,dra7xx_radio";
214                 gpios = <&gpio6 20 0>;
215         };
216 };
218 &dra7_pmx_core {
219         dcan1_pins_default: dcan1_pins_default {
220                 pinctrl-single,pins = <
221                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
222                         0x418   (PULL_UP | MUX_MODE1)           /* wakeup0.dcan1_rx */
223                 >;
224         };
226         dcan1_pins_sleep: dcan1_pins_sleep {
227                 pinctrl-single,pins = <
228                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
229                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
230                 >;
231         };
233         mmc1_pins_default: pinmux_mmc1_default_pins {
234                 pinctrl-single,pins = <
235                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_clk.clk */
236                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_cmd.cmd */
237                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat0.dat0 */
238                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat1.dat1 */
239                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat2.dat2 */
240                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat3.dat3 */
241                         0x36c (PIN_INPUT | MUX_MODE14)          /* mmc1sdcd.gpio187 */
242                 >;
243         };
245         mmc1_pins_hs: pinmux_mmc1_hs_pins {
246                 pinctrl-single,pins = <
247                         0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_clk.clk */
248                         0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_cmd.cmd */
249                         0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat0.dat0 */
250                         0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat1.dat1 */
251                         0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat2.dat2 */
252                         0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat3.dat3 */
253                 >;
254         };
256         mmc2_pins_default: mmc2_pins_default {
257                 pinctrl-single,pins = <
258                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
259                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
260                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
261                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
262                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
263                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
264                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
265                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
266                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
267                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
268                 >;
269         };
271         mmc2_pins_hs: pinmux_mmc2_hs_pins {
272                 pinctrl-single,pins = <
273                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
274                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
275                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
276                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
277                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
278                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
279                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
280                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
281                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
282                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
283                 >;
284         };
285 };
287 &i2c1 {
288         status = "okay";
289         clock-frequency = <400000>;
291         tps659038: tps659038@58 {
292                 compatible = "ti,tps659038";
293                 reg = <0x58>;
295                 tps659038_pmic {
296                         compatible = "ti,tps659038-pmic";
298                         regulators {
299                                 smps123_reg: smps123 {
300                                         /* VDD_MPU */
301                                         regulator-name = "smps123";
302                                         regulator-min-microvolt = < 850000>;
303                                         regulator-max-microvolt = <1250000>;
304                                         regulator-always-on;
305                                         regulator-boot-on;
306                                 };
308                                 smps45_reg: smps45 {
309                                         /* VDD_DSPEVE */
310                                         regulator-name = "smps45";
311                                         regulator-min-microvolt = < 850000>;
312                                         regulator-max-microvolt = <1150000>;
313                                         regulator-boot-on;
314                                         regulator-always-on;
315                                 };
317                                 smps6_reg: smps6 {
318                                         /* VDD_GPU - over VDD_SMPS6 */
319                                         regulator-name = "smps6";
320                                         regulator-min-microvolt = <850000>;
321                                         regulator-max-microvolt = <1250000>;
322                                         regulator-boot-on;
323                                         regulator-always-on;
324                                 };
326                                 smps7_reg: smps7 {
327                                         /* CORE_VDD */
328                                         regulator-name = "smps7";
329                                         regulator-min-microvolt = <850000>;
330                                         regulator-max-microvolt = <1060000>;
331                                         regulator-always-on;
332                                         regulator-boot-on;
333                                 };
335                                 smps8_reg: smps8 {
336                                         /* VDD_IVAHD */
337                                         regulator-name = "smps8";
338                                         regulator-min-microvolt = < 850000>;
339                                         regulator-max-microvolt = <1250000>;
340                                         regulator-boot-on;
341                                         regulator-always-on;
342                                 };
344                                 smps9_reg: smps9 {
345                                         /* VDDS1V8 */
346                                         regulator-name = "smps9";
347                                         regulator-min-microvolt = <1800000>;
348                                         regulator-max-microvolt = <1800000>;
349                                         regulator-always-on;
350                                         regulator-boot-on;
351                                 };
353                                 ldo1_reg: ldo1 {
354                                         /* LDO1_OUT --> SDIO  */
355                                         regulator-name = "ldo1";
356                                         regulator-min-microvolt = <1800000>;
357                                         regulator-max-microvolt = <3300000>;
358                                         regulator-boot-on;
359                                         regulator-always-on;
360                                 };
362                                 ldo2_reg: ldo2 {
363                                         /* VDD_RTCIO */
364                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
365                                         regulator-name = "ldo2";
366                                         regulator-min-microvolt = <3300000>;
367                                         regulator-max-microvolt = <3300000>;
368                                         regulator-boot-on;
369                                         regulator-always-on;
370                                 };
372                                 ldo3_reg: ldo3 {
373                                         /* VDDA_1V8_PHY */
374                                         regulator-name = "ldo3";
375                                         regulator-min-microvolt = <1800000>;
376                                         regulator-max-microvolt = <1800000>;
377                                         regulator-always-on;
378                                         regulator-boot-on;
379                                 };
381                                 ldo9_reg: ldo9 {
382                                         /* VDD_RTC */
383                                         regulator-name = "ldo9";
384                                         regulator-min-microvolt = <1050000>;
385                                         regulator-max-microvolt = <1050000>;
386                                         regulator-boot-on;
387                                         regulator-always-on;
388                                 };
390                                 ldoln_reg: ldoln {
391                                         /* VDDA_1V8_PLL */
392                                         regulator-name = "ldoln";
393                                         regulator-min-microvolt = <1800000>;
394                                         regulator-max-microvolt = <1800000>;
395                                         regulator-always-on;
396                                         regulator-boot-on;
397                                 };
399                                 ldousb_reg: ldousb {
400                                         /* VDDA_3V_USB: VDDA_USBHS33 */
401                                         regulator-name = "ldousb";
402                                         regulator-min-microvolt = <3300000>;
403                                         regulator-max-microvolt = <3300000>;
404                                         regulator-boot-on;
405                                         regulator-always-on;
406                                 };
408                                 /* REGEN1 is unused */
410                                 regen2: regen2 {
411                                         /* Needed for PMIC internal resources */
412                                         regulator-name = "regen2";
413                                         regulator-boot-on;
414                                         regulator-always-on;
415                                 };
417                                 /* REGEN3 is unused */
419                                 sysen1: sysen1 {
420                                         /* PMIC_REGEN_3V3 */
421                                         regulator-name = "sysen1";
422                                         regulator-boot-on;
423                                         regulator-always-on;
424                                 };
426                                 sysen2: sysen2 {
427                                         /* PMIC_REGEN_DDR */
428                                         regulator-name = "sysen2";
429                                         regulator-boot-on;
430                                         regulator-always-on;
431                                 };
432                         };
433                 };
434         };
436         pcf_lcd: gpio@20 {
437                 compatible = "nxp,pcf8575";
438                 reg = <0x20>;
439                 gpio-controller;
440                 #gpio-cells = <2>;
441         };
443         pcf_gpio_21: gpio@21 {
444                 compatible = "ti,pcf8575";
445                 reg = <0x21>;
446                 lines-initial-states = <0x1408>;
447                 gpio-controller;
448                 #gpio-cells = <2>;
449                 interrupt-parent = <&gpio6>;
450                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
451                 interrupt-controller;
452                 #interrupt-cells = <2>;
453         };
455         tlv320aic3106: tlv320aic3106@18 {
456                 compatible = "ti,tlv320aic3106";
457                 reg = <0x18>;
458                 adc-settle-ms = <40>;
459                 ai3x-micbias-vg = <1>;          /* 2.0V */
460                 status = "okay";
462                 /* Regulators */
463                 AVDD-supply = <&evm_3v3_sw>;
464                 IOVDD-supply = <&evm_3v3_sw>;
465                 DRVDD-supply = <&evm_3v3_sw>;
466                 DVDD-supply = <&aic_dvdd>;
467         };
468 };
470 &i2c2 {
471         status = "okay";
472         clock-frequency = <400000>;
474         pcf_hdmi: gpio@26 {
475                 compatible = "nxp,pcf8575";
476                 reg = <0x26>;
477                 lines-initial-states = <0xffeb>;
478                 gpio-controller;
479                 #gpio-cells = <2>;
480         };
481 };
483 &i2c3 {
484         status = "okay";
485         clock-frequency = <3400000>;
486 };
488 &mcspi1 {
489         status = "okay";
490 };
492 &mcspi2 {
493         status = "okay";
494 };
496 &uart1 {
497         status = "okay";
498         interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
499                                &dra7_pmx_core 0x3e0>;
500 };
502 &uart2 {
503         status = "okay";
504 };
506 &uart3 {
507         status = "okay";
508         gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
509 };
511 &mmc1 {
512         status = "okay";
513         pbias-supply = <&pbias_mmc_reg>;
514         vmmc-supply = <&evm_3v3_sd>;
515         vmmc_aux-supply = <&ldo1_reg>;
516         bus-width = <4>;
517         /*
518          * SDCD signal is not being used here - using the fact that GPIO mode
519          * is always hardwired.
520          */
521         cd-gpios = <&gpio6 27 0>;
522         pinctrl-names = "default", "hs";
523         pinctrl-0 = <&mmc1_pins_default>;
524         pinctrl-1 = <&mmc1_pins_hs>;
525 };
527 &mmc2 {
528         status = "okay";
529         vmmc-supply = <&evm_3v3_sw>;
530         bus-width = <8>;
531         pinctrl-names = "default", "hs";
532         pinctrl-0 = <&mmc2_pins_default>;
533         pinctrl-1 = <&mmc2_pins_hs>;
534 };
536 &mmc4 {
537         status = "okay";
538         vmmc-supply = <&vmmcwl_fixed>;
539         bus-width = <4>;
540         cap-power-off-card;
541         keep-power-in-suspend;
542         ti,non-removable;
544         #address-cells = <1>;
545         #size-cells = <0>;
546         wlcore: wlcore@0 {
547                 compatible = "ti,wlcore";
548                 reg = <2>;
549                 interrupt-parent = <&gpio5>;
550                 interrupts = <7 IRQ_TYPE_NONE>;
551         };
552 };
554 &cpu0 {
555         cpu0-voltdm = <&voltdm_mpu>;
556         voltage-tolerance = <1>;
557 };
559 &voltdm_mpu {
560         vdd-supply = <&smps123_reg>;
561 };
563 &voltdm_dspeve {
564         vdd-supply = <&smps45_reg>;
565 };
567 &voltdm_gpu {
568         vdd-supply = <&smps6_reg>;
569 };
571 &voltdm_ivahd {
572         vdd-supply = <&smps8_reg>;
573 };
575 &voltdm_core {
576         vdd-supply = <&smps7_reg>;
577 };
579 &qspi {
580         status = "okay";
582         spi-max-frequency = <48000000>;
583         m25p80@0 {
584                 compatible = "s25fl256s1";
585                 spi-max-frequency = <48000000>;
586                 reg = <0>;
587                 spi-tx-bus-width = <1>;
588                 spi-rx-bus-width = <4>;
589                 spi-cpol;
590                 spi-cpha;
591                 #address-cells = <1>;
592                 #size-cells = <1>;
594                 /* MTD partition table.
595                  * The ROM checks the first four physical blocks
596                  * for a valid file to boot and the flash here is
597                  * 64KiB block size.
598                  */
599                 partition@0 {
600                         label = "QSPI.SPL";
601                         reg = <0x00000000 0x000010000>;
602                 };
603                 partition@1 {
604                         label = "QSPI.SPL.backup1";
605                         reg = <0x00010000 0x00010000>;
606                 };
607                 partition@2 {
608                         label = "QSPI.SPL.backup2";
609                         reg = <0x00020000 0x00010000>;
610                 };
611                 partition@3 {
612                         label = "QSPI.SPL.backup3";
613                         reg = <0x00030000 0x00010000>;
614                 };
615                 partition@4 {
616                         label = "QSPI.u-boot";
617                         reg = <0x00040000 0x00100000>;
618                 };
619                 partition@5 {
620                         label = "QSPI.u-boot-spl-os";
621                         reg = <0x00140000 0x00080000>;
622                 };
623                 partition@6 {
624                         label = "QSPI.u-boot-env";
625                         reg = <0x001c0000 0x00010000>;
626                 };
627                 partition@7 {
628                         label = "QSPI.u-boot-env.backup1";
629                         reg = <0x001d0000 0x0010000>;
630                 };
631                 partition@8 {
632                         label = "QSPI.kernel";
633                         reg = <0x001e0000 0x0800000>;
634                 };
635                 partition@9 {
636                         label = "QSPI.file-system";
637                         reg = <0x009e0000 0x01620000>;
638                 };
639         };
640 };
642 &omap_dwc3_1 {
643         extcon = <&extcon1>;
644 };
646 &omap_dwc3_2 {
647         extcon = <&extcon2>;
648 };
650 &usb1 {
651         dr_mode = "peripheral";
652 };
654 &usb2 {
655         dr_mode = "host";
656 };
658 &mac {
659         status = "okay";
660         dual_emac;
661 };
663 &cpsw_emac0 {
664         phy_id = <&davinci_mdio>, <2>;
665         phy-mode = "rgmii";
666         dual_emac_res_vlan = <1>;
667 };
669 &cpsw_emac1 {
670         phy_id = <&davinci_mdio>, <3>;
671         phy-mode = "rgmii";
672         dual_emac_res_vlan = <2>;
673 };
675 &elm {
676         status = "okay";
677 };
679 &gpmc {
680         status = "disabled";
681         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
682         nand@0,0 {
683                 reg = <0 0 4>;          /* device IO registers */
684                 ti,nand-ecc-opt = "bch8";
685                 ti,elm-id = <&elm>;
686                 nand-bus-width = <16>;
687                 gpmc,device-width = <2>;
688                 gpmc,sync-clk-ps = <0>;
689                 gpmc,cs-on-ns = <0>;
690                 gpmc,cs-rd-off-ns = <80>;
691                 gpmc,cs-wr-off-ns = <80>;
692                 gpmc,adv-on-ns = <0>;
693                 gpmc,adv-rd-off-ns = <60>;
694                 gpmc,adv-wr-off-ns = <60>;
695                 gpmc,we-on-ns = <10>;
696                 gpmc,we-off-ns = <50>;
697                 gpmc,oe-on-ns = <4>;
698                 gpmc,oe-off-ns = <40>;
699                 gpmc,access-ns = <40>;
700                 gpmc,wr-access-ns = <80>;
701                 gpmc,rd-cycle-ns = <80>;
702                 gpmc,wr-cycle-ns = <80>;
703                 gpmc,bus-turnaround-ns = <0>;
704                 gpmc,cycle2cycle-delay-ns = <0>;
705                 gpmc,clk-activation-ns = <0>;
706                 gpmc,wait-monitoring-ns = <0>;
707                 gpmc,wr-data-mux-bus-ns = <0>;
708                 /* MTD partition table */
709                 /* All SPL-* partitions are sized to minimal length
710                  * which can be independently programmable. For
711                  * NAND flash this is equal to size of erase-block */
712                 #address-cells = <1>;
713                 #size-cells = <1>;
714                 partition@0 {
715                         label = "NAND.SPL";
716                         reg = <0x00000000 0x000020000>;
717                 };
718                 partition@1 {
719                         label = "NAND.SPL.backup1";
720                         reg = <0x00020000 0x00020000>;
721                 };
722                 partition@2 {
723                         label = "NAND.SPL.backup2";
724                         reg = <0x00040000 0x00020000>;
725                 };
726                 partition@3 {
727                         label = "NAND.SPL.backup3";
728                         reg = <0x00060000 0x00020000>;
729                 };
730                 partition@4 {
731                         label = "NAND.u-boot-spl-os";
732                         reg = <0x00080000 0x00040000>;
733                 };
734                 partition@5 {
735                         label = "NAND.u-boot";
736                         reg = <0x000c0000 0x00100000>;
737                 };
738                 partition@6 {
739                         label = "NAND.u-boot-env";
740                         reg = <0x001c0000 0x00020000>;
741                 };
742                 partition@7 {
743                         label = "NAND.u-boot-env.backup1";
744                         reg = <0x001e0000 0x00020000>;
745                 };
746                 partition@8 {
747                         label = "NAND.kernel";
748                         reg = <0x00200000 0x00800000>;
749                 };
750                 partition@9 {
751                         label = "NAND.file-system";
752                         reg = <0x00a00000 0x0f600000>;
753                 };
754         };
755 };
757 &gpio7 {
758         ti,no-reset-on-init;
759         ti,no-idle-on-init;
760 };
762 &dss {
763         status = "ok";
765         vdda_video-supply = <&ldoln_reg>;
766 };
768 &hdmi {
769         status = "ok";
770         vdda-supply = <&ldo3_reg>;
772         port {
773                 hdmi_out: endpoint {
774                         remote-endpoint = <&tpd12s015_in>;
775                 };
776         };
777 };
779 &dcan1 {
780         status = "ok";
781         pinctrl-names = "default", "sleep";
782         pinctrl-0 = <&dcan1_pins_default>;
783         pinctrl-1 = <&dcan1_pins_sleep>;
784 };
786 &mailbox5 {
787         status = "okay";
788         mbox_ipu1_legacy: mbox_ipu1_legacy {
789                 status = "okay";
790         };
791         mbox_dsp1_legacy: mbox_dsp1_legacy {
792                 status = "okay";
793         };
794 };
796 &mailbox6 {
797         status = "okay";
798         mbox_ipu2_legacy: mbox_ipu2_legacy {
799                 status = "okay";
800         };
801         mbox_dsp2_legacy: mbox_dsp2_legacy {
802                 status = "okay";
803         };
804 };
806 &mmu0_dsp1 {
807         status = "okay";
808 };
810 &mmu1_dsp1 {
811         status = "okay";
812 };
814 &mmu0_dsp2 {
815         status = "okay";
816 };
818 &mmu1_dsp2 {
819         status = "okay";
820 };
822 &mmu_ipu1 {
823         status = "okay";
824 };
826 &mmu_ipu2 {
827         status = "okay";
828 };
830 &ipu2 {
831         status = "okay";
832         memory-region = <&ipu2_cma_pool>;
833         mboxes = <&mailbox6 &mbox_ipu2_legacy>;
834         timers = <&timer3>;
835         watchdog-timers = <&timer4>, <&timer9>;
836 };
838 &ipu1 {
839         status = "okay";
840         memory-region = <&ipu1_cma_pool>;
841         mboxes = <&mailbox5 &mbox_ipu1_legacy>;
842         timers = <&timer11>;
843 };
845 &dsp1 {
846         status = "okay";
847         memory-region = <&dsp1_cma_pool>;
848         mboxes = <&mailbox5 &mbox_dsp1_legacy>;
849         timers = <&timer5>;
850 };
852 &dsp2 {
853         status = "okay";
854         memory-region = <&dsp2_cma_pool>;
855         mboxes = <&mailbox6 &mbox_dsp2_legacy>;
856         timers = <&timer6>;
857 };
859 &atl {
860         status = "okay";
862         atl1 {
863                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
864                 aws = <DRA7_ATL_WS_MCASP6_FSX>;
865         };
867         atl2 {
868                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
869                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
870         };
871 };
873 &mcasp2 {
874         fck_parent = "atl_clkin2_ck";
876         status = "okay";
878         op-mode = <0>;  /* MCASP_IIS_MODE */
879         tdm-slots = <2>;
880         /* 8 serializer */
881         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
882                 1 1 1 1 1 1 1 1
883         >;
884 };
886 &mcasp3 {
887         fck_parent = "atl_clkin2_ck";
889         status = "okay";
891         op-mode = <0>;          /* MCASP_IIS_MODE */
892         tdm-slots = <2>;
893         /* 4 serializer */
894         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
895                 1 2 0 0
896         >;
897 };
899 &mcasp6 {
900         fck_parent = "atl_clkin1_ck";
902         status = "okay";
904         op-mode = <0>;  /* MCASP_IIS_MODE */
905         tdm-slots = <8>;
906         /* 4 serializer */
907         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
908                 1 2 0 0
909         >;
910         tx-num-evt = <8>;
911         rx-num-evt = <8>;
912 };
914 &usb2_phy1 {
915         phy-supply = <&ldousb_reg>;
916 };
918 &usb2_phy2 {
919         phy-supply = <&ldousb_reg>;
920 };