TEMP: ARM: dts: dra7-evm: add i2c2 pinmux back in kernel
[android-sdk/kernel-video.git] / arch / arm / boot / dts / dra7-evm.dts
1 /*
2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clk/ti-dra7-atl.h>
15 / {
16         model = "TI DRA742";
17         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
19         memory {
20                 device_type = "memory";
21                 reg = <0x80000000 0x60000000>; /* 1536 MB */
22         };
24         reserved-memory {
25                 #address-cells = <1>;
26                 #size-cells = <1>;
27                 ranges;
29                 ipu2_cma_pool: ipu2_cma@95800000 {
30                         compatible = "shared-dma-pool";
31                         reg = <0x95800000 0x3800000>;
32                         reusable;
33                         status = "okay";
34                 };
36                 dsp1_cma_pool: dsp1_cma@99000000 {
37                         compatible = "shared-dma-pool";
38                         reg = <0x99000000 0x4000000>;
39                         reusable;
40                         status = "okay";
41                 };
43                 ipu1_cma_pool: ipu1_cma@9d000000 {
44                         compatible = "shared-dma-pool";
45                         reg = <0x9d000000 0x2000000>;
46                         reusable;
47                         status = "okay";
48                 };
50                 dsp2_cma_pool: dsp2_cma@9f000000 {
51                         compatible = "shared-dma-pool";
52                         reg = <0x9f000000 0x800000>;
53                         reusable;
54                         status = "okay";
55                 };
57                 /* Required by cmem driver used by radio */
58                 cmem_radio: cmem@95400000 {
59                         reg = <0x95400000 0x400000>;
60                         no-map;
61                         status = "okay";
62                 };
63         };
65         extcon1: dra7x_usbid_extcon1 {
66                 compatible = "linux,extcon-gpio";
67                 gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_LOW>;
68                 cable-name = "USB-HOST";
69         };
71         extcon2: dra7x_usbid_extcon2 {
72                 compatible = "linux,extcon-gpio";
73                 gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_LOW>;
74                 cable-name = "USB-HOST";
75         };
77         evm_3v3_sd: fixedregulator-sd {
78                 compatible = "regulator-fixed";
79                 regulator-name = "evm_3v3_sd";
80                 regulator-min-microvolt = <3300000>;
81                 regulator-max-microvolt = <3300000>;
82                 enable-active-high;
83                 gpio = <&pcf_gpio_21 5 0>;
84         };
86         evm_3v3_sw: fixedregulator-evm_3v3_sw {
87                 compatible = "regulator-fixed";
88                 regulator-name = "evm_3v3_sw";
89                 vin-supply = <&sysen1>;
90                 regulator-min-microvolt = <3300000>;
91                 regulator-max-microvolt = <3300000>;
92         };
94         aic_dvdd: fixedregulator-aic_dvdd {
95                 /* TPS77018DBVT */
96                 compatible = "regulator-fixed";
97                 regulator-name = "aic_dvdd";
98                 vin-supply = <&evm_3v3_sw>;
99                 regulator-min-microvolt = <1800000>;
100                 regulator-max-microvolt = <1800000>;
101         };
103         vmmcwl_fixed: fixedregulator-mmcwl {
104                 compatible = "regulator-fixed";
105                 regulator-name = "vmmcwl_fixed";
106                 regulator-min-microvolt = <1800000>;
107                 regulator-max-microvolt = <1800000>;
108                 gpio = <&gpio5 8 0>;    /* gpio5_8 */
109                 startup-delay-us = <70000>;
110                 enable-active-high;
111         };
113         kim {
114                 compatible = "kim";
115                 nshutdown_gpio = <132>;
116                 dev_name = "/dev/ttyS2";
117                 flow_cntrl = <1>;
118                 baud_rate = <3686400>;
119         };
121         btwilink {
122                 compatible = "btwilink";
123         };
125         vtt_fixed: fixedregulator-vtt {
126                 compatible = "regulator-fixed";
127                 regulator-name = "vtt_fixed";
128                 regulator-min-microvolt = <1350000>;
129                 regulator-max-microvolt = <1350000>;
130                 regulator-always-on;
131                 regulator-boot-on;
132                 enable-active-high;
133                 vin-supply = <&sysen2>;
134                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
135         };
137         aliases {
138                 display0 = &hdmi0;
139                 sound0 = &primary_sound;
140                 sound1 = &hdmi;
141         };
143         hdmi0: connector@1 {
144                 compatible = "hdmi-connector";
145                 label = "hdmi";
147                 type = "a";
149                 port {
150                         hdmi_connector_in: endpoint {
151                                 remote-endpoint = <&tpd12s015_out>;
152                         };
153                 };
154         };
156         tpd12s015: encoder@1 {
157                 compatible = "ti,dra7evm-tpd12s015";
159                 gpios = <&pcf_hdmi 4 0>,        /* P4, CT CP HPD */
160                         <&pcf_hdmi 5 0>,        /* P5, LS OE */
161                         <&gpio7 12 0>;  /* gpio7_12/sp1_cs2, HPD */
163                 ports {
164                         #address-cells = <1>;
165                         #size-cells = <0>;
167                         port@0 {
168                                 reg = <0>;
170                                 tpd12s015_in: endpoint@0 {
171                                         remote-endpoint = <&hdmi_out>;
172                                 };
173                         };
175                         port@1 {
176                                 reg = <1>;
178                                 tpd12s015_out: endpoint@0 {
179                                         remote-endpoint = <&hdmi_connector_in>;
180                                 };
181                         };
182                 };
183         };
185     ocp {
186         gpu: gpu@0x56000000 {
187             gpu0-voltdm = <&voltdm_gpu>;
188         };
189     };
191         primary_sound: primary_sound {
192                 compatible = "ti,dra7xx-evm-audio";
193                 ti,model = "DRA7xx-EVM";
194                 ti,always-on;
195                 ti,audio-codec = <&tlv320aic3106>;
196                 ti,mcasp-controller = <&mcasp3>;
197                 ti,codec-clock-rate = <11289600>;
198                 clocks = <&atl_clkin2_ck>;
199                 clock-names = "mclk";
200                 ti,audio-routing =
201                         "Headphone Jack",       "HPLOUT",
202                         "Headphone Jack",       "HPROUT",
203                         "Line Out",             "LLOUT",
204                         "Line Out",             "RLOUT",
205                         "MIC3L",                "Mic Jack",
206                         "MIC3R",                "Mic Jack",
207                         "Mic Jack",             "Mic Bias",
208                         "LINE1L",               "Line In",
209                         "LINE1R",               "Line In";
210         };
212         radio {
213                 compatible = "ti,dra7xx_radio";
214                 gpios = <&gpio6 20 0>;
215         };
216 };
218 &dra7_pmx_core {
219         i2c2_pins: pinmux_i2c2_pins {
220                 pinctrl-single,pins = <
221                         0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
222                         0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
223                 >;
224         };
226         dcan1_pins_default: dcan1_pins_default {
227                 pinctrl-single,pins = <
228                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
229                         0x418   (PULL_UP | MUX_MODE1)           /* wakeup0.dcan1_rx */
230                 >;
231         };
233         dcan1_pins_sleep: dcan1_pins_sleep {
234                 pinctrl-single,pins = <
235                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
236                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
237                 >;
238         };
240         mmc1_pins_default: pinmux_mmc1_default_pins {
241                 pinctrl-single,pins = <
242                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_clk.clk */
243                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_cmd.cmd */
244                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat0.dat0 */
245                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat1.dat1 */
246                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat2.dat2 */
247                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat3.dat3 */
248                         0x36c (PIN_INPUT | MUX_MODE14)          /* mmc1sdcd.gpio187 */
249                 >;
250         };
252         mmc1_pins_hs: pinmux_mmc1_hs_pins {
253                 pinctrl-single,pins = <
254                         0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_clk.clk */
255                         0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_cmd.cmd */
256                         0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat0.dat0 */
257                         0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat1.dat1 */
258                         0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat2.dat2 */
259                         0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat3.dat3 */
260                 >;
261         };
263         mmc2_pins_default: mmc2_pins_default {
264                 pinctrl-single,pins = <
265                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
266                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
267                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
268                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
269                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
270                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
271                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
272                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
273                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
274                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
275                 >;
276         };
278         mmc2_pins_hs: pinmux_mmc2_hs_pins {
279                 pinctrl-single,pins = <
280                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
281                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
282                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
283                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
284                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
285                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
286                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
287                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
288                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
289                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
290                 >;
291         };
292 };
294 &i2c1 {
295         status = "okay";
296         clock-frequency = <400000>;
298         tps659038: tps659038@58 {
299                 compatible = "ti,tps659038";
300                 reg = <0x58>;
302                 tps659038_pmic {
303                         compatible = "ti,tps659038-pmic";
305                         regulators {
306                                 smps123_reg: smps123 {
307                                         /* VDD_MPU */
308                                         regulator-name = "smps123";
309                                         regulator-min-microvolt = < 850000>;
310                                         regulator-max-microvolt = <1250000>;
311                                         regulator-always-on;
312                                         regulator-boot-on;
313                                 };
315                                 smps45_reg: smps45 {
316                                         /* VDD_DSPEVE */
317                                         regulator-name = "smps45";
318                                         regulator-min-microvolt = < 850000>;
319                                         regulator-max-microvolt = <1150000>;
320                                         regulator-boot-on;
321                                         regulator-always-on;
322                                 };
324                                 smps6_reg: smps6 {
325                                         /* VDD_GPU - over VDD_SMPS6 */
326                                         regulator-name = "smps6";
327                                         regulator-min-microvolt = <850000>;
328                                         regulator-max-microvolt = <1250000>;
329                                         regulator-boot-on;
330                                         regulator-always-on;
331                                 };
333                                 smps7_reg: smps7 {
334                                         /* CORE_VDD */
335                                         regulator-name = "smps7";
336                                         regulator-min-microvolt = <850000>;
337                                         regulator-max-microvolt = <1060000>;
338                                         regulator-always-on;
339                                         regulator-boot-on;
340                                 };
342                                 smps8_reg: smps8 {
343                                         /* VDD_IVAHD */
344                                         regulator-name = "smps8";
345                                         regulator-min-microvolt = < 850000>;
346                                         regulator-max-microvolt = <1250000>;
347                                         regulator-boot-on;
348                                         regulator-always-on;
349                                 };
351                                 smps9_reg: smps9 {
352                                         /* VDDS1V8 */
353                                         regulator-name = "smps9";
354                                         regulator-min-microvolt = <1800000>;
355                                         regulator-max-microvolt = <1800000>;
356                                         regulator-always-on;
357                                         regulator-boot-on;
358                                 };
360                                 ldo1_reg: ldo1 {
361                                         /* LDO1_OUT --> SDIO  */
362                                         regulator-name = "ldo1";
363                                         regulator-min-microvolt = <1800000>;
364                                         regulator-max-microvolt = <3300000>;
365                                         regulator-boot-on;
366                                         regulator-always-on;
367                                 };
369                                 ldo2_reg: ldo2 {
370                                         /* VDD_RTCIO */
371                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
372                                         regulator-name = "ldo2";
373                                         regulator-min-microvolt = <3300000>;
374                                         regulator-max-microvolt = <3300000>;
375                                         regulator-boot-on;
376                                         regulator-always-on;
377                                 };
379                                 ldo3_reg: ldo3 {
380                                         /* VDDA_1V8_PHY */
381                                         regulator-name = "ldo3";
382                                         regulator-min-microvolt = <1800000>;
383                                         regulator-max-microvolt = <1800000>;
384                                         regulator-always-on;
385                                         regulator-boot-on;
386                                 };
388                                 ldo9_reg: ldo9 {
389                                         /* VDD_RTC */
390                                         regulator-name = "ldo9";
391                                         regulator-min-microvolt = <1050000>;
392                                         regulator-max-microvolt = <1050000>;
393                                         regulator-boot-on;
394                                         regulator-always-on;
395                                 };
397                                 ldoln_reg: ldoln {
398                                         /* VDDA_1V8_PLL */
399                                         regulator-name = "ldoln";
400                                         regulator-min-microvolt = <1800000>;
401                                         regulator-max-microvolt = <1800000>;
402                                         regulator-always-on;
403                                         regulator-boot-on;
404                                 };
406                                 ldousb_reg: ldousb {
407                                         /* VDDA_3V_USB: VDDA_USBHS33 */
408                                         regulator-name = "ldousb";
409                                         regulator-min-microvolt = <3300000>;
410                                         regulator-max-microvolt = <3300000>;
411                                         regulator-boot-on;
412                                         regulator-always-on;
413                                 };
415                                 /* REGEN1 is unused */
417                                 regen2: regen2 {
418                                         /* Needed for PMIC internal resources */
419                                         regulator-name = "regen2";
420                                         regulator-boot-on;
421                                         regulator-always-on;
422                                 };
424                                 /* REGEN3 is unused */
426                                 sysen1: sysen1 {
427                                         /* PMIC_REGEN_3V3 */
428                                         regulator-name = "sysen1";
429                                         regulator-boot-on;
430                                         regulator-always-on;
431                                 };
433                                 sysen2: sysen2 {
434                                         /* PMIC_REGEN_DDR */
435                                         regulator-name = "sysen2";
436                                         regulator-boot-on;
437                                         regulator-always-on;
438                                 };
439                         };
440                 };
441         };
443         pcf_lcd: gpio@20 {
444                 compatible = "nxp,pcf8575";
445                 reg = <0x20>;
446                 gpio-controller;
447                 #gpio-cells = <2>;
448         };
450         pcf_gpio_21: gpio@21 {
451                 compatible = "ti,pcf8575";
452                 reg = <0x21>;
453                 lines-initial-states = <0x1408>;
454                 gpio-controller;
455                 #gpio-cells = <2>;
456                 interrupt-parent = <&gpio6>;
457                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
458                 interrupt-controller;
459                 #interrupt-cells = <2>;
460         };
462         tlv320aic3106: tlv320aic3106@18 {
463                 compatible = "ti,tlv320aic3106";
464                 reg = <0x18>;
465                 adc-settle-ms = <40>;
466                 ai3x-micbias-vg = <1>;          /* 2.0V */
467                 status = "okay";
469                 /* Regulators */
470                 AVDD-supply = <&evm_3v3_sw>;
471                 IOVDD-supply = <&evm_3v3_sw>;
472                 DRVDD-supply = <&evm_3v3_sw>;
473                 DVDD-supply = <&aic_dvdd>;
474         };
475 };
477 &i2c2 {
478         status = "okay";
479         pinctrl-names = "default";
480         pinctrl-0 = <&i2c2_pins>;
481         clock-frequency = <400000>;
483         pcf_hdmi: gpio@26 {
484                 compatible = "nxp,pcf8575";
485                 reg = <0x26>;
486                 lines-initial-states = <0xffeb>;
487                 gpio-controller;
488                 #gpio-cells = <2>;
489         };
490 };
492 &i2c3 {
493         status = "okay";
494         clock-frequency = <3400000>;
495 };
497 &mcspi1 {
498         status = "okay";
499 };
501 &mcspi2 {
502         status = "okay";
503 };
505 &uart1 {
506         status = "okay";
507         interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
508                                &dra7_pmx_core 0x3e0>;
509 };
511 &uart2 {
512         status = "okay";
513 };
515 &uart3 {
516         status = "okay";
517         gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
518 };
520 &mmc1 {
521         status = "okay";
522         pbias-supply = <&pbias_mmc_reg>;
523         vmmc-supply = <&evm_3v3_sd>;
524         vmmc_aux-supply = <&ldo1_reg>;
525         bus-width = <4>;
526         /*
527          * SDCD signal is not being used here - using the fact that GPIO mode
528          * is always hardwired.
529          */
530         cd-gpios = <&gpio6 27 0>;
531         pinctrl-names = "default", "hs";
532         pinctrl-0 = <&mmc1_pins_default>;
533         pinctrl-1 = <&mmc1_pins_hs>;
534 };
536 &mmc2 {
537         status = "okay";
538         vmmc-supply = <&evm_3v3_sw>;
539         bus-width = <8>;
540         pinctrl-names = "default", "hs";
541         pinctrl-0 = <&mmc2_pins_default>;
542         pinctrl-1 = <&mmc2_pins_hs>;
543 };
545 &mmc4 {
546         status = "okay";
547         vmmc-supply = <&vmmcwl_fixed>;
548         bus-width = <4>;
549         cap-power-off-card;
550         keep-power-in-suspend;
551         ti,non-removable;
553         #address-cells = <1>;
554         #size-cells = <0>;
555         wlcore: wlcore@0 {
556                 compatible = "ti,wlcore";
557                 reg = <2>;
558                 interrupt-parent = <&gpio5>;
559                 interrupts = <7 IRQ_TYPE_NONE>;
560         };
561 };
563 &cpu0 {
564         cpu0-voltdm = <&voltdm_mpu>;
565         voltage-tolerance = <1>;
566 };
568 &voltdm_mpu {
569         vdd-supply = <&smps123_reg>;
570 };
572 &voltdm_dspeve {
573         vdd-supply = <&smps45_reg>;
574 };
576 &voltdm_gpu {
577         vdd-supply = <&smps6_reg>;
578 };
580 &voltdm_ivahd {
581         vdd-supply = <&smps8_reg>;
582 };
584 &voltdm_core {
585         vdd-supply = <&smps7_reg>;
586 };
588 &qspi {
589         status = "okay";
591         spi-max-frequency = <48000000>;
592         m25p80@0 {
593                 compatible = "s25fl256s1";
594                 spi-max-frequency = <48000000>;
595                 reg = <0>;
596                 spi-tx-bus-width = <1>;
597                 spi-rx-bus-width = <4>;
598                 spi-cpol;
599                 spi-cpha;
600                 #address-cells = <1>;
601                 #size-cells = <1>;
603                 /* MTD partition table.
604                  * The ROM checks the first four physical blocks
605                  * for a valid file to boot and the flash here is
606                  * 64KiB block size.
607                  */
608                 partition@0 {
609                         label = "QSPI.SPL";
610                         reg = <0x00000000 0x000010000>;
611                 };
612                 partition@1 {
613                         label = "QSPI.SPL.backup1";
614                         reg = <0x00010000 0x00010000>;
615                 };
616                 partition@2 {
617                         label = "QSPI.SPL.backup2";
618                         reg = <0x00020000 0x00010000>;
619                 };
620                 partition@3 {
621                         label = "QSPI.SPL.backup3";
622                         reg = <0x00030000 0x00010000>;
623                 };
624                 partition@4 {
625                         label = "QSPI.u-boot";
626                         reg = <0x00040000 0x00100000>;
627                 };
628                 partition@5 {
629                         label = "QSPI.u-boot-spl-os";
630                         reg = <0x00140000 0x00080000>;
631                 };
632                 partition@6 {
633                         label = "QSPI.u-boot-env";
634                         reg = <0x001c0000 0x00010000>;
635                 };
636                 partition@7 {
637                         label = "QSPI.u-boot-env.backup1";
638                         reg = <0x001d0000 0x0010000>;
639                 };
640                 partition@8 {
641                         label = "QSPI.kernel";
642                         reg = <0x001e0000 0x0800000>;
643                 };
644                 partition@9 {
645                         label = "QSPI.file-system";
646                         reg = <0x009e0000 0x01620000>;
647                 };
648         };
649 };
651 &omap_dwc3_1 {
652         extcon = <&extcon1>;
653 };
655 &omap_dwc3_2 {
656         extcon = <&extcon2>;
657 };
659 &usb1 {
660         dr_mode = "peripheral";
661 };
663 &usb2 {
664         dr_mode = "host";
665 };
667 &mac {
668         status = "okay";
669         dual_emac;
670 };
672 &cpsw_emac0 {
673         phy_id = <&davinci_mdio>, <2>;
674         phy-mode = "rgmii";
675         dual_emac_res_vlan = <1>;
676 };
678 &cpsw_emac1 {
679         phy_id = <&davinci_mdio>, <3>;
680         phy-mode = "rgmii";
681         dual_emac_res_vlan = <2>;
682 };
684 &elm {
685         status = "okay";
686 };
688 &gpmc {
689         status = "disabled";
690         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
691         nand@0,0 {
692                 reg = <0 0 4>;          /* device IO registers */
693                 ti,nand-ecc-opt = "bch8";
694                 ti,elm-id = <&elm>;
695                 nand-bus-width = <16>;
696                 gpmc,device-width = <2>;
697                 gpmc,sync-clk-ps = <0>;
698                 gpmc,cs-on-ns = <0>;
699                 gpmc,cs-rd-off-ns = <80>;
700                 gpmc,cs-wr-off-ns = <80>;
701                 gpmc,adv-on-ns = <0>;
702                 gpmc,adv-rd-off-ns = <60>;
703                 gpmc,adv-wr-off-ns = <60>;
704                 gpmc,we-on-ns = <10>;
705                 gpmc,we-off-ns = <50>;
706                 gpmc,oe-on-ns = <4>;
707                 gpmc,oe-off-ns = <40>;
708                 gpmc,access-ns = <40>;
709                 gpmc,wr-access-ns = <80>;
710                 gpmc,rd-cycle-ns = <80>;
711                 gpmc,wr-cycle-ns = <80>;
712                 gpmc,bus-turnaround-ns = <0>;
713                 gpmc,cycle2cycle-delay-ns = <0>;
714                 gpmc,clk-activation-ns = <0>;
715                 gpmc,wait-monitoring-ns = <0>;
716                 gpmc,wr-data-mux-bus-ns = <0>;
717                 /* MTD partition table */
718                 /* All SPL-* partitions are sized to minimal length
719                  * which can be independently programmable. For
720                  * NAND flash this is equal to size of erase-block */
721                 #address-cells = <1>;
722                 #size-cells = <1>;
723                 partition@0 {
724                         label = "NAND.SPL";
725                         reg = <0x00000000 0x000020000>;
726                 };
727                 partition@1 {
728                         label = "NAND.SPL.backup1";
729                         reg = <0x00020000 0x00020000>;
730                 };
731                 partition@2 {
732                         label = "NAND.SPL.backup2";
733                         reg = <0x00040000 0x00020000>;
734                 };
735                 partition@3 {
736                         label = "NAND.SPL.backup3";
737                         reg = <0x00060000 0x00020000>;
738                 };
739                 partition@4 {
740                         label = "NAND.u-boot-spl-os";
741                         reg = <0x00080000 0x00040000>;
742                 };
743                 partition@5 {
744                         label = "NAND.u-boot";
745                         reg = <0x000c0000 0x00100000>;
746                 };
747                 partition@6 {
748                         label = "NAND.u-boot-env";
749                         reg = <0x001c0000 0x00020000>;
750                 };
751                 partition@7 {
752                         label = "NAND.u-boot-env.backup1";
753                         reg = <0x001e0000 0x00020000>;
754                 };
755                 partition@8 {
756                         label = "NAND.kernel";
757                         reg = <0x00200000 0x00800000>;
758                 };
759                 partition@9 {
760                         label = "NAND.file-system";
761                         reg = <0x00a00000 0x0f600000>;
762                 };
763         };
764 };
766 &gpio7 {
767         ti,no-reset-on-init;
768         ti,no-idle-on-init;
769 };
771 &dss {
772         status = "ok";
774         vdda_video-supply = <&ldoln_reg>;
775 };
777 &hdmi {
778         status = "ok";
779         vdda-supply = <&ldo3_reg>;
781         port {
782                 hdmi_out: endpoint {
783                         remote-endpoint = <&tpd12s015_in>;
784                 };
785         };
786 };
788 &dcan1 {
789         status = "ok";
790         pinctrl-names = "default", "sleep";
791         pinctrl-0 = <&dcan1_pins_default>;
792         pinctrl-1 = <&dcan1_pins_sleep>;
793 };
795 &mailbox5 {
796         status = "okay";
797         mbox_ipu1_legacy: mbox_ipu1_legacy {
798                 status = "okay";
799         };
800         mbox_dsp1_legacy: mbox_dsp1_legacy {
801                 status = "okay";
802         };
803 };
805 &mailbox6 {
806         status = "okay";
807         mbox_ipu2_legacy: mbox_ipu2_legacy {
808                 status = "okay";
809         };
810         mbox_dsp2_legacy: mbox_dsp2_legacy {
811                 status = "okay";
812         };
813 };
815 &mmu0_dsp1 {
816         status = "okay";
817 };
819 &mmu1_dsp1 {
820         status = "okay";
821 };
823 &mmu0_dsp2 {
824         status = "okay";
825 };
827 &mmu1_dsp2 {
828         status = "okay";
829 };
831 &mmu_ipu1 {
832         status = "okay";
833 };
835 &mmu_ipu2 {
836         status = "okay";
837 };
839 &ipu2 {
840         status = "okay";
841         memory-region = <&ipu2_cma_pool>;
842         mboxes = <&mailbox6 &mbox_ipu2_legacy>;
843         timers = <&timer3>;
844         watchdog-timers = <&timer4>, <&timer9>;
845 };
847 &ipu1 {
848         status = "okay";
849         memory-region = <&ipu1_cma_pool>;
850         mboxes = <&mailbox5 &mbox_ipu1_legacy>;
851         timers = <&timer11>;
852 };
854 &dsp1 {
855         status = "okay";
856         memory-region = <&dsp1_cma_pool>;
857         mboxes = <&mailbox5 &mbox_dsp1_legacy>;
858         timers = <&timer5>;
859 };
861 &dsp2 {
862         status = "okay";
863         memory-region = <&dsp2_cma_pool>;
864         mboxes = <&mailbox6 &mbox_dsp2_legacy>;
865         timers = <&timer6>;
866 };
868 &atl {
869         status = "okay";
871         atl1 {
872                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
873                 aws = <DRA7_ATL_WS_MCASP6_FSX>;
874         };
876         atl2 {
877                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
878                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
879         };
880 };
882 &mcasp2 {
883         fck_parent = "atl_clkin2_ck";
885         status = "okay";
887         op-mode = <0>;  /* MCASP_IIS_MODE */
888         tdm-slots = <2>;
889         /* 8 serializer */
890         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
891                 1 1 1 1 1 1 1 1
892         >;
893 };
895 &mcasp3 {
896         fck_parent = "atl_clkin2_ck";
898         status = "okay";
900         op-mode = <0>;          /* MCASP_IIS_MODE */
901         tdm-slots = <2>;
902         /* 4 serializer */
903         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
904                 1 2 0 0
905         >;
906 };
908 &mcasp6 {
909         fck_parent = "atl_clkin1_ck";
911         status = "okay";
913         op-mode = <0>;  /* MCASP_IIS_MODE */
914         tdm-slots = <8>;
915         /* 4 serializer */
916         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
917                 1 2 0 0
918         >;
919         tx-num-evt = <8>;
920         rx-num-evt = <8>;
921 };
923 &usb2_phy1 {
924         phy-supply = <&ldousb_reg>;
925 };
927 &usb2_phy2 {
928         phy-supply = <&ldousb_reg>;
929 };