Merge branch 'p-ti-linux-3.14.y-common' into p-ti-linux-3.14.y-android
[android-sdk/kernel-video.git] / arch / arm / boot / dts / dra7-evm.dts
1 /*
2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clk/ti-dra7-atl.h>
15 / {
16         model = "TI DRA742";
17         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
19         memory {
20                 device_type = "memory";
21                 reg = <0x80000000 0x60000000>; /* 1536 MB */
22         };
24         reserved_mem: reserved-memory {
25                 #address-cells = <1>;
26                 #size-cells = <1>;
27                 ranges;
29                 ipu2_cma_pool: ipu2_cma@95800000 {
30                         compatible = "shared-dma-pool";
31                         reg = <0x95800000 0x3800000>;
32                         reusable;
33                         status = "okay";
34                 };
36                 dsp1_cma_pool: dsp1_cma@99000000 {
37                         compatible = "shared-dma-pool";
38                         reg = <0x99000000 0x4000000>;
39                         reusable;
40                         status = "okay";
41                 };
43                 ipu1_cma_pool: ipu1_cma@9d000000 {
44                         compatible = "shared-dma-pool";
45                         reg = <0x9d000000 0x2000000>;
46                         reusable;
47                         status = "okay";
48                 };
50                 dsp2_cma_pool: dsp2_cma@9f000000 {
51                         compatible = "shared-dma-pool";
52                         reg = <0x9f000000 0x800000>;
53                         reusable;
54                         status = "okay";
55                 };
56         };
58         extcon_usb1: extcon_usb1 {
59                 compatible = "linux,extcon-usb-gpio";
60                 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
61         };
63         extcon_usb2: extcon_usb2 {
64                 compatible = "linux,extcon-usb-gpio";
65                 id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
66         };
68         evm_3v3_sd: fixedregulator-sd {
69                 compatible = "regulator-fixed";
70                 regulator-name = "evm_3v3_sd";
71                 regulator-min-microvolt = <3300000>;
72                 regulator-max-microvolt = <3300000>;
73                 enable-active-high;
74                 gpio = <&pcf_gpio_21 5 0>;
75         };
77         evm_3v3_sw: fixedregulator-evm_3v3_sw {
78                 compatible = "regulator-fixed";
79                 regulator-name = "evm_3v3_sw";
80                 vin-supply = <&sysen1>;
81                 regulator-min-microvolt = <3300000>;
82                 regulator-max-microvolt = <3300000>;
83         };
85         aic_dvdd: fixedregulator-aic_dvdd {
86                 /* TPS77018DBVT */
87                 compatible = "regulator-fixed";
88                 regulator-name = "aic_dvdd";
89                 vin-supply = <&evm_3v3_sw>;
90                 regulator-min-microvolt = <1800000>;
91                 regulator-max-microvolt = <1800000>;
92         };
94         vmmcwl_fixed: fixedregulator-mmcwl {
95                 compatible = "regulator-fixed";
96                 regulator-name = "vmmcwl_fixed";
97                 regulator-min-microvolt = <1800000>;
98                 regulator-max-microvolt = <1800000>;
99                 gpio = <&gpio5 8 0>;    /* gpio5_8 */
100                 startup-delay-us = <70000>;
101                 enable-active-high;
102         };
104         kim {
105                 compatible = "kim";
106                 nshutdown_gpio = <132>;
107                 dev_name = "/dev/ttyS2";
108                 flow_cntrl = <1>;
109                 baud_rate = <3686400>;
110         };
112         btwilink {
113                 compatible = "btwilink";
114         };
116         vtt_fixed: fixedregulator-vtt {
117                 compatible = "regulator-fixed";
118                 regulator-name = "vtt_fixed";
119                 regulator-min-microvolt = <1350000>;
120                 regulator-max-microvolt = <1350000>;
121                 regulator-always-on;
122                 regulator-boot-on;
123                 enable-active-high;
124                 vin-supply = <&sysen2>;
125                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
126         };
128         aliases {
129                 display0 = &hdmi0;
130                 sound0 = &primary_sound;
131                 sound1 = &hdmi;
132         };
134         hdmi0: connector@1 {
135                 compatible = "hdmi-connector";
136                 label = "hdmi";
138                 type = "a";
140                 port {
141                         hdmi_connector_in: endpoint {
142                                 remote-endpoint = <&tpd12s015_out>;
143                         };
144                 };
145         };
147         tpd12s015: encoder@1 {
148                 compatible = "ti,dra7evm-tpd12s015";
150                 gpios = <&pcf_hdmi 4 0>,        /* P4, CT CP HPD */
151                         <&pcf_hdmi 5 0>,        /* P5, LS OE */
152                         <&gpio7 12 0>;  /* gpio7_12/sp1_cs2, HPD */
154                 ports {
155                         #address-cells = <1>;
156                         #size-cells = <0>;
158                         port@0 {
159                                 reg = <0>;
161                                 tpd12s015_in: endpoint@0 {
162                                         remote-endpoint = <&hdmi_out>;
163                                 };
164                         };
166                         port@1 {
167                                 reg = <1>;
169                                 tpd12s015_out: endpoint@0 {
170                                         remote-endpoint = <&hdmi_connector_in>;
171                                 };
172                         };
173                 };
174         };
176     ocp {
177         gpu: gpu@0x56000000 {
178             gpu0-voltdm = <&voltdm_gpu>;
179         };
180     };
182         primary_sound: primary_sound {
183                 compatible = "ti,dra7xx-evm-audio";
184                 ti,model = "DRA7xx-EVM";
185                 ti,always-on;
186                 ti,audio-codec = <&tlv320aic3106>;
187                 ti,mcasp-controller = <&mcasp3>;
188                 ti,codec-clock-rate = <11289600>;
189                 clocks = <&atl_clkin2_ck>;
190                 clock-names = "mclk";
191                 ti,audio-routing =
192                         "Headphone Jack",       "HPLOUT",
193                         "Headphone Jack",       "HPROUT",
194                         "Line Out",             "LLOUT",
195                         "Line Out",             "RLOUT",
196                         "MIC3L",                "Mic Jack",
197                         "MIC3R",                "Mic Jack",
198                         "Mic Jack",             "Mic Bias",
199                         "LINE1L",               "Line In",
200                         "LINE1R",               "Line In";
201         };
203         btwilink_sound: btwilink_sound {
204                 #sound-dai-cells = <0>;
205                 compatible = "linux,bt-sco-audio";
206                 status = "okay";
207         };
209         simple_bt_sco_card: bt_sco_card {
210                 compatible = "simple-audio-card";
211                 simple-audio-card,name = "DRA7xx-WiLink";
212                 simple-audio-card,format = "dsp_a";
213                 simple-audio-card,frame-master = <&btwilink_codec>;
214                 simple-audio-card,bitclock-master = <&btwilink_codec>;
215                 simple-audio-card,frame-inversion;
217                 simple-audio-card,cpu {
218                         sound-dai = <&mcasp7>;
219                 };
221                 btwilink_codec: simple-audio-card,codec {
222                         sound-dai = <&btwilink_sound>;
223                 };
224         };
225 };
227 &dra7_pmx_core {
228         dcan1_pins_default: dcan1_pins_default {
229                 pinctrl-single,pins = <
230                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
231                         0x418   (PULL_UP | MUX_MODE1)           /* wakeup0.dcan1_rx */
232                 >;
233         };
235         dcan1_pins_sleep: dcan1_pins_sleep {
236                 pinctrl-single,pins = <
237                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
238                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
239                 >;
240         };
242         mmc1_pins_default: pinmux_mmc1_default_pins {
243                 pinctrl-single,pins = <
244                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_clk.clk */
245                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_cmd.cmd */
246                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat0.dat0 */
247                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat1.dat1 */
248                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat2.dat2 */
249                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat3.dat3 */
250                         0x36c (PIN_INPUT | MUX_MODE14)          /* mmc1sdcd.gpio187 */
251                 >;
252         };
254         mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
255                 pinctrl-single,pins = <
256                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_clk.clk */
257                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_cmd.cmd */
258                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat0.dat0 */
259                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat1.dat1 */
260                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat2.dat2 */
261                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat3.dat3 */
262                 >;
263         };
265         mmc1_pins_hs: pinmux_mmc1_hs_pins {
266                 pinctrl-single,pins = <
267                         0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_clk.clk */
268                         0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_cmd.cmd */
269                         0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat0.dat0 */
270                         0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat1.dat1 */
271                         0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat2.dat2 */
272                         0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat3.dat3 */
273                 >;
274         };
276         mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
277                 pinctrl-single,pins = <
278                         0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_clk.clk */
279                         0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_cmd.cmd */
280                         0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat0.dat0 */
281                         0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat1.dat1 */
282                         0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat2.dat2 */
283                         0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat3.dat3 */
284                 >;
285         };
287         mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
288                 pinctrl-single,pins = <
289                         0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_clk.clk */
290                         0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_cmd.cmd */
291                         0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_dat0.dat0 */
292                         0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_dat1.dat1 */
293                         0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_dat2.dat2 */
294                         0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_dat3.dat3 */
295                 >;
296         };
298         mmc2_pins_default: mmc2_pins_default {
299                 pinctrl-single,pins = <
300                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
301                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
302                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
303                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
304                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
305                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
306                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
307                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
308                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
309                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
310                 >;
311         };
313         mmc2_pins_hs: pinmux_mmc2_hs_pins {
314                 pinctrl-single,pins = <
315                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
316                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
317                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
318                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
319                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
320                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
321                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
322                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
323                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
324                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
325                 >;
326         };
328         mmc2_pins_ddr_3_3v: pinmux_mmc2_ddr_3_3v_pins {
329                 pinctrl-single,pins = <
330                         0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
331                         0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
332                         0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
333                         0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
334                         0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
335                         0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
336                         0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
337                         0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
338                         0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
339                         0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
340                 >;
341         };
342 };
344 &dra7_iodelay_core {
345         mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
346                 pinctrl-single,pins = <
347                         0x618 (A_DELAY(572) | G_DELAY(540))     /* CFG_MMC1_CLK_IN */
348                         0x624 (A_DELAY(0) | G_DELAY(600))       /* CFG_MMC1_CMD_IN */
349                         0x630 (A_DELAY(403) | G_DELAY(120))     /* CFG_MMC1_DAT0_IN */
350                         0x63c (A_DELAY(23) | G_DELAY(60))       /* CFG_MMC1_DAT1_IN */
351                         0x648 (A_DELAY(25) | G_DELAY(60))       /* CFG_MMC1_DAT2_IN */
352                         0x654 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT3_IN */
353                         0x620 (A_DELAY(1525) | G_DELAY(0))      /* CFG_MMC1_CLK_IN */
354                         0x628 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_CMD_OEN */
355                         0x62c (A_DELAY(55) | G_DELAY(0))        /* CFG_MMC1_CMD_OUT */
356                         0x634 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT0_OEN */
357                         0x638 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT0_OUT */
358                         0x640 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT1_OEN */
359                         0x644 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT1_OUT */
360                         0x64c (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT2_OEN */
361                         0x650 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT2_OUT */
362                         0x658 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT3_OEN */
363                         0x65c (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT3_OUT */
364                 >;
365         };
367         mmc2_iodelay_ddr_3_3v_conf: mmc2_iodelay_ddr_3_3v_conf {
368                 pinctrl-single,pins = <
369                         0x18c (A_DELAY(0) | G_DELAY(120))       /* CFG_GPMC_A19_IN */
370                         0x1a4 (A_DELAY(265) | G_DELAY(360))     /* CFG_GPMC_A20_IN */
371                         0x1b0 (A_DELAY(0) | G_DELAY(120))       /* CFG_GPMC_A21_IN */
372                         0x1bc (A_DELAY(0) | G_DELAY(120))       /* CFG_GPMC_A22_IN */
373                         0x1c8 (A_DELAY(287) | G_DELAY(420))     /* CFG_GPMC_A23_IN */
374                         0x1d4 (A_DELAY(144) | G_DELAY(240))     /* CFG_GPMC_A24_IN */
375                         0x1e0 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A25_IN */
376                         0x1ec (A_DELAY(0) | G_DELAY(120))       /* CFG_GPMC_A26_IN */
377                         0x1f8 (A_DELAY(120) | G_DELAY(180))     /* CFG_GPMC_A27_IN */
378                         0x360 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_CS1_IN */
379                         0x190 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A19_OEN */
380                         0x194 (A_DELAY(174) | G_DELAY(0))       /* CFG_GPMC_A19_OUT */
381                         0x1a8 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A20_OEN */
382                         0x1ac (A_DELAY(168) | G_DELAY(0))       /* CFG_GPMC_A20_OUT */
383                         0x1b4 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A21_OEN */
384                         0x1b8 (A_DELAY(136) | G_DELAY(0))       /* CFG_GPMC_A21_OUT */
385                         0x1c0 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A22_OEN */
386                         0x1c4 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A22_OUT */
387                         0x1d0 (A_DELAY(879) | G_DELAY(0))       /* CFG_GPMC_A23_OUT */
388                         0x1d8 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A24_OEN */
389                         0x1dc (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A24_OUT */
390                         0x1e4 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A25_OEN */
391                         0x1e8 (A_DELAY(34) | G_DELAY(0))        /* CFG_GPMC_A25_OUT */
392                         0x1f0 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A26_OEN */
393                         0x1f4 (A_DELAY(120) | G_DELAY(0))       /* CFG_GPMC_A26_OUT */
394                         0x1fc (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A27_OEN */
395                         0x200 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A27_OUT */
396                         0x364 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_CS1_OEN */
397                         0x368 (A_DELAY(11) | G_DELAY(0))        /* CFG_GPMC_CS1_OUT */
398                 >;
399         };
400 };
402 &i2c1 {
403         status = "okay";
404         clock-frequency = <400000>;
406         tps659038: tps659038@58 {
407                 compatible = "ti,tps659038";
408                 reg = <0x58>;
410                 tps659038_pmic {
411                         compatible = "ti,tps659038-pmic";
413                         regulators {
414                                 smps123_reg: smps123 {
415                                         /* VDD_MPU */
416                                         regulator-name = "smps123";
417                                         regulator-min-microvolt = < 850000>;
418                                         regulator-max-microvolt = <1250000>;
419                                         regulator-always-on;
420                                         regulator-boot-on;
421                                 };
423                                 smps45_reg: smps45 {
424                                         /* VDD_DSPEVE */
425                                         regulator-name = "smps45";
426                                         regulator-min-microvolt = < 850000>;
427                                         regulator-max-microvolt = <1150000>;
428                                         regulator-boot-on;
429                                         regulator-always-on;
430                                 };
432                                 smps6_reg: smps6 {
433                                         /* VDD_GPU - over VDD_SMPS6 */
434                                         regulator-name = "smps6";
435                                         regulator-min-microvolt = <850000>;
436                                         regulator-max-microvolt = <1250000>;
437                                         regulator-boot-on;
438                                         regulator-always-on;
439                                 };
441                                 smps7_reg: smps7 {
442                                         /* CORE_VDD */
443                                         regulator-name = "smps7";
444                                         regulator-min-microvolt = <850000>;
445                                         regulator-max-microvolt = <1060000>;
446                                         regulator-always-on;
447                                         regulator-boot-on;
448                                 };
450                                 smps8_reg: smps8 {
451                                         /* VDD_IVAHD */
452                                         regulator-name = "smps8";
453                                         regulator-min-microvolt = < 850000>;
454                                         regulator-max-microvolt = <1250000>;
455                                         regulator-boot-on;
456                                         regulator-always-on;
457                                 };
459                                 smps9_reg: smps9 {
460                                         /* VDDS1V8 */
461                                         regulator-name = "smps9";
462                                         regulator-min-microvolt = <1800000>;
463                                         regulator-max-microvolt = <1800000>;
464                                         regulator-always-on;
465                                         regulator-boot-on;
466                                 };
468                                 ldo1_reg: ldo1 {
469                                         /* LDO1_OUT --> SDIO  */
470                                         regulator-name = "ldo1";
471                                         regulator-min-microvolt = <1800000>;
472                                         regulator-max-microvolt = <3300000>;
473                                         regulator-boot-on;
474                                         regulator-always-on;
475                                 };
477                                 ldo2_reg: ldo2 {
478                                         /* VDD_RTCIO */
479                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
480                                         regulator-name = "ldo2";
481                                         regulator-min-microvolt = <3300000>;
482                                         regulator-max-microvolt = <3300000>;
483                                         regulator-boot-on;
484                                         regulator-always-on;
485                                 };
487                                 ldo3_reg: ldo3 {
488                                         /* VDDA_1V8_PHY */
489                                         regulator-name = "ldo3";
490                                         regulator-min-microvolt = <1800000>;
491                                         regulator-max-microvolt = <1800000>;
492                                         regulator-always-on;
493                                         regulator-boot-on;
494                                 };
496                                 ldo9_reg: ldo9 {
497                                         /* VDD_RTC */
498                                         regulator-name = "ldo9";
499                                         regulator-min-microvolt = <1050000>;
500                                         regulator-max-microvolt = <1050000>;
501                                         regulator-boot-on;
502                                         regulator-always-on;
503                                 };
505                                 ldoln_reg: ldoln {
506                                         /* VDDA_1V8_PLL */
507                                         regulator-name = "ldoln";
508                                         regulator-min-microvolt = <1800000>;
509                                         regulator-max-microvolt = <1800000>;
510                                         regulator-always-on;
511                                         regulator-boot-on;
512                                 };
514                                 ldousb_reg: ldousb {
515                                         /* VDDA_3V_USB: VDDA_USBHS33 */
516                                         regulator-name = "ldousb";
517                                         regulator-min-microvolt = <3300000>;
518                                         regulator-max-microvolt = <3300000>;
519                                         regulator-boot-on;
520                                         regulator-always-on;
521                                 };
523                                 /* REGEN1 is unused */
525                                 regen2: regen2 {
526                                         /* Needed for PMIC internal resources */
527                                         regulator-name = "regen2";
528                                         regulator-boot-on;
529                                         regulator-always-on;
530                                 };
532                                 /* REGEN3 is unused */
534                                 sysen1: sysen1 {
535                                         /* PMIC_REGEN_3V3 */
536                                         regulator-name = "sysen1";
537                                         regulator-boot-on;
538                                         regulator-always-on;
539                                 };
541                                 sysen2: sysen2 {
542                                         /* PMIC_REGEN_DDR */
543                                         regulator-name = "sysen2";
544                                         regulator-boot-on;
545                                         regulator-always-on;
546                                 };
547                         };
548                 };
549         };
551         pcf_lcd: gpio@20 {
552                 compatible = "nxp,pcf8575";
553                 reg = <0x20>;
554                 gpio-controller;
555                 #gpio-cells = <2>;
556         };
558         pcf_gpio_21: gpio@21 {
559                 compatible = "nxp,pcf8575";
560                 reg = <0x21>;
561                 lines-initial-states = <0x1408>;
562                 gpio-controller;
563                 #gpio-cells = <2>;
564                 interrupt-parent = <&gpio6>;
565                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
566                 interrupt-controller;
567                 #interrupt-cells = <2>;
568         };
571         tlv320aic3106: tlv320aic3106@18 {
572                 compatible = "ti,tlv320aic3106";
573                 reg = <0x18>;
574                 adc-settle-ms = <40>;
575                 ai3x-micbias-vg = <1>;          /* 2.0V */
576                 status = "okay";
578                 /* Regulators */
579                 AVDD-supply = <&evm_3v3_sw>;
580                 IOVDD-supply = <&evm_3v3_sw>;
581                 DRVDD-supply = <&evm_3v3_sw>;
582                 DVDD-supply = <&aic_dvdd>;
583         };
584 };
586 i2c_p3_exp: &i2c2 {
587         status = "okay";
588         clock-frequency = <400000>;
590         pcf_hdmi: gpio@26 {
591                 compatible = "nxp,pcf8575";
592                 reg = <0x26>;
593                 lines-initial-states = <0xffeb>;
594                 gpio-controller;
595                 #gpio-cells = <2>;
596         };
598         ov10633@37 {
599                 compatible = "ovti,ov10633";
600                 reg = <0x37>;
602                 mux-gpios = <&pcf_hdmi 3        GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
603                 port {
604                         onboardLI: endpoint {
605                                 remote-endpoint = <&vin1a>;
606                                 hsync-active = <1>;
607                                 vsync-active = <1>;
608                                 pclk-sample = <0>;
609                         };
610                 };
611         };
612 };
614 &i2c3 {
615         status = "okay";
616         clock-frequency = <3400000>;
617 };
619 &mcspi1 {
620         status = "okay";
621 };
623 &mcspi2 {
624         status = "okay";
625 };
627 &uart1 {
628         status = "okay";
629         interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
630                                &dra7_pmx_core 0x3e0>;
631 };
633 &uart2 {
634         status = "okay";
635 };
637 &uart3 {
638         status = "okay";
639         gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
640 };
642 &mmc1 {
643         status = "okay";
644         pbias-supply = <&pbias_mmc_reg>;
645         vmmc-supply = <&evm_3v3_sd>;
646         vmmc_aux-supply = <&ldo1_reg>;
647         bus-width = <4>;
648         /*
649          * SDCD signal is not being used here - using the fact that GPIO mode
650          * is always hardwired.
651          */
652         cd-gpios = <&gpio6 27 0>;
653         pinctrl-names = "default", "hs", "sdr12", "sdr25", "ddr50";
654         pinctrl-0 = <&mmc1_pins_default>;
655         pinctrl-1 = <&mmc1_pins_hs>;
656         pinctrl-2 = <&mmc1_pins_sdr12>;
657         pinctrl-3 = <&mmc1_pins_sdr25>;
658         pinctrl-4 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>;
659         sd-uhs-ddr50;
660         sd-uhs-sdr25;
661         sd-uhs-sdr12;
662 };
664 &mmc2 {
665         status = "okay";
666         vmmc-supply = <&evm_3v3_sw>;
667         bus-width = <8>;
668         pinctrl-names = "default", "hs", "ddr_3_3v";
669         pinctrl-0 = <&mmc2_pins_default>;
670         pinctrl-1 = <&mmc2_pins_hs>;
671         pinctrl-2 = <&mmc2_pins_ddr_3_3v &mmc2_iodelay_ddr_3_3v_conf>;
672         mmc-ddr-1_8v;
673 };
675 &mmc4 {
676         status = "okay";
677         vmmc-supply = <&vmmcwl_fixed>;
678         bus-width = <4>;
679         cap-power-off-card;
680         keep-power-in-suspend;
681         ti,non-removable;
683         #address-cells = <1>;
684         #size-cells = <0>;
685         wlcore: wlcore@0 {
686                 compatible = "ti,wlcore";
687                 reg = <2>;
688                 interrupt-parent = <&gpio5>;
689                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
690         };
691 };
693 &cpu0 {
694         cpu0-voltdm = <&voltdm_mpu>;
695         voltage-tolerance = <1>;
696 };
698 &voltdm_mpu {
699         vdd-supply = <&smps123_reg>;
700 };
702 &voltdm_dspeve {
703         vdd-supply = <&smps45_reg>;
704 };
706 &voltdm_gpu {
707         vdd-supply = <&smps6_reg>;
708 };
710 &voltdm_ivahd {
711         vdd-supply = <&smps8_reg>;
712 };
714 &voltdm_core {
715         vdd-supply = <&smps7_reg>;
716 };
718 &qspi {
719         status = "okay";
721         spi-max-frequency = <48000000>;
722         m25p80@0 {
723                 compatible = "s25fl256s1";
724                 spi-max-frequency = <48000000>;
725                 reg = <0>;
726                 spi-tx-bus-width = <1>;
727                 spi-rx-bus-width = <4>;
728                 spi-cpol;
729                 spi-cpha;
730                 #address-cells = <1>;
731                 #size-cells = <1>;
733                 /* MTD partition table.
734                  * The ROM checks the first four physical blocks
735                  * for a valid file to boot and the flash here is
736                  * 64KiB block size.
737                  */
738                 partition@0 {
739                         label = "QSPI.SPL";
740                         reg = <0x00000000 0x000010000>;
741                 };
742                 partition@1 {
743                         label = "QSPI.SPL.backup1";
744                         reg = <0x00010000 0x00010000>;
745                 };
746                 partition@2 {
747                         label = "QSPI.SPL.backup2";
748                         reg = <0x00020000 0x00010000>;
749                 };
750                 partition@3 {
751                         label = "QSPI.SPL.backup3";
752                         reg = <0x00030000 0x00010000>;
753                 };
754                 partition@4 {
755                         label = "QSPI.u-boot";
756                         reg = <0x00040000 0x00100000>;
757                 };
758                 partition@5 {
759                         label = "QSPI.u-boot-spl-os";
760                         reg = <0x00140000 0x00080000>;
761                 };
762                 partition@6 {
763                         label = "QSPI.u-boot-env";
764                         reg = <0x001c0000 0x00010000>;
765                 };
766                 partition@7 {
767                         label = "QSPI.u-boot-env.backup1";
768                         reg = <0x001d0000 0x0010000>;
769                 };
770                 partition@8 {
771                         label = "QSPI.kernel";
772                         reg = <0x001e0000 0x0800000>;
773                 };
774                 partition@9 {
775                         label = "QSPI.file-system";
776                         reg = <0x009e0000 0x01620000>;
777                 };
778         };
779 };
781 &omap_dwc3_1 {
782         extcon = <&extcon_usb1>;
783 };
785 &omap_dwc3_2 {
786         extcon = <&extcon_usb2>;
787 };
789 &usb1 {
790         dr_mode = "peripheral";
791 };
793 &usb2 {
794         dr_mode = "host";
795 };
797 &mac {
798         status = "okay";
799         dual_emac;
800 };
802 &cpsw_emac0 {
803         phy_id = <&davinci_mdio>, <2>;
804         phy-mode = "rgmii";
805         dual_emac_res_vlan = <1>;
806 };
808 &cpsw_emac1 {
809         phy_id = <&davinci_mdio>, <3>;
810         phy-mode = "rgmii";
811         dual_emac_res_vlan = <2>;
812 };
814 &elm {
815         status = "okay";
816 };
818 &gpmc {
819         status = "disabled";
820         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
821         nand@0,0 {
822                 reg = <0 0 4>;          /* device IO registers */
823                 ti,nand-ecc-opt = "bch8";
824                 ti,elm-id = <&elm>;
825                 nand-bus-width = <16>;
826                 gpmc,device-width = <2>;
827                 gpmc,sync-clk-ps = <0>;
828                 gpmc,cs-on-ns = <0>;
829                 gpmc,cs-rd-off-ns = <80>;
830                 gpmc,cs-wr-off-ns = <80>;
831                 gpmc,adv-on-ns = <0>;
832                 gpmc,adv-rd-off-ns = <60>;
833                 gpmc,adv-wr-off-ns = <60>;
834                 gpmc,we-on-ns = <10>;
835                 gpmc,we-off-ns = <50>;
836                 gpmc,oe-on-ns = <4>;
837                 gpmc,oe-off-ns = <40>;
838                 gpmc,access-ns = <40>;
839                 gpmc,wr-access-ns = <80>;
840                 gpmc,rd-cycle-ns = <80>;
841                 gpmc,wr-cycle-ns = <80>;
842                 gpmc,bus-turnaround-ns = <0>;
843                 gpmc,cycle2cycle-delay-ns = <0>;
844                 gpmc,clk-activation-ns = <0>;
845                 gpmc,wait-monitoring-ns = <0>;
846                 gpmc,wr-data-mux-bus-ns = <0>;
847                 /* MTD partition table */
848                 /* All SPL-* partitions are sized to minimal length
849                  * which can be independently programmable. For
850                  * NAND flash this is equal to size of erase-block */
851                 #address-cells = <1>;
852                 #size-cells = <1>;
853                 partition@0 {
854                         label = "NAND.SPL";
855                         reg = <0x00000000 0x000020000>;
856                 };
857                 partition@1 {
858                         label = "NAND.SPL.backup1";
859                         reg = <0x00020000 0x00020000>;
860                 };
861                 partition@2 {
862                         label = "NAND.SPL.backup2";
863                         reg = <0x00040000 0x00020000>;
864                 };
865                 partition@3 {
866                         label = "NAND.SPL.backup3";
867                         reg = <0x00060000 0x00020000>;
868                 };
869                 partition@4 {
870                         label = "NAND.u-boot-spl-os";
871                         reg = <0x00080000 0x00040000>;
872                 };
873                 partition@5 {
874                         label = "NAND.u-boot";
875                         reg = <0x000c0000 0x00100000>;
876                 };
877                 partition@6 {
878                         label = "NAND.u-boot-env";
879                         reg = <0x001c0000 0x00020000>;
880                 };
881                 partition@7 {
882                         label = "NAND.u-boot-env.backup1";
883                         reg = <0x001e0000 0x00020000>;
884                 };
885                 partition@8 {
886                         label = "NAND.kernel";
887                         reg = <0x00200000 0x00800000>;
888                 };
889                 partition@9 {
890                         label = "NAND.file-system";
891                         reg = <0x00a00000 0x0f600000>;
892                 };
893         };
894 };
896 &gpio7 {
897         ti,no-reset-on-init;
898         ti,no-idle-on-init;
899 };
901 &dss {
902         status = "ok";
904         vdda_video-supply = <&ldoln_reg>;
905 };
907 &hdmi {
908         status = "ok";
909         vdda-supply = <&ldo3_reg>;
911         port {
912                 hdmi_out: endpoint {
913                         remote-endpoint = <&tpd12s015_in>;
914                 };
915         };
916 };
918 &dcan1 {
919         status = "ok";
920         pinctrl-names = "default", "sleep";
921         pinctrl-0 = <&dcan1_pins_default>;
922         pinctrl-1 = <&dcan1_pins_sleep>;
923 };
925 &mailbox5 {
926         status = "okay";
927         mbox_ipu1_legacy: mbox_ipu1_legacy {
928                 status = "okay";
929         };
930         mbox_dsp1_legacy: mbox_dsp1_legacy {
931                 status = "okay";
932         };
933 };
935 &mailbox6 {
936         status = "okay";
937         mbox_ipu2_legacy: mbox_ipu2_legacy {
938                 status = "okay";
939         };
940         mbox_dsp2_legacy: mbox_dsp2_legacy {
941                 status = "okay";
942         };
943 };
945 &mmu0_dsp1 {
946         status = "okay";
947 };
949 &mmu1_dsp1 {
950         status = "okay";
951 };
953 &mmu0_dsp2 {
954         status = "okay";
955 };
957 &mmu1_dsp2 {
958         status = "okay";
959 };
961 &mmu_ipu1 {
962         status = "okay";
963 };
965 &mmu_ipu2 {
966         status = "okay";
967 };
969 &ipu2 {
970         status = "okay";
971         memory-region = <&ipu2_cma_pool>;
972         mboxes = <&mailbox6 &mbox_ipu2_legacy>;
973         timers = <&timer3>;
974         watchdog-timers = <&timer4>, <&timer9>;
975 };
977 &ipu1 {
978         status = "okay";
979         memory-region = <&ipu1_cma_pool>;
980         mboxes = <&mailbox5 &mbox_ipu1_legacy>;
981         timers = <&timer11>;
982         watchdog-timers = <&timer7>, <&timer8>;
983 };
985 &dsp1 {
986         status = "okay";
987         memory-region = <&dsp1_cma_pool>;
988         mboxes = <&mailbox5 &mbox_dsp1_legacy>;
989         timers = <&timer5>;
990         watchdog-timers = <&timer10>;
991 };
993 &dsp2 {
994         status = "okay";
995         memory-region = <&dsp2_cma_pool>;
996         mboxes = <&mailbox6 &mbox_dsp2_legacy>;
997         timers = <&timer6>;
998 };
1000 &atl {
1001         status = "okay";
1003         atl2 {
1004                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
1005                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
1006         };
1007 };
1009 &mcasp3 {
1010         fck_parent = "atl_clkin2_ck";
1012         status = "okay";
1014         op-mode = <0>;          /* MCASP_IIS_MODE */
1015         tdm-slots = <2>;
1016         /* 4 serializer */
1017         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
1018                 1 2 0 0
1019         >;
1020 };
1022 &mcasp7 {
1023         #sound-dai-cells = <0>;
1025         status = "okay";
1027         op-mode = <0>;  /* MCASP_IIS_MODE */
1028         tdm-slots = <4>;
1029         /* 4 serializer */
1030         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
1031                 2 1 0 0
1032         >;
1033         tx-num-evt = <8>;
1034         rx-num-evt = <8>;
1035 };
1037 &usb2_phy1 {
1038         phy-supply = <&ldousb_reg>;
1039 };
1041 &usb2_phy2 {
1042         phy-supply = <&ldousb_reg>;
1043 };
1045 &vip1 {
1046         status = "okay";
1047 };
1049 &vin1a {
1050         endpoint@0 {
1051                 slave-mode;
1052                 remote-endpoint = <&onboardLI>;
1053         };
1054 };
1056 #include "dra7xx-jamr3.dtsi"