ARM: dts: omap: Add enable optional clks during reset
[android-sdk/kernel-video.git] / arch / arm / boot / dts / dra7-evm.dts
1 /*
2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clk/ti-dra7-atl.h>
15 / {
16         model = "TI DRA742";
17         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
19         memory {
20                 device_type = "memory";
21                 reg = <0x80000000 0x60000000>; /* 1536 MB */
22         };
24         reserved_mem: reserved-memory {
25                 #address-cells = <1>;
26                 #size-cells = <1>;
27                 ranges;
29                 ipu2_cma_pool: ipu2_cma@95800000 {
30                         compatible = "shared-dma-pool";
31                         reg = <0x95800000 0x3800000>;
32                         reusable;
33                         status = "okay";
34                 };
36                 dsp1_cma_pool: dsp1_cma@99000000 {
37                         compatible = "shared-dma-pool";
38                         reg = <0x99000000 0x4000000>;
39                         reusable;
40                         status = "okay";
41                 };
43                 ipu1_cma_pool: ipu1_cma@9d000000 {
44                         compatible = "shared-dma-pool";
45                         reg = <0x9d000000 0x2000000>;
46                         reusable;
47                         status = "okay";
48                 };
50                 dsp2_cma_pool: dsp2_cma@9f000000 {
51                         compatible = "shared-dma-pool";
52                         reg = <0x9f000000 0x800000>;
53                         reusable;
54                         status = "okay";
55                 };
56         };
58         extcon_usb1: extcon_usb1 {
59                 compatible = "linux,extcon-usb-gpio";
60                 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
61         };
63         extcon_usb2: extcon_usb2 {
64                 compatible = "linux,extcon-usb-gpio";
65                 id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
66         };
68         evm_3v3_sd: fixedregulator-sd {
69                 compatible = "regulator-fixed";
70                 regulator-name = "evm_3v3_sd";
71                 regulator-min-microvolt = <3300000>;
72                 regulator-max-microvolt = <3300000>;
73                 enable-active-high;
74                 gpio = <&pcf_gpio_21 5 0>;
75         };
77         evm_3v3_sw: fixedregulator-evm_3v3_sw {
78                 compatible = "regulator-fixed";
79                 regulator-name = "evm_3v3_sw";
80                 vin-supply = <&sysen1>;
81                 regulator-min-microvolt = <3300000>;
82                 regulator-max-microvolt = <3300000>;
83         };
85         aic_dvdd: fixedregulator-aic_dvdd {
86                 /* TPS77018DBVT */
87                 compatible = "regulator-fixed";
88                 regulator-name = "aic_dvdd";
89                 vin-supply = <&evm_3v3_sw>;
90                 regulator-min-microvolt = <1800000>;
91                 regulator-max-microvolt = <1800000>;
92         };
94         vmmcwl_fixed: fixedregulator-mmcwl {
95                 compatible = "regulator-fixed";
96                 regulator-name = "vmmcwl_fixed";
97                 regulator-min-microvolt = <1800000>;
98                 regulator-max-microvolt = <1800000>;
99                 gpio = <&gpio5 8 0>;    /* gpio5_8 */
100                 startup-delay-us = <70000>;
101                 enable-active-high;
102         };
104         kim {
105                 compatible = "kim";
106                 nshutdown_gpio = <132>;
107                 dev_name = "/dev/ttyS2";
108                 flow_cntrl = <1>;
109                 baud_rate = <3686400>;
110         };
112         btwilink {
113                 compatible = "btwilink";
114         };
116         vtt_fixed: fixedregulator-vtt {
117                 compatible = "regulator-fixed";
118                 regulator-name = "vtt_fixed";
119                 regulator-min-microvolt = <1350000>;
120                 regulator-max-microvolt = <1350000>;
121                 regulator-always-on;
122                 regulator-boot-on;
123                 enable-active-high;
124                 vin-supply = <&sysen2>;
125                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
126         };
128         aliases {
129                 display0 = &hdmi0;
130                 sound0 = &primary_sound;
131                 sound1 = &hdmi;
132         };
134         hdmi0: connector@1 {
135                 compatible = "hdmi-connector";
136                 label = "hdmi";
138                 type = "a";
140                 port {
141                         hdmi_connector_in: endpoint {
142                                 remote-endpoint = <&tpd12s015_out>;
143                         };
144                 };
145         };
147         tpd12s015: encoder@1 {
148                 compatible = "ti,dra7evm-tpd12s015";
150                 pinctrl-names = "i2c", "ddc";
151                 pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
152                 pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;
154                 ddc-i2c-bus = <&i2c2>;
155                 mcasp-gpio = <&mcasp8>;
157                 gpios = <&pcf_hdmi 4 0>,        /* P4, CT CP HPD */
158                         <&pcf_hdmi 5 0>,        /* P5, LS OE */
159                         <&gpio7 12 0>;  /* gpio7_12/sp1_cs2, HPD */
161                 ports {
162                         #address-cells = <1>;
163                         #size-cells = <0>;
165                         port@0 {
166                                 reg = <0>;
168                                 tpd12s015_in: endpoint@0 {
169                                         remote-endpoint = <&hdmi_out>;
170                                 };
171                         };
173                         port@1 {
174                                 reg = <1>;
176                                 tpd12s015_out: endpoint@0 {
177                                         remote-endpoint = <&hdmi_connector_in>;
178                                 };
179                         };
180                 };
181         };
183     ocp {
184         gpu: gpu@0x56000000 {
185             gpu0-voltdm = <&voltdm_gpu>;
186         };
187     };
189         primary_sound: primary_sound {
190                 compatible = "ti,dra7xx-evm-audio";
191                 ti,model = "DRA7xx-EVM";
192                 ti,always-on;
193                 ti,audio-codec = <&tlv320aic3106>;
194                 ti,mcasp-controller = <&mcasp3>;
195                 ti,codec-clock-rate = <11289600>;
196                 clocks = <&atl_clkin2_ck>;
197                 clock-names = "mclk";
198                 ti,audio-routing =
199                         "Headphone Jack",       "HPLOUT",
200                         "Headphone Jack",       "HPROUT",
201                         "Line Out",             "LLOUT",
202                         "Line Out",             "RLOUT",
203                         "MIC3L",                "Mic Jack",
204                         "MIC3R",                "Mic Jack",
205                         "Mic Jack",             "Mic Bias",
206                         "LINE1L",               "Line In",
207                         "LINE1R",               "Line In";
208         };
210         btwilink_sound: btwilink_sound {
211                 #sound-dai-cells = <0>;
212                 compatible = "linux,bt-sco-audio";
213                 status = "okay";
214         };
216         simple_bt_sco_card: bt_sco_card {
217                 compatible = "simple-audio-card";
218                 simple-audio-card,name = "DRA7xx-WiLink";
219                 simple-audio-card,format = "dsp_a";
220                 simple-audio-card,frame-master = <&btwilink_codec>;
221                 simple-audio-card,bitclock-master = <&btwilink_codec>;
222                 simple-audio-card,frame-inversion;
224                 simple-audio-card,cpu {
225                         sound-dai = <&mcasp7>;
226                 };
228                 btwilink_codec: simple-audio-card,codec {
229                         sound-dai = <&btwilink_sound>;
230                 };
231         };
232 };
234 &dra7_pmx_core {
235         hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
236                 pinctrl-single,pins = <
237                         /* this pin is used as a GPIO via mcasp */
238                         0x2fc   (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
239                 >;
240         };
242         hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
243                 pinctrl-single,pins = <
244                         0x408   (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
245                         0x40c   (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
246                 >;
247         };
249         hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
250                 pinctrl-single,pins = <
251                         0x408   (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
252                         0x40c   (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
253                 >;
254         };
256         dcan1_pins_default: dcan1_pins_default {
257                 pinctrl-single,pins = <
258                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
259                         0x418   (PULL_UP | MUX_MODE1)           /* wakeup0.dcan1_rx */
260                 >;
261         };
263         dcan1_pins_sleep: dcan1_pins_sleep {
264                 pinctrl-single,pins = <
265                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
266                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
267                 >;
268         };
270         mmc1_pins_default: pinmux_mmc1_default_pins {
271                 pinctrl-single,pins = <
272                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_clk.clk */
273                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_cmd.cmd */
274                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat0.dat0 */
275                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat1.dat1 */
276                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat2.dat2 */
277                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat3.dat3 */
278                         0x36c (PIN_INPUT | MUX_MODE14)          /* mmc1sdcd.gpio187 */
279                 >;
280         };
282         mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
283                 pinctrl-single,pins = <
284                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_clk.clk */
285                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_cmd.cmd */
286                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat0.dat0 */
287                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat1.dat1 */
288                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat2.dat2 */
289                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat3.dat3 */
290                 >;
291         };
293         mmc1_pins_hs: pinmux_mmc1_hs_pins {
294                 pinctrl-single,pins = <
295                         0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_clk.clk */
296                         0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_cmd.cmd */
297                         0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat0.dat0 */
298                         0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat1.dat1 */
299                         0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat2.dat2 */
300                         0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat3.dat3 */
301                 >;
302         };
304         mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
305                 pinctrl-single,pins = <
306                         0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_clk.clk */
307                         0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_cmd.cmd */
308                         0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat0.dat0 */
309                         0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat1.dat1 */
310                         0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat2.dat2 */
311                         0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat3.dat3 */
312                 >;
313         };
315         mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
316                 pinctrl-single,pins = <
317                         0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_clk.clk */
318                         0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_cmd.cmd */
319                         0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_dat0.dat0 */
320                         0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_dat1.dat1 */
321                         0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_dat2.dat2 */
322                         0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_dat3.dat3 */
323                 >;
324         };
326         mmc2_pins_default: mmc2_pins_default {
327                 pinctrl-single,pins = <
328                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
329                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
330                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
331                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
332                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
333                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
334                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
335                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
336                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
337                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
338                 >;
339         };
341         mmc2_pins_hs: pinmux_mmc2_hs_pins {
342                 pinctrl-single,pins = <
343                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
344                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
345                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
346                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
347                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
348                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
349                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
350                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
351                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
352                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
353                 >;
354         };
356         mmc2_pins_ddr_3_3v: pinmux_mmc2_ddr_3_3v_pins {
357                 pinctrl-single,pins = <
358                         0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
359                         0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
360                         0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
361                         0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
362                         0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
363                         0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
364                         0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
365                         0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
366                         0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
367                         0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
368                 >;
369         };
371         mmc4_pins_default: mmc4_pins_default {
372                 pinctrl-single,pins = <
373                         0x3E8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
374                         0x3EC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
375                         0x3F0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
376                         0x3F4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
377                         0x3F8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
378                         0x3FC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
379                 >;
380         };
382         mmc4_pins_hs: pinmux_mmc4_hs_pins {
383                 pinctrl-single,pins = <
384                         0x3E8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
385                         0x3EC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
386                         0x3F0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
387                         0x3F4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
388                         0x3F8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
389                         0x3FC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
390                 >;
391         };
392 };
394 &dra7_iodelay_core {
395         mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
396                 pinctrl-single,pins = <
397                         0x618 (A_DELAY(572) | G_DELAY(540))     /* CFG_MMC1_CLK_IN */
398                         0x624 (A_DELAY(0) | G_DELAY(600))       /* CFG_MMC1_CMD_IN */
399                         0x630 (A_DELAY(403) | G_DELAY(120))     /* CFG_MMC1_DAT0_IN */
400                         0x63c (A_DELAY(23) | G_DELAY(60))       /* CFG_MMC1_DAT1_IN */
401                         0x648 (A_DELAY(25) | G_DELAY(60))       /* CFG_MMC1_DAT2_IN */
402                         0x654 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT3_IN */
403                         0x620 (A_DELAY(1525) | G_DELAY(0))      /* CFG_MMC1_CLK_IN */
404                         0x628 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_CMD_OEN */
405                         0x62c (A_DELAY(55) | G_DELAY(0))        /* CFG_MMC1_CMD_OUT */
406                         0x634 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT0_OEN */
407                         0x638 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT0_OUT */
408                         0x640 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT1_OEN */
409                         0x644 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT1_OUT */
410                         0x64c (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT2_OEN */
411                         0x650 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT2_OUT */
412                         0x658 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT3_OEN */
413                         0x65c (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT3_OUT */
414                 >;
415         };
417         mmc2_iodelay_ddr_3_3v_conf: mmc2_iodelay_ddr_3_3v_conf {
418                 pinctrl-single,pins = <
419                         0x18c (A_DELAY(0) | G_DELAY(120))       /* CFG_GPMC_A19_IN */
420                         0x1a4 (A_DELAY(265) | G_DELAY(360))     /* CFG_GPMC_A20_IN */
421                         0x1b0 (A_DELAY(0) | G_DELAY(120))       /* CFG_GPMC_A21_IN */
422                         0x1bc (A_DELAY(0) | G_DELAY(120))       /* CFG_GPMC_A22_IN */
423                         0x1c8 (A_DELAY(287) | G_DELAY(420))     /* CFG_GPMC_A23_IN */
424                         0x1d4 (A_DELAY(144) | G_DELAY(240))     /* CFG_GPMC_A24_IN */
425                         0x1e0 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A25_IN */
426                         0x1ec (A_DELAY(0) | G_DELAY(120))       /* CFG_GPMC_A26_IN */
427                         0x1f8 (A_DELAY(120) | G_DELAY(180))     /* CFG_GPMC_A27_IN */
428                         0x360 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_CS1_IN */
429                         0x190 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A19_OEN */
430                         0x194 (A_DELAY(174) | G_DELAY(0))       /* CFG_GPMC_A19_OUT */
431                         0x1a8 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A20_OEN */
432                         0x1ac (A_DELAY(168) | G_DELAY(0))       /* CFG_GPMC_A20_OUT */
433                         0x1b4 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A21_OEN */
434                         0x1b8 (A_DELAY(136) | G_DELAY(0))       /* CFG_GPMC_A21_OUT */
435                         0x1c0 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A22_OEN */
436                         0x1c4 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A22_OUT */
437                         0x1d0 (A_DELAY(879) | G_DELAY(0))       /* CFG_GPMC_A23_OUT */
438                         0x1d8 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A24_OEN */
439                         0x1dc (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A24_OUT */
440                         0x1e4 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A25_OEN */
441                         0x1e8 (A_DELAY(34) | G_DELAY(0))        /* CFG_GPMC_A25_OUT */
442                         0x1f0 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A26_OEN */
443                         0x1f4 (A_DELAY(120) | G_DELAY(0))       /* CFG_GPMC_A26_OUT */
444                         0x1fc (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A27_OEN */
445                         0x200 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A27_OUT */
446                         0x364 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_CS1_OEN */
447                         0x368 (A_DELAY(11) | G_DELAY(0))        /* CFG_GPMC_CS1_OUT */
448                 >;
449         };
451         mmc4_iodelay_ds_manual1_conf: mmc4_iodelay_ds_manual1_conf {
452                 pinctrl-single,pins = <
453                         0x840 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART1_CTSN_IN */
454                         0x848 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART1_CTSN_OUT */
455                         0x84c (A_DELAY(96) | G_DELAY(0))        /* CFG_UART1_RTSN_IN */
456                         0x850 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART1_RTSN_OEN */
457                         0x854 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART1_RTSN_OUT */
458                         0x870 (A_DELAY(582) | G_DELAY(0))       /* CFG_UART2_CTSN_IN */
459                         0x874 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_CTSN_OEN */
460                         0x878 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_CTSN_OUT */
461                         0x87C (A_DELAY(391) | G_DELAY(0))       /* RCFG_UART2_RTSN_IN */
462                         0x880 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_RTSN_OEN */
463                         0x884 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_RTSN_OUT */
464                         0x888 (A_DELAY(561) | G_DELAY(0))       /* RCFG_UART2_RXD_IN */
465                         0x88c (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_RXD_OEN */
466                         0x890 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_RXD_OUT */
467                         0x894 (A_DELAY(588) | G_DELAY(0))       /* CFG_UART2_TXD_IN */
468                         0x898 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_TXD_OEN */
469                         0x89c (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_TXD_OUT */
470                 >;
471         };
473         mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf {
474                 pinctrl-single,pins = <
475                         0x840 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART1_CTSN_IN */
476                         0x848 (A_DELAY(2651) | G_DELAY(0))      /* CFG_UART1_CTSN_OUT */
477                         0x84c (A_DELAY(1572) | G_DELAY(0))      /* CFG_UART1_RTSN_IN */
478                         0x850 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART1_RTSN_OEN */
479                         0x854 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART1_RTSN_OUT */
480                         0x870 (A_DELAY(1913) | G_DELAY(0))      /* CFG_UART2_CTSN_IN */
481                         0x874 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_CTSN_OEN */
482                         0x878 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_CTSN_OUT */
483                         0x87C (A_DELAY(1721) | G_DELAY(0))      /* RCFG_UART2_RTSN_IN */
484                         0x880 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_RTSN_OEN */
485                         0x884 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_RTSN_OUT */
486                         0x888 (A_DELAY(1891) | G_DELAY(0))      /* RCFG_UART2_RXD_IN */
487                         0x88c (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_RXD_OEN */
488                         0x890 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_RXD_OUT */
489                         0x894 (A_DELAY(1919) | G_DELAY(0))      /* CFG_UART2_TXD_IN */
490                         0x898 (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_TXD_OEN */
491                         0x89c (A_DELAY(0) | G_DELAY(0))         /* CFG_UART2_TXD_OUT */
492                 >;
493         };
494 };
496 &i2c1 {
497         status = "okay";
498         clock-frequency = <400000>;
500         tps659038: tps659038@58 {
501                 compatible = "ti,tps659038";
502                 reg = <0x58>;
504                 tps659038_pmic {
505                         compatible = "ti,tps659038-pmic";
507                         regulators {
508                                 smps123_reg: smps123 {
509                                         /* VDD_MPU */
510                                         regulator-name = "smps123";
511                                         regulator-min-microvolt = < 850000>;
512                                         regulator-max-microvolt = <1250000>;
513                                         regulator-always-on;
514                                         regulator-boot-on;
515                                 };
517                                 smps45_reg: smps45 {
518                                         /* VDD_DSPEVE */
519                                         regulator-name = "smps45";
520                                         regulator-min-microvolt = < 850000>;
521                                         regulator-max-microvolt = <1150000>;
522                                         regulator-boot-on;
523                                         regulator-always-on;
524                                 };
526                                 smps6_reg: smps6 {
527                                         /* VDD_GPU - over VDD_SMPS6 */
528                                         regulator-name = "smps6";
529                                         regulator-min-microvolt = <850000>;
530                                         regulator-max-microvolt = <1250000>;
531                                         regulator-boot-on;
532                                         regulator-always-on;
533                                 };
535                                 smps7_reg: smps7 {
536                                         /* CORE_VDD */
537                                         regulator-name = "smps7";
538                                         regulator-min-microvolt = <850000>;
539                                         regulator-max-microvolt = <1060000>;
540                                         regulator-always-on;
541                                         regulator-boot-on;
542                                 };
544                                 smps8_reg: smps8 {
545                                         /* VDD_IVAHD */
546                                         regulator-name = "smps8";
547                                         regulator-min-microvolt = < 850000>;
548                                         regulator-max-microvolt = <1250000>;
549                                         regulator-boot-on;
550                                         regulator-always-on;
551                                 };
553                                 smps9_reg: smps9 {
554                                         /* VDDS1V8 */
555                                         regulator-name = "smps9";
556                                         regulator-min-microvolt = <1800000>;
557                                         regulator-max-microvolt = <1800000>;
558                                         regulator-always-on;
559                                         regulator-boot-on;
560                                 };
562                                 ldo1_reg: ldo1 {
563                                         /* LDO1_OUT --> SDIO  */
564                                         regulator-name = "ldo1";
565                                         regulator-min-microvolt = <1800000>;
566                                         regulator-max-microvolt = <3300000>;
567                                         regulator-boot-on;
568                                         regulator-always-on;
569                                 };
571                                 ldo2_reg: ldo2 {
572                                         /* VDD_RTCIO */
573                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
574                                         regulator-name = "ldo2";
575                                         regulator-min-microvolt = <3300000>;
576                                         regulator-max-microvolt = <3300000>;
577                                         regulator-boot-on;
578                                         regulator-always-on;
579                                 };
581                                 ldo3_reg: ldo3 {
582                                         /* VDDA_1V8_PHY */
583                                         regulator-name = "ldo3";
584                                         regulator-min-microvolt = <1800000>;
585                                         regulator-max-microvolt = <1800000>;
586                                         regulator-always-on;
587                                         regulator-boot-on;
588                                 };
590                                 ldo9_reg: ldo9 {
591                                         /* VDD_RTC */
592                                         regulator-name = "ldo9";
593                                         regulator-min-microvolt = <1050000>;
594                                         regulator-max-microvolt = <1050000>;
595                                         regulator-boot-on;
596                                         regulator-always-on;
597                                 };
599                                 ldoln_reg: ldoln {
600                                         /* VDDA_1V8_PLL */
601                                         regulator-name = "ldoln";
602                                         regulator-min-microvolt = <1800000>;
603                                         regulator-max-microvolt = <1800000>;
604                                         regulator-always-on;
605                                         regulator-boot-on;
606                                 };
608                                 ldousb_reg: ldousb {
609                                         /* VDDA_3V_USB: VDDA_USBHS33 */
610                                         regulator-name = "ldousb";
611                                         regulator-min-microvolt = <3300000>;
612                                         regulator-max-microvolt = <3300000>;
613                                         regulator-boot-on;
614                                         regulator-always-on;
615                                 };
617                                 /* REGEN1 is unused */
619                                 regen2: regen2 {
620                                         /* Needed for PMIC internal resources */
621                                         regulator-name = "regen2";
622                                         regulator-boot-on;
623                                         regulator-always-on;
624                                 };
626                                 /* REGEN3 is unused */
628                                 sysen1: sysen1 {
629                                         /* PMIC_REGEN_3V3 */
630                                         regulator-name = "sysen1";
631                                         regulator-boot-on;
632                                         regulator-always-on;
633                                 };
635                                 sysen2: sysen2 {
636                                         /* PMIC_REGEN_DDR */
637                                         regulator-name = "sysen2";
638                                         regulator-boot-on;
639                                         regulator-always-on;
640                                 };
641                         };
642                 };
643         };
645         pcf_lcd: gpio@20 {
646                 compatible = "nxp,pcf8575";
647                 reg = <0x20>;
648                 gpio-controller;
649                 #gpio-cells = <2>;
650         };
652         pcf_gpio_21: gpio@21 {
653                 compatible = "nxp,pcf8575";
654                 reg = <0x21>;
655                 lines-initial-states = <0x1408>;
656                 gpio-controller;
657                 #gpio-cells = <2>;
658                 interrupt-parent = <&gpio6>;
659                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
660                 interrupt-controller;
661                 #interrupt-cells = <2>;
662         };
665         tlv320aic3106: tlv320aic3106@18 {
666                 compatible = "ti,tlv320aic3106";
667                 reg = <0x18>;
668                 adc-settle-ms = <40>;
669                 ai3x-micbias-vg = <1>;          /* 2.0V */
670                 status = "okay";
672                 /* Regulators */
673                 AVDD-supply = <&evm_3v3_sw>;
674                 IOVDD-supply = <&evm_3v3_sw>;
675                 DRVDD-supply = <&evm_3v3_sw>;
676                 DVDD-supply = <&aic_dvdd>;
677         };
678 };
680 i2c_p3_exp: &i2c2 {
681         status = "okay";
682         clock-frequency = <400000>;
684         pcf_hdmi: gpio@26 {
685                 compatible = "nxp,pcf8575";
686                 reg = <0x26>;
687                 lines-initial-states = <0xffeb>;
688                 gpio-controller;
689                 #gpio-cells = <2>;
690         };
692         ov10633@37 {
693                 compatible = "ovti,ov10633";
694                 reg = <0x37>;
696                 mux-gpios = <&pcf_hdmi 3        GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
697                 port {
698                         onboardLI: endpoint {
699                                 remote-endpoint = <&vin1a>;
700                                 hsync-active = <1>;
701                                 vsync-active = <1>;
702                                 pclk-sample = <0>;
703                         };
704                 };
705         };
706 };
708 &i2c3 {
709         status = "okay";
710         clock-frequency = <3400000>;
711 };
713 &mcspi1 {
714         status = "okay";
715 };
717 &mcspi2 {
718         status = "okay";
719 };
721 &uart1 {
722         status = "okay";
723         interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
724                                &dra7_pmx_core 0x3e0>;
725 };
727 &uart2 {
728         status = "okay";
729 };
731 &uart3 {
732         status = "okay";
733         gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
734 };
736 &mmc1 {
737         status = "okay";
738         pbias-supply = <&pbias_mmc_reg>;
739         vmmc-supply = <&evm_3v3_sd>;
740         vmmc_aux-supply = <&ldo1_reg>;
741         bus-width = <4>;
742         /*
743          * SDCD signal is not being used here - using the fact that GPIO mode
744          * is always hardwired.
745          */
746         cd-gpios = <&gpio6 27 0>;
747         pinctrl-names = "default", "hs", "sdr12", "sdr25", "ddr50";
748         pinctrl-0 = <&mmc1_pins_default>;
749         pinctrl-1 = <&mmc1_pins_hs>;
750         pinctrl-2 = <&mmc1_pins_sdr12>;
751         pinctrl-3 = <&mmc1_pins_sdr25>;
752         pinctrl-4 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>;
753         sd-uhs-ddr50;
754         sd-uhs-sdr25;
755         sd-uhs-sdr12;
756 };
758 &mmc2 {
759         status = "okay";
760         vmmc-supply = <&evm_3v3_sw>;
761         bus-width = <8>;
762         pinctrl-names = "default", "hs", "ddr_3_3v";
763         pinctrl-0 = <&mmc2_pins_default>;
764         pinctrl-1 = <&mmc2_pins_hs>;
765         pinctrl-2 = <&mmc2_pins_ddr_3_3v &mmc2_iodelay_ddr_3_3v_conf>;
766         mmc-ddr-1_8v;
767 };
769 &mmc4 {
770         status = "okay";
771         vmmc-supply = <&vmmcwl_fixed>;
772         bus-width = <4>;
773         cap-power-off-card;
774         keep-power-in-suspend;
775         ti,non-removable;
776         pinctrl-names = "default", "hs";
777         pinctrl-0 = <&mmc4_pins_default &mmc4_iodelay_ds_manual1_conf>;
778         pinctrl-1 = <&mmc4_pins_hs &mmc4_iodelay_manual1_conf>;
780         #address-cells = <1>;
781         #size-cells = <0>;
782         wlcore: wlcore@0 {
783                 compatible = "ti,wl1835";
784                 reg = <2>;
785                 interrupt-parent = <&gpio5>;
786                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
787         };
788 };
790 &cpu0 {
791         cpu0-voltdm = <&voltdm_mpu>;
792         voltage-tolerance = <1>;
793 };
795 &voltdm_mpu {
796         vdd-supply = <&smps123_reg>;
797 };
799 &voltdm_dspeve {
800         vdd-supply = <&smps45_reg>;
801 };
803 &voltdm_gpu {
804         vdd-supply = <&smps6_reg>;
805 };
807 &voltdm_ivahd {
808         vdd-supply = <&smps8_reg>;
809 };
811 &voltdm_core {
812         vdd-supply = <&smps7_reg>;
813 };
815 &qspi {
816         status = "okay";
818         spi-max-frequency = <48000000>;
819         m25p80@0 {
820                 compatible = "s25fl256s1";
821                 spi-max-frequency = <48000000>;
822                 reg = <0>;
823                 spi-tx-bus-width = <1>;
824                 spi-rx-bus-width = <4>;
825                 spi-cpol;
826                 spi-cpha;
827                 #address-cells = <1>;
828                 #size-cells = <1>;
830                 /* MTD partition table.
831                  * The ROM checks the first four physical blocks
832                  * for a valid file to boot and the flash here is
833                  * 64KiB block size.
834                  */
835                 partition@0 {
836                         label = "QSPI.SPL";
837                         reg = <0x00000000 0x000010000>;
838                 };
839                 partition@1 {
840                         label = "QSPI.SPL.backup1";
841                         reg = <0x00010000 0x00010000>;
842                 };
843                 partition@2 {
844                         label = "QSPI.SPL.backup2";
845                         reg = <0x00020000 0x00010000>;
846                 };
847                 partition@3 {
848                         label = "QSPI.SPL.backup3";
849                         reg = <0x00030000 0x00010000>;
850                 };
851                 partition@4 {
852                         label = "QSPI.u-boot";
853                         reg = <0x00040000 0x00100000>;
854                 };
855                 partition@5 {
856                         label = "QSPI.u-boot-spl-os";
857                         reg = <0x00140000 0x00080000>;
858                 };
859                 partition@6 {
860                         label = "QSPI.u-boot-env";
861                         reg = <0x001c0000 0x00010000>;
862                 };
863                 partition@7 {
864                         label = "QSPI.u-boot-env.backup1";
865                         reg = <0x001d0000 0x0010000>;
866                 };
867                 partition@8 {
868                         label = "QSPI.kernel";
869                         reg = <0x001e0000 0x0800000>;
870                 };
871                 partition@9 {
872                         label = "QSPI.file-system";
873                         reg = <0x009e0000 0x01620000>;
874                 };
875         };
876 };
878 &omap_dwc3_1 {
879         extcon = <&extcon_usb1>;
880 };
882 &omap_dwc3_2 {
883         extcon = <&extcon_usb2>;
884 };
886 &usb1 {
887         dr_mode = "peripheral";
888 };
890 &usb2 {
891         dr_mode = "host";
892 };
894 &mac {
895         status = "okay";
896         dual_emac;
897         ti,no-idle;
898 };
900 &cpsw_emac0 {
901         phy_id = <&davinci_mdio>, <2>;
902         phy-mode = "rgmii";
903         dual_emac_res_vlan = <1>;
904 };
906 &cpsw_emac1 {
907         phy_id = <&davinci_mdio>, <3>;
908         phy-mode = "rgmii";
909         dual_emac_res_vlan = <2>;
910 };
912 &elm {
913         status = "okay";
914 };
916 &gpmc {
917         status = "disabled";
918         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
919         nand@0,0 {
920                 reg = <0 0 4>;          /* device IO registers */
921                 ti,nand-ecc-opt = "bch8";
922                 ti,elm-id = <&elm>;
923                 nand-bus-width = <16>;
924                 gpmc,device-width = <2>;
925                 gpmc,sync-clk-ps = <0>;
926                 gpmc,cs-on-ns = <0>;
927                 gpmc,cs-rd-off-ns = <80>;
928                 gpmc,cs-wr-off-ns = <80>;
929                 gpmc,adv-on-ns = <0>;
930                 gpmc,adv-rd-off-ns = <60>;
931                 gpmc,adv-wr-off-ns = <60>;
932                 gpmc,we-on-ns = <10>;
933                 gpmc,we-off-ns = <50>;
934                 gpmc,oe-on-ns = <4>;
935                 gpmc,oe-off-ns = <40>;
936                 gpmc,access-ns = <40>;
937                 gpmc,wr-access-ns = <80>;
938                 gpmc,rd-cycle-ns = <80>;
939                 gpmc,wr-cycle-ns = <80>;
940                 gpmc,bus-turnaround-ns = <0>;
941                 gpmc,cycle2cycle-delay-ns = <0>;
942                 gpmc,clk-activation-ns = <0>;
943                 gpmc,wait-monitoring-ns = <0>;
944                 gpmc,wr-data-mux-bus-ns = <0>;
945                 /* MTD partition table */
946                 /* All SPL-* partitions are sized to minimal length
947                  * which can be independently programmable. For
948                  * NAND flash this is equal to size of erase-block */
949                 #address-cells = <1>;
950                 #size-cells = <1>;
951                 partition@0 {
952                         label = "NAND.SPL";
953                         reg = <0x00000000 0x000020000>;
954                 };
955                 partition@1 {
956                         label = "NAND.SPL.backup1";
957                         reg = <0x00020000 0x00020000>;
958                 };
959                 partition@2 {
960                         label = "NAND.SPL.backup2";
961                         reg = <0x00040000 0x00020000>;
962                 };
963                 partition@3 {
964                         label = "NAND.SPL.backup3";
965                         reg = <0x00060000 0x00020000>;
966                 };
967                 partition@4 {
968                         label = "NAND.u-boot-spl-os";
969                         reg = <0x00080000 0x00040000>;
970                 };
971                 partition@5 {
972                         label = "NAND.u-boot";
973                         reg = <0x000c0000 0x00100000>;
974                 };
975                 partition@6 {
976                         label = "NAND.u-boot-env";
977                         reg = <0x001c0000 0x00020000>;
978                 };
979                 partition@7 {
980                         label = "NAND.u-boot-env.backup1";
981                         reg = <0x001e0000 0x00020000>;
982                 };
983                 partition@8 {
984                         label = "NAND.kernel";
985                         reg = <0x00200000 0x00800000>;
986                 };
987                 partition@9 {
988                         label = "NAND.file-system";
989                         reg = <0x00a00000 0x0f600000>;
990                 };
991         };
992 };
994 &gpio7 {
995         ti,no-reset-on-init;
996         ti,no-idle-on-init;
997 };
999 &dss {
1000         status = "ok";
1002         vdda_video-supply = <&ldoln_reg>;
1003 };
1005 &hdmi {
1006         status = "ok";
1007         vdda-supply = <&ldo3_reg>;
1009         port {
1010                 hdmi_out: endpoint {
1011                         remote-endpoint = <&tpd12s015_in>;
1012                 };
1013         };
1014 };
1016 &dcan1 {
1017         status = "ok";
1018         pinctrl-names = "default", "sleep";
1019         pinctrl-0 = <&dcan1_pins_default>;
1020         pinctrl-1 = <&dcan1_pins_sleep>;
1021 };
1023 &mailbox5 {
1024         status = "okay";
1025         mbox_ipu1_legacy: mbox_ipu1_legacy {
1026                 status = "okay";
1027         };
1028         mbox_dsp1_legacy: mbox_dsp1_legacy {
1029                 status = "okay";
1030         };
1031 };
1033 &mailbox6 {
1034         status = "okay";
1035         mbox_ipu2_legacy: mbox_ipu2_legacy {
1036                 status = "okay";
1037         };
1038         mbox_dsp2_legacy: mbox_dsp2_legacy {
1039                 status = "okay";
1040         };
1041 };
1043 &mmu0_dsp1 {
1044         status = "okay";
1045 };
1047 &mmu1_dsp1 {
1048         status = "okay";
1049 };
1051 &mmu0_dsp2 {
1052         status = "okay";
1053 };
1055 &mmu1_dsp2 {
1056         status = "okay";
1057 };
1059 &mmu_ipu1 {
1060         status = "okay";
1061 };
1063 &mmu_ipu2 {
1064         status = "okay";
1065 };
1067 &ipu2 {
1068         status = "okay";
1069         memory-region = <&ipu2_cma_pool>;
1070         mboxes = <&mailbox6 &mbox_ipu2_legacy>;
1071         timers = <&timer3>;
1072         watchdog-timers = <&timer4>, <&timer9>;
1073 };
1075 &ipu1 {
1076         status = "okay";
1077         memory-region = <&ipu1_cma_pool>;
1078         mboxes = <&mailbox5 &mbox_ipu1_legacy>;
1079         timers = <&timer11>;
1080         watchdog-timers = <&timer7>, <&timer8>;
1081 };
1083 &dsp1 {
1084         status = "okay";
1085         memory-region = <&dsp1_cma_pool>;
1086         mboxes = <&mailbox5 &mbox_dsp1_legacy>;
1087         timers = <&timer5>;
1088         watchdog-timers = <&timer10>;
1089 };
1091 &dsp2 {
1092         status = "okay";
1093         memory-region = <&dsp2_cma_pool>;
1094         mboxes = <&mailbox6 &mbox_dsp2_legacy>;
1095         timers = <&timer6>;
1096 };
1098 &atl {
1099         status = "okay";
1101         atl2 {
1102                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
1103                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
1104         };
1105 };
1107 &mcasp3 {
1108         fck_parent = "atl_clkin2_ck";
1110         status = "okay";
1112         op-mode = <0>;          /* MCASP_IIS_MODE */
1113         tdm-slots = <2>;
1114         /* 4 serializer */
1115         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
1116                 1 2 0 0
1117         >;
1118         tx-num-evt = <8>;
1119         rx-num-evt = <8>;
1120 };
1122 &mcasp7 {
1123         #sound-dai-cells = <0>;
1125         status = "okay";
1127         op-mode = <0>;  /* MCASP_IIS_MODE */
1128         tdm-slots = <4>;
1129         /* 4 serializer */
1130         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
1131                 2 1 0 0
1132         >;
1133         tx-num-evt = <8>;
1134         rx-num-evt = <8>;
1135 };
1137 &mcasp8 {
1138         /* not used for audio. only the AXR2 pin is used as GPIO */
1139         status = "okay";
1140 };
1142 &usb2_phy1 {
1143         phy-supply = <&ldousb_reg>;
1144 };
1146 &usb2_phy2 {
1147         phy-supply = <&ldousb_reg>;
1148 };
1150 &vip1 {
1151         status = "okay";
1152 };
1154 video_in: &vin1a {
1155         status = "okay";
1156         endpoint@0 {
1157                 slave-mode;
1158                 remote-endpoint = <&onboardLI>;
1159         };
1160 };
1162 #include "dra7xx-jamr3.dtsi"
1164 &tvp_5158{
1165         mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_HIGH>,     /*CAM_FPD_MUX_S0*/
1166                         <&pcf_jamr3_21 8 GPIO_ACTIVE_LOW>;      /*SEL_TVP_FPD*/
1167 };