1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
13 / {
14 model = "TI DRA742";
15 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
17 memory {
18 device_type = "memory";
19 reg = <0x80000000 0x60000000>; /* 1536 MB */
20 };
22 reserved-memory {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges;
27 ipu2_cma_pool: ipu2_cma@95800000 {
28 compatible = "shared-dma-pool";
29 reg = <0x95800000 0x3800000>;
30 reusable;
31 status = "okay";
32 };
34 dsp1_cma_pool: dsp1_cma@99000000 {
35 compatible = "shared-dma-pool";
36 reg = <0x99000000 0x4000000>;
37 reusable;
38 status = "okay";
39 };
41 ipu1_cma_pool: ipu1_cma@9d000000 {
42 compatible = "shared-dma-pool";
43 reg = <0x9d000000 0x2000000>;
44 reusable;
45 status = "okay";
46 };
48 dsp2_cma_pool: dsp2_cma@9f000000 {
49 compatible = "shared-dma-pool";
50 reg = <0x9f000000 0x800000>;
51 reusable;
52 status = "okay";
53 };
54 };
56 evm_3v3_sw: fixedregulator-evm_3v3_sw {
57 compatible = "regulator-fixed";
58 regulator-name = "evm_3v3_sw";
59 regulator-min-microvolt = <3300000>;
60 regulator-max-microvolt = <3300000>;
61 };
63 vtt_fixed: fixedregulator-vtt {
64 compatible = "regulator-fixed";
65 regulator-name = "vtt_fixed";
66 regulator-min-microvolt = <1350000>;
67 regulator-max-microvolt = <1350000>;
68 regulator-always-on;
69 regulator-boot-on;
70 enable-active-high;
71 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
72 };
73 };
75 &dra7_pmx_core {
76 pinctrl-names = "default";
77 pinctrl-0 = <&vtt_pin>;
79 vtt_pin: pinmux_vtt_pin {
80 pinctrl-single,pins = <
81 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* gpio7_11 */
82 >;
83 };
85 i2c1_pins: pinmux_i2c1_pins {
86 pinctrl-single,pins = <
87 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
88 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
89 >;
90 };
92 i2c2_pins: pinmux_i2c2_pins {
93 pinctrl-single,pins = <
94 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
95 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
96 >;
97 };
99 i2c3_pins: pinmux_i2c3_pins {
100 pinctrl-single,pins = <
101 0x410 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
102 0x414 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
103 >;
104 };
106 mcspi1_pins: pinmux_mcspi1_pins {
107 pinctrl-single,pins = <
108 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */
109 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */
110 0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */
111 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
112 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */
113 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */
114 >;
115 };
117 mcspi2_pins: pinmux_mcspi2_pins {
118 pinctrl-single,pins = <
119 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
120 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
121 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
122 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
123 >;
124 };
126 uart1_pins: pinmux_uart1_pins {
127 pinctrl-single,pins = <
128 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
129 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
130 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
131 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
132 >;
133 };
135 uart2_pins: pinmux_uart2_pins {
136 pinctrl-single,pins = <
137 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
138 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
139 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
140 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
141 >;
142 };
144 uart3_pins: pinmux_uart3_pins {
145 pinctrl-single,pins = <
146 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
147 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
148 >;
149 };
151 qspi1_pins: pinmux_qspi1_pins {
152 pinctrl-single,pins = <
153 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
154 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
155 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
156 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
157 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
158 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
159 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
160 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
161 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
162 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
163 >;
164 };
166 usb1_pins: pinmux_usb1_pins {
167 pinctrl-single,pins = <
168 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
169 >;
170 };
172 usb2_pins: pinmux_usb2_pins {
173 pinctrl-single,pins = <
174 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
175 >;
176 };
177 };
179 &i2c1 {
180 status = "okay";
181 pinctrl-names = "default";
182 pinctrl-0 = <&i2c1_pins>;
183 clock-frequency = <400000>;
185 tps659038: tps659038@58 {
186 compatible = "ti,tps659038";
187 reg = <0x58>;
189 tps659038_pmic {
190 compatible = "ti,tps659038-pmic";
192 regulators {
193 smps123_reg: smps123 {
194 /* VDD_MPU */
195 regulator-name = "smps123";
196 regulator-min-microvolt = < 850000>;
197 regulator-max-microvolt = <1250000>;
198 regulator-always-on;
199 regulator-boot-on;
200 };
202 smps45_reg: smps45 {
203 /* VDD_DSPEVE */
204 regulator-name = "smps45";
205 regulator-min-microvolt = < 850000>;
206 regulator-max-microvolt = <1150000>;
207 regulator-boot-on;
208 };
210 smps6_reg: smps6 {
211 /* VDD_GPU - over VDD_SMPS6 */
212 regulator-name = "smps6";
213 regulator-min-microvolt = <850000>;
214 regulator-max-microvolt = <12500000>;
215 regulator-boot-on;
216 };
218 smps7_reg: smps7 {
219 /* CORE_VDD */
220 regulator-name = "smps7";
221 regulator-min-microvolt = <850000>;
222 regulator-max-microvolt = <1030000>;
223 regulator-always-on;
224 regulator-boot-on;
225 };
227 smps8_reg: smps8 {
228 /* VDD_IVAHD */
229 regulator-name = "smps8";
230 regulator-min-microvolt = < 850000>;
231 regulator-max-microvolt = <1250000>;
232 regulator-boot-on;
233 };
235 smps9_reg: smps9 {
236 /* VDDS1V8 */
237 regulator-name = "smps9";
238 regulator-min-microvolt = <1800000>;
239 regulator-max-microvolt = <1800000>;
240 regulator-always-on;
241 regulator-boot-on;
242 };
244 ldo1_reg: ldo1 {
245 /* LDO1_OUT --> SDIO */
246 regulator-name = "ldo1";
247 regulator-min-microvolt = <1800000>;
248 regulator-max-microvolt = <3300000>;
249 regulator-boot-on;
250 };
252 ldo2_reg: ldo2 {
253 /* VDD_RTCIO */
254 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
255 regulator-name = "ldo2";
256 regulator-min-microvolt = <3300000>;
257 regulator-max-microvolt = <3300000>;
258 regulator-boot-on;
259 };
261 ldo3_reg: ldo3 {
262 /* VDDA_1V8_PHY */
263 regulator-name = "ldo3";
264 regulator-min-microvolt = <1800000>;
265 regulator-max-microvolt = <1800000>;
266 regulator-boot-on;
267 };
269 ldo9_reg: ldo9 {
270 /* VDD_RTC */
271 regulator-name = "ldo9";
272 regulator-min-microvolt = <1050000>;
273 regulator-max-microvolt = <1050000>;
274 regulator-boot-on;
275 regulator-always-on;
276 };
278 ldoln_reg: ldoln {
279 /* VDDA_1V8_PLL */
280 regulator-name = "ldoln";
281 regulator-min-microvolt = <1800000>;
282 regulator-max-microvolt = <1800000>;
283 regulator-always-on;
284 regulator-boot-on;
285 };
287 ldousb_reg: ldousb {
288 /* VDDA_3V_USB: VDDA_USBHS33 */
289 regulator-name = "ldousb";
290 regulator-min-microvolt = <3300000>;
291 regulator-max-microvolt = <3300000>;
292 regulator-boot-on;
293 };
294 };
295 };
296 };
297 };
299 &i2c2 {
300 status = "okay";
301 pinctrl-names = "default";
302 pinctrl-0 = <&i2c2_pins>;
303 clock-frequency = <400000>;
304 };
306 &i2c3 {
307 status = "okay";
308 pinctrl-names = "default";
309 pinctrl-0 = <&i2c3_pins>;
310 clock-frequency = <3400000>;
311 };
313 &mcspi1 {
314 status = "okay";
315 pinctrl-names = "default";
316 pinctrl-0 = <&mcspi1_pins>;
317 };
319 &mcspi2 {
320 status = "okay";
321 pinctrl-names = "default";
322 pinctrl-0 = <&mcspi2_pins>;
323 };
325 &uart1 {
326 status = "okay";
327 pinctrl-names = "default";
328 pinctrl-0 = <&uart1_pins>;
329 };
331 &uart2 {
332 status = "okay";
333 pinctrl-names = "default";
334 pinctrl-0 = <&uart2_pins>;
335 };
337 &uart3 {
338 status = "okay";
339 pinctrl-names = "default";
340 pinctrl-0 = <&uart3_pins>;
341 };
343 &mmc1 {
344 status = "okay";
345 vmmc-supply = <&ldo1_reg>;
346 bus-width = <4>;
347 };
349 &mmc2 {
350 status = "okay";
351 vmmc-supply = <&evm_3v3_sw>;
352 bus-width = <8>;
353 };
355 &cpu0 {
356 cpu0-supply = <&smps123_reg>;
357 };
359 &qspi {
360 status = "okay";
361 pinctrl-names = "default";
362 pinctrl-0 = <&qspi1_pins>;
364 spi-max-frequency = <48000000>;
365 m25p80@0 {
366 compatible = "s25fl256s1";
367 spi-max-frequency = <48000000>;
368 reg = <0>;
369 spi-tx-bus-width = <1>;
370 spi-rx-bus-width = <4>;
371 spi-cpol;
372 spi-cpha;
373 #address-cells = <1>;
374 #size-cells = <1>;
376 /* MTD partition table.
377 * The ROM checks the first four physical blocks
378 * for a valid file to boot and the flash here is
379 * 64KiB block size.
380 */
381 partition@0 {
382 label = "QSPI.SPL";
383 reg = <0x00000000 0x000010000>;
384 };
385 partition@1 {
386 label = "QSPI.SPL.backup1";
387 reg = <0x00010000 0x00010000>;
388 };
389 partition@2 {
390 label = "QSPI.SPL.backup2";
391 reg = <0x00020000 0x00010000>;
392 };
393 partition@3 {
394 label = "QSPI.SPL.backup3";
395 reg = <0x00030000 0x00010000>;
396 };
397 partition@4 {
398 label = "QSPI.u-boot";
399 reg = <0x00040000 0x00100000>;
400 };
401 partition@5 {
402 label = "QSPI.u-boot-spl-os";
403 reg = <0x00140000 0x00010000>;
404 };
405 partition@6 {
406 label = "QSPI.u-boot-env";
407 reg = <0x00150000 0x00010000>;
408 };
409 partition@7 {
410 label = "QSPI.u-boot-env.backup1";
411 reg = <0x00160000 0x0010000>;
412 };
413 partition@8 {
414 label = "QSPI.kernel";
415 reg = <0x00170000 0x0800000>;
416 };
417 partition@9 {
418 label = "QSPI.file-system";
419 reg = <0x00970000 0x01690000>;
420 };
421 };
422 };
424 &usb1 {
425 dr_mode = "peripheral";
426 pinctrl-names = "default";
427 pinctrl-0 = <&usb1_pins>;
428 };
430 &usb2 {
431 dr_mode = "host";
432 pinctrl-names = "default";
433 pinctrl-0 = <&usb2_pins>;
434 };
436 &gpio7 {
437 ti,no-reset-on-init;
438 ti,no-idle-on-init;
439 };
441 &mailbox5 {
442 status = "okay";
443 mbox_ipu1_legacy: mbox_ipu1_legacy {
444 status = "okay";
445 };
446 mbox_dsp1_legacy: mbox_dsp1_legacy {
447 status = "okay";
448 };
449 };
451 &mailbox6 {
452 status = "okay";
453 mbox_ipu2_legacy: mbox_ipu2_legacy {
454 status = "okay";
455 };
456 mbox_dsp2_legacy: mbox_dsp2_legacy {
457 status = "okay";
458 };
459 };
461 &mmu0_dsp1 {
462 status = "okay";
463 };
465 &mmu1_dsp1 {
466 status = "okay";
467 };
469 &mmu0_dsp2 {
470 status = "okay";
471 };
473 &mmu1_dsp2 {
474 status = "okay";
475 };
477 &mmu_ipu1 {
478 status = "okay";
479 };
481 &mmu_ipu2 {
482 status = "okay";
483 };
485 &ipu2 {
486 status = "okay";
487 memory-region = <&ipu2_cma_pool>;
488 mboxes = <&mailbox6 &mbox_ipu2_legacy>;
489 timers = <&timer3>;
490 watchdog-timers = <&timer4>, <&timer9>;
491 };
493 &ipu1 {
494 status = "okay";
495 memory-region = <&ipu1_cma_pool>;
496 mboxes = <&mailbox5 &mbox_ipu1_legacy>;
497 timers = <&timer11>;
498 };
500 &dsp1 {
501 status = "okay";
502 memory-region = <&dsp1_cma_pool>;
503 mboxes = <&mailbox5 &mbox_dsp1_legacy>;
504 timers = <&timer5>;
505 };
507 &dsp2 {
508 status = "okay";
509 memory-region = <&dsp2_cma_pool>;
510 mboxes = <&mailbox6 &mbox_dsp2_legacy>;
511 timers = <&timer6>;
512 };