arch/arm/boot/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/clk/ti-dra7-atl.h>
  14
  15 / {
  16         model = "TI DRA742";
  17         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  18
  19         memory {
  20                 device_type = "memory";
  21                 reg = <0x80000000 0x60000000>; /* 1536 MB */
  22         };
  23
  24         reserved_mem: reserved-memory {
  25                 #address-cells = <1>;
  26                 #size-cells = <1>;
  27                 ranges;
  28
  29                 ipu2_cma_pool: ipu2_cma@95800000 {
  30                         compatible = "shared-dma-pool";
  31                         reg = <0x95800000 0x3800000>;
  32                         reusable;
  33                         status = "okay";
  34                 };
  35
  36                 dsp1_cma_pool: dsp1_cma@99000000 {
  37                         compatible = "shared-dma-pool";
  38                         reg = <0x99000000 0x4000000>;
  39                         reusable;
  40                         status = "okay";
  41                 };
  42
  43                 ipu1_cma_pool: ipu1_cma@9d000000 {
  44                         compatible = "shared-dma-pool";
  45                         reg = <0x9d000000 0x2000000>;
  46                         reusable;
  47                         status = "okay";
  48                 };
  49
  50                 dsp2_cma_pool: dsp2_cma@9f000000 {
  51                         compatible = "shared-dma-pool";
  52                         reg = <0x9f000000 0x800000>;
  53                         reusable;
  54                         status = "okay";
  55                 };
  56         };
  57
  58         extcon_usb1: extcon_usb1 {
  59                 compatible = "linux,extcon-usb-gpio";
  60                 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  61         };
  62
  63         extcon_usb2: extcon_usb2 {
  64                 compatible = "linux,extcon-usb-gpio";
  65                 id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  66         };
  67
  68         evm_3v3_sd: fixedregulator-sd {
  69                 compatible = "regulator-fixed";
  70                 regulator-name = "evm_3v3_sd";
  71                 regulator-min-microvolt = <3300000>;
  72                 regulator-max-microvolt = <3300000>;
  73                 enable-active-high;
  74                 gpio = <&pcf_gpio_21 5 0>;
  75         };
  76
  77         evm_3v3_sw: fixedregulator-evm_3v3_sw {
  78                 compatible = "regulator-fixed";
  79                 regulator-name = "evm_3v3_sw";
  80                 vin-supply = <&sysen1>;
  81                 regulator-min-microvolt = <3300000>;
  82                 regulator-max-microvolt = <3300000>;
  83         };
  84
  85         aic_dvdd: fixedregulator-aic_dvdd {
  86                 /* TPS77018DBVT */
  87                 compatible = "regulator-fixed";
  88                 regulator-name = "aic_dvdd";
  89                 vin-supply = <&evm_3v3_sw>;
  90                 regulator-min-microvolt = <1800000>;
  91                 regulator-max-microvolt = <1800000>;
  92         };
  93
  94         vmmcwl_fixed: fixedregulator-mmcwl {
  95                 compatible = "regulator-fixed";
  96                 regulator-name = "vmmcwl_fixed";
  97                 regulator-min-microvolt = <1800000>;
  98                 regulator-max-microvolt = <1800000>;
  99                 gpio = <&gpio5 8 0>;    /* gpio5_8 */
 100                 startup-delay-us = <70000>;
 101                 enable-active-high;
 102         };
 103
 104         kim {
 105                 compatible = "kim";
 106                 nshutdown_gpio = <132>;
 107                 dev_name = "/dev/ttyS2";
 108                 flow_cntrl = <1>;
 109                 baud_rate = <3686400>;
 110         };
 111
 112         btwilink {
 113                 compatible = "btwilink";
 114         };
 115
 116         vtt_fixed: fixedregulator-vtt {
 117                 compatible = "regulator-fixed";
 118                 regulator-name = "vtt_fixed";
 119                 regulator-min-microvolt = <1350000>;
 120                 regulator-max-microvolt = <1350000>;
 121                 regulator-always-on;
 122                 regulator-boot-on;
 123                 enable-active-high;
 124                 vin-supply = <&sysen2>;
 125                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
 126         };
 127
 128         aliases {
 129                 display0 = &hdmi0;
 130                 sound0 = &primary_sound;
 131                 sound1 = &hdmi;
 132         };
 133
 134         hdmi0: connector@1 {
 135                 compatible = "hdmi-connector";
 136                 label = "hdmi";
 137
 138                 type = "a";
 139
 140                 port {
 141                         hdmi_connector_in: endpoint {
 142                                 remote-endpoint = <&tpd12s015_out>;
 143                         };
 144                 };
 145         };
 146
 147         tpd12s015: encoder@1 {
 148                 compatible = "ti,dra7evm-tpd12s015";
 149
 150                 pinctrl-names = "i2c", "ddc";
 151                 pinctrl-0 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_i2c>;
 152                 pinctrl-1 = <&hdmi_i2c_sel_pin &hdmi_i2c_pins_ddc>;
 153
 154                 ddc-i2c-bus = <&i2c2>;
 155                 mcasp-gpio = <&mcasp8>;
 156
 157                 gpios = <&pcf_hdmi 4 0>,        /* P4, CT CP HPD */
 158                         <&pcf_hdmi 5 0>,        /* P5, LS OE */
 159                         <&gpio7 12 0>;  /* gpio7_12/sp1_cs2, HPD */
 160
 161                 ports {
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164
 165                         port@0 {
 166                                 reg = <0>;
 167
 168                                 tpd12s015_in: endpoint@0 {
 169                                         remote-endpoint = <&hdmi_out>;
 170                                 };
 171                         };
 172
 173                         port@1 {
 174                                 reg = <1>;
 175
 176                                 tpd12s015_out: endpoint@0 {
 177                                         remote-endpoint = <&hdmi_connector_in>;
 178                                 };
 179                         };
 180                 };
 181         };
 182
 183     ocp {
 184         gpu: gpu@0x56000000 {
 185             gpu0-voltdm = <&voltdm_gpu>;
 186         };
 187     };
 188
 189         primary_sound: primary_sound {
 190                 compatible = "ti,dra7xx-evm-audio";
 191                 ti,model = "DRA7xx-EVM";
 192                 ti,always-on;
 193                 ti,audio-codec = <&tlv320aic3106>;
 194                 ti,mcasp-controller = <&mcasp3>;
 195                 ti,codec-clock-rate = <11289600>;
 196                 clocks = <&atl_clkin2_ck>;
 197                 clock-names = "mclk";
 198                 ti,audio-routing =
 199                         "Headphone Jack",       "HPLOUT",
 200                         "Headphone Jack",       "HPROUT",
 201                         "Line Out",             "LLOUT",
 202                         "Line Out",             "RLOUT",
 203                         "MIC3L",                "Mic Jack",
 204                         "MIC3R",                "Mic Jack",
 205                         "Mic Jack",             "Mic Bias",
 206                         "LINE1L",               "Line In",
 207                         "LINE1R",               "Line In";
 208         };
 209
 210         btwilink_sound: btwilink_sound {
 211                 #sound-dai-cells = <0>;
 212                 compatible = "linux,bt-sco-audio";
 213                 status = "okay";
 214         };
 215
 216         simple_bt_sco_card: bt_sco_card {
 217                 compatible = "simple-audio-card";
 218                 simple-audio-card,name = "DRA7xx-WiLink";
 219                 simple-audio-card,format = "dsp_a";
 220                 simple-audio-card,frame-master = <&btwilink_codec>;
 221                 simple-audio-card,bitclock-master = <&btwilink_codec>;
 222                 simple-audio-card,frame-inversion;
 223
 224                 simple-audio-card,cpu {
 225                         sound-dai = <&mcasp7>;
 226                 };
 227
 228                 btwilink_codec: simple-audio-card,codec {
 229                         sound-dai = <&btwilink_sound>;
 230                 };
 231         };
 232 };
 233
 234 &dra7_pmx_core {
 235         hdmi_i2c_sel_pin: pinmux_hdmi_i2c_sel_pin {
 236                 pinctrl-single,pins = <
 237                         /* this pin is used as a GPIO via mcasp */
 238                         0x2fc   (PIN_OUTPUT | MUX_MODE1) /* mcasp8_axr2 */
 239                 >;
 240         };
 241
 242         hdmi_i2c_pins_i2c: pinmux_hdmi_i2c_pins_default {
 243                 pinctrl-single,pins = <
 244                         0x408   (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
 245                         0x40c   (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
 246                 >;
 247         };
 248
 249         hdmi_i2c_pins_ddc: pinmux_hdmi_i2c_pins_ddc {
 250                 pinctrl-single,pins = <
 251                         0x408   (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
 252                         0x40c   (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
 253                 >;
 254         };
 255
 256         dcan1_pins_default: dcan1_pins_default {
 257                 pinctrl-single,pins = <
 258                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 259                         0x418   (PULL_UP | MUX_MODE1)           /* wakeup0.dcan1_rx */
 260                 >;
 261         };
 262
 263         dcan1_pins_sleep: dcan1_pins_sleep {
 264                 pinctrl-single,pins = <
 265                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
 266                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
 267                 >;
 268         };
 269
 270         mmc1_pins_default: pinmux_mmc1_default_pins {
 271                 pinctrl-single,pins = <
 272                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_clk.clk */
 273                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_cmd.cmd */
 274                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat0.dat0 */
 275                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat1.dat1 */
 276                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat2.dat2 */
 277                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat3.dat3 */
 278                         0x36c (PIN_INPUT | MUX_MODE14)          /* mmc1sdcd.gpio187 */
 279                 >;
 280         };
 281
 282         mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
 283                 pinctrl-single,pins = <
 284                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_clk.clk */
 285                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_cmd.cmd */
 286                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat0.dat0 */
 287                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat1.dat1 */
 288                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat2.dat2 */
 289                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat3.dat3 */
 290                 >;
 291         };
 292
 293         mmc1_pins_hs: pinmux_mmc1_hs_pins {
 294                 pinctrl-single,pins = <
 295                         0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_clk.clk */
 296                         0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_cmd.cmd */
 297                         0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat0.dat0 */
 298                         0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat1.dat1 */
 299                         0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat2.dat2 */
 300                         0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat3.dat3 */
 301                 >;
 302         };
 303
 304         mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
 305                 pinctrl-single,pins = <
 306                         0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_clk.clk */
 307                         0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_cmd.cmd */
 308                         0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat0.dat0 */
 309                         0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat1.dat1 */
 310                         0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat2.dat2 */
 311                         0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat3.dat3 */
 312                 >;
 313         };
 314
 315         mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
 316                 pinctrl-single,pins = <
 317                         0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_clk.clk */
 318                         0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_cmd.cmd */
 319                         0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_dat0.dat0 */
 320                         0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_dat1.dat1 */
 321                         0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_dat2.dat2 */
 322                         0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)      /* mmc1_dat3.dat3 */
 323                 >;
 324         };
 325
 326         mmc2_pins_default: mmc2_pins_default {
 327                 pinctrl-single,pins = <
 328                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 329                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 330                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 331                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 332                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 333                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 334                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 335                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 336                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 337                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 338                 >;
 339         };
 340
 341         mmc2_pins_hs: pinmux_mmc2_hs_pins {
 342                 pinctrl-single,pins = <
 343                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 344                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 345                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 346                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 347                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 348                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 349                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 350                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 351                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 352                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 353                 >;
 354         };
 355
 356         mmc2_pins_ddr_3_3v: pinmux_mmc2_ddr_3_3v_pins {
 357                 pinctrl-single,pins = <
 358                         0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 359                         0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 360                         0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 361                         0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 362                         0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 363                         0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 364                         0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 365                         0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 366                         0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 367                         0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 368                 >;
 369         };
 370 };
 371
 372 &dra7_iodelay_core {
 373         mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
 374                 pinctrl-single,pins = <
 375                         0x618 (A_DELAY(572) | G_DELAY(540))     /* CFG_MMC1_CLK_IN */
 376                         0x624 (A_DELAY(0) | G_DELAY(600))       /* CFG_MMC1_CMD_IN */
 377                         0x630 (A_DELAY(403) | G_DELAY(120))     /* CFG_MMC1_DAT0_IN */
 378                         0x63c (A_DELAY(23) | G_DELAY(60))       /* CFG_MMC1_DAT1_IN */
 379                         0x648 (A_DELAY(25) | G_DELAY(60))       /* CFG_MMC1_DAT2_IN */
 380                         0x654 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT3_IN */
 381                         0x620 (A_DELAY(1525) | G_DELAY(0))      /* CFG_MMC1_CLK_IN */
 382                         0x628 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_CMD_OEN */
 383                         0x62c (A_DELAY(55) | G_DELAY(0))        /* CFG_MMC1_CMD_OUT */
 384                         0x634 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT0_OEN */
 385                         0x638 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT0_OUT */
 386                         0x640 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT1_OEN */
 387                         0x644 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT1_OUT */
 388                         0x64c (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT2_OEN */
 389                         0x650 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT2_OUT */
 390                         0x658 (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT3_OEN */
 391                         0x65c (A_DELAY(0) | G_DELAY(0))         /* CFG_MMC1_DAT3_OUT */
 392                 >;
 393         };
 394
 395         mmc2_iodelay_ddr_3_3v_conf: mmc2_iodelay_ddr_3_3v_conf {
 396                 pinctrl-single,pins = <
 397                         0x18c (A_DELAY(0) | G_DELAY(120))       /* CFG_GPMC_A19_IN */
 398                         0x1a4 (A_DELAY(265) | G_DELAY(360))     /* CFG_GPMC_A20_IN */
 399                         0x1b0 (A_DELAY(0) | G_DELAY(120))       /* CFG_GPMC_A21_IN */
 400                         0x1bc (A_DELAY(0) | G_DELAY(120))       /* CFG_GPMC_A22_IN */
 401                         0x1c8 (A_DELAY(287) | G_DELAY(420))     /* CFG_GPMC_A23_IN */
 402                         0x1d4 (A_DELAY(144) | G_DELAY(240))     /* CFG_GPMC_A24_IN */
 403                         0x1e0 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A25_IN */
 404                         0x1ec (A_DELAY(0) | G_DELAY(120))       /* CFG_GPMC_A26_IN */
 405                         0x1f8 (A_DELAY(120) | G_DELAY(180))     /* CFG_GPMC_A27_IN */
 406                         0x360 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_CS1_IN */
 407                         0x190 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A19_OEN */
 408                         0x194 (A_DELAY(174) | G_DELAY(0))       /* CFG_GPMC_A19_OUT */
 409                         0x1a8 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A20_OEN */
 410                         0x1ac (A_DELAY(168) | G_DELAY(0))       /* CFG_GPMC_A20_OUT */
 411                         0x1b4 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A21_OEN */
 412                         0x1b8 (A_DELAY(136) | G_DELAY(0))       /* CFG_GPMC_A21_OUT */
 413                         0x1c0 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A22_OEN */
 414                         0x1c4 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A22_OUT */
 415                         0x1d0 (A_DELAY(879) | G_DELAY(0))       /* CFG_GPMC_A23_OUT */
 416                         0x1d8 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A24_OEN */
 417                         0x1dc (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A24_OUT */
 418                         0x1e4 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A25_OEN */
 419                         0x1e8 (A_DELAY(34) | G_DELAY(0))        /* CFG_GPMC_A25_OUT */
 420                         0x1f0 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A26_OEN */
 421                         0x1f4 (A_DELAY(120) | G_DELAY(0))       /* CFG_GPMC_A26_OUT */
 422                         0x1fc (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A27_OEN */
 423                         0x200 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_A27_OUT */
 424                         0x364 (A_DELAY(0) | G_DELAY(0))         /* CFG_GPMC_CS1_OEN */
 425                         0x368 (A_DELAY(11) | G_DELAY(0))        /* CFG_GPMC_CS1_OUT */
 426                 >;
 427         };
 428 };
 429
 430 &i2c1 {
 431         status = "okay";
 432         clock-frequency = <400000>;
 433
 434         tps659038: tps659038@58 {
 435                 compatible = "ti,tps659038";
 436                 reg = <0x58>;
 437
 438                 tps659038_pmic {
 439                         compatible = "ti,tps659038-pmic";
 440
 441                         regulators {
 442                                 smps123_reg: smps123 {
 443                                         /* VDD_MPU */
 444                                         regulator-name = "smps123";
 445                                         regulator-min-microvolt = < 850000>;
 446                                         regulator-max-microvolt = <1250000>;
 447                                         regulator-always-on;
 448                                         regulator-boot-on;
 449                                 };
 450
 451                                 smps45_reg: smps45 {
 452                                         /* VDD_DSPEVE */
 453                                         regulator-name = "smps45";
 454                                         regulator-min-microvolt = < 850000>;
 455                                         regulator-max-microvolt = <1150000>;
 456                                         regulator-boot-on;
 457                                         regulator-always-on;
 458                                 };
 459
 460                                 smps6_reg: smps6 {
 461                                         /* VDD_GPU - over VDD_SMPS6 */
 462                                         regulator-name = "smps6";
 463                                         regulator-min-microvolt = <850000>;
 464                                         regulator-max-microvolt = <1250000>;
 465                                         regulator-boot-on;
 466                                         regulator-always-on;
 467                                 };
 468
 469                                 smps7_reg: smps7 {
 470                                         /* CORE_VDD */
 471                                         regulator-name = "smps7";
 472                                         regulator-min-microvolt = <850000>;
 473                                         regulator-max-microvolt = <1060000>;
 474                                         regulator-always-on;
 475                                         regulator-boot-on;
 476                                 };
 477
 478                                 smps8_reg: smps8 {
 479                                         /* VDD_IVAHD */
 480                                         regulator-name = "smps8";
 481                                         regulator-min-microvolt = < 850000>;
 482                                         regulator-max-microvolt = <1250000>;
 483                                         regulator-boot-on;
 484                                         regulator-always-on;
 485                                 };
 486
 487                                 smps9_reg: smps9 {
 488                                         /* VDDS1V8 */
 489                                         regulator-name = "smps9";
 490                                         regulator-min-microvolt = <1800000>;
 491                                         regulator-max-microvolt = <1800000>;
 492                                         regulator-always-on;
 493                                         regulator-boot-on;
 494                                 };
 495
 496                                 ldo1_reg: ldo1 {
 497                                         /* LDO1_OUT --> SDIO  */
 498                                         regulator-name = "ldo1";
 499                                         regulator-min-microvolt = <1800000>;
 500                                         regulator-max-microvolt = <3300000>;
 501                                         regulator-boot-on;
 502                                         regulator-always-on;
 503                                 };
 504
 505                                 ldo2_reg: ldo2 {
 506                                         /* VDD_RTCIO */
 507                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 508                                         regulator-name = "ldo2";
 509                                         regulator-min-microvolt = <3300000>;
 510                                         regulator-max-microvolt = <3300000>;
 511                                         regulator-boot-on;
 512                                         regulator-always-on;
 513                                 };
 514
 515                                 ldo3_reg: ldo3 {
 516                                         /* VDDA_1V8_PHY */
 517                                         regulator-name = "ldo3";
 518                                         regulator-min-microvolt = <1800000>;
 519                                         regulator-max-microvolt = <1800000>;
 520                                         regulator-always-on;
 521                                         regulator-boot-on;
 522                                 };
 523
 524                                 ldo9_reg: ldo9 {
 525                                         /* VDD_RTC */
 526                                         regulator-name = "ldo9";
 527                                         regulator-min-microvolt = <1050000>;
 528                                         regulator-max-microvolt = <1050000>;
 529                                         regulator-boot-on;
 530                                         regulator-always-on;
 531                                 };
 532
 533                                 ldoln_reg: ldoln {
 534                                         /* VDDA_1V8_PLL */
 535                                         regulator-name = "ldoln";
 536                                         regulator-min-microvolt = <1800000>;
 537                                         regulator-max-microvolt = <1800000>;
 538                                         regulator-always-on;
 539                                         regulator-boot-on;
 540                                 };
 541
 542                                 ldousb_reg: ldousb {
 543                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 544                                         regulator-name = "ldousb";
 545                                         regulator-min-microvolt = <3300000>;
 546                                         regulator-max-microvolt = <3300000>;
 547                                         regulator-boot-on;
 548                                         regulator-always-on;
 549                                 };
 550
 551                                 /* REGEN1 is unused */
 552
 553                                 regen2: regen2 {
 554                                         /* Needed for PMIC internal resources */
 555                                         regulator-name = "regen2";
 556                                         regulator-boot-on;
 557                                         regulator-always-on;
 558                                 };
 559
 560                                 /* REGEN3 is unused */
 561
 562                                 sysen1: sysen1 {
 563                                         /* PMIC_REGEN_3V3 */
 564                                         regulator-name = "sysen1";
 565                                         regulator-boot-on;
 566                                         regulator-always-on;
 567                                 };
 568
 569                                 sysen2: sysen2 {
 570                                         /* PMIC_REGEN_DDR */
 571                                         regulator-name = "sysen2";
 572                                         regulator-boot-on;
 573                                         regulator-always-on;
 574                                 };
 575                         };
 576                 };
 577         };
 578
 579         pcf_lcd: gpio@20 {
 580                 compatible = "nxp,pcf8575";
 581                 reg = <0x20>;
 582                 gpio-controller;
 583                 #gpio-cells = <2>;
 584         };
 585
 586         pcf_gpio_21: gpio@21 {
 587                 compatible = "nxp,pcf8575";
 588                 reg = <0x21>;
 589                 lines-initial-states = <0x1408>;
 590                 gpio-controller;
 591                 #gpio-cells = <2>;
 592                 interrupt-parent = <&gpio6>;
 593                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 594                 interrupt-controller;
 595                 #interrupt-cells = <2>;
 596         };
 597
 598
 599         tlv320aic3106: tlv320aic3106@18 {
 600                 compatible = "ti,tlv320aic3106";
 601                 reg = <0x18>;
 602                 adc-settle-ms = <40>;
 603                 ai3x-micbias-vg = <1>;          /* 2.0V */
 604                 status = "okay";
 605
 606                 /* Regulators */
 607                 AVDD-supply = <&evm_3v3_sw>;
 608                 IOVDD-supply = <&evm_3v3_sw>;
 609                 DRVDD-supply = <&evm_3v3_sw>;
 610                 DVDD-supply = <&aic_dvdd>;
 611         };
 612 };
 613
 614 i2c_p3_exp: &i2c2 {
 615         status = "okay";
 616         clock-frequency = <400000>;
 617
 618         pcf_hdmi: gpio@26 {
 619                 compatible = "nxp,pcf8575";
 620                 reg = <0x26>;
 621                 lines-initial-states = <0xffeb>;
 622                 gpio-controller;
 623                 #gpio-cells = <2>;
 624         };
 625
 626         ov10633@37 {
 627                 compatible = "ovti,ov10633";
 628                 reg = <0x37>;
 629
 630                 mux-gpios = <&pcf_hdmi 3        GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
 631                 port {
 632                         onboardLI: endpoint {
 633                                 remote-endpoint = <&vin1a>;
 634                                 hsync-active = <1>;
 635                                 vsync-active = <1>;
 636                                 pclk-sample = <0>;
 637                         };
 638                 };
 639         };
 640 };
 641
 642 &i2c3 {
 643         status = "okay";
 644         clock-frequency = <3400000>;
 645 };
 646
 647 &mcspi1 {
 648         status = "okay";
 649 };
 650
 651 &mcspi2 {
 652         status = "okay";
 653 };
 654
 655 &uart1 {
 656         status = "okay";
 657         interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
 658                                &dra7_pmx_core 0x3e0>;
 659 };
 660
 661 &uart2 {
 662         status = "okay";
 663 };
 664
 665 &uart3 {
 666         status = "okay";
 667         gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
 668 };
 669
 670 &mmc1 {
 671         status = "okay";
 672         pbias-supply = <&pbias_mmc_reg>;
 673         vmmc-supply = <&evm_3v3_sd>;
 674         vmmc_aux-supply = <&ldo1_reg>;
 675         bus-width = <4>;
 676         /*
 677          * SDCD signal is not being used here - using the fact that GPIO mode
 678          * is always hardwired.
 679          */
 680         cd-gpios = <&gpio6 27 0>;
 681         pinctrl-names = "default", "hs", "sdr12", "sdr25", "ddr50";
 682         pinctrl-0 = <&mmc1_pins_default>;
 683         pinctrl-1 = <&mmc1_pins_hs>;
 684         pinctrl-2 = <&mmc1_pins_sdr12>;
 685         pinctrl-3 = <&mmc1_pins_sdr25>;
 686         pinctrl-4 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>;
 687         sd-uhs-ddr50;
 688         sd-uhs-sdr25;
 689         sd-uhs-sdr12;
 690 };
 691
 692 &mmc2 {
 693         status = "okay";
 694         vmmc-supply = <&evm_3v3_sw>;
 695         bus-width = <8>;
 696         pinctrl-names = "default", "hs", "ddr_3_3v";
 697         pinctrl-0 = <&mmc2_pins_default>;
 698         pinctrl-1 = <&mmc2_pins_hs>;
 699         pinctrl-2 = <&mmc2_pins_ddr_3_3v &mmc2_iodelay_ddr_3_3v_conf>;
 700         mmc-ddr-1_8v;
 701 };
 702
 703 &mmc4 {
 704         status = "okay";
 705         vmmc-supply = <&vmmcwl_fixed>;
 706         bus-width = <4>;
 707         cap-power-off-card;
 708         keep-power-in-suspend;
 709         ti,non-removable;
 710
 711         #address-cells = <1>;
 712         #size-cells = <0>;
 713         wlcore: wlcore@0 {
 714                 compatible = "ti,wlcore";
 715                 reg = <2>;
 716                 interrupt-parent = <&gpio5>;
 717                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 718         };
 719 };
 720
 721 &cpu0 {
 722         cpu0-voltdm = <&voltdm_mpu>;
 723         voltage-tolerance = <1>;
 724 };
 725
 726 &voltdm_mpu {
 727         vdd-supply = <&smps123_reg>;
 728 };
 729
 730 &voltdm_dspeve {
 731         vdd-supply = <&smps45_reg>;
 732 };
 733
 734 &voltdm_gpu {
 735         vdd-supply = <&smps6_reg>;
 736 };
 737
 738 &voltdm_ivahd {
 739         vdd-supply = <&smps8_reg>;
 740 };
 741
 742 &voltdm_core {
 743         vdd-supply = <&smps7_reg>;
 744 };
 745
 746 &qspi {
 747         status = "okay";
 748
 749         spi-max-frequency = <48000000>;
 750         m25p80@0 {
 751                 compatible = "s25fl256s1";
 752                 spi-max-frequency = <48000000>;
 753                 reg = <0>;
 754                 spi-tx-bus-width = <1>;
 755                 spi-rx-bus-width = <4>;
 756                 spi-cpol;
 757                 spi-cpha;
 758                 #address-cells = <1>;
 759                 #size-cells = <1>;
 760
 761                 /* MTD partition table.
 762                  * The ROM checks the first four physical blocks
 763                  * for a valid file to boot and the flash here is
 764                  * 64KiB block size.
 765                  */
 766                 partition@0 {
 767                         label = "QSPI.SPL";
 768                         reg = <0x00000000 0x000010000>;
 769                 };
 770                 partition@1 {
 771                         label = "QSPI.SPL.backup1";
 772                         reg = <0x00010000 0x00010000>;
 773                 };
 774                 partition@2 {
 775                         label = "QSPI.SPL.backup2";
 776                         reg = <0x00020000 0x00010000>;
 777                 };
 778                 partition@3 {
 779                         label = "QSPI.SPL.backup3";
 780                         reg = <0x00030000 0x00010000>;
 781                 };
 782                 partition@4 {
 783                         label = "QSPI.u-boot";
 784                         reg = <0x00040000 0x00100000>;
 785                 };
 786                 partition@5 {
 787                         label = "QSPI.u-boot-spl-os";
 788                         reg = <0x00140000 0x00080000>;
 789                 };
 790                 partition@6 {
 791                         label = "QSPI.u-boot-env";
 792                         reg = <0x001c0000 0x00010000>;
 793                 };
 794                 partition@7 {
 795                         label = "QSPI.u-boot-env.backup1";
 796                         reg = <0x001d0000 0x0010000>;
 797                 };
 798                 partition@8 {
 799                         label = "QSPI.kernel";
 800                         reg = <0x001e0000 0x0800000>;
 801                 };
 802                 partition@9 {
 803                         label = "QSPI.file-system";
 804                         reg = <0x009e0000 0x01620000>;
 805                 };
 806         };
 807 };
 808
 809 &omap_dwc3_1 {
 810         extcon = <&extcon_usb1>;
 811 };
 812
 813 &omap_dwc3_2 {
 814         extcon = <&extcon_usb2>;
 815 };
 816
 817 &usb1 {
 818         dr_mode = "otg";
 819 };
 820
 821 &usb2 {
 822         dr_mode = "host";
 823 };
 824
 825 &mac {
 826         status = "okay";
 827         dual_emac;
 828         ti,no-idle;
 829 };
 830
 831 &cpsw_emac0 {
 832         phy_id = <&davinci_mdio>, <2>;
 833         phy-mode = "rgmii";
 834         dual_emac_res_vlan = <1>;
 835 };
 836
 837 &cpsw_emac1 {
 838         phy_id = <&davinci_mdio>, <3>;
 839         phy-mode = "rgmii";
 840         dual_emac_res_vlan = <2>;
 841 };
 842
 843 &elm {
 844         status = "okay";
 845 };
 846
 847 &gpmc {
 848         status = "disabled";
 849         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 850         nand@0,0 {
 851                 reg = <0 0 4>;          /* device IO registers */
 852                 ti,nand-ecc-opt = "bch8";
 853                 ti,elm-id = <&elm>;
 854                 nand-bus-width = <16>;
 855                 gpmc,device-width = <2>;
 856                 gpmc,sync-clk-ps = <0>;
 857                 gpmc,cs-on-ns = <0>;
 858                 gpmc,cs-rd-off-ns = <80>;
 859                 gpmc,cs-wr-off-ns = <80>;
 860                 gpmc,adv-on-ns = <0>;
 861                 gpmc,adv-rd-off-ns = <60>;
 862                 gpmc,adv-wr-off-ns = <60>;
 863                 gpmc,we-on-ns = <10>;
 864                 gpmc,we-off-ns = <50>;
 865                 gpmc,oe-on-ns = <4>;
 866                 gpmc,oe-off-ns = <40>;
 867                 gpmc,access-ns = <40>;
 868                 gpmc,wr-access-ns = <80>;
 869                 gpmc,rd-cycle-ns = <80>;
 870                 gpmc,wr-cycle-ns = <80>;
 871                 gpmc,bus-turnaround-ns = <0>;
 872                 gpmc,cycle2cycle-delay-ns = <0>;
 873                 gpmc,clk-activation-ns = <0>;
 874                 gpmc,wait-monitoring-ns = <0>;
 875                 gpmc,wr-data-mux-bus-ns = <0>;
 876                 /* MTD partition table */
 877                 /* All SPL-* partitions are sized to minimal length
 878                  * which can be independently programmable. For
 879                  * NAND flash this is equal to size of erase-block */
 880                 #address-cells = <1>;
 881                 #size-cells = <1>;
 882                 partition@0 {
 883                         label = "NAND.SPL";
 884                         reg = <0x00000000 0x000020000>;
 885                 };
 886                 partition@1 {
 887                         label = "NAND.SPL.backup1";
 888                         reg = <0x00020000 0x00020000>;
 889                 };
 890                 partition@2 {
 891                         label = "NAND.SPL.backup2";
 892                         reg = <0x00040000 0x00020000>;
 893                 };
 894                 partition@3 {
 895                         label = "NAND.SPL.backup3";
 896                         reg = <0x00060000 0x00020000>;
 897                 };
 898                 partition@4 {
 899                         label = "NAND.u-boot-spl-os";
 900                         reg = <0x00080000 0x00040000>;
 901                 };
 902                 partition@5 {
 903                         label = "NAND.u-boot";
 904                         reg = <0x000c0000 0x00100000>;
 905                 };
 906                 partition@6 {
 907                         label = "NAND.u-boot-env";
 908                         reg = <0x001c0000 0x00020000>;
 909                 };
 910                 partition@7 {
 911                         label = "NAND.u-boot-env.backup1";
 912                         reg = <0x001e0000 0x00020000>;
 913                 };
 914                 partition@8 {
 915                         label = "NAND.kernel";
 916                         reg = <0x00200000 0x00800000>;
 917                 };
 918                 partition@9 {
 919                         label = "NAND.file-system";
 920                         reg = <0x00a00000 0x0f600000>;
 921                 };
 922         };
 923 };
 924
 925 &gpio7 {
 926         ti,no-reset-on-init;
 927         ti,no-idle-on-init;
 928 };
 929
 930 &dss {
 931         status = "ok";
 932
 933         vdda_video-supply = <&ldoln_reg>;
 934 };
 935
 936 &hdmi {
 937         status = "ok";
 938         vdda-supply = <&ldo3_reg>;
 939
 940         port {
 941                 hdmi_out: endpoint {
 942                         remote-endpoint = <&tpd12s015_in>;
 943                 };
 944         };
 945 };
 946
 947 &dcan1 {
 948         status = "ok";
 949         pinctrl-names = "default", "sleep";
 950         pinctrl-0 = <&dcan1_pins_default>;
 951         pinctrl-1 = <&dcan1_pins_sleep>;
 952 };
 953
 954 &mailbox5 {
 955         status = "okay";
 956         mbox_ipu1_legacy: mbox_ipu1_legacy {
 957                 status = "okay";
 958         };
 959         mbox_dsp1_legacy: mbox_dsp1_legacy {
 960                 status = "okay";
 961         };
 962 };
 963
 964 &mailbox6 {
 965         status = "okay";
 966         mbox_ipu2_legacy: mbox_ipu2_legacy {
 967                 status = "okay";
 968         };
 969         mbox_dsp2_legacy: mbox_dsp2_legacy {
 970                 status = "okay";
 971         };
 972 };
 973
 974 &mmu0_dsp1 {
 975         status = "okay";
 976 };
 977
 978 &mmu1_dsp1 {
 979         status = "okay";
 980 };
 981
 982 &mmu0_dsp2 {
 983         status = "okay";
 984 };
 985
 986 &mmu1_dsp2 {
 987         status = "okay";
 988 };
 989
 990 &mmu_ipu1 {
 991         status = "okay";
 992 };
 993
 994 &mmu_ipu2 {
 995         status = "okay";
 996 };
 997
 998 &ipu2 {
 999         status = "okay";
1000         memory-region = <&ipu2_cma_pool>;
1001         mboxes = <&mailbox6 &mbox_ipu2_legacy>;
1002         timers = <&timer3>;
1003         watchdog-timers = <&timer4>, <&timer9>;
1004 };
1005
1006 &ipu1 {
1007         status = "okay";
1008         memory-region = <&ipu1_cma_pool>;
1009         mboxes = <&mailbox5 &mbox_ipu1_legacy>;
1010         timers = <&timer11>;
1011         watchdog-timers = <&timer7>, <&timer8>;
1012 };
1013
1014 &dsp1 {
1015         status = "okay";
1016         memory-region = <&dsp1_cma_pool>;
1017         mboxes = <&mailbox5 &mbox_dsp1_legacy>;
1018         timers = <&timer5>;
1019         watchdog-timers = <&timer10>;
1020 };
1021
1022 &dsp2 {
1023         status = "okay";
1024         memory-region = <&dsp2_cma_pool>;
1025         mboxes = <&mailbox6 &mbox_dsp2_legacy>;
1026         timers = <&timer6>;
1027 };
1028
1029 &atl {
1030         status = "okay";
1031
1032         atl2 {
1033                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
1034                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
1035         };
1036 };
1037
1038 &mcasp3 {
1039         fck_parent = "atl_clkin2_ck";
1040
1041         status = "okay";
1042
1043         op-mode = <0>;          /* MCASP_IIS_MODE */
1044         tdm-slots = <2>;
1045         /* 4 serializer */
1046         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
1047                 1 2 0 0
1048         >;
1049         tx-num-evt = <8>;
1050         rx-num-evt = <8>;
1051 };
1052
1053 &mcasp7 {
1054         #sound-dai-cells = <0>;
1055
1056         status = "okay";
1057
1058         op-mode = <0>;  /* MCASP_IIS_MODE */
1059         tdm-slots = <4>;
1060         /* 4 serializer */
1061         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
1062                 2 1 0 0
1063         >;
1064         tx-num-evt = <8>;
1065         rx-num-evt = <8>;
1066 };
1067
1068 &mcasp8 {
1069         /* not used for audio. only the AXR2 pin is used as GPIO */
1070         status = "okay";
1071 };
1072
1073 &usb2_phy1 {
1074         phy-supply = <&ldousb_reg>;
1075 };
1076
1077 &usb2_phy2 {
1078         phy-supply = <&ldousb_reg>;
1079 };
1080
1081 &vip1 {
1082         status = "okay";
1083 };
1084
1085 &vin1a {
1086         endpoint@0 {
1087                 slave-mode;
1088                 remote-endpoint = <&onboardLI>;
1089         };
1090 };
1091
1092 #include "dra7xx-jamr3.dtsi"