1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clk/ti-dra7-atl.h>
15 / {
16 model = "TI DRA742";
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
19 memory {
20 device_type = "memory";
21 reg = <0x80000000 0x60000000>; /* 1536 MB */
22 };
24 reserved-memory {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
29 ipu2_cma_pool: ipu2_cma@95800000 {
30 compatible = "shared-dma-pool";
31 reg = <0x95800000 0x3800000>;
32 reusable;
33 status = "okay";
34 };
36 dsp1_cma_pool: dsp1_cma@99000000 {
37 compatible = "shared-dma-pool";
38 reg = <0x99000000 0x4000000>;
39 reusable;
40 status = "okay";
41 };
43 ipu1_cma_pool: ipu1_cma@9d000000 {
44 compatible = "shared-dma-pool";
45 reg = <0x9d000000 0x2000000>;
46 reusable;
47 status = "okay";
48 };
50 dsp2_cma_pool: dsp2_cma@9f000000 {
51 compatible = "shared-dma-pool";
52 reg = <0x9f000000 0x800000>;
53 reusable;
54 status = "okay";
55 };
56 };
58 extcon1: dra7x_usbid_extcon1 {
59 compatible = "linux,extcon-gpio";
60 gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_LOW>;
61 cable-name = "USB-HOST";
62 };
64 extcon2: dra7x_usbid_extcon2 {
65 compatible = "linux,extcon-gpio";
66 gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_LOW>;
67 cable-name = "USB-HOST";
68 };
70 evm_3v3_sd: fixedregulator-sd {
71 compatible = "regulator-fixed";
72 regulator-name = "evm_3v3_sd";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 enable-active-high;
76 gpio = <&pcf_gpio_21 5 0>;
77 };
79 evm_3v3_sw: fixedregulator-evm_3v3_sw {
80 compatible = "regulator-fixed";
81 regulator-name = "evm_3v3_sw";
82 vin-supply = <&sysen1>;
83 regulator-min-microvolt = <3300000>;
84 regulator-max-microvolt = <3300000>;
85 };
87 aic_dvdd: fixedregulator-aic_dvdd {
88 /* TPS77018DBVT */
89 compatible = "regulator-fixed";
90 regulator-name = "aic_dvdd";
91 vin-supply = <&evm_3v3_sw>;
92 regulator-min-microvolt = <1800000>;
93 regulator-max-microvolt = <1800000>;
94 };
96 vmmcwl_fixed: fixedregulator-mmcwl {
97 compatible = "regulator-fixed";
98 regulator-name = "vmmcwl_fixed";
99 regulator-min-microvolt = <1800000>;
100 regulator-max-microvolt = <1800000>;
101 gpio = <&gpio5 8 0>; /* gpio5_8 */
102 startup-delay-us = <70000>;
103 enable-active-high;
104 };
106 kim {
107 compatible = "kim";
108 nshutdown_gpio = <132>;
109 dev_name = "/dev/ttyS2";
110 flow_cntrl = <1>;
111 baud_rate = <3686400>;
112 };
114 btwilink {
115 compatible = "btwilink";
116 };
118 vtt_fixed: fixedregulator-vtt {
119 compatible = "regulator-fixed";
120 regulator-name = "vtt_fixed";
121 regulator-min-microvolt = <1350000>;
122 regulator-max-microvolt = <1350000>;
123 regulator-always-on;
124 regulator-boot-on;
125 enable-active-high;
126 vin-supply = <&sysen2>;
127 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
128 };
130 aliases {
131 display0 = &hdmi0;
132 sound0 = &primary_sound;
133 sound1 = &hdmi;
134 };
136 hdmi0: connector@1 {
137 compatible = "hdmi-connector";
138 label = "hdmi";
140 type = "a";
142 port {
143 hdmi_connector_in: endpoint {
144 remote-endpoint = <&tpd12s015_out>;
145 };
146 };
147 };
149 tpd12s015: encoder@1 {
150 compatible = "ti,dra7evm-tpd12s015";
152 gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
153 <&pcf_hdmi 5 0>, /* P5, LS OE */
154 <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
156 ports {
157 #address-cells = <1>;
158 #size-cells = <0>;
160 port@0 {
161 reg = <0>;
163 tpd12s015_in: endpoint@0 {
164 remote-endpoint = <&hdmi_out>;
165 };
166 };
168 port@1 {
169 reg = <1>;
171 tpd12s015_out: endpoint@0 {
172 remote-endpoint = <&hdmi_connector_in>;
173 };
174 };
175 };
176 };
178 primary_sound: primary_sound {
179 compatible = "ti,dra7xx-evm-audio";
180 ti,model = "DRA7xx-EVM";
181 ti,audio-codec = <&tlv320aic3106>;
182 ti,mcasp-controller = <&mcasp3>;
183 ti,codec-clock-rate = <5644800>;
184 clocks = <&atl_clkin2_ck>;
185 clock-names = "mclk";
186 ti,audio-routing =
187 "Headphone Jack", "HPLOUT",
188 "Headphone Jack", "HPROUT",
189 "Line Out", "LLOUT",
190 "Line Out", "RLOUT",
191 "MIC3L", "Mic Jack",
192 "MIC3R", "Mic Jack",
193 "Mic Jack", "Mic Bias",
194 "LINE1L", "Line In",
195 "LINE1R", "Line In";
196 };
197 };
199 &dra7_pmx_core {
200 wlan_pins: pinmux_wlan_pins {
201 pinctrl-single,pins = <
202 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
203 0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
204 0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
205 0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
206 0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
207 0x3fc (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
208 0x2cc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr6.gpio5_8 - WLAN_EN */
209 >;
210 };
212 wlirq_pins: pinmux_wlirq_pins {
213 pinctrl-single,pins = <
214 0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */
215 >;
216 };
218 dcan1_pins_default: dcan1_pins_default {
219 pinctrl-single,pins = <
220 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
221 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
222 >;
223 };
225 dcan1_pins_sleep: dcan1_pins_sleep {
226 pinctrl-single,pins = <
227 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
228 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
229 >;
230 };
232 mmc1_pins_default: pinmux_mmc1_default_pins {
233 pinctrl-single,pins = <
234 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
235 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
236 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
237 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
238 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
239 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
240 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio187 */
241 >;
242 };
244 mmc1_pins_hs: pinmux_mmc1_hs_pins {
245 pinctrl-single,pins = <
246 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
247 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
248 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
249 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
250 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
251 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
252 >;
253 };
255 mmc2_pins_default: mmc2_pins_default {
256 pinctrl-single,pins = <
257 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
258 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
259 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
260 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
261 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
262 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
263 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
264 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
265 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
266 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
267 >;
268 };
270 mmc2_pins_hs: pinmux_mmc2_hs_pins {
271 pinctrl-single,pins = <
272 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
273 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
274 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
275 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
276 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
277 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
278 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
279 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
280 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
281 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
282 >;
283 };
284 };
286 &i2c1 {
287 status = "okay";
288 clock-frequency = <400000>;
290 tps659038: tps659038@58 {
291 compatible = "ti,tps659038";
292 reg = <0x58>;
294 tps659038_pmic {
295 compatible = "ti,tps659038-pmic";
297 regulators {
298 smps123_reg: smps123 {
299 /* VDD_MPU */
300 regulator-name = "smps123";
301 regulator-min-microvolt = < 850000>;
302 regulator-max-microvolt = <1250000>;
303 regulator-always-on;
304 regulator-boot-on;
305 };
307 smps45_reg: smps45 {
308 /* VDD_DSPEVE */
309 regulator-name = "smps45";
310 regulator-min-microvolt = < 850000>;
311 regulator-max-microvolt = <1150000>;
312 regulator-boot-on;
313 regulator-always-on;
314 };
316 smps6_reg: smps6 {
317 /* VDD_GPU - over VDD_SMPS6 */
318 regulator-name = "smps6";
319 regulator-min-microvolt = <850000>;
320 regulator-max-microvolt = <1250000>;
321 regulator-boot-on;
322 regulator-always-on;
323 };
325 smps7_reg: smps7 {
326 /* CORE_VDD */
327 regulator-name = "smps7";
328 regulator-min-microvolt = <850000>;
329 regulator-max-microvolt = <1060000>;
330 regulator-always-on;
331 regulator-boot-on;
332 };
334 smps8_reg: smps8 {
335 /* VDD_IVAHD */
336 regulator-name = "smps8";
337 regulator-min-microvolt = < 850000>;
338 regulator-max-microvolt = <1250000>;
339 regulator-boot-on;
340 regulator-always-on;
341 };
343 smps9_reg: smps9 {
344 /* VDDS1V8 */
345 regulator-name = "smps9";
346 regulator-min-microvolt = <1800000>;
347 regulator-max-microvolt = <1800000>;
348 regulator-always-on;
349 regulator-boot-on;
350 };
352 ldo1_reg: ldo1 {
353 /* LDO1_OUT --> SDIO */
354 regulator-name = "ldo1";
355 regulator-min-microvolt = <1800000>;
356 regulator-max-microvolt = <3300000>;
357 regulator-boot-on;
358 regulator-always-on;
359 };
361 ldo2_reg: ldo2 {
362 /* VDD_RTCIO */
363 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
364 regulator-name = "ldo2";
365 regulator-min-microvolt = <3300000>;
366 regulator-max-microvolt = <3300000>;
367 regulator-boot-on;
368 regulator-always-on;
369 };
371 ldo3_reg: ldo3 {
372 /* VDDA_1V8_PHY */
373 regulator-name = "ldo3";
374 regulator-min-microvolt = <1800000>;
375 regulator-max-microvolt = <1800000>;
376 regulator-always-on;
377 regulator-boot-on;
378 };
380 ldo9_reg: ldo9 {
381 /* VDD_RTC */
382 regulator-name = "ldo9";
383 regulator-min-microvolt = <1050000>;
384 regulator-max-microvolt = <1050000>;
385 regulator-boot-on;
386 regulator-always-on;
387 };
389 ldoln_reg: ldoln {
390 /* VDDA_1V8_PLL */
391 regulator-name = "ldoln";
392 regulator-min-microvolt = <1800000>;
393 regulator-max-microvolt = <1800000>;
394 regulator-always-on;
395 regulator-boot-on;
396 };
398 ldousb_reg: ldousb {
399 /* VDDA_3V_USB: VDDA_USBHS33 */
400 regulator-name = "ldousb";
401 regulator-min-microvolt = <3300000>;
402 regulator-max-microvolt = <3300000>;
403 regulator-boot-on;
404 regulator-always-on;
405 };
407 /* REGEN1 is unused */
409 regen2: regen2 {
410 /* Needed for PMIC internal resources */
411 regulator-name = "regen2";
412 regulator-boot-on;
413 regulator-always-on;
414 };
416 /* REGEN3 is unused */
418 sysen1: sysen1 {
419 /* PMIC_REGEN_3V3 */
420 regulator-name = "sysen1";
421 regulator-boot-on;
422 regulator-always-on;
423 };
425 sysen2: sysen2 {
426 /* PMIC_REGEN_DDR */
427 regulator-name = "sysen2";
428 regulator-boot-on;
429 regulator-always-on;
430 };
431 };
432 };
433 };
435 pcf_lcd: gpio@20 {
436 compatible = "nxp,pcf8575";
437 reg = <0x20>;
438 gpio-controller;
439 #gpio-cells = <2>;
440 };
442 pcf_gpio_21: gpio@21 {
443 compatible = "ti,pcf8575";
444 reg = <0x21>;
445 lines-initial-states = <0x1408>;
446 gpio-controller;
447 #gpio-cells = <2>;
448 interrupt-parent = <&gpio6>;
449 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
452 };
454 mxt244: touchscreen@4a {
455 compatible = "atmel,mXT244";
456 status = "okay";
457 reg = <0x4a>;
458 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
460 atmel,config = <
461 /* MXT244_GEN_COMMAND(6) */
462 0x00 0x00 0x00 0x00 0x00 0x00
463 /* MXT244_GEN_POWER(7) */
464 0x20 0xff 0x32
465 /* MXT244_GEN_ACQUIRE(8) */
466 0x0a 0x00 0x05 0x00 0x00 0x00 0x09 0x23
467 /* MXT244_TOUCH_MULTI(9) */
468 0x00 0x00 0x00 0x13 0x0b 0x00 0x00 0x00 0x02 0x00
469 0x00 0x01 0x01 0x0e 0x0a 0x0a 0x0a 0x0a 0x00 0x00
470 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
471 0x00
472 /* MXT244_TOUCH_KEYARRAY(15) */
473 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
474 0x00
475 /* MXT244_COMMSCONFIG_T18(2) */
476 0x00 0x00
477 /* MXT244_SPT_GPIOPWM(19) */
478 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
479 0x00 0x00 0x00 0x00 0x00 0x00
480 /* MXT244_PROCI_GRIPFACE(20) */
481 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x28 0x04
482 0x0f 0x0a
483 /* MXT244_PROCG_NOISE(22) */
484 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x23 0x00
485 0x00 0x05 0x0f 0x19 0x23 0x2d 0x03
486 /* MXT244_TOUCH_PROXIMITY(23) */
487 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
488 0x00 0x00 0x00 0x00 0x00
489 /* MXT244_PROCI_ONETOUCH(24) */
490 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
491 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
492 /* MXT244_SPT_SELFTEST(25) */
493 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
494 0x00 0x00 0x00 0x00
495 /* MXT244_PROCI_TWOTOUCH(27) */
496 0x00 0x00 0x00 0x00 0x00 0x00 0x00
497 /* MXT244_SPT_CTECONFIG(28) */
498 0x00 0x00 0x02 0x08 0x10 0x00
499 >;
501 atmel,x_line = <18>;
502 atmel,y_line = <12>;
503 atmel,x_size = <800>;
504 atmel,y_size = <480>;
505 atmel,blen = <0x01>;
506 atmel,threshold = <30>;
507 atmel,voltage = <2800000>;
508 atmel,orient = <0x4>;
509 };
511 tlv320aic3106: tlv320aic3106@18 {
512 compatible = "ti,tlv320aic3106";
513 reg = <0x18>;
514 adc-settle-ms = <40>;
515 ai3x-micbias-vg = <1>; /* 2.0V */
516 status = "okay";
518 /* Regulators */
519 AVDD-supply = <&evm_3v3_sw>;
520 IOVDD-supply = <&evm_3v3_sw>;
521 DRVDD-supply = <&evm_3v3_sw>;
522 DVDD-supply = <&aic_dvdd>;
523 };
524 };
526 &i2c2 {
527 status = "okay";
528 clock-frequency = <400000>;
530 pcf_hdmi: gpio@26 {
531 compatible = "nxp,pcf8575";
532 reg = <0x26>;
533 lines-initial-states = <0xffeb>;
534 gpio-controller;
535 #gpio-cells = <2>;
536 };
537 };
539 &i2c3 {
540 status = "okay";
541 clock-frequency = <3400000>;
542 };
544 &mcspi1 {
545 status = "okay";
546 };
548 &mcspi2 {
549 status = "okay";
550 };
552 &uart1 {
553 status = "okay";
554 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
555 &dra7_pmx_core 0x3e0>;
556 };
558 &uart2 {
559 status = "okay";
560 };
562 &uart3 {
563 status = "okay";
564 gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
565 };
567 &mmc1 {
568 status = "okay";
569 pbias-supply = <&pbias_mmc_reg>;
570 vmmc-supply = <&evm_3v3_sd>;
571 vmmc_aux-supply = <&ldo1_reg>;
572 bus-width = <4>;
573 /*
574 * SDCD signal is not being used here - using the fact that GPIO mode
575 * is always hardwired.
576 */
577 cd-gpios = <&gpio6 27 0>;
578 pinctrl-names = "default", "hs";
579 pinctrl-0 = <&mmc1_pins_default>;
580 pinctrl-1 = <&mmc1_pins_hs>;
581 };
583 &mmc2 {
584 status = "okay";
585 vmmc-supply = <&evm_3v3_sw>;
586 bus-width = <8>;
587 pinctrl-names = "default", "hs";
588 pinctrl-0 = <&mmc2_pins_default>;
589 pinctrl-1 = <&mmc2_pins_hs>;
590 };
592 &mmc4 {
593 status = "okay";
594 vmmc-supply = <&vmmcwl_fixed>;
595 bus-width = <4>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&wlan_pins &wlirq_pins>;
598 cap-power-off-card;
599 keep-power-in-suspend;
600 ti,non-removable;
602 #address-cells = <1>;
603 #size-cells = <0>;
604 wlcore: wlcore@0 {
605 compatible = "ti,wlcore";
606 reg = <2>;
607 interrupt-parent = <&gpio5>;
608 interrupts = <7 IRQ_TYPE_NONE>;
609 };
610 };
612 &cpu0 {
613 cpu0-voltdm = <&voltdm_mpu>;
614 voltage-tolerance = <1>;
615 };
617 &voltdm_mpu {
618 vdd-supply = <&smps123_reg>;
619 };
621 &voltdm_dspeve {
622 vdd-supply = <&smps45_reg>;
623 };
625 &voltdm_gpu {
626 vdd-supply = <&smps6_reg>;
627 };
629 &voltdm_ivahd {
630 vdd-supply = <&smps8_reg>;
631 };
633 &voltdm_core {
634 vdd-supply = <&smps7_reg>;
635 };
637 &qspi {
638 status = "okay";
640 spi-max-frequency = <48000000>;
641 m25p80@0 {
642 compatible = "s25fl256s1";
643 spi-max-frequency = <48000000>;
644 reg = <0>;
645 spi-tx-bus-width = <1>;
646 spi-rx-bus-width = <4>;
647 spi-cpol;
648 spi-cpha;
649 #address-cells = <1>;
650 #size-cells = <1>;
652 /* MTD partition table.
653 * The ROM checks the first four physical blocks
654 * for a valid file to boot and the flash here is
655 * 64KiB block size.
656 */
657 partition@0 {
658 label = "QSPI.SPL";
659 reg = <0x00000000 0x000010000>;
660 };
661 partition@1 {
662 label = "QSPI.SPL.backup1";
663 reg = <0x00010000 0x00010000>;
664 };
665 partition@2 {
666 label = "QSPI.SPL.backup2";
667 reg = <0x00020000 0x00010000>;
668 };
669 partition@3 {
670 label = "QSPI.SPL.backup3";
671 reg = <0x00030000 0x00010000>;
672 };
673 partition@4 {
674 label = "QSPI.u-boot";
675 reg = <0x00040000 0x00100000>;
676 };
677 partition@5 {
678 label = "QSPI.u-boot-spl-os";
679 reg = <0x00140000 0x00080000>;
680 };
681 partition@6 {
682 label = "QSPI.u-boot-env";
683 reg = <0x001c0000 0x00010000>;
684 };
685 partition@7 {
686 label = "QSPI.u-boot-env.backup1";
687 reg = <0x001d0000 0x0010000>;
688 };
689 partition@8 {
690 label = "QSPI.kernel";
691 reg = <0x001e0000 0x0800000>;
692 };
693 partition@9 {
694 label = "QSPI.file-system";
695 reg = <0x009e0000 0x01620000>;
696 };
697 };
698 };
700 &omap_dwc3_1 {
701 extcon = <&extcon1>;
702 };
704 &omap_dwc3_2 {
705 extcon = <&extcon2>;
706 };
708 &usb1 {
709 dr_mode = "peripheral";
710 };
712 &usb2 {
713 dr_mode = "host";
714 };
716 &mac {
717 status = "okay";
718 dual_emac;
719 };
721 &cpsw_emac0 {
722 phy_id = <&davinci_mdio>, <2>;
723 phy-mode = "rgmii";
724 dual_emac_res_vlan = <1>;
725 };
727 &cpsw_emac1 {
728 phy_id = <&davinci_mdio>, <3>;
729 phy-mode = "rgmii";
730 dual_emac_res_vlan = <2>;
731 };
733 &elm {
734 status = "okay";
735 };
737 &gpmc {
738 status = "disabled";
739 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
740 nand@0,0 {
741 reg = <0 0 4>; /* device IO registers */
742 ti,nand-ecc-opt = "bch8";
743 ti,elm-id = <&elm>;
744 nand-bus-width = <16>;
745 gpmc,device-width = <2>;
746 gpmc,sync-clk-ps = <0>;
747 gpmc,cs-on-ns = <0>;
748 gpmc,cs-rd-off-ns = <80>;
749 gpmc,cs-wr-off-ns = <80>;
750 gpmc,adv-on-ns = <0>;
751 gpmc,adv-rd-off-ns = <60>;
752 gpmc,adv-wr-off-ns = <60>;
753 gpmc,we-on-ns = <10>;
754 gpmc,we-off-ns = <50>;
755 gpmc,oe-on-ns = <4>;
756 gpmc,oe-off-ns = <40>;
757 gpmc,access-ns = <40>;
758 gpmc,wr-access-ns = <80>;
759 gpmc,rd-cycle-ns = <80>;
760 gpmc,wr-cycle-ns = <80>;
761 gpmc,bus-turnaround-ns = <0>;
762 gpmc,cycle2cycle-delay-ns = <0>;
763 gpmc,clk-activation-ns = <0>;
764 gpmc,wait-monitoring-ns = <0>;
765 gpmc,wr-data-mux-bus-ns = <0>;
766 /* MTD partition table */
767 /* All SPL-* partitions are sized to minimal length
768 * which can be independently programmable. For
769 * NAND flash this is equal to size of erase-block */
770 #address-cells = <1>;
771 #size-cells = <1>;
772 partition@0 {
773 label = "NAND.SPL";
774 reg = <0x00000000 0x000020000>;
775 };
776 partition@1 {
777 label = "NAND.SPL.backup1";
778 reg = <0x00020000 0x00020000>;
779 };
780 partition@2 {
781 label = "NAND.SPL.backup2";
782 reg = <0x00040000 0x00020000>;
783 };
784 partition@3 {
785 label = "NAND.SPL.backup3";
786 reg = <0x00060000 0x00020000>;
787 };
788 partition@4 {
789 label = "NAND.u-boot-spl-os";
790 reg = <0x00080000 0x00040000>;
791 };
792 partition@5 {
793 label = "NAND.u-boot";
794 reg = <0x000c0000 0x00100000>;
795 };
796 partition@6 {
797 label = "NAND.u-boot-env";
798 reg = <0x001c0000 0x00020000>;
799 };
800 partition@7 {
801 label = "NAND.u-boot-env.backup1";
802 reg = <0x001e0000 0x00020000>;
803 };
804 partition@8 {
805 label = "NAND.kernel";
806 reg = <0x00200000 0x00800000>;
807 };
808 partition@9 {
809 label = "NAND.file-system";
810 reg = <0x00a00000 0x0f600000>;
811 };
812 };
813 };
815 &gpio7 {
816 ti,no-reset-on-init;
817 ti,no-idle-on-init;
818 };
820 &dss {
821 status = "ok";
823 vdda_video-supply = <&ldoln_reg>;
824 };
826 &hdmi {
827 status = "ok";
828 vdda-supply = <&ldo3_reg>;
830 port {
831 hdmi_out: endpoint {
832 remote-endpoint = <&tpd12s015_in>;
833 };
834 };
835 };
837 &dcan1 {
838 status = "ok";
839 pinctrl-names = "default", "sleep";
840 pinctrl-0 = <&dcan1_pins_default>;
841 pinctrl-1 = <&dcan1_pins_sleep>;
842 };
844 &mailbox5 {
845 status = "okay";
846 mbox_ipu1_legacy: mbox_ipu1_legacy {
847 status = "okay";
848 };
849 mbox_dsp1_legacy: mbox_dsp1_legacy {
850 status = "okay";
851 };
852 };
854 &mailbox6 {
855 status = "okay";
856 mbox_ipu2_legacy: mbox_ipu2_legacy {
857 status = "okay";
858 };
859 mbox_dsp2_legacy: mbox_dsp2_legacy {
860 status = "okay";
861 };
862 };
864 &mmu0_dsp1 {
865 status = "okay";
866 };
868 &mmu1_dsp1 {
869 status = "okay";
870 };
872 &mmu0_dsp2 {
873 status = "okay";
874 };
876 &mmu1_dsp2 {
877 status = "okay";
878 };
880 &mmu_ipu1 {
881 status = "okay";
882 };
884 &mmu_ipu2 {
885 status = "okay";
886 };
888 &ipu2 {
889 status = "okay";
890 memory-region = <&ipu2_cma_pool>;
891 mboxes = <&mailbox6 &mbox_ipu2_legacy>;
892 timers = <&timer3>;
893 watchdog-timers = <&timer4>, <&timer9>;
894 };
896 &ipu1 {
897 status = "okay";
898 memory-region = <&ipu1_cma_pool>;
899 mboxes = <&mailbox5 &mbox_ipu1_legacy>;
900 timers = <&timer11>;
901 };
903 &dsp1 {
904 status = "okay";
905 memory-region = <&dsp1_cma_pool>;
906 mboxes = <&mailbox5 &mbox_dsp1_legacy>;
907 timers = <&timer5>;
908 };
910 &dsp2 {
911 status = "okay";
912 memory-region = <&dsp2_cma_pool>;
913 mboxes = <&mailbox6 &mbox_dsp2_legacy>;
914 timers = <&timer6>;
915 };
917 &atl {
918 status = "okay";
920 atl2 {
921 bws = <DRA7_ATL_WS_MCASP2_FSX>;
922 aws = <DRA7_ATL_WS_MCASP3_FSX>;
923 };
924 };
926 &mcasp3 {
927 fck_parent = "atl_clkin2_ck";
929 status = "okay";
931 op-mode = <0>; /* MCASP_IIS_MODE */
932 tdm-slots = <2>;
933 /* 4 serializer */
934 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
935 1 2 0 0
936 >;
937 };
939 &usb2_phy1 {
940 phy-supply = <&ldousb_reg>;
941 };
943 &usb2_phy2 {
944 phy-supply = <&ldousb_reg>;
945 };