1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clk/ti-dra7-atl.h>
15 / {
16 model = "TI DRA742";
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
19 memory {
20 device_type = "memory";
21 reg = <0x80000000 0x60000000>; /* 1536 MB */
22 };
24 reserved-memory {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
29 ipu2_cma_pool: ipu2_cma@95800000 {
30 compatible = "shared-dma-pool";
31 reg = <0x95800000 0x3800000>;
32 reusable;
33 status = "okay";
34 };
36 dsp1_cma_pool: dsp1_cma@99000000 {
37 compatible = "shared-dma-pool";
38 reg = <0x99000000 0x4000000>;
39 reusable;
40 status = "okay";
41 };
43 ipu1_cma_pool: ipu1_cma@9d000000 {
44 compatible = "shared-dma-pool";
45 reg = <0x9d000000 0x2000000>;
46 reusable;
47 status = "okay";
48 };
50 dsp2_cma_pool: dsp2_cma@9f000000 {
51 compatible = "shared-dma-pool";
52 reg = <0x9f000000 0x800000>;
53 reusable;
54 status = "okay";
55 };
56 };
58 extcon1: dra7x_usbid_extcon1 {
59 compatible = "linux,extcon-gpio";
60 gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_LOW>;
61 cable-name = "USB-HOST";
62 };
64 extcon2: dra7x_usbid_extcon2 {
65 compatible = "linux,extcon-gpio";
66 gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_LOW>;
67 cable-name = "USB-HOST";
68 };
70 evm_3v3_sd: fixedregulator-sd {
71 compatible = "regulator-fixed";
72 regulator-name = "evm_3v3_sd";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 enable-active-high;
76 gpio = <&pcf_gpio_21 5 0>;
77 };
79 evm_3v3_sw: fixedregulator-evm_3v3_sw {
80 compatible = "regulator-fixed";
81 regulator-name = "evm_3v3_sw";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
84 };
86 aic_dvdd: fixedregulator-aic_dvdd {
87 /* TPS77018DBVT */
88 compatible = "regulator-fixed";
89 regulator-name = "aic_dvdd";
90 vin-supply = <&evm_3v3_sw>;
91 regulator-min-microvolt = <1800000>;
92 regulator-max-microvolt = <1800000>;
93 };
95 vmmcwl_fixed: fixedregulator-mmcwl {
96 compatible = "regulator-fixed";
97 regulator-name = "vmmcwl_fixed";
98 regulator-min-microvolt = <1800000>;
99 regulator-max-microvolt = <1800000>;
100 gpio = <&gpio5 8 0>; /* gpio5_8 */
101 startup-delay-us = <70000>;
102 enable-active-high;
103 };
105 kim {
106 compatible = "kim";
107 nshutdown_gpio = <132>;
108 dev_name = "/dev/ttyO2";
109 flow_cntrl = <1>;
110 baud_rate = <3686400>;
111 };
113 btwilink {
114 compatible = "btwilink";
115 };
117 vtt_fixed: fixedregulator-vtt {
118 compatible = "regulator-fixed";
119 regulator-name = "vtt_fixed";
120 regulator-min-microvolt = <1350000>;
121 regulator-max-microvolt = <1350000>;
122 regulator-always-on;
123 regulator-boot-on;
124 enable-active-high;
125 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
126 };
128 aliases {
129 display0 = &hdmi0;
130 sound0 = &primary_sound;
131 sound1 = &hdmi;
132 };
134 hdmi0: connector@1 {
135 compatible = "omapdss,hdmi-connector";
136 label = "hdmi";
138 type = "a";
140 port {
141 hdmi_connector_in: endpoint {
142 remote-endpoint = <&tpd12s015_out>;
143 };
144 };
145 };
147 tpd12s015: encoder@1 {
148 compatible = "ti,dra7evm-tpd12s015";
150 pinctrl-names = "default";
151 pinctrl-0 = <&hpd_pin>;
153 gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
154 <&pcf_hdmi 5 0>, /* P5, LS OE */
155 <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
157 ports {
158 #address-cells = <1>;
159 #size-cells = <0>;
161 port@0 {
162 reg = <0>;
164 tpd12s015_in: endpoint@0 {
165 remote-endpoint = <&hdmi_out>;
166 };
167 };
169 port@1 {
170 reg = <1>;
172 tpd12s015_out: endpoint@0 {
173 remote-endpoint = <&hdmi_connector_in>;
174 };
175 };
176 };
177 };
179 ocp {
180 gpu: gpu@0x56000000 {
181 gpu0-voltdm = <&voltdm_gpu>;
182 };
183 };
185 primary_sound: primary_sound {
186 compatible = "ti,dra7xx-evm-audio";
187 ti,model = "DRA7xx-EVM";
188 ti,always-on;
189 ti,audio-codec = <&tlv320aic3106>;
190 ti,mcasp-controller = <&mcasp3>;
191 ti,codec-clock-rate = <11289600>;
192 clocks = <&atl_clkin2_ck>;
193 clock-names = "mclk";
194 ti,audio-routing =
195 "Headphone Jack", "HPLOUT",
196 "Headphone Jack", "HPROUT",
197 "Line Out", "LLOUT",
198 "Line Out", "RLOUT",
199 "MIC3L", "Mic Jack",
200 "MIC3R", "Mic Jack",
201 "Mic Jack", "Mic Bias",
202 "LINE1L", "Line In",
203 "LINE1R", "Line In";
204 };
206 radio {
207 compatible = "ti,dra7xx_radio";
208 gpios = <&gpio6 20 0>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&radio_pins>;
212 };
213 };
215 &dra7_pmx_core {
216 pinctrl-names = "default";
217 pinctrl-0 = <&vtt_pin>;
219 vtt_pin: pinmux_vtt_pin {
220 pinctrl-single,pins = <
221 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* gpio7_11 */
222 >;
223 };
225 i2c1_pins: pinmux_i2c1_pins {
226 pinctrl-single,pins = <
227 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
228 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
229 >;
230 };
232 i2c2_pins: pinmux_i2c2_pins {
233 pinctrl-single,pins = <
234 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
235 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
236 >;
237 };
239 i2c3_pins: pinmux_i2c3_pins {
240 pinctrl-single,pins = <
241 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
242 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
243 >;
244 };
246 mcspi1_pins: pinmux_mcspi1_pins {
247 pinctrl-single,pins = <
248 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
249 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
250 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
251 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
252 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs1 */
253 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
254 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
255 >;
256 };
258 uart1_pins: pinmux_uart1_pins {
259 pinctrl-single,pins = <
260 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
261 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
262 >;
263 };
265 bt_uart3_pins: pinmux_uart3_pins {
266 pinctrl-single,pins = <
267 0x3c0 (PIN_INPUT_PULLUP | MUX_MODE1) /* spi2_sclk.uart3_rxd */
268 0x3c4 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* spi2_d1.uart3_txd */
269 0x3c8 (PIN_INPUT | MUX_MODE1) /* spi2.d0.uart3_ctsn */
270 0x3cc (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* spi2_cs0.uart3_rtsn */
271 0x2bc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr2.gpio5_4 - BT_EN */
272 >;
273 };
275 qspi1_pins: pinmux_qspi1_pins {
276 pinctrl-single,pins = <
277 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
278 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
279 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
280 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
281 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
282 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
283 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
284 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
285 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
286 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
287 >;
288 };
290 usb1_pins: pinmux_usb1_pins {
291 pinctrl-single,pins = <
292 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
293 >;
294 };
296 usb2_pins: pinmux_usb2_pins {
297 pinctrl-single,pins = <
298 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
299 >;
300 };
302 wlan_pins: pinmux_wlan_pins {
303 pinctrl-single,pins = <
304 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
305 0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
306 0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
307 0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
308 0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
309 0x3fc (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
310 0x2cc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr6.gpio5_8 - WLAN_EN */
311 >;
312 };
314 wlirq_pins: pinmux_wlirq_pins {
315 pinctrl-single,pins = <
316 0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */
317 >;
318 };
320 cpsw_default: cpsw_default {
321 pinctrl-single,pins = <
322 /* Slave 1 */
323 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
324 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
325 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
326 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
327 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
328 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
329 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
330 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
331 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
332 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
333 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
334 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
336 /* Slave 2 */
337 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
338 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
339 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
340 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
341 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
342 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
343 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
344 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
345 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
346 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
347 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
348 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
349 >;
351 };
353 cpsw_sleep: cpsw_sleep {
354 pinctrl-single,pins = <
355 /* Slave 1 */
356 0x250 (PIN_OFF_NONE)
357 0x254 (PIN_OFF_NONE)
358 0x258 (PIN_OFF_NONE)
359 0x25c (PIN_OFF_NONE)
360 0x260 (PIN_OFF_NONE)
361 0x264 (PIN_OFF_NONE)
362 0x268 (PIN_OFF_NONE)
363 0x26c (PIN_OFF_NONE)
364 0x270 (PIN_OFF_NONE)
365 0x274 (PIN_OFF_NONE)
366 0x278 (PIN_OFF_NONE)
367 0x27c (PIN_OFF_NONE)
369 /* Slave 1 */
370 0x198 (PIN_OFF_NONE)
371 0x19c (PIN_OFF_NONE)
372 0x1a0 (PIN_OFF_NONE)
373 0x1a4 (PIN_OFF_NONE)
374 0x1a8 (PIN_OFF_NONE)
375 0x1ac (PIN_OFF_NONE)
376 0x1b0 (PIN_OFF_NONE)
377 0x1b4 (PIN_OFF_NONE)
378 0x1b8 (PIN_OFF_NONE)
379 0x1bc (PIN_OFF_NONE)
380 0x1c0 (PIN_OFF_NONE)
381 0x1c4 (PIN_OFF_NONE)
382 >;
383 };
385 davinci_mdio_default: davinci_mdio_default {
386 pinctrl-single,pins = <
387 /* MDIO */
388 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */
389 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk */
390 >;
391 };
393 davinci_mdio_sleep: davinci_mdio_sleep {
394 pinctrl-single,pins = <
395 0x23c (PIN_OFF_NONE)
396 0x240 (PIN_OFF_NONE)
397 >;
398 };
400 nand_flash_x16: nand_flash_x16 {
401 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
402 * So NAND flash requires following switch settings:
403 * SW5.9 (GPMC_WPN) = LOW
404 * SW5.1 (NAND_BOOTn) = HIGH */
405 pinctrl-single,pins = <
406 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
407 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
408 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
409 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
410 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
411 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
412 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
413 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
414 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
415 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
416 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
417 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
418 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
419 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
420 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
421 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
422 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
423 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
424 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
425 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
426 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
427 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
428 >;
429 };
431 vout1_pins: pinmux_vout1_pins {
432 pinctrl-single,pins = <
433 0x1C8 (PIN_OUTPUT | MUX_MODE0) /* vout1_clk */
434 0x1CC (PIN_OUTPUT | MUX_MODE0) /* vout1_de */
435 0x1D0 (PIN_OUTPUT | MUX_MODE0) /* vout1_fld */
436 0x1D4 (PIN_OUTPUT | MUX_MODE0) /* vout1_hsync */
437 0x1D8 (PIN_OUTPUT | MUX_MODE0) /* vout1_vsync */
438 0x1DC (PIN_OUTPUT | MUX_MODE0) /* vout1_d0 */
439 0x1E0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d1 */
440 0x1E4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d2 */
441 0x1E8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d3 */
442 0x1EC (PIN_OUTPUT | MUX_MODE0) /* vout1_d4 */
443 0x1F0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d5 */
444 0x1F4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d6 */
445 0x1F8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d7 */
446 0x1FC (PIN_OUTPUT | MUX_MODE0) /* vout1_d8 */
447 0x200 (PIN_OUTPUT | MUX_MODE0) /* vout1_d9 */
448 0x204 (PIN_OUTPUT | MUX_MODE0) /* vout1_d10 */
449 0x208 (PIN_OUTPUT | MUX_MODE0) /* vout1_d11 */
450 0x20C (PIN_OUTPUT | MUX_MODE0) /* vout1_d12 */
451 0x210 (PIN_OUTPUT | MUX_MODE0) /* vout1_d13 */
452 0x214 (PIN_OUTPUT | MUX_MODE0) /* vout1_d14 */
453 0x218 (PIN_OUTPUT | MUX_MODE0) /* vout1_d15 */
454 0x21C (PIN_OUTPUT | MUX_MODE0) /* vout1_d16 */
455 0x220 (PIN_OUTPUT | MUX_MODE0) /* vout1_d17 */
456 0x224 (PIN_OUTPUT | MUX_MODE0) /* vout1_d18 */
457 0x228 (PIN_OUTPUT | MUX_MODE0) /* vout1_d19 */
458 0x22C (PIN_OUTPUT | MUX_MODE0) /* vout1_d20 */
459 0x230 (PIN_OUTPUT | MUX_MODE0) /* vout1_d21 */
460 0x234 (PIN_OUTPUT | MUX_MODE0) /* vout1_d22 */
461 0x238 (PIN_OUTPUT | MUX_MODE0) /* vout1_d23 */
462 >;
463 };
465 hpd_pin: pinmux_hpd_pin {
466 pinctrl-single,pins = <
467 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 */
468 >;
469 };
471 tsc_pins: pinmux_tsc_pins {
472 pinctrl-single,pins = <
473 0x420 (PIN_INPUT_PULLUP | MUX_MODE1) /* sys_nirq2 */
474 >;
475 };
477 dcan1_pins_default: dcan1_pins_default {
478 pinctrl-single,pins = <
479 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
480 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
481 >;
482 };
484 dcan1_pins_sleep: dcan1_pins_sleep {
485 pinctrl-single,pins = <
486 0x3d0 (MUX_MODE15) /* dcan1_tx.off */
487 0x418 (MUX_MODE15) /* wakeup0.off */
488 >;
489 };
491 atl_pins: pinmux_atl_pins {
492 pinctrl-single,pins = <
493 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
494 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
495 >;
496 };
498 mcasp2_pins: pinmux_mcasp2_pins {
499 pinctrl-single,pins = <
500 0x02F4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_aclkx */
501 0x02F8 (PIN_INPUT_SLEW | MUX_MODE0) /* mcasp2_afsx */
502 0x0304 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr0 */
503 0x0308 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr1 */
504 0x030C (PIN_INPUT_SLEW | MUX_MODE0) /* mcasp2_axr2 */
505 0x0310 (PIN_INPUT_SLEW | MUX_MODE0) /* mcasp2_axr3 */
506 0x0314 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr4 */
507 0x0318 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr5 */
508 0x031c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr6 */
509 0x0320 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr7 */
510 >;
511 };
513 mcasp3_pins: pinmux_mcasp3_pins {
514 pinctrl-single,pins = <
515 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
516 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
517 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
518 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
519 >;
520 };
522 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
523 pinctrl-single,pins = <
524 0x324 (PIN_OFF_NONE)
525 0x328 (PIN_OFF_NONE)
526 0x32c (PIN_OFF_NONE)
527 0x330 (PIN_OFF_NONE)
528 >;
529 };
531 mcasp6_pins: pinmux_mcasp6_pins {
532 pinctrl-single,pins = <
533 0x2d4 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mcasp6_axr0 */
534 0x2d8 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp6_axr1 */
535 0x2dc (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mcasp6_clkx */
536 0x2e0 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp6_fsx */
537 >;
538 };
540 radio_pins: pinmux_radio_pins {
541 pinctrl-single,pins = <
542 0x0334 (PIN_INPUT | MUX_MODE4) /* i2c4_sda */
543 0x0338 (PIN_INPUT | MUX_MODE4) /* i2c4_scl */
544 0x02A0 (PIN_INPUT | MUX_MODE14) /* gpio6_20 */
545 >;
546 };
547 };
549 &i2c1 {
550 status = "okay";
551 pinctrl-names = "default";
552 pinctrl-0 = <&i2c1_pins>;
553 clock-frequency = <400000>;
555 tps659038: tps659038@58 {
556 compatible = "ti,tps659038";
557 reg = <0x58>;
559 tps659038_pmic {
560 compatible = "ti,tps659038-pmic";
562 regulators {
563 smps123_reg: smps123 {
564 /* VDD_MPU */
565 regulator-name = "smps123";
566 regulator-min-microvolt = < 850000>;
567 regulator-max-microvolt = <1250000>;
568 regulator-always-on;
569 regulator-boot-on;
570 };
572 smps45_reg: smps45 {
573 /* VDD_DSPEVE */
574 regulator-name = "smps45";
575 regulator-min-microvolt = < 850000>;
576 regulator-max-microvolt = <1150000>;
577 regulator-boot-on;
578 };
580 smps6_reg: smps6 {
581 /* VDD_GPU - over VDD_SMPS6 */
582 regulator-name = "smps6";
583 regulator-min-microvolt = <850000>;
584 regulator-max-microvolt = <1250000>;
585 regulator-boot-on;
586 };
588 smps7_reg: smps7 {
589 /* CORE_VDD */
590 regulator-name = "smps7";
591 regulator-min-microvolt = <850000>;
592 regulator-max-microvolt = <1060000>;
593 regulator-always-on;
594 regulator-boot-on;
595 };
597 smps8_reg: smps8 {
598 /* VDD_IVAHD */
599 regulator-name = "smps8";
600 regulator-min-microvolt = < 850000>;
601 regulator-max-microvolt = <1250000>;
602 regulator-boot-on;
603 };
605 smps9_reg: smps9 {
606 /* VDDS1V8 */
607 regulator-name = "smps9";
608 regulator-min-microvolt = <1800000>;
609 regulator-max-microvolt = <1800000>;
610 regulator-always-on;
611 regulator-boot-on;
612 };
614 ldo1_reg: ldo1 {
615 /* LDO1_OUT --> SDIO */
616 regulator-name = "ldo1";
617 regulator-min-microvolt = <1800000>;
618 regulator-max-microvolt = <3300000>;
619 regulator-boot-on;
620 };
622 ldo2_reg: ldo2 {
623 /* VDD_RTCIO */
624 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
625 regulator-name = "ldo2";
626 regulator-min-microvolt = <3300000>;
627 regulator-max-microvolt = <3300000>;
628 regulator-boot-on;
629 };
631 ldo3_reg: ldo3 {
632 /* VDDA_1V8_PHY */
633 regulator-name = "ldo3";
634 regulator-min-microvolt = <1800000>;
635 regulator-max-microvolt = <1800000>;
636 regulator-always-on;
637 regulator-boot-on;
638 };
640 ldo9_reg: ldo9 {
641 /* VDD_RTC */
642 regulator-name = "ldo9";
643 regulator-min-microvolt = <1050000>;
644 regulator-max-microvolt = <1050000>;
645 regulator-boot-on;
646 regulator-always-on;
647 };
649 ldoln_reg: ldoln {
650 /* VDDA_1V8_PLL */
651 regulator-name = "ldoln";
652 regulator-min-microvolt = <1800000>;
653 regulator-max-microvolt = <1800000>;
654 regulator-always-on;
655 regulator-boot-on;
656 };
658 ldousb_reg: ldousb {
659 /* VDDA_3V_USB: VDDA_USBHS33 */
660 regulator-name = "ldousb";
661 regulator-min-microvolt = <3300000>;
662 regulator-max-microvolt = <3300000>;
663 regulator-boot-on;
664 };
665 };
666 };
667 };
669 pcf_lcd: gpio@20 {
670 compatible = "nxp,pcf8575";
671 reg = <0x20>;
672 gpio-controller;
673 #gpio-cells = <2>;
674 };
676 pcf_gpio_21: gpio@21 {
677 compatible = "ti,pcf8575";
678 reg = <0x21>;
679 lines-initial-states = <0x1408>;
680 gpio-controller;
681 #gpio-cells = <2>;
682 interrupt-parent = <&gpio6>;
683 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
684 interrupt-controller;
685 #interrupt-cells = <2>;
686 };
688 tlv320aic3106: tlv320aic3106@18 {
689 compatible = "ti,tlv320aic3106";
690 reg = <0x18>;
691 adc-settle-ms = <40>;
692 ai3x-micbias-vg = <1>; /* 2.0V */
693 status = "okay";
695 /* Regulators */
696 AVDD-supply = <&evm_3v3_sw>;
697 IOVDD-supply = <&evm_3v3_sw>;
698 DRVDD-supply = <&evm_3v3_sw>;
699 DVDD-supply = <&aic_dvdd>;
700 };
701 };
703 &i2c2 {
704 status = "okay";
705 pinctrl-names = "default";
706 pinctrl-0 = <&i2c2_pins>;
707 clock-frequency = <400000>;
709 pcf_hdmi: gpio@26 {
710 compatible = "nxp,pcf8575";
711 reg = <0x26>;
712 lines-initial-states = <0xffeb>;
713 gpio-controller;
714 #gpio-cells = <2>;
715 };
716 };
718 &i2c3 {
719 status = "okay";
720 pinctrl-names = "default";
721 pinctrl-0 = <&i2c3_pins>;
722 clock-frequency = <400000>;
723 };
725 &uart1 {
726 status = "okay";
727 pinctrl-names = "default";
728 pinctrl-0 = <&uart1_pins>;
730 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
731 &dra7_pmx_core 0x3e0>;
732 };
734 &uart3 {
735 status = "okay";
736 pinctrl-names = "default";
737 pinctrl-0 = <&bt_uart3_pins>;
738 gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
739 };
741 &mmc1 {
742 status = "okay";
743 pbias-supply = <&pbias_mmc_reg>;
744 vmmc-supply = <&evm_3v3_sd>;
745 vmmc_aux-supply = <&ldo1_reg>;
746 bus-width = <4>;
747 /*
748 * SDCD signal is not being used here - using the fact that GPIO mode
749 * is always hardwired.
750 */
751 cd-gpios = <&gpio6 27 0>;
752 };
754 &mmc2 {
755 status = "okay";
756 vmmc-supply = <&evm_3v3_sw>;
757 bus-width = <8>;
758 };
760 &mmc4 {
761 status = "okay";
762 vmmc-supply = <&vmmcwl_fixed>;
763 bus-width = <4>;
764 pinctrl-names = "default";
765 pinctrl-0 = <&wlan_pins &wlirq_pins>;
766 cap-power-off-card;
767 keep-power-in-suspend;
768 ti,non-removable;
770 #address-cells = <1>;
771 #size-cells = <0>;
772 wlcore: wlcore@0 {
773 compatible = "ti,wlcore";
774 reg = <2>;
775 interrupt-parent = <&gpio5>;
776 interrupts = <7 IRQ_TYPE_NONE>;
777 };
778 };
780 &cpu0 {
781 cpu0-voltdm = <&voltdm_mpu>;
782 voltage-tolerance = <1>;
783 };
785 &voltdm_mpu {
786 vdd-supply = <&smps123_reg>;
787 };
789 &voltdm_dspeve {
790 vdd-supply = <&smps45_reg>;
791 };
793 &voltdm_gpu {
794 vdd-supply = <&smps6_reg>;
795 };
797 &voltdm_ivahd {
798 vdd-supply = <&smps8_reg>;
799 };
801 &voltdm_core {
802 vdd-supply = <&smps7_reg>;
803 };
805 &qspi {
806 status = "okay";
807 pinctrl-names = "default";
808 pinctrl-0 = <&qspi1_pins>;
810 spi-max-frequency = <48000000>;
811 m25p80@0 {
812 compatible = "s25fl256s1";
813 spi-max-frequency = <48000000>;
814 reg = <0>;
815 spi-tx-bus-width = <1>;
816 spi-rx-bus-width = <4>;
817 spi-cpol;
818 spi-cpha;
819 #address-cells = <1>;
820 #size-cells = <1>;
822 /* MTD partition table.
823 * The ROM checks the first four physical blocks
824 * for a valid file to boot and the flash here is
825 * 64KiB block size.
826 */
827 partition@0 {
828 label = "QSPI.SPL";
829 reg = <0x00000000 0x000010000>;
830 };
831 partition@1 {
832 label = "QSPI.SPL.backup1";
833 reg = <0x00010000 0x00010000>;
834 };
835 partition@2 {
836 label = "QSPI.SPL.backup2";
837 reg = <0x00020000 0x00010000>;
838 };
839 partition@3 {
840 label = "QSPI.SPL.backup3";
841 reg = <0x00030000 0x00010000>;
842 };
843 partition@4 {
844 label = "QSPI.u-boot";
845 reg = <0x00040000 0x00100000>;
846 };
847 partition@5 {
848 label = "QSPI.u-boot-spl-os";
849 reg = <0x00140000 0x00080000>;
850 };
851 partition@6 {
852 label = "QSPI.u-boot-env";
853 reg = <0x001c0000 0x00010000>;
854 };
855 partition@7 {
856 label = "QSPI.u-boot-env.backup1";
857 reg = <0x001d0000 0x0010000>;
858 };
859 partition@8 {
860 label = "QSPI.kernel";
861 reg = <0x001e0000 0x0800000>;
862 };
863 partition@9 {
864 label = "QSPI.file-system";
865 reg = <0x009e0000 0x01620000>;
866 };
867 };
868 };
870 &omap_dwc3_1 {
871 extcon = <&extcon1>;
872 };
874 &omap_dwc3_2 {
875 extcon = <&extcon2>;
876 };
878 &usb1 {
879 dr_mode = "otg";
880 pinctrl-names = "default";
881 pinctrl-0 = <&usb1_pins>;
882 };
884 &usb2 {
885 dr_mode = "host";
886 pinctrl-names = "default";
887 pinctrl-0 = <&usb2_pins>;
888 };
890 &mac {
891 status = "okay";
892 pinctrl-names = "default", "sleep";
893 pinctrl-0 = <&cpsw_default>;
894 pinctrl-1 = <&cpsw_sleep>;
895 dual_emac;
896 };
898 &cpsw_emac0 {
899 phy_id = <&davinci_mdio>, <2>;
900 phy-mode = "rgmii";
901 dual_emac_res_vlan = <1>;
902 };
904 &cpsw_emac1 {
905 phy_id = <&davinci_mdio>, <3>;
906 phy-mode = "rgmii";
907 dual_emac_res_vlan = <2>;
908 };
910 &davinci_mdio {
911 pinctrl-names = "default", "sleep";
912 pinctrl-0 = <&davinci_mdio_default>;
913 pinctrl-1 = <&davinci_mdio_sleep>;
914 };
916 &elm {
917 status = "okay";
918 };
920 &gpmc {
921 status = "okay";
922 pinctrl-names = "default";
923 pinctrl-0 = <&nand_flash_x16>;
924 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
925 nand@0,0 {
926 reg = <0 0 4>; /* device IO registers */
927 ti,nand-ecc-opt = "bch8";
928 ti,elm-id = <&elm>;
929 nand-bus-width = <16>;
930 gpmc,device-width = <2>;
931 gpmc,sync-clk-ps = <0>;
932 gpmc,cs-on-ns = <0>;
933 gpmc,cs-rd-off-ns = <80>;
934 gpmc,cs-wr-off-ns = <80>;
935 gpmc,adv-on-ns = <0>;
936 gpmc,adv-rd-off-ns = <60>;
937 gpmc,adv-wr-off-ns = <60>;
938 gpmc,we-on-ns = <10>;
939 gpmc,we-off-ns = <50>;
940 gpmc,oe-on-ns = <4>;
941 gpmc,oe-off-ns = <40>;
942 gpmc,access-ns = <40>;
943 gpmc,wr-access-ns = <80>;
944 gpmc,rd-cycle-ns = <80>;
945 gpmc,wr-cycle-ns = <80>;
946 gpmc,bus-turnaround-ns = <0>;
947 gpmc,cycle2cycle-delay-ns = <0>;
948 gpmc,clk-activation-ns = <0>;
949 gpmc,wait-monitoring-ns = <0>;
950 gpmc,wr-data-mux-bus-ns = <0>;
951 /* MTD partition table */
952 /* All SPL-* partitions are sized to minimal length
953 * which can be independently programmable. For
954 * NAND flash this is equal to size of erase-block */
955 #address-cells = <1>;
956 #size-cells = <1>;
957 partition@0 {
958 label = "NAND.SPL";
959 reg = <0x00000000 0x000020000>;
960 };
961 partition@1 {
962 label = "NAND.SPL.backup1";
963 reg = <0x00020000 0x00020000>;
964 };
965 partition@2 {
966 label = "NAND.SPL.backup2";
967 reg = <0x00040000 0x00020000>;
968 };
969 partition@3 {
970 label = "NAND.SPL.backup3";
971 reg = <0x00060000 0x00020000>;
972 };
973 partition@4 {
974 label = "NAND.u-boot-spl-os";
975 reg = <0x00080000 0x00040000>;
976 };
977 partition@5 {
978 label = "NAND.u-boot";
979 reg = <0x000c0000 0x00100000>;
980 };
981 partition@6 {
982 label = "NAND.u-boot-env";
983 reg = <0x001c0000 0x00020000>;
984 };
985 partition@7 {
986 label = "NAND.u-boot-env.backup1";
987 reg = <0x001e0000 0x00020000>;
988 };
989 partition@8 {
990 label = "NAND.kernel";
991 reg = <0x00200000 0x00800000>;
992 };
993 partition@9 {
994 label = "NAND.file-system";
995 reg = <0x00a00000 0x0f600000>;
996 };
997 };
998 };
1000 &gpio7 {
1001 ti,no-reset-on-init;
1002 ti,no-idle-on-init;
1003 };
1005 &dss {
1006 status = "ok";
1008 vdda_video-supply = <&ldoln_reg>;
1009 };
1011 &hdmi {
1012 status = "ok";
1013 vdda-supply = <&ldo3_reg>;
1015 port {
1016 hdmi_out: endpoint {
1017 remote-endpoint = <&tpd12s015_in>;
1018 };
1019 };
1020 };
1022 &dcan1 {
1023 status = "ok";
1024 pinctrl-names = "default", "sleep";
1025 pinctrl-0 = <&dcan1_pins_default>;
1026 pinctrl-1 = <&dcan1_pins_sleep>;
1027 };
1029 &mailbox5 {
1030 status = "okay";
1031 mbox_ipu1_legacy: mbox_ipu1_legacy {
1032 status = "okay";
1033 };
1034 mbox_dsp1_legacy: mbox_dsp1_legacy {
1035 status = "okay";
1036 };
1037 };
1039 &mailbox6 {
1040 status = "okay";
1041 mbox_ipu2_legacy: mbox_ipu2_legacy {
1042 status = "okay";
1043 };
1044 mbox_dsp2_legacy: mbox_dsp2_legacy {
1045 status = "okay";
1046 };
1047 };
1049 &mmu0_dsp1 {
1050 status = "okay";
1051 };
1053 &mmu1_dsp1 {
1054 status = "okay";
1055 };
1057 &mmu0_dsp2 {
1058 status = "okay";
1059 };
1061 &mmu1_dsp2 {
1062 status = "okay";
1063 };
1065 &mmu_ipu1 {
1066 status = "okay";
1067 };
1069 &mmu_ipu2 {
1070 status = "okay";
1071 };
1073 &ipu2 {
1074 status = "okay";
1075 memory-region = <&ipu2_cma_pool>;
1076 mboxes = <&mailbox6 &mbox_ipu2_legacy>;
1077 timers = <&timer3>;
1078 watchdog-timers = <&timer4>, <&timer9>;
1079 };
1081 &ipu1 {
1082 status = "okay";
1083 memory-region = <&ipu1_cma_pool>;
1084 mboxes = <&mailbox5 &mbox_ipu1_legacy>;
1085 timers = <&timer11>;
1086 };
1088 &dsp1 {
1089 status = "okay";
1090 memory-region = <&dsp1_cma_pool>;
1091 mboxes = <&mailbox5 &mbox_dsp1_legacy>;
1092 timers = <&timer5>;
1093 };
1095 &dsp2 {
1096 status = "okay";
1097 memory-region = <&dsp2_cma_pool>;
1098 mboxes = <&mailbox6 &mbox_dsp2_legacy>;
1099 timers = <&timer6>;
1100 };
1102 &atl {
1103 pinctrl-names = "default";
1104 pinctrl-0 = <&atl_pins>;
1106 status = "okay";
1108 atl1 {
1109 bws = <DRA7_ATL_WS_MCASP2_FSX>;
1110 aws = <DRA7_ATL_WS_MCASP6_FSX>;
1111 };
1113 atl2 {
1114 bws = <DRA7_ATL_WS_MCASP2_FSX>;
1115 aws = <DRA7_ATL_WS_MCASP3_FSX>;
1116 };
1117 };
1119 &mcasp2 {
1120 pinctrl-names = "default";
1121 pinctrl-0 = <&mcasp2_pins>;
1123 fck_parent = "atl_clkin2_ck";
1125 status = "okay";
1127 op-mode = <0>; /* MCASP_IIS_MODE */
1128 tdm-slots = <2>;
1129 /* 8 serializer */
1130 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1131 1 1 1 1 1 1 1 1
1132 >;
1133 };
1135 &mcasp3 {
1136 pinctrl-names = "default", "sleep";
1137 pinctrl-0 = <&mcasp3_pins>;
1138 pinctrl-1 = <&mcasp3_sleep_pins>;
1140 fck_parent = "atl_clkin2_ck";
1142 status = "okay";
1144 op-mode = <0>; /* MCASP_IIS_MODE */
1145 tdm-slots = <2>;
1146 /* 4 serializer */
1147 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1148 1 2 0 0
1149 >;
1150 };
1152 &mcasp6 {
1153 pinctrl-names = "default";
1154 pinctrl-0 = <&mcasp6_pins>;
1156 fck_parent = "atl_clkin1_ck";
1158 status = "okay";
1160 op-mode = <0>; /* MCASP_IIS_MODE */
1161 tdm-slots = <8>;
1162 /* 4 serializer */
1163 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1164 1 2 0 0
1165 >;
1166 tx-num-evt = <8>;
1167 rx-num-evt = <8>;
1168 };