1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clk/ti-dra7-atl.h>
15 / {
16 model = "TI DRA742";
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
19 memory {
20 device_type = "memory";
21 reg = <0x80000000 0x60000000>; /* 1536 MB */
22 };
24 reserved-memory {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
29 ipu2_cma_pool: ipu2_cma@95800000 {
30 compatible = "shared-dma-pool";
31 reg = <0x95800000 0x3800000>;
32 reusable;
33 status = "okay";
34 };
36 dsp1_cma_pool: dsp1_cma@99000000 {
37 compatible = "shared-dma-pool";
38 reg = <0x99000000 0x4000000>;
39 reusable;
40 status = "okay";
41 };
43 ipu1_cma_pool: ipu1_cma@9d000000 {
44 compatible = "shared-dma-pool";
45 reg = <0x9d000000 0x2000000>;
46 reusable;
47 status = "okay";
48 };
50 dsp2_cma_pool: dsp2_cma@9f000000 {
51 compatible = "shared-dma-pool";
52 reg = <0x9f000000 0x800000>;
53 reusable;
54 status = "okay";
55 };
56 };
58 extcon1: dra7x_usbid_extcon1 {
59 compatible = "linux,extcon-gpio";
60 gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_LOW>;
61 cable-name = "USB-HOST";
62 };
64 extcon2: dra7x_usbid_extcon2 {
65 compatible = "linux,extcon-gpio";
66 gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_LOW>;
67 cable-name = "USB-HOST";
68 };
70 evm_3v3_sd: fixedregulator-sd {
71 compatible = "regulator-fixed";
72 regulator-name = "evm_3v3_sd";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 enable-active-high;
76 gpio = <&pcf_gpio_21 5 0>;
77 };
79 evm_3v3_sw: fixedregulator-evm_3v3_sw {
80 compatible = "regulator-fixed";
81 regulator-name = "evm_3v3_sw";
82 vin-supply = <&sysen1>;
83 regulator-min-microvolt = <3300000>;
84 regulator-max-microvolt = <3300000>;
85 };
87 aic_dvdd: fixedregulator-aic_dvdd {
88 /* TPS77018DBVT */
89 compatible = "regulator-fixed";
90 regulator-name = "aic_dvdd";
91 vin-supply = <&evm_3v3_sw>;
92 regulator-min-microvolt = <1800000>;
93 regulator-max-microvolt = <1800000>;
94 };
96 vmmcwl_fixed: fixedregulator-mmcwl {
97 compatible = "regulator-fixed";
98 regulator-name = "vmmcwl_fixed";
99 regulator-min-microvolt = <1800000>;
100 regulator-max-microvolt = <1800000>;
101 gpio = <&gpio5 8 0>; /* gpio5_8 */
102 startup-delay-us = <70000>;
103 enable-active-high;
104 };
106 kim {
107 compatible = "kim";
108 nshutdown_gpio = <132>;
109 dev_name = "/dev/ttyS2";
110 flow_cntrl = <1>;
111 baud_rate = <3686400>;
112 };
114 btwilink {
115 compatible = "btwilink";
116 };
118 vtt_fixed: fixedregulator-vtt {
119 compatible = "regulator-fixed";
120 regulator-name = "vtt_fixed";
121 regulator-min-microvolt = <1350000>;
122 regulator-max-microvolt = <1350000>;
123 regulator-always-on;
124 regulator-boot-on;
125 enable-active-high;
126 vin-supply = <&sysen2>;
127 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
128 };
130 aliases {
131 display0 = &hdmi0;
132 sound0 = &primary_sound;
133 sound1 = &hdmi;
134 };
136 hdmi0: connector@1 {
137 compatible = "hdmi-connector";
138 label = "hdmi";
140 type = "a";
142 port {
143 hdmi_connector_in: endpoint {
144 remote-endpoint = <&tpd12s015_out>;
145 };
146 };
147 };
149 tpd12s015: encoder@1 {
150 compatible = "ti,dra7evm-tpd12s015";
152 gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
153 <&pcf_hdmi 5 0>, /* P5, LS OE */
154 <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
156 ports {
157 #address-cells = <1>;
158 #size-cells = <0>;
160 port@0 {
161 reg = <0>;
163 tpd12s015_in: endpoint@0 {
164 remote-endpoint = <&hdmi_out>;
165 };
166 };
168 port@1 {
169 reg = <1>;
171 tpd12s015_out: endpoint@0 {
172 remote-endpoint = <&hdmi_connector_in>;
173 };
174 };
175 };
176 };
178 primary_sound: primary_sound {
179 compatible = "ti,dra7xx-evm-audio";
180 ti,model = "DRA7xx-EVM";
181 ti,audio-codec = <&tlv320aic3106>;
182 ti,mcasp-controller = <&mcasp3>;
183 ti,codec-clock-rate = <5644800>;
184 clocks = <&atl_clkin2_ck>;
185 clock-names = "mclk";
186 ti,audio-routing =
187 "Headphone Jack", "HPLOUT",
188 "Headphone Jack", "HPROUT",
189 "Line Out", "LLOUT",
190 "Line Out", "RLOUT",
191 "MIC3L", "Mic Jack",
192 "MIC3R", "Mic Jack",
193 "Mic Jack", "Mic Bias",
194 "LINE1L", "Line In",
195 "LINE1R", "Line In";
196 };
197 };
199 &dra7_pmx_core {
200 dcan1_pins_default: dcan1_pins_default {
201 pinctrl-single,pins = <
202 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
203 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
204 >;
205 };
207 dcan1_pins_sleep: dcan1_pins_sleep {
208 pinctrl-single,pins = <
209 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
210 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
211 >;
212 };
214 mmc1_pins_default: pinmux_mmc1_default_pins {
215 pinctrl-single,pins = <
216 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
217 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
218 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
219 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
220 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
221 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
222 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio187 */
223 >;
224 };
226 mmc1_pins_hs: pinmux_mmc1_hs_pins {
227 pinctrl-single,pins = <
228 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
229 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
230 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
231 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
232 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
233 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
234 >;
235 };
237 mmc2_pins_default: mmc2_pins_default {
238 pinctrl-single,pins = <
239 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
240 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
241 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
242 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
243 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
244 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
245 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
246 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
247 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
248 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
249 >;
250 };
252 mmc2_pins_hs: pinmux_mmc2_hs_pins {
253 pinctrl-single,pins = <
254 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
255 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
256 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
257 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
258 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
259 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
260 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
261 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
262 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
263 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
264 >;
265 };
266 };
268 &i2c1 {
269 status = "okay";
270 clock-frequency = <400000>;
272 tps659038: tps659038@58 {
273 compatible = "ti,tps659038";
274 reg = <0x58>;
276 tps659038_pmic {
277 compatible = "ti,tps659038-pmic";
279 regulators {
280 smps123_reg: smps123 {
281 /* VDD_MPU */
282 regulator-name = "smps123";
283 regulator-min-microvolt = < 850000>;
284 regulator-max-microvolt = <1250000>;
285 regulator-always-on;
286 regulator-boot-on;
287 };
289 smps45_reg: smps45 {
290 /* VDD_DSPEVE */
291 regulator-name = "smps45";
292 regulator-min-microvolt = < 850000>;
293 regulator-max-microvolt = <1150000>;
294 regulator-boot-on;
295 regulator-always-on;
296 };
298 smps6_reg: smps6 {
299 /* VDD_GPU - over VDD_SMPS6 */
300 regulator-name = "smps6";
301 regulator-min-microvolt = <850000>;
302 regulator-max-microvolt = <1250000>;
303 regulator-boot-on;
304 regulator-always-on;
305 };
307 smps7_reg: smps7 {
308 /* CORE_VDD */
309 regulator-name = "smps7";
310 regulator-min-microvolt = <850000>;
311 regulator-max-microvolt = <1060000>;
312 regulator-always-on;
313 regulator-boot-on;
314 };
316 smps8_reg: smps8 {
317 /* VDD_IVAHD */
318 regulator-name = "smps8";
319 regulator-min-microvolt = < 850000>;
320 regulator-max-microvolt = <1250000>;
321 regulator-boot-on;
322 regulator-always-on;
323 };
325 smps9_reg: smps9 {
326 /* VDDS1V8 */
327 regulator-name = "smps9";
328 regulator-min-microvolt = <1800000>;
329 regulator-max-microvolt = <1800000>;
330 regulator-always-on;
331 regulator-boot-on;
332 };
334 ldo1_reg: ldo1 {
335 /* LDO1_OUT --> SDIO */
336 regulator-name = "ldo1";
337 regulator-min-microvolt = <1800000>;
338 regulator-max-microvolt = <3300000>;
339 regulator-boot-on;
340 regulator-always-on;
341 };
343 ldo2_reg: ldo2 {
344 /* VDD_RTCIO */
345 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
346 regulator-name = "ldo2";
347 regulator-min-microvolt = <3300000>;
348 regulator-max-microvolt = <3300000>;
349 regulator-boot-on;
350 regulator-always-on;
351 };
353 ldo3_reg: ldo3 {
354 /* VDDA_1V8_PHY */
355 regulator-name = "ldo3";
356 regulator-min-microvolt = <1800000>;
357 regulator-max-microvolt = <1800000>;
358 regulator-always-on;
359 regulator-boot-on;
360 };
362 ldo9_reg: ldo9 {
363 /* VDD_RTC */
364 regulator-name = "ldo9";
365 regulator-min-microvolt = <1050000>;
366 regulator-max-microvolt = <1050000>;
367 regulator-boot-on;
368 regulator-always-on;
369 };
371 ldoln_reg: ldoln {
372 /* VDDA_1V8_PLL */
373 regulator-name = "ldoln";
374 regulator-min-microvolt = <1800000>;
375 regulator-max-microvolt = <1800000>;
376 regulator-always-on;
377 regulator-boot-on;
378 };
380 ldousb_reg: ldousb {
381 /* VDDA_3V_USB: VDDA_USBHS33 */
382 regulator-name = "ldousb";
383 regulator-min-microvolt = <3300000>;
384 regulator-max-microvolt = <3300000>;
385 regulator-boot-on;
386 regulator-always-on;
387 };
389 /* REGEN1 is unused */
391 regen2: regen2 {
392 /* Needed for PMIC internal resources */
393 regulator-name = "regen2";
394 regulator-boot-on;
395 regulator-always-on;
396 };
398 /* REGEN3 is unused */
400 sysen1: sysen1 {
401 /* PMIC_REGEN_3V3 */
402 regulator-name = "sysen1";
403 regulator-boot-on;
404 regulator-always-on;
405 };
407 sysen2: sysen2 {
408 /* PMIC_REGEN_DDR */
409 regulator-name = "sysen2";
410 regulator-boot-on;
411 regulator-always-on;
412 };
413 };
414 };
415 };
417 pcf_lcd: gpio@20 {
418 compatible = "nxp,pcf8575";
419 reg = <0x20>;
420 gpio-controller;
421 #gpio-cells = <2>;
422 };
424 pcf_gpio_21: gpio@21 {
425 compatible = "ti,pcf8575";
426 reg = <0x21>;
427 lines-initial-states = <0x1408>;
428 gpio-controller;
429 #gpio-cells = <2>;
430 interrupt-parent = <&gpio6>;
431 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
434 };
436 mxt244: touchscreen@4a {
437 compatible = "atmel,mXT244";
438 status = "okay";
439 reg = <0x4a>;
440 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
442 atmel,config = <
443 /* MXT244_GEN_COMMAND(6) */
444 0x00 0x00 0x00 0x00 0x00 0x00
445 /* MXT244_GEN_POWER(7) */
446 0x20 0xff 0x32
447 /* MXT244_GEN_ACQUIRE(8) */
448 0x0a 0x00 0x05 0x00 0x00 0x00 0x09 0x23
449 /* MXT244_TOUCH_MULTI(9) */
450 0x00 0x00 0x00 0x13 0x0b 0x00 0x00 0x00 0x02 0x00
451 0x00 0x01 0x01 0x0e 0x0a 0x0a 0x0a 0x0a 0x00 0x00
452 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
453 0x00
454 /* MXT244_TOUCH_KEYARRAY(15) */
455 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
456 0x00
457 /* MXT244_COMMSCONFIG_T18(2) */
458 0x00 0x00
459 /* MXT244_SPT_GPIOPWM(19) */
460 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
461 0x00 0x00 0x00 0x00 0x00 0x00
462 /* MXT244_PROCI_GRIPFACE(20) */
463 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x28 0x04
464 0x0f 0x0a
465 /* MXT244_PROCG_NOISE(22) */
466 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x23 0x00
467 0x00 0x05 0x0f 0x19 0x23 0x2d 0x03
468 /* MXT244_TOUCH_PROXIMITY(23) */
469 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
470 0x00 0x00 0x00 0x00 0x00
471 /* MXT244_PROCI_ONETOUCH(24) */
472 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
473 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
474 /* MXT244_SPT_SELFTEST(25) */
475 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
476 0x00 0x00 0x00 0x00
477 /* MXT244_PROCI_TWOTOUCH(27) */
478 0x00 0x00 0x00 0x00 0x00 0x00 0x00
479 /* MXT244_SPT_CTECONFIG(28) */
480 0x00 0x00 0x02 0x08 0x10 0x00
481 >;
483 atmel,x_line = <18>;
484 atmel,y_line = <12>;
485 atmel,x_size = <800>;
486 atmel,y_size = <480>;
487 atmel,blen = <0x01>;
488 atmel,threshold = <30>;
489 atmel,voltage = <2800000>;
490 atmel,orient = <0x4>;
491 };
493 tlv320aic3106: tlv320aic3106@18 {
494 compatible = "ti,tlv320aic3106";
495 reg = <0x18>;
496 adc-settle-ms = <40>;
497 ai3x-micbias-vg = <1>; /* 2.0V */
498 status = "okay";
500 /* Regulators */
501 AVDD-supply = <&evm_3v3_sw>;
502 IOVDD-supply = <&evm_3v3_sw>;
503 DRVDD-supply = <&evm_3v3_sw>;
504 DVDD-supply = <&aic_dvdd>;
505 };
506 };
508 &i2c2 {
509 status = "okay";
510 clock-frequency = <400000>;
512 pcf_hdmi: gpio@26 {
513 compatible = "nxp,pcf8575";
514 reg = <0x26>;
515 lines-initial-states = <0xffeb>;
516 gpio-controller;
517 #gpio-cells = <2>;
518 };
519 };
521 &i2c3 {
522 status = "okay";
523 clock-frequency = <3400000>;
524 };
526 &mcspi1 {
527 status = "okay";
528 };
530 &mcspi2 {
531 status = "okay";
532 };
534 &uart1 {
535 status = "okay";
536 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
537 &dra7_pmx_core 0x3e0>;
538 };
540 &uart2 {
541 status = "okay";
542 };
544 &uart3 {
545 status = "okay";
546 gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
547 };
549 &mmc1 {
550 status = "okay";
551 pbias-supply = <&pbias_mmc_reg>;
552 vmmc-supply = <&evm_3v3_sd>;
553 vmmc_aux-supply = <&ldo1_reg>;
554 bus-width = <4>;
555 /*
556 * SDCD signal is not being used here - using the fact that GPIO mode
557 * is always hardwired.
558 */
559 cd-gpios = <&gpio6 27 0>;
560 pinctrl-names = "default", "hs";
561 pinctrl-0 = <&mmc1_pins_default>;
562 pinctrl-1 = <&mmc1_pins_hs>;
563 };
565 &mmc2 {
566 status = "okay";
567 vmmc-supply = <&evm_3v3_sw>;
568 bus-width = <8>;
569 pinctrl-names = "default", "hs";
570 pinctrl-0 = <&mmc2_pins_default>;
571 pinctrl-1 = <&mmc2_pins_hs>;
572 };
574 &mmc4 {
575 status = "okay";
576 vmmc-supply = <&vmmcwl_fixed>;
577 bus-width = <4>;
578 cap-power-off-card;
579 keep-power-in-suspend;
580 ti,non-removable;
582 #address-cells = <1>;
583 #size-cells = <0>;
584 wlcore: wlcore@0 {
585 compatible = "ti,wlcore";
586 reg = <2>;
587 interrupt-parent = <&gpio5>;
588 interrupts = <7 IRQ_TYPE_NONE>;
589 };
590 };
592 &cpu0 {
593 cpu0-voltdm = <&voltdm_mpu>;
594 voltage-tolerance = <1>;
595 };
597 &voltdm_mpu {
598 vdd-supply = <&smps123_reg>;
599 };
601 &voltdm_dspeve {
602 vdd-supply = <&smps45_reg>;
603 };
605 &voltdm_gpu {
606 vdd-supply = <&smps6_reg>;
607 };
609 &voltdm_ivahd {
610 vdd-supply = <&smps8_reg>;
611 };
613 &voltdm_core {
614 vdd-supply = <&smps7_reg>;
615 };
617 &qspi {
618 status = "okay";
620 spi-max-frequency = <48000000>;
621 m25p80@0 {
622 compatible = "s25fl256s1";
623 spi-max-frequency = <48000000>;
624 reg = <0>;
625 spi-tx-bus-width = <1>;
626 spi-rx-bus-width = <4>;
627 spi-cpol;
628 spi-cpha;
629 #address-cells = <1>;
630 #size-cells = <1>;
632 /* MTD partition table.
633 * The ROM checks the first four physical blocks
634 * for a valid file to boot and the flash here is
635 * 64KiB block size.
636 */
637 partition@0 {
638 label = "QSPI.SPL";
639 reg = <0x00000000 0x000010000>;
640 };
641 partition@1 {
642 label = "QSPI.SPL.backup1";
643 reg = <0x00010000 0x00010000>;
644 };
645 partition@2 {
646 label = "QSPI.SPL.backup2";
647 reg = <0x00020000 0x00010000>;
648 };
649 partition@3 {
650 label = "QSPI.SPL.backup3";
651 reg = <0x00030000 0x00010000>;
652 };
653 partition@4 {
654 label = "QSPI.u-boot";
655 reg = <0x00040000 0x00100000>;
656 };
657 partition@5 {
658 label = "QSPI.u-boot-spl-os";
659 reg = <0x00140000 0x00080000>;
660 };
661 partition@6 {
662 label = "QSPI.u-boot-env";
663 reg = <0x001c0000 0x00010000>;
664 };
665 partition@7 {
666 label = "QSPI.u-boot-env.backup1";
667 reg = <0x001d0000 0x0010000>;
668 };
669 partition@8 {
670 label = "QSPI.kernel";
671 reg = <0x001e0000 0x0800000>;
672 };
673 partition@9 {
674 label = "QSPI.file-system";
675 reg = <0x009e0000 0x01620000>;
676 };
677 };
678 };
680 &omap_dwc3_1 {
681 extcon = <&extcon1>;
682 };
684 &omap_dwc3_2 {
685 extcon = <&extcon2>;
686 };
688 &usb1 {
689 dr_mode = "peripheral";
690 };
692 &usb2 {
693 dr_mode = "host";
694 };
696 &mac {
697 status = "okay";
698 dual_emac;
699 };
701 &cpsw_emac0 {
702 phy_id = <&davinci_mdio>, <2>;
703 phy-mode = "rgmii";
704 dual_emac_res_vlan = <1>;
705 };
707 &cpsw_emac1 {
708 phy_id = <&davinci_mdio>, <3>;
709 phy-mode = "rgmii";
710 dual_emac_res_vlan = <2>;
711 };
713 &elm {
714 status = "okay";
715 };
717 &gpmc {
718 status = "disabled";
719 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
720 nand@0,0 {
721 reg = <0 0 4>; /* device IO registers */
722 ti,nand-ecc-opt = "bch8";
723 ti,elm-id = <&elm>;
724 nand-bus-width = <16>;
725 gpmc,device-width = <2>;
726 gpmc,sync-clk-ps = <0>;
727 gpmc,cs-on-ns = <0>;
728 gpmc,cs-rd-off-ns = <80>;
729 gpmc,cs-wr-off-ns = <80>;
730 gpmc,adv-on-ns = <0>;
731 gpmc,adv-rd-off-ns = <60>;
732 gpmc,adv-wr-off-ns = <60>;
733 gpmc,we-on-ns = <10>;
734 gpmc,we-off-ns = <50>;
735 gpmc,oe-on-ns = <4>;
736 gpmc,oe-off-ns = <40>;
737 gpmc,access-ns = <40>;
738 gpmc,wr-access-ns = <80>;
739 gpmc,rd-cycle-ns = <80>;
740 gpmc,wr-cycle-ns = <80>;
741 gpmc,bus-turnaround-ns = <0>;
742 gpmc,cycle2cycle-delay-ns = <0>;
743 gpmc,clk-activation-ns = <0>;
744 gpmc,wait-monitoring-ns = <0>;
745 gpmc,wr-data-mux-bus-ns = <0>;
746 /* MTD partition table */
747 /* All SPL-* partitions are sized to minimal length
748 * which can be independently programmable. For
749 * NAND flash this is equal to size of erase-block */
750 #address-cells = <1>;
751 #size-cells = <1>;
752 partition@0 {
753 label = "NAND.SPL";
754 reg = <0x00000000 0x000020000>;
755 };
756 partition@1 {
757 label = "NAND.SPL.backup1";
758 reg = <0x00020000 0x00020000>;
759 };
760 partition@2 {
761 label = "NAND.SPL.backup2";
762 reg = <0x00040000 0x00020000>;
763 };
764 partition@3 {
765 label = "NAND.SPL.backup3";
766 reg = <0x00060000 0x00020000>;
767 };
768 partition@4 {
769 label = "NAND.u-boot-spl-os";
770 reg = <0x00080000 0x00040000>;
771 };
772 partition@5 {
773 label = "NAND.u-boot";
774 reg = <0x000c0000 0x00100000>;
775 };
776 partition@6 {
777 label = "NAND.u-boot-env";
778 reg = <0x001c0000 0x00020000>;
779 };
780 partition@7 {
781 label = "NAND.u-boot-env.backup1";
782 reg = <0x001e0000 0x00020000>;
783 };
784 partition@8 {
785 label = "NAND.kernel";
786 reg = <0x00200000 0x00800000>;
787 };
788 partition@9 {
789 label = "NAND.file-system";
790 reg = <0x00a00000 0x0f600000>;
791 };
792 };
793 };
795 &gpio7 {
796 ti,no-reset-on-init;
797 ti,no-idle-on-init;
798 };
800 &dss {
801 status = "ok";
803 vdda_video-supply = <&ldoln_reg>;
804 };
806 &hdmi {
807 status = "ok";
808 vdda-supply = <&ldo3_reg>;
810 port {
811 hdmi_out: endpoint {
812 remote-endpoint = <&tpd12s015_in>;
813 };
814 };
815 };
817 &dcan1 {
818 status = "ok";
819 pinctrl-names = "default", "sleep";
820 pinctrl-0 = <&dcan1_pins_default>;
821 pinctrl-1 = <&dcan1_pins_sleep>;
822 };
824 &mailbox5 {
825 status = "okay";
826 mbox_ipu1_legacy: mbox_ipu1_legacy {
827 status = "okay";
828 };
829 mbox_dsp1_legacy: mbox_dsp1_legacy {
830 status = "okay";
831 };
832 };
834 &mailbox6 {
835 status = "okay";
836 mbox_ipu2_legacy: mbox_ipu2_legacy {
837 status = "okay";
838 };
839 mbox_dsp2_legacy: mbox_dsp2_legacy {
840 status = "okay";
841 };
842 };
844 &mmu0_dsp1 {
845 status = "okay";
846 };
848 &mmu1_dsp1 {
849 status = "okay";
850 };
852 &mmu0_dsp2 {
853 status = "okay";
854 };
856 &mmu1_dsp2 {
857 status = "okay";
858 };
860 &mmu_ipu1 {
861 status = "okay";
862 };
864 &mmu_ipu2 {
865 status = "okay";
866 };
868 &ipu2 {
869 status = "okay";
870 memory-region = <&ipu2_cma_pool>;
871 mboxes = <&mailbox6 &mbox_ipu2_legacy>;
872 timers = <&timer3>;
873 watchdog-timers = <&timer4>, <&timer9>;
874 };
876 &ipu1 {
877 status = "okay";
878 memory-region = <&ipu1_cma_pool>;
879 mboxes = <&mailbox5 &mbox_ipu1_legacy>;
880 timers = <&timer11>;
881 };
883 &dsp1 {
884 status = "okay";
885 memory-region = <&dsp1_cma_pool>;
886 mboxes = <&mailbox5 &mbox_dsp1_legacy>;
887 timers = <&timer5>;
888 };
890 &dsp2 {
891 status = "okay";
892 memory-region = <&dsp2_cma_pool>;
893 mboxes = <&mailbox6 &mbox_dsp2_legacy>;
894 timers = <&timer6>;
895 };
897 &atl {
898 status = "okay";
900 atl2 {
901 bws = <DRA7_ATL_WS_MCASP2_FSX>;
902 aws = <DRA7_ATL_WS_MCASP3_FSX>;
903 };
904 };
906 &mcasp3 {
907 fck_parent = "atl_clkin2_ck";
909 status = "okay";
911 op-mode = <0>; /* MCASP_IIS_MODE */
912 tdm-slots = <2>;
913 /* 4 serializer */
914 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
915 1 2 0 0
916 >;
917 };
919 &usb2_phy1 {
920 phy-supply = <&ldousb_reg>;
921 };
923 &usb2_phy2 {
924 phy-supply = <&ldousb_reg>;
925 };