arch/arm/boot/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/clk/ti-dra7-atl.h>
  14
  15 / {
  16         model = "TI DRA742";
  17         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  18
  19         memory {
  20                 device_type = "memory";
  21                 reg = <0x80000000 0x60000000>; /* 1536 MB */
  22         };
  23
  24         reserved-memory {
  25                 #address-cells = <1>;
  26                 #size-cells = <1>;
  27                 ranges;
  28
  29                 ipu2_cma_pool: ipu2_cma@95800000 {
  30                         compatible = "shared-dma-pool";
  31                         reg = <0x95800000 0x3800000>;
  32                         reusable;
  33                         status = "okay";
  34                 };
  35
  36                 dsp1_cma_pool: dsp1_cma@99000000 {
  37                         compatible = "shared-dma-pool";
  38                         reg = <0x99000000 0x4000000>;
  39                         reusable;
  40                         status = "okay";
  41                 };
  42
  43                 ipu1_cma_pool: ipu1_cma@9d000000 {
  44                         compatible = "shared-dma-pool";
  45                         reg = <0x9d000000 0x2000000>;
  46                         reusable;
  47                         status = "okay";
  48                 };
  49
  50                 dsp2_cma_pool: dsp2_cma@9f000000 {
  51                         compatible = "shared-dma-pool";
  52                         reg = <0x9f000000 0x800000>;
  53                         reusable;
  54                         status = "okay";
  55                 };
  56         };
  57
  58         extcon1: dra7x_usbid_extcon1 {
  59                 compatible = "linux,extcon-gpio";
  60                 gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_LOW>;
  61                 cable-name = "USB-HOST";
  62         };
  63
  64         extcon2: dra7x_usbid_extcon2 {
  65                 compatible = "linux,extcon-gpio";
  66                 gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_LOW>;
  67                 cable-name = "USB-HOST";
  68         };
  69
  70         evm_3v3_sd: fixedregulator-sd {
  71                 compatible = "regulator-fixed";
  72                 regulator-name = "evm_3v3_sd";
  73                 regulator-min-microvolt = <3300000>;
  74                 regulator-max-microvolt = <3300000>;
  75                 enable-active-high;
  76                 gpio = <&pcf_gpio_21 5 0>;
  77         };
  78
  79         evm_3v3_sw: fixedregulator-evm_3v3_sw {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "evm_3v3_sw";
  82                 vin-supply = <&sysen1>;
  83                 regulator-min-microvolt = <3300000>;
  84                 regulator-max-microvolt = <3300000>;
  85         };
  86
  87         aic_dvdd: fixedregulator-aic_dvdd {
  88                 /* TPS77018DBVT */
  89                 compatible = "regulator-fixed";
  90                 regulator-name = "aic_dvdd";
  91                 vin-supply = <&evm_3v3_sw>;
  92                 regulator-min-microvolt = <1800000>;
  93                 regulator-max-microvolt = <1800000>;
  94         };
  95
  96         vmmcwl_fixed: fixedregulator-mmcwl {
  97                 compatible = "regulator-fixed";
  98                 regulator-name = "vmmcwl_fixed";
  99                 regulator-min-microvolt = <1800000>;
 100                 regulator-max-microvolt = <1800000>;
 101                 gpio = <&gpio5 8 0>;    /* gpio5_8 */
 102                 startup-delay-us = <70000>;
 103                 enable-active-high;
 104         };
 105
 106         kim {
 107                 compatible = "kim";
 108                 nshutdown_gpio = <132>;
 109                 dev_name = "/dev/ttyS2";
 110                 flow_cntrl = <1>;
 111                 baud_rate = <3686400>;
 112         };
 113
 114         btwilink {
 115                 compatible = "btwilink";
 116         };
 117
 118         vtt_fixed: fixedregulator-vtt {
 119                 compatible = "regulator-fixed";
 120                 regulator-name = "vtt_fixed";
 121                 regulator-min-microvolt = <1350000>;
 122                 regulator-max-microvolt = <1350000>;
 123                 regulator-always-on;
 124                 regulator-boot-on;
 125                 enable-active-high;
 126                 vin-supply = <&sysen2>;
 127                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
 128         };
 129
 130         aliases {
 131                 display0 = &hdmi0;
 132                 sound0 = &primary_sound;
 133                 sound1 = &hdmi;
 134         };
 135
 136         hdmi0: connector@1 {
 137                 compatible = "hdmi-connector";
 138                 label = "hdmi";
 139
 140                 type = "a";
 141
 142                 port {
 143                         hdmi_connector_in: endpoint {
 144                                 remote-endpoint = <&tpd12s015_out>;
 145                         };
 146                 };
 147         };
 148
 149         tpd12s015: encoder@1 {
 150                 compatible = "ti,dra7evm-tpd12s015";
 151
 152                 gpios = <&pcf_hdmi 4 0>,        /* P4, CT CP HPD */
 153                         <&pcf_hdmi 5 0>,        /* P5, LS OE */
 154                         <&gpio7 12 0>;  /* gpio7_12/sp1_cs2, HPD */
 155
 156                 ports {
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159
 160                         port@0 {
 161                                 reg = <0>;
 162
 163                                 tpd12s015_in: endpoint@0 {
 164                                         remote-endpoint = <&hdmi_out>;
 165                                 };
 166                         };
 167
 168                         port@1 {
 169                                 reg = <1>;
 170
 171                                 tpd12s015_out: endpoint@0 {
 172                                         remote-endpoint = <&hdmi_connector_in>;
 173                                 };
 174                         };
 175                 };
 176         };
 177
 178         primary_sound: primary_sound {
 179                 compatible = "ti,dra7xx-evm-audio";
 180                 ti,model = "DRA7xx-EVM";
 181                 ti,audio-codec = <&tlv320aic3106>;
 182                 ti,mcasp-controller = <&mcasp3>;
 183                 ti,codec-clock-rate = <5644800>;
 184                 clocks = <&atl_clkin2_ck>;
 185                 clock-names = "mclk";
 186                 ti,audio-routing =
 187                         "Headphone Jack",       "HPLOUT",
 188                         "Headphone Jack",       "HPROUT",
 189                         "Line Out",             "LLOUT",
 190                         "Line Out",             "RLOUT",
 191                         "MIC3L",                "Mic Jack",
 192                         "MIC3R",                "Mic Jack",
 193                         "Mic Jack",             "Mic Bias",
 194                         "LINE1L",               "Line In",
 195                         "LINE1R",               "Line In";
 196         };
 197 };
 198
 199 &dra7_pmx_core {
 200         dcan1_pins_default: dcan1_pins_default {
 201                 pinctrl-single,pins = <
 202                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 203                         0x418   (PULL_UP | MUX_MODE1)           /* wakeup0.dcan1_rx */
 204                 >;
 205         };
 206
 207         dcan1_pins_sleep: dcan1_pins_sleep {
 208                 pinctrl-single,pins = <
 209                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
 210                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
 211                 >;
 212         };
 213
 214         mmc1_pins_default: pinmux_mmc1_default_pins {
 215                 pinctrl-single,pins = <
 216                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_clk.clk */
 217                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_cmd.cmd */
 218                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat0.dat0 */
 219                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat1.dat1 */
 220                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat2.dat2 */
 221                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat3.dat3 */
 222                         0x36c (PIN_INPUT | MUX_MODE14)          /* mmc1sdcd.gpio187 */
 223                 >;
 224         };
 225
 226         mmc1_pins_hs: pinmux_mmc1_hs_pins {
 227                 pinctrl-single,pins = <
 228                         0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_clk.clk */
 229                         0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_cmd.cmd */
 230                         0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat0.dat0 */
 231                         0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat1.dat1 */
 232                         0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat2.dat2 */
 233                         0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat3.dat3 */
 234                 >;
 235         };
 236
 237         mmc2_pins_default: mmc2_pins_default {
 238                 pinctrl-single,pins = <
 239                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 240                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 241                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 242                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 243                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 244                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 245                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 246                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 247                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 248                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 249                 >;
 250         };
 251
 252         mmc2_pins_hs: pinmux_mmc2_hs_pins {
 253                 pinctrl-single,pins = <
 254                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 255                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 256                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 257                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 258                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 259                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 260                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 261                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 262                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 263                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 264                 >;
 265         };
 266 };
 267
 268 &i2c1 {
 269         status = "okay";
 270         clock-frequency = <400000>;
 271
 272         tps659038: tps659038@58 {
 273                 compatible = "ti,tps659038";
 274                 reg = <0x58>;
 275
 276                 tps659038_pmic {
 277                         compatible = "ti,tps659038-pmic";
 278
 279                         regulators {
 280                                 smps123_reg: smps123 {
 281                                         /* VDD_MPU */
 282                                         regulator-name = "smps123";
 283                                         regulator-min-microvolt = < 850000>;
 284                                         regulator-max-microvolt = <1250000>;
 285                                         regulator-always-on;
 286                                         regulator-boot-on;
 287                                 };
 288
 289                                 smps45_reg: smps45 {
 290                                         /* VDD_DSPEVE */
 291                                         regulator-name = "smps45";
 292                                         regulator-min-microvolt = < 850000>;
 293                                         regulator-max-microvolt = <1150000>;
 294                                         regulator-boot-on;
 295                                         regulator-always-on;
 296                                 };
 297
 298                                 smps6_reg: smps6 {
 299                                         /* VDD_GPU - over VDD_SMPS6 */
 300                                         regulator-name = "smps6";
 301                                         regulator-min-microvolt = <850000>;
 302                                         regulator-max-microvolt = <1250000>;
 303                                         regulator-boot-on;
 304                                         regulator-always-on;
 305                                 };
 306
 307                                 smps7_reg: smps7 {
 308                                         /* CORE_VDD */
 309                                         regulator-name = "smps7";
 310                                         regulator-min-microvolt = <850000>;
 311                                         regulator-max-microvolt = <1060000>;
 312                                         regulator-always-on;
 313                                         regulator-boot-on;
 314                                 };
 315
 316                                 smps8_reg: smps8 {
 317                                         /* VDD_IVAHD */
 318                                         regulator-name = "smps8";
 319                                         regulator-min-microvolt = < 850000>;
 320                                         regulator-max-microvolt = <1250000>;
 321                                         regulator-boot-on;
 322                                         regulator-always-on;
 323                                 };
 324
 325                                 smps9_reg: smps9 {
 326                                         /* VDDS1V8 */
 327                                         regulator-name = "smps9";
 328                                         regulator-min-microvolt = <1800000>;
 329                                         regulator-max-microvolt = <1800000>;
 330                                         regulator-always-on;
 331                                         regulator-boot-on;
 332                                 };
 333
 334                                 ldo1_reg: ldo1 {
 335                                         /* LDO1_OUT --> SDIO  */
 336                                         regulator-name = "ldo1";
 337                                         regulator-min-microvolt = <1800000>;
 338                                         regulator-max-microvolt = <3300000>;
 339                                         regulator-boot-on;
 340                                         regulator-always-on;
 341                                 };
 342
 343                                 ldo2_reg: ldo2 {
 344                                         /* VDD_RTCIO */
 345                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 346                                         regulator-name = "ldo2";
 347                                         regulator-min-microvolt = <3300000>;
 348                                         regulator-max-microvolt = <3300000>;
 349                                         regulator-boot-on;
 350                                         regulator-always-on;
 351                                 };
 352
 353                                 ldo3_reg: ldo3 {
 354                                         /* VDDA_1V8_PHY */
 355                                         regulator-name = "ldo3";
 356                                         regulator-min-microvolt = <1800000>;
 357                                         regulator-max-microvolt = <1800000>;
 358                                         regulator-always-on;
 359                                         regulator-boot-on;
 360                                 };
 361
 362                                 ldo9_reg: ldo9 {
 363                                         /* VDD_RTC */
 364                                         regulator-name = "ldo9";
 365                                         regulator-min-microvolt = <1050000>;
 366                                         regulator-max-microvolt = <1050000>;
 367                                         regulator-boot-on;
 368                                         regulator-always-on;
 369                                 };
 370
 371                                 ldoln_reg: ldoln {
 372                                         /* VDDA_1V8_PLL */
 373                                         regulator-name = "ldoln";
 374                                         regulator-min-microvolt = <1800000>;
 375                                         regulator-max-microvolt = <1800000>;
 376                                         regulator-always-on;
 377                                         regulator-boot-on;
 378                                 };
 379
 380                                 ldousb_reg: ldousb {
 381                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 382                                         regulator-name = "ldousb";
 383                                         regulator-min-microvolt = <3300000>;
 384                                         regulator-max-microvolt = <3300000>;
 385                                         regulator-boot-on;
 386                                         regulator-always-on;
 387                                 };
 388
 389                                 /* REGEN1 is unused */
 390
 391                                 regen2: regen2 {
 392                                         /* Needed for PMIC internal resources */
 393                                         regulator-name = "regen2";
 394                                         regulator-boot-on;
 395                                         regulator-always-on;
 396                                 };
 397
 398                                 /* REGEN3 is unused */
 399
 400                                 sysen1: sysen1 {
 401                                         /* PMIC_REGEN_3V3 */
 402                                         regulator-name = "sysen1";
 403                                         regulator-boot-on;
 404                                         regulator-always-on;
 405                                 };
 406
 407                                 sysen2: sysen2 {
 408                                         /* PMIC_REGEN_DDR */
 409                                         regulator-name = "sysen2";
 410                                         regulator-boot-on;
 411                                         regulator-always-on;
 412                                 };
 413                         };
 414                 };
 415         };
 416
 417         pcf_lcd: gpio@20 {
 418                 compatible = "nxp,pcf8575";
 419                 reg = <0x20>;
 420                 gpio-controller;
 421                 #gpio-cells = <2>;
 422         };
 423
 424         pcf_gpio_21: gpio@21 {
 425                 compatible = "ti,pcf8575";
 426                 reg = <0x21>;
 427                 lines-initial-states = <0x1408>;
 428                 gpio-controller;
 429                 #gpio-cells = <2>;
 430                 interrupt-parent = <&gpio6>;
 431                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 432                 interrupt-controller;
 433                 #interrupt-cells = <2>;
 434         };
 435
 436         tlv320aic3106: tlv320aic3106@18 {
 437                 compatible = "ti,tlv320aic3106";
 438                 reg = <0x18>;
 439                 adc-settle-ms = <40>;
 440                 ai3x-micbias-vg = <1>;          /* 2.0V */
 441                 status = "okay";
 442
 443                 /* Regulators */
 444                 AVDD-supply = <&evm_3v3_sw>;
 445                 IOVDD-supply = <&evm_3v3_sw>;
 446                 DRVDD-supply = <&evm_3v3_sw>;
 447                 DVDD-supply = <&aic_dvdd>;
 448         };
 449 };
 450
 451 &i2c2 {
 452         status = "okay";
 453         clock-frequency = <400000>;
 454
 455         pcf_hdmi: gpio@26 {
 456                 compatible = "nxp,pcf8575";
 457                 reg = <0x26>;
 458                 lines-initial-states = <0xffeb>;
 459                 gpio-controller;
 460                 #gpio-cells = <2>;
 461         };
 462
 463         ov10633@37 {
 464                 compatible = "ovti,ov10633";
 465                 reg = <0x37>;
 466
 467                 mux-gpios = <&pcf_hdmi 3        GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
 468                 port {
 469                         onboardLI: endpoint {
 470                                 remote-endpoint = <&vin1a>;
 471                                 hsync-active = <1>;
 472                                 vsync-active = <1>;
 473                                 pclk-sample = <1>;
 474                         };
 475                 };
 476         };
 477 };
 478
 479 &i2c3 {
 480         status = "okay";
 481         clock-frequency = <3400000>;
 482 };
 483
 484 &mcspi1 {
 485         status = "okay";
 486 };
 487
 488 &mcspi2 {
 489         status = "okay";
 490 };
 491
 492 &uart1 {
 493         status = "okay";
 494         interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
 495                                &dra7_pmx_core 0x3e0>;
 496 };
 497
 498 &uart2 {
 499         status = "okay";
 500 };
 501
 502 &uart3 {
 503         status = "okay";
 504         gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
 505 };
 506
 507 &mmc1 {
 508         status = "okay";
 509         pbias-supply = <&pbias_mmc_reg>;
 510         vmmc-supply = <&evm_3v3_sd>;
 511         vmmc_aux-supply = <&ldo1_reg>;
 512         bus-width = <4>;
 513         /*
 514          * SDCD signal is not being used here - using the fact that GPIO mode
 515          * is always hardwired.
 516          */
 517         cd-gpios = <&gpio6 27 0>;
 518         pinctrl-names = "default", "hs";
 519         pinctrl-0 = <&mmc1_pins_default>;
 520         pinctrl-1 = <&mmc1_pins_hs>;
 521 };
 522
 523 &mmc2 {
 524         status = "okay";
 525         vmmc-supply = <&evm_3v3_sw>;
 526         bus-width = <8>;
 527         pinctrl-names = "default", "hs";
 528         pinctrl-0 = <&mmc2_pins_default>;
 529         pinctrl-1 = <&mmc2_pins_hs>;
 530 };
 531
 532 &mmc4 {
 533         status = "okay";
 534         vmmc-supply = <&vmmcwl_fixed>;
 535         bus-width = <4>;
 536         cap-power-off-card;
 537         keep-power-in-suspend;
 538         ti,non-removable;
 539
 540         #address-cells = <1>;
 541         #size-cells = <0>;
 542         wlcore: wlcore@0 {
 543                 compatible = "ti,wlcore";
 544                 reg = <2>;
 545                 interrupt-parent = <&gpio5>;
 546                 interrupts = <7 IRQ_TYPE_NONE>;
 547         };
 548 };
 549
 550 &cpu0 {
 551         cpu0-voltdm = <&voltdm_mpu>;
 552         voltage-tolerance = <1>;
 553 };
 554
 555 &voltdm_mpu {
 556         vdd-supply = <&smps123_reg>;
 557 };
 558
 559 &voltdm_dspeve {
 560         vdd-supply = <&smps45_reg>;
 561 };
 562
 563 &voltdm_gpu {
 564         vdd-supply = <&smps6_reg>;
 565 };
 566
 567 &voltdm_ivahd {
 568         vdd-supply = <&smps8_reg>;
 569 };
 570
 571 &voltdm_core {
 572         vdd-supply = <&smps7_reg>;
 573 };
 574
 575 &qspi {
 576         status = "okay";
 577
 578         spi-max-frequency = <48000000>;
 579         m25p80@0 {
 580                 compatible = "s25fl256s1";
 581                 spi-max-frequency = <48000000>;
 582                 reg = <0>;
 583                 spi-tx-bus-width = <1>;
 584                 spi-rx-bus-width = <4>;
 585                 spi-cpol;
 586                 spi-cpha;
 587                 #address-cells = <1>;
 588                 #size-cells = <1>;
 589
 590                 /* MTD partition table.
 591                  * The ROM checks the first four physical blocks
 592                  * for a valid file to boot and the flash here is
 593                  * 64KiB block size.
 594                  */
 595                 partition@0 {
 596                         label = "QSPI.SPL";
 597                         reg = <0x00000000 0x000010000>;
 598                 };
 599                 partition@1 {
 600                         label = "QSPI.SPL.backup1";
 601                         reg = <0x00010000 0x00010000>;
 602                 };
 603                 partition@2 {
 604                         label = "QSPI.SPL.backup2";
 605                         reg = <0x00020000 0x00010000>;
 606                 };
 607                 partition@3 {
 608                         label = "QSPI.SPL.backup3";
 609                         reg = <0x00030000 0x00010000>;
 610                 };
 611                 partition@4 {
 612                         label = "QSPI.u-boot";
 613                         reg = <0x00040000 0x00100000>;
 614                 };
 615                 partition@5 {
 616                         label = "QSPI.u-boot-spl-os";
 617                         reg = <0x00140000 0x00080000>;
 618                 };
 619                 partition@6 {
 620                         label = "QSPI.u-boot-env";
 621                         reg = <0x001c0000 0x00010000>;
 622                 };
 623                 partition@7 {
 624                         label = "QSPI.u-boot-env.backup1";
 625                         reg = <0x001d0000 0x0010000>;
 626                 };
 627                 partition@8 {
 628                         label = "QSPI.kernel";
 629                         reg = <0x001e0000 0x0800000>;
 630                 };
 631                 partition@9 {
 632                         label = "QSPI.file-system";
 633                         reg = <0x009e0000 0x01620000>;
 634                 };
 635         };
 636 };
 637
 638 &omap_dwc3_1 {
 639         extcon = <&extcon1>;
 640 };
 641
 642 &omap_dwc3_2 {
 643         extcon = <&extcon2>;
 644 };
 645
 646 &usb1 {
 647         dr_mode = "peripheral";
 648 };
 649
 650 &usb2 {
 651         dr_mode = "host";
 652 };
 653
 654 &mac {
 655         status = "okay";
 656         dual_emac;
 657 };
 658
 659 &cpsw_emac0 {
 660         phy_id = <&davinci_mdio>, <2>;
 661         phy-mode = "rgmii";
 662         dual_emac_res_vlan = <1>;
 663 };
 664
 665 &cpsw_emac1 {
 666         phy_id = <&davinci_mdio>, <3>;
 667         phy-mode = "rgmii";
 668         dual_emac_res_vlan = <2>;
 669 };
 670
 671 &elm {
 672         status = "okay";
 673 };
 674
 675 &gpmc {
 676         status = "disabled";
 677         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 678         nand@0,0 {
 679                 reg = <0 0 4>;          /* device IO registers */
 680                 ti,nand-ecc-opt = "bch8";
 681                 ti,elm-id = <&elm>;
 682                 nand-bus-width = <16>;
 683                 gpmc,device-width = <2>;
 684                 gpmc,sync-clk-ps = <0>;
 685                 gpmc,cs-on-ns = <0>;
 686                 gpmc,cs-rd-off-ns = <80>;
 687                 gpmc,cs-wr-off-ns = <80>;
 688                 gpmc,adv-on-ns = <0>;
 689                 gpmc,adv-rd-off-ns = <60>;
 690                 gpmc,adv-wr-off-ns = <60>;
 691                 gpmc,we-on-ns = <10>;
 692                 gpmc,we-off-ns = <50>;
 693                 gpmc,oe-on-ns = <4>;
 694                 gpmc,oe-off-ns = <40>;
 695                 gpmc,access-ns = <40>;
 696                 gpmc,wr-access-ns = <80>;
 697                 gpmc,rd-cycle-ns = <80>;
 698                 gpmc,wr-cycle-ns = <80>;
 699                 gpmc,bus-turnaround-ns = <0>;
 700                 gpmc,cycle2cycle-delay-ns = <0>;
 701                 gpmc,clk-activation-ns = <0>;
 702                 gpmc,wait-monitoring-ns = <0>;
 703                 gpmc,wr-data-mux-bus-ns = <0>;
 704                 /* MTD partition table */
 705                 /* All SPL-* partitions are sized to minimal length
 706                  * which can be independently programmable. For
 707                  * NAND flash this is equal to size of erase-block */
 708                 #address-cells = <1>;
 709                 #size-cells = <1>;
 710                 partition@0 {
 711                         label = "NAND.SPL";
 712                         reg = <0x00000000 0x000020000>;
 713                 };
 714                 partition@1 {
 715                         label = "NAND.SPL.backup1";
 716                         reg = <0x00020000 0x00020000>;
 717                 };
 718                 partition@2 {
 719                         label = "NAND.SPL.backup2";
 720                         reg = <0x00040000 0x00020000>;
 721                 };
 722                 partition@3 {
 723                         label = "NAND.SPL.backup3";
 724                         reg = <0x00060000 0x00020000>;
 725                 };
 726                 partition@4 {
 727                         label = "NAND.u-boot-spl-os";
 728                         reg = <0x00080000 0x00040000>;
 729                 };
 730                 partition@5 {
 731                         label = "NAND.u-boot";
 732                         reg = <0x000c0000 0x00100000>;
 733                 };
 734                 partition@6 {
 735                         label = "NAND.u-boot-env";
 736                         reg = <0x001c0000 0x00020000>;
 737                 };
 738                 partition@7 {
 739                         label = "NAND.u-boot-env.backup1";
 740                         reg = <0x001e0000 0x00020000>;
 741                 };
 742                 partition@8 {
 743                         label = "NAND.kernel";
 744                         reg = <0x00200000 0x00800000>;
 745                 };
 746                 partition@9 {
 747                         label = "NAND.file-system";
 748                         reg = <0x00a00000 0x0f600000>;
 749                 };
 750         };
 751 };
 752
 753 &gpio7 {
 754         ti,no-reset-on-init;
 755         ti,no-idle-on-init;
 756 };
 757
 758 &dss {
 759         status = "ok";
 760
 761         vdda_video-supply = <&ldoln_reg>;
 762 };
 763
 764 &hdmi {
 765         status = "ok";
 766         vdda-supply = <&ldo3_reg>;
 767
 768         port {
 769                 hdmi_out: endpoint {
 770                         remote-endpoint = <&tpd12s015_in>;
 771                 };
 772         };
 773 };
 774
 775 &dcan1 {
 776         status = "ok";
 777         pinctrl-names = "default", "sleep";
 778         pinctrl-0 = <&dcan1_pins_default>;
 779         pinctrl-1 = <&dcan1_pins_sleep>;
 780 };
 781
 782 &mailbox5 {
 783         status = "okay";
 784         mbox_ipu1_legacy: mbox_ipu1_legacy {
 785                 status = "okay";
 786         };
 787         mbox_dsp1_legacy: mbox_dsp1_legacy {
 788                 status = "okay";
 789         };
 790 };
 791
 792 &mailbox6 {
 793         status = "okay";
 794         mbox_ipu2_legacy: mbox_ipu2_legacy {
 795                 status = "okay";
 796         };
 797         mbox_dsp2_legacy: mbox_dsp2_legacy {
 798                 status = "okay";
 799         };
 800 };
 801
 802 &mmu0_dsp1 {
 803         status = "okay";
 804 };
 805
 806 &mmu1_dsp1 {
 807         status = "okay";
 808 };
 809
 810 &mmu0_dsp2 {
 811         status = "okay";
 812 };
 813
 814 &mmu1_dsp2 {
 815         status = "okay";
 816 };
 817
 818 &mmu_ipu1 {
 819         status = "okay";
 820 };
 821
 822 &mmu_ipu2 {
 823         status = "okay";
 824 };
 825
 826 &ipu2 {
 827         status = "okay";
 828         memory-region = <&ipu2_cma_pool>;
 829         mboxes = <&mailbox6 &mbox_ipu2_legacy>;
 830         timers = <&timer3>;
 831         watchdog-timers = <&timer4>, <&timer9>;
 832 };
 833
 834 &ipu1 {
 835         status = "okay";
 836         memory-region = <&ipu1_cma_pool>;
 837         mboxes = <&mailbox5 &mbox_ipu1_legacy>;
 838         timers = <&timer11>;
 839 };
 840
 841 &dsp1 {
 842         status = "okay";
 843         memory-region = <&dsp1_cma_pool>;
 844         mboxes = <&mailbox5 &mbox_dsp1_legacy>;
 845         timers = <&timer5>;
 846 };
 847
 848 &dsp2 {
 849         status = "okay";
 850         memory-region = <&dsp2_cma_pool>;
 851         mboxes = <&mailbox6 &mbox_dsp2_legacy>;
 852         timers = <&timer6>;
 853 };
 854
 855 &atl {
 856         status = "okay";
 857
 858         atl2 {
 859                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 860                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 861         };
 862 };
 863
 864 &mcasp3 {
 865         fck_parent = "atl_clkin2_ck";
 866
 867         status = "okay";
 868
 869         op-mode = <0>;          /* MCASP_IIS_MODE */
 870         tdm-slots = <2>;
 871         /* 4 serializer */
 872         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 873                 1 2 0 0
 874         >;
 875 };
 876
 877 &usb2_phy1 {
 878         phy-supply = <&ldousb_reg>;
 879 };
 880
 881 &usb2_phy2 {
 882         phy-supply = <&ldousb_reg>;
 883 };
 884
 885 &vip1 {
 886         status = "okay";
 887 };
 888
 889 &vin1a {
 890         endpoint@0 {
 891                 slave-mode;
 892                 remote-endpoint = <&onboardLI>;
 893         };
 894 };