1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clk/ti-dra7-atl.h>
15 / {
16 model = "TI DRA742";
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
19 memory {
20 device_type = "memory";
21 reg = <0x80000000 0x60000000>; /* 1536 MB */
22 };
24 reserved-memory {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
29 ipu2_cma_pool: ipu2_cma@95800000 {
30 compatible = "shared-dma-pool";
31 reg = <0x95800000 0x3800000>;
32 reusable;
33 status = "okay";
34 };
36 dsp1_cma_pool: dsp1_cma@99000000 {
37 compatible = "shared-dma-pool";
38 reg = <0x99000000 0x4000000>;
39 reusable;
40 status = "okay";
41 };
43 ipu1_cma_pool: ipu1_cma@9d000000 {
44 compatible = "shared-dma-pool";
45 reg = <0x9d000000 0x2000000>;
46 reusable;
47 status = "okay";
48 };
50 dsp2_cma_pool: dsp2_cma@9f000000 {
51 compatible = "shared-dma-pool";
52 reg = <0x9f000000 0x800000>;
53 reusable;
54 status = "okay";
55 };
56 };
58 extcon1: dra7x_usbid_extcon1 {
59 compatible = "linux,extcon-gpio";
60 gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_LOW>;
61 cable-name = "USB-HOST";
62 };
64 extcon2: dra7x_usbid_extcon2 {
65 compatible = "linux,extcon-gpio";
66 gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_LOW>;
67 cable-name = "USB-HOST";
68 };
70 evm_3v3_sd: fixedregulator-sd {
71 compatible = "regulator-fixed";
72 regulator-name = "evm_3v3_sd";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 enable-active-high;
76 gpio = <&pcf_gpio_21 5 0>;
77 };
79 evm_3v3_sw: fixedregulator-evm_3v3_sw {
80 compatible = "regulator-fixed";
81 regulator-name = "evm_3v3_sw";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
84 };
86 aic_dvdd: fixedregulator-aic_dvdd {
87 /* TPS77018DBVT */
88 compatible = "regulator-fixed";
89 regulator-name = "aic_dvdd";
90 vin-supply = <&evm_3v3_sw>;
91 regulator-min-microvolt = <1800000>;
92 regulator-max-microvolt = <1800000>;
93 };
95 vmmcwl_fixed: fixedregulator-mmcwl {
96 compatible = "regulator-fixed";
97 regulator-name = "vmmcwl_fixed";
98 regulator-min-microvolt = <1800000>;
99 regulator-max-microvolt = <1800000>;
100 gpio = <&gpio5 8 0>; /* gpio5_8 */
101 startup-delay-us = <70000>;
102 enable-active-high;
103 };
105 kim {
106 compatible = "kim";
107 nshutdown_gpio = <132>;
108 dev_name = "/dev/ttyO2";
109 flow_cntrl = <1>;
110 baud_rate = <3686400>;
111 };
113 btwilink {
114 compatible = "btwilink";
115 };
117 vtt_fixed: fixedregulator-vtt {
118 compatible = "regulator-fixed";
119 regulator-name = "vtt_fixed";
120 regulator-min-microvolt = <1350000>;
121 regulator-max-microvolt = <1350000>;
122 regulator-always-on;
123 regulator-boot-on;
124 enable-active-high;
125 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
126 };
128 aliases {
129 display0 = &hdmi0;
130 sound0 = &primary_sound;
131 sound1 = &hdmi;
132 };
134 hdmi0: connector@1 {
135 compatible = "hdmi-connector";
136 label = "hdmi";
138 type = "a";
140 port {
141 hdmi_connector_in: endpoint {
142 remote-endpoint = <&tpd12s015_out>;
143 };
144 };
145 };
147 tpd12s015: encoder@1 {
148 compatible = "ti,dra7evm-tpd12s015";
150 pinctrl-names = "default";
151 pinctrl-0 = <&hpd_pin>;
153 gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
154 <&pcf_hdmi 5 0>, /* P5, LS OE */
155 <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
157 ports {
158 #address-cells = <1>;
159 #size-cells = <0>;
161 port@0 {
162 reg = <0>;
164 tpd12s015_in: endpoint@0 {
165 remote-endpoint = <&hdmi_out>;
166 };
167 };
169 port@1 {
170 reg = <1>;
172 tpd12s015_out: endpoint@0 {
173 remote-endpoint = <&hdmi_connector_in>;
174 };
175 };
176 };
177 };
179 primary_sound: primary_sound {
180 compatible = "ti,dra7xx-evm-audio";
181 ti,model = "DRA7xx-EVM";
182 ti,audio-codec = <&tlv320aic3106>;
183 ti,mcasp-controller = <&mcasp3>;
184 ti,codec-clock-rate = <5644800>;
185 clocks = <&atl_clkin2_ck>;
186 clock-names = "mclk";
187 ti,audio-routing =
188 "Headphone Jack", "HPLOUT",
189 "Headphone Jack", "HPROUT",
190 "Line Out", "LLOUT",
191 "Line Out", "RLOUT",
192 "MIC3L", "Mic Jack",
193 "MIC3R", "Mic Jack",
194 "Mic Jack", "Mic Bias",
195 "LINE1L", "Line In",
196 "LINE1R", "Line In";
197 };
198 };
200 &dra7_pmx_core {
201 pinctrl-names = "default";
202 pinctrl-0 = <&vtt_pin>;
204 vtt_pin: pinmux_vtt_pin {
205 pinctrl-single,pins = <
206 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* gpio7_11 */
207 >;
208 };
210 i2c1_pins: pinmux_i2c1_pins {
211 pinctrl-single,pins = <
212 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
213 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
214 >;
215 };
217 i2c2_pins: pinmux_i2c2_pins {
218 pinctrl-single,pins = <
219 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
220 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
221 >;
222 };
224 i2c3_pins: pinmux_i2c3_pins {
225 pinctrl-single,pins = <
226 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
227 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
228 >;
229 };
231 mcspi1_pins: pinmux_mcspi1_pins {
232 pinctrl-single,pins = <
233 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
234 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
235 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
236 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
237 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs1 */
238 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
239 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
240 >;
241 };
243 uart1_pins: pinmux_uart1_pins {
244 pinctrl-single,pins = <
245 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
246 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
247 >;
248 };
250 bt_uart3_pins: pinmux_uart3_pins {
251 pinctrl-single,pins = <
252 0x3c0 (PIN_INPUT_PULLUP | MUX_MODE1) /* spi2_sclk.uart3_rxd */
253 0x3c4 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* spi2_d1.uart3_txd */
254 0x3c8 (PIN_INPUT | MUX_MODE1) /* spi2.d0.uart3_ctsn */
255 0x3cc (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* spi2_cs0.uart3_rtsn */
256 0x2bc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr2.gpio5_4 - BT_EN */
257 >;
258 };
260 qspi1_pins: pinmux_qspi1_pins {
261 pinctrl-single,pins = <
262 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
263 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
264 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
265 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
266 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
267 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
268 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
269 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
270 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
271 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
272 >;
273 };
275 usb1_pins: pinmux_usb1_pins {
276 pinctrl-single,pins = <
277 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
278 >;
279 };
281 usb2_pins: pinmux_usb2_pins {
282 pinctrl-single,pins = <
283 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
284 >;
285 };
287 wlan_pins: pinmux_wlan_pins {
288 pinctrl-single,pins = <
289 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
290 0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
291 0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
292 0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
293 0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
294 0x3fc (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
295 0x2cc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr6.gpio5_8 - WLAN_EN */
296 >;
297 };
299 wlirq_pins: pinmux_wlirq_pins {
300 pinctrl-single,pins = <
301 0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */
302 >;
303 };
305 cpsw_default: cpsw_default {
306 pinctrl-single,pins = <
307 /* Slave 1 */
308 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
309 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
310 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
311 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
312 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
313 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
314 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
315 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
316 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
317 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
318 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
319 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
321 /* Slave 2 */
322 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
323 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
324 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
325 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
326 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
327 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
328 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
329 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
330 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
331 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
332 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
333 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
334 >;
336 };
338 cpsw_sleep: cpsw_sleep {
339 pinctrl-single,pins = <
340 /* Slave 1 */
341 0x250 (PIN_OFF_NONE)
342 0x254 (PIN_OFF_NONE)
343 0x258 (PIN_OFF_NONE)
344 0x25c (PIN_OFF_NONE)
345 0x260 (PIN_OFF_NONE)
346 0x264 (PIN_OFF_NONE)
347 0x268 (PIN_OFF_NONE)
348 0x26c (PIN_OFF_NONE)
349 0x270 (PIN_OFF_NONE)
350 0x274 (PIN_OFF_NONE)
351 0x278 (PIN_OFF_NONE)
352 0x27c (PIN_OFF_NONE)
354 /* Slave 1 */
355 0x198 (PIN_OFF_NONE)
356 0x19c (PIN_OFF_NONE)
357 0x1a0 (PIN_OFF_NONE)
358 0x1a4 (PIN_OFF_NONE)
359 0x1a8 (PIN_OFF_NONE)
360 0x1ac (PIN_OFF_NONE)
361 0x1b0 (PIN_OFF_NONE)
362 0x1b4 (PIN_OFF_NONE)
363 0x1b8 (PIN_OFF_NONE)
364 0x1bc (PIN_OFF_NONE)
365 0x1c0 (PIN_OFF_NONE)
366 0x1c4 (PIN_OFF_NONE)
367 >;
368 };
370 davinci_mdio_default: davinci_mdio_default {
371 pinctrl-single,pins = <
372 /* MDIO */
373 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */
374 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk */
375 >;
376 };
378 davinci_mdio_sleep: davinci_mdio_sleep {
379 pinctrl-single,pins = <
380 0x23c (PIN_OFF_NONE)
381 0x240 (PIN_OFF_NONE)
382 >;
383 };
385 nand_flash_x16: nand_flash_x16 {
386 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
387 * So NAND flash requires following switch settings:
388 * SW5.9 (GPMC_WPN) = LOW
389 * SW5.1 (NAND_BOOTn) = HIGH */
390 pinctrl-single,pins = <
391 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
392 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
393 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
394 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
395 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
396 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
397 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
398 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
399 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
400 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
401 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
402 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
403 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
404 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
405 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
406 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
407 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
408 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
409 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
410 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
411 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
412 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
413 >;
414 };
416 vout1_pins: pinmux_vout1_pins {
417 pinctrl-single,pins = <
418 0x1C8 (PIN_OUTPUT | MUX_MODE0) /* vout1_clk */
419 0x1CC (PIN_OUTPUT | MUX_MODE0) /* vout1_de */
420 0x1D0 (PIN_OUTPUT | MUX_MODE0) /* vout1_fld */
421 0x1D4 (PIN_OUTPUT | MUX_MODE0) /* vout1_hsync */
422 0x1D8 (PIN_OUTPUT | MUX_MODE0) /* vout1_vsync */
423 0x1DC (PIN_OUTPUT | MUX_MODE0) /* vout1_d0 */
424 0x1E0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d1 */
425 0x1E4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d2 */
426 0x1E8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d3 */
427 0x1EC (PIN_OUTPUT | MUX_MODE0) /* vout1_d4 */
428 0x1F0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d5 */
429 0x1F4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d6 */
430 0x1F8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d7 */
431 0x1FC (PIN_OUTPUT | MUX_MODE0) /* vout1_d8 */
432 0x200 (PIN_OUTPUT | MUX_MODE0) /* vout1_d9 */
433 0x204 (PIN_OUTPUT | MUX_MODE0) /* vout1_d10 */
434 0x208 (PIN_OUTPUT | MUX_MODE0) /* vout1_d11 */
435 0x20C (PIN_OUTPUT | MUX_MODE0) /* vout1_d12 */
436 0x210 (PIN_OUTPUT | MUX_MODE0) /* vout1_d13 */
437 0x214 (PIN_OUTPUT | MUX_MODE0) /* vout1_d14 */
438 0x218 (PIN_OUTPUT | MUX_MODE0) /* vout1_d15 */
439 0x21C (PIN_OUTPUT | MUX_MODE0) /* vout1_d16 */
440 0x220 (PIN_OUTPUT | MUX_MODE0) /* vout1_d17 */
441 0x224 (PIN_OUTPUT | MUX_MODE0) /* vout1_d18 */
442 0x228 (PIN_OUTPUT | MUX_MODE0) /* vout1_d19 */
443 0x22C (PIN_OUTPUT | MUX_MODE0) /* vout1_d20 */
444 0x230 (PIN_OUTPUT | MUX_MODE0) /* vout1_d21 */
445 0x234 (PIN_OUTPUT | MUX_MODE0) /* vout1_d22 */
446 0x238 (PIN_OUTPUT | MUX_MODE0) /* vout1_d23 */
447 >;
448 };
450 hpd_pin: pinmux_hpd_pin {
451 pinctrl-single,pins = <
452 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 */
453 >;
454 };
456 tsc_pins: pinmux_tsc_pins {
457 pinctrl-single,pins = <
458 0x420 (PIN_INPUT_PULLUP | MUX_MODE1) /* sys_nirq2 */
459 >;
460 };
462 dcan1_pins_default: dcan1_pins_default {
463 pinctrl-single,pins = <
464 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
465 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
466 >;
467 };
469 dcan1_pins_sleep: dcan1_pins_sleep {
470 pinctrl-single,pins = <
471 0x3d0 (MUX_MODE15) /* dcan1_tx.off */
472 0x418 (MUX_MODE15) /* wakeup0.off */
473 >;
474 };
476 atl_pins: pinmux_atl_pins {
477 pinctrl-single,pins = <
478 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
479 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
480 >;
481 };
483 mcasp3_pins: pinmux_mcasp3_pins {
484 pinctrl-single,pins = <
485 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
486 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
487 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
488 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
489 >;
490 };
492 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
493 pinctrl-single,pins = <
494 0x324 (PIN_OFF_NONE)
495 0x328 (PIN_OFF_NONE)
496 0x32c (PIN_OFF_NONE)
497 0x330 (PIN_OFF_NONE)
498 >;
499 };
500 };
502 &i2c1 {
503 status = "okay";
504 pinctrl-names = "default";
505 pinctrl-0 = <&i2c1_pins>;
506 clock-frequency = <400000>;
508 tps659038: tps659038@58 {
509 compatible = "ti,tps659038";
510 reg = <0x58>;
512 tps659038_pmic {
513 compatible = "ti,tps659038-pmic";
515 regulators {
516 smps123_reg: smps123 {
517 /* VDD_MPU */
518 regulator-name = "smps123";
519 regulator-min-microvolt = < 850000>;
520 regulator-max-microvolt = <1250000>;
521 regulator-always-on;
522 regulator-boot-on;
523 };
525 smps45_reg: smps45 {
526 /* VDD_DSPEVE */
527 regulator-name = "smps45";
528 regulator-min-microvolt = < 850000>;
529 regulator-max-microvolt = <1150000>;
530 regulator-boot-on;
531 };
533 smps6_reg: smps6 {
534 /* VDD_GPU - over VDD_SMPS6 */
535 regulator-name = "smps6";
536 regulator-min-microvolt = <850000>;
537 regulator-max-microvolt = <1250000>;
538 regulator-boot-on;
539 };
541 smps7_reg: smps7 {
542 /* CORE_VDD */
543 regulator-name = "smps7";
544 regulator-min-microvolt = <850000>;
545 regulator-max-microvolt = <1060000>;
546 regulator-always-on;
547 regulator-boot-on;
548 };
550 smps8_reg: smps8 {
551 /* VDD_IVAHD */
552 regulator-name = "smps8";
553 regulator-min-microvolt = < 850000>;
554 regulator-max-microvolt = <1250000>;
555 regulator-boot-on;
556 };
558 smps9_reg: smps9 {
559 /* VDDS1V8 */
560 regulator-name = "smps9";
561 regulator-min-microvolt = <1800000>;
562 regulator-max-microvolt = <1800000>;
563 regulator-always-on;
564 regulator-boot-on;
565 };
567 ldo1_reg: ldo1 {
568 /* LDO1_OUT --> SDIO */
569 regulator-name = "ldo1";
570 regulator-min-microvolt = <1800000>;
571 regulator-max-microvolt = <3300000>;
572 regulator-boot-on;
573 };
575 ldo2_reg: ldo2 {
576 /* VDD_RTCIO */
577 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
578 regulator-name = "ldo2";
579 regulator-min-microvolt = <3300000>;
580 regulator-max-microvolt = <3300000>;
581 regulator-boot-on;
582 };
584 ldo3_reg: ldo3 {
585 /* VDDA_1V8_PHY */
586 regulator-name = "ldo3";
587 regulator-min-microvolt = <1800000>;
588 regulator-max-microvolt = <1800000>;
589 regulator-always-on;
590 regulator-boot-on;
591 };
593 ldo9_reg: ldo9 {
594 /* VDD_RTC */
595 regulator-name = "ldo9";
596 regulator-min-microvolt = <1050000>;
597 regulator-max-microvolt = <1050000>;
598 regulator-boot-on;
599 regulator-always-on;
600 };
602 ldoln_reg: ldoln {
603 /* VDDA_1V8_PLL */
604 regulator-name = "ldoln";
605 regulator-min-microvolt = <1800000>;
606 regulator-max-microvolt = <1800000>;
607 regulator-always-on;
608 regulator-boot-on;
609 };
611 ldousb_reg: ldousb {
612 /* VDDA_3V_USB: VDDA_USBHS33 */
613 regulator-name = "ldousb";
614 regulator-min-microvolt = <3300000>;
615 regulator-max-microvolt = <3300000>;
616 regulator-boot-on;
617 };
618 };
619 };
620 };
622 pcf_lcd: gpio@20 {
623 compatible = "nxp,pcf8575";
624 reg = <0x20>;
625 gpio-controller;
626 #gpio-cells = <2>;
627 };
629 pcf_gpio_21: gpio@21 {
630 compatible = "ti,pcf8575";
631 reg = <0x21>;
632 lines-initial-states = <0x1408>;
633 gpio-controller;
634 #gpio-cells = <2>;
635 interrupt-parent = <&gpio6>;
636 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
637 interrupt-controller;
638 #interrupt-cells = <2>;
639 };
641 mxt244: touchscreen@4a {
642 compatible = "atmel,mXT244";
643 status = "okay";
644 reg = <0x4a>;
645 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
646 pinctrl-0 = <&tsc_pins>;
648 atmel,config = <
649 /* MXT244_GEN_COMMAND(6) */
650 0x00 0x00 0x00 0x00 0x00 0x00
651 /* MXT244_GEN_POWER(7) */
652 0x20 0xff 0x32
653 /* MXT244_GEN_ACQUIRE(8) */
654 0x0a 0x00 0x05 0x00 0x00 0x00 0x09 0x23
655 /* MXT244_TOUCH_MULTI(9) */
656 0x00 0x00 0x00 0x13 0x0b 0x00 0x00 0x00 0x02 0x00
657 0x00 0x01 0x01 0x0e 0x0a 0x0a 0x0a 0x0a 0x00 0x00
658 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
659 0x00
660 /* MXT244_TOUCH_KEYARRAY(15) */
661 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
662 0x00
663 /* MXT244_COMMSCONFIG_T18(2) */
664 0x00 0x00
665 /* MXT244_SPT_GPIOPWM(19) */
666 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
667 0x00 0x00 0x00 0x00 0x00 0x00
668 /* MXT244_PROCI_GRIPFACE(20) */
669 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x28 0x04
670 0x0f 0x0a
671 /* MXT244_PROCG_NOISE(22) */
672 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x23 0x00
673 0x00 0x05 0x0f 0x19 0x23 0x2d 0x03
674 /* MXT244_TOUCH_PROXIMITY(23) */
675 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
676 0x00 0x00 0x00 0x00 0x00
677 /* MXT244_PROCI_ONETOUCH(24) */
678 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
679 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
680 /* MXT244_SPT_SELFTEST(25) */
681 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
682 0x00 0x00 0x00 0x00
683 /* MXT244_PROCI_TWOTOUCH(27) */
684 0x00 0x00 0x00 0x00 0x00 0x00 0x00
685 /* MXT244_SPT_CTECONFIG(28) */
686 0x00 0x00 0x02 0x08 0x10 0x00
687 >;
689 atmel,x_line = <18>;
690 atmel,y_line = <12>;
691 atmel,x_size = <800>;
692 atmel,y_size = <480>;
693 atmel,blen = <0x01>;
694 atmel,threshold = <30>;
695 atmel,voltage = <2800000>;
696 atmel,orient = <0x4>;
697 };
699 tlv320aic3106: tlv320aic3106@18 {
700 compatible = "ti,tlv320aic3106";
701 reg = <0x18>;
702 adc-settle-ms = <40>;
703 ai3x-micbias-vg = <1>; /* 2.0V */
704 status = "okay";
706 /* Regulators */
707 AVDD-supply = <&evm_3v3_sw>;
708 IOVDD-supply = <&evm_3v3_sw>;
709 DRVDD-supply = <&evm_3v3_sw>;
710 DVDD-supply = <&aic_dvdd>;
711 };
712 };
714 &i2c2 {
715 status = "okay";
716 pinctrl-names = "default";
717 pinctrl-0 = <&i2c2_pins>;
718 clock-frequency = <400000>;
720 pcf_hdmi: gpio@26 {
721 compatible = "nxp,pcf8575";
722 reg = <0x26>;
723 lines-initial-states = <0xffeb>;
724 gpio-controller;
725 #gpio-cells = <2>;
726 };
727 };
729 &i2c3 {
730 status = "okay";
731 pinctrl-names = "default";
732 pinctrl-0 = <&i2c3_pins>;
733 clock-frequency = <400000>;
734 };
736 &uart1 {
737 status = "okay";
738 pinctrl-names = "default";
739 pinctrl-0 = <&uart1_pins>;
741 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
742 &dra7_pmx_core 0x3e0>;
743 };
745 &uart3 {
746 status = "okay";
747 pinctrl-names = "default";
748 pinctrl-0 = <&bt_uart3_pins>;
749 gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
750 };
752 &mmc1 {
753 status = "okay";
754 pbias-supply = <&pbias_mmc_reg>;
755 vmmc-supply = <&evm_3v3_sd>;
756 vmmc_aux-supply = <&ldo1_reg>;
757 bus-width = <4>;
758 /*
759 * SDCD signal is not being used here - using the fact that GPIO mode
760 * is always hardwired.
761 */
762 cd-gpios = <&gpio6 27 0>;
763 };
765 &mmc2 {
766 status = "okay";
767 vmmc-supply = <&evm_3v3_sw>;
768 bus-width = <8>;
769 };
771 &mmc4 {
772 status = "okay";
773 vmmc-supply = <&vmmcwl_fixed>;
774 bus-width = <4>;
775 pinctrl-names = "default";
776 pinctrl-0 = <&wlan_pins &wlirq_pins>;
777 cap-power-off-card;
778 keep-power-in-suspend;
779 ti,non-removable;
781 #address-cells = <1>;
782 #size-cells = <0>;
783 wlcore: wlcore@0 {
784 compatible = "ti,wlcore";
785 reg = <2>;
786 interrupt-parent = <&gpio5>;
787 interrupts = <7 IRQ_TYPE_NONE>;
788 };
789 };
791 &cpu0 {
792 cpu0-voltdm = <&voltdm_mpu>;
793 voltage-tolerance = <1>;
794 };
796 &voltdm_mpu {
797 vdd-supply = <&smps123_reg>;
798 };
800 &voltdm_dspeve {
801 vdd-supply = <&smps45_reg>;
802 };
804 &voltdm_gpu {
805 vdd-supply = <&smps6_reg>;
806 };
808 &voltdm_ivahd {
809 vdd-supply = <&smps8_reg>;
810 };
812 &voltdm_core {
813 vdd-supply = <&smps7_reg>;
814 };
816 &qspi {
817 status = "okay";
818 pinctrl-names = "default";
819 pinctrl-0 = <&qspi1_pins>;
821 spi-max-frequency = <48000000>;
822 m25p80@0 {
823 compatible = "s25fl256s1";
824 spi-max-frequency = <48000000>;
825 reg = <0>;
826 spi-tx-bus-width = <1>;
827 spi-rx-bus-width = <4>;
828 spi-cpol;
829 spi-cpha;
830 #address-cells = <1>;
831 #size-cells = <1>;
833 /* MTD partition table.
834 * The ROM checks the first four physical blocks
835 * for a valid file to boot and the flash here is
836 * 64KiB block size.
837 */
838 partition@0 {
839 label = "QSPI.SPL";
840 reg = <0x00000000 0x000010000>;
841 };
842 partition@1 {
843 label = "QSPI.SPL.backup1";
844 reg = <0x00010000 0x00010000>;
845 };
846 partition@2 {
847 label = "QSPI.SPL.backup2";
848 reg = <0x00020000 0x00010000>;
849 };
850 partition@3 {
851 label = "QSPI.SPL.backup3";
852 reg = <0x00030000 0x00010000>;
853 };
854 partition@4 {
855 label = "QSPI.u-boot";
856 reg = <0x00040000 0x00100000>;
857 };
858 partition@5 {
859 label = "QSPI.u-boot-spl-os";
860 reg = <0x00140000 0x00080000>;
861 };
862 partition@6 {
863 label = "QSPI.u-boot-env";
864 reg = <0x001c0000 0x00010000>;
865 };
866 partition@7 {
867 label = "QSPI.u-boot-env.backup1";
868 reg = <0x001d0000 0x0010000>;
869 };
870 partition@8 {
871 label = "QSPI.kernel";
872 reg = <0x001e0000 0x0800000>;
873 };
874 partition@9 {
875 label = "QSPI.file-system";
876 reg = <0x009e0000 0x01620000>;
877 };
878 };
879 };
881 &omap_dwc3_1 {
882 extcon = <&extcon1>;
883 };
885 &omap_dwc3_2 {
886 extcon = <&extcon2>;
887 };
889 &usb1 {
890 dr_mode = "otg";
891 pinctrl-names = "default";
892 pinctrl-0 = <&usb1_pins>;
893 };
895 &usb2 {
896 dr_mode = "host";
897 pinctrl-names = "default";
898 pinctrl-0 = <&usb2_pins>;
899 };
901 &mac {
902 status = "okay";
903 pinctrl-names = "default", "sleep";
904 pinctrl-0 = <&cpsw_default>;
905 pinctrl-1 = <&cpsw_sleep>;
906 dual_emac;
907 };
909 &cpsw_emac0 {
910 phy_id = <&davinci_mdio>, <2>;
911 phy-mode = "rgmii";
912 dual_emac_res_vlan = <1>;
913 };
915 &cpsw_emac1 {
916 phy_id = <&davinci_mdio>, <3>;
917 phy-mode = "rgmii";
918 dual_emac_res_vlan = <2>;
919 };
921 &davinci_mdio {
922 pinctrl-names = "default", "sleep";
923 pinctrl-0 = <&davinci_mdio_default>;
924 pinctrl-1 = <&davinci_mdio_sleep>;
925 };
927 &elm {
928 status = "okay";
929 };
931 &gpmc {
932 status = "disabled";
933 pinctrl-names = "default";
934 pinctrl-0 = <&nand_flash_x16>;
935 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
936 nand@0,0 {
937 reg = <0 0 4>; /* device IO registers */
938 ti,nand-ecc-opt = "bch8";
939 ti,elm-id = <&elm>;
940 nand-bus-width = <16>;
941 gpmc,device-width = <2>;
942 gpmc,sync-clk-ps = <0>;
943 gpmc,cs-on-ns = <0>;
944 gpmc,cs-rd-off-ns = <80>;
945 gpmc,cs-wr-off-ns = <80>;
946 gpmc,adv-on-ns = <0>;
947 gpmc,adv-rd-off-ns = <60>;
948 gpmc,adv-wr-off-ns = <60>;
949 gpmc,we-on-ns = <10>;
950 gpmc,we-off-ns = <50>;
951 gpmc,oe-on-ns = <4>;
952 gpmc,oe-off-ns = <40>;
953 gpmc,access-ns = <40>;
954 gpmc,wr-access-ns = <80>;
955 gpmc,rd-cycle-ns = <80>;
956 gpmc,wr-cycle-ns = <80>;
957 gpmc,bus-turnaround-ns = <0>;
958 gpmc,cycle2cycle-delay-ns = <0>;
959 gpmc,clk-activation-ns = <0>;
960 gpmc,wait-monitoring-ns = <0>;
961 gpmc,wr-data-mux-bus-ns = <0>;
962 /* MTD partition table */
963 /* All SPL-* partitions are sized to minimal length
964 * which can be independently programmable. For
965 * NAND flash this is equal to size of erase-block */
966 #address-cells = <1>;
967 #size-cells = <1>;
968 partition@0 {
969 label = "NAND.SPL";
970 reg = <0x00000000 0x000020000>;
971 };
972 partition@1 {
973 label = "NAND.SPL.backup1";
974 reg = <0x00020000 0x00020000>;
975 };
976 partition@2 {
977 label = "NAND.SPL.backup2";
978 reg = <0x00040000 0x00020000>;
979 };
980 partition@3 {
981 label = "NAND.SPL.backup3";
982 reg = <0x00060000 0x00020000>;
983 };
984 partition@4 {
985 label = "NAND.u-boot-spl-os";
986 reg = <0x00080000 0x00040000>;
987 };
988 partition@5 {
989 label = "NAND.u-boot";
990 reg = <0x000c0000 0x00100000>;
991 };
992 partition@6 {
993 label = "NAND.u-boot-env";
994 reg = <0x001c0000 0x00020000>;
995 };
996 partition@7 {
997 label = "NAND.u-boot-env.backup1";
998 reg = <0x001e0000 0x00020000>;
999 };
1000 partition@8 {
1001 label = "NAND.kernel";
1002 reg = <0x00200000 0x00800000>;
1003 };
1004 partition@9 {
1005 label = "NAND.file-system";
1006 reg = <0x00a00000 0x0f600000>;
1007 };
1008 };
1009 };
1011 &gpio7 {
1012 ti,no-reset-on-init;
1013 ti,no-idle-on-init;
1014 };
1016 &dss {
1017 status = "ok";
1019 vdda_video-supply = <&ldoln_reg>;
1020 };
1022 &hdmi {
1023 status = "ok";
1024 vdda-supply = <&ldo3_reg>;
1026 port {
1027 hdmi_out: endpoint {
1028 remote-endpoint = <&tpd12s015_in>;
1029 };
1030 };
1031 };
1033 &dcan1 {
1034 status = "ok";
1035 pinctrl-names = "default", "sleep";
1036 pinctrl-0 = <&dcan1_pins_default>;
1037 pinctrl-1 = <&dcan1_pins_sleep>;
1038 };
1040 &mailbox5 {
1041 status = "okay";
1042 mbox_ipu1_legacy: mbox_ipu1_legacy {
1043 status = "okay";
1044 };
1045 mbox_dsp1_legacy: mbox_dsp1_legacy {
1046 status = "okay";
1047 };
1048 };
1050 &mailbox6 {
1051 status = "okay";
1052 mbox_ipu2_legacy: mbox_ipu2_legacy {
1053 status = "okay";
1054 };
1055 mbox_dsp2_legacy: mbox_dsp2_legacy {
1056 status = "okay";
1057 };
1058 };
1060 &mmu0_dsp1 {
1061 status = "okay";
1062 };
1064 &mmu1_dsp1 {
1065 status = "okay";
1066 };
1068 &mmu0_dsp2 {
1069 status = "okay";
1070 };
1072 &mmu1_dsp2 {
1073 status = "okay";
1074 };
1076 &mmu_ipu1 {
1077 status = "okay";
1078 };
1080 &mmu_ipu2 {
1081 status = "okay";
1082 };
1084 &ipu2 {
1085 status = "okay";
1086 memory-region = <&ipu2_cma_pool>;
1087 mboxes = <&mailbox6 &mbox_ipu2_legacy>;
1088 timers = <&timer3>;
1089 watchdog-timers = <&timer4>, <&timer9>;
1090 };
1092 &ipu1 {
1093 status = "okay";
1094 memory-region = <&ipu1_cma_pool>;
1095 mboxes = <&mailbox5 &mbox_ipu1_legacy>;
1096 timers = <&timer11>;
1097 };
1099 &dsp1 {
1100 status = "okay";
1101 memory-region = <&dsp1_cma_pool>;
1102 mboxes = <&mailbox5 &mbox_dsp1_legacy>;
1103 timers = <&timer5>;
1104 };
1106 &dsp2 {
1107 status = "okay";
1108 memory-region = <&dsp2_cma_pool>;
1109 mboxes = <&mailbox6 &mbox_dsp2_legacy>;
1110 timers = <&timer6>;
1111 };
1113 &atl {
1114 pinctrl-names = "default";
1115 pinctrl-0 = <&atl_pins>;
1117 status = "okay";
1119 atl2 {
1120 bws = <DRA7_ATL_WS_MCASP2_FSX>;
1121 aws = <DRA7_ATL_WS_MCASP3_FSX>;
1122 };
1123 };
1125 &mcasp3 {
1126 pinctrl-names = "default", "sleep";
1127 pinctrl-0 = <&mcasp3_pins>;
1128 pinctrl-1 = <&mcasp3_sleep_pins>;
1130 fck_parent = "atl_clkin2_ck";
1132 status = "okay";
1134 op-mode = <0>; /* MCASP_IIS_MODE */
1135 tdm-slots = <2>;
1136 /* 4 serializer */
1137 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1138 1 2 0 0
1139 >;
1140 };