arch/arm/boot/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/clk/ti-dra7-atl.h>
  14
  15 / {
  16         model = "TI DRA742";
  17         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  18
  19         memory {
  20                 device_type = "memory";
  21                 reg = <0x80000000 0x60000000>; /* 1536 MB */
  22         };
  23
  24         reserved-memory {
  25                 #address-cells = <1>;
  26                 #size-cells = <1>;
  27                 ranges;
  28
  29                 ipu2_cma_pool: ipu2_cma@95800000 {
  30                         compatible = "shared-dma-pool";
  31                         reg = <0x95800000 0x3800000>;
  32                         reusable;
  33                         status = "okay";
  34                 };
  35
  36                 dsp1_cma_pool: dsp1_cma@99000000 {
  37                         compatible = "shared-dma-pool";
  38                         reg = <0x99000000 0x4000000>;
  39                         reusable;
  40                         status = "okay";
  41                 };
  42
  43                 ipu1_cma_pool: ipu1_cma@9d000000 {
  44                         compatible = "shared-dma-pool";
  45                         reg = <0x9d000000 0x2000000>;
  46                         reusable;
  47                         status = "okay";
  48                 };
  49
  50                 dsp2_cma_pool: dsp2_cma@9f000000 {
  51                         compatible = "shared-dma-pool";
  52                         reg = <0x9f000000 0x800000>;
  53                         reusable;
  54                         status = "okay";
  55                 };
  56
  57                 /* Required by cmem driver used by radio */
  58                 cmem_radio: cmem@95400000 {
  59                         reg = <0x95400000 0x400000>;
  60                         no-map;
  61                         status = "okay";
  62                 };
  63         };
  64
  65         extcon1: dra7x_usbid_extcon1 {
  66                 compatible = "linux,extcon-gpio";
  67                 gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_LOW>;
  68                 cable-name = "USB-HOST";
  69         };
  70
  71         extcon2: dra7x_usbid_extcon2 {
  72                 compatible = "linux,extcon-gpio";
  73                 gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_LOW>;
  74                 cable-name = "USB-HOST";
  75         };
  76
  77         evm_3v3_sd: fixedregulator-sd {
  78                 compatible = "regulator-fixed";
  79                 regulator-name = "evm_3v3_sd";
  80                 regulator-min-microvolt = <3300000>;
  81                 regulator-max-microvolt = <3300000>;
  82                 enable-active-high;
  83                 gpio = <&pcf_gpio_21 5 0>;
  84         };
  85
  86         evm_3v3_sw: fixedregulator-evm_3v3_sw {
  87                 compatible = "regulator-fixed";
  88                 regulator-name = "evm_3v3_sw";
  89                 vin-supply = <&sysen1>;
  90                 regulator-min-microvolt = <3300000>;
  91                 regulator-max-microvolt = <3300000>;
  92         };
  93
  94         aic_dvdd: fixedregulator-aic_dvdd {
  95                 /* TPS77018DBVT */
  96                 compatible = "regulator-fixed";
  97                 regulator-name = "aic_dvdd";
  98                 vin-supply = <&evm_3v3_sw>;
  99                 regulator-min-microvolt = <1800000>;
 100                 regulator-max-microvolt = <1800000>;
 101         };
 102
 103         vmmcwl_fixed: fixedregulator-mmcwl {
 104                 compatible = "regulator-fixed";
 105                 regulator-name = "vmmcwl_fixed";
 106                 regulator-min-microvolt = <1800000>;
 107                 regulator-max-microvolt = <1800000>;
 108                 gpio = <&gpio5 8 0>;    /* gpio5_8 */
 109                 startup-delay-us = <70000>;
 110                 enable-active-high;
 111         };
 112
 113         kim {
 114                 compatible = "kim";
 115                 nshutdown_gpio = <132>;
 116                 dev_name = "/dev/ttyS2";
 117                 flow_cntrl = <1>;
 118                 baud_rate = <3686400>;
 119         };
 120
 121         btwilink {
 122                 compatible = "btwilink";
 123         };
 124
 125         vtt_fixed: fixedregulator-vtt {
 126                 compatible = "regulator-fixed";
 127                 regulator-name = "vtt_fixed";
 128                 regulator-min-microvolt = <1350000>;
 129                 regulator-max-microvolt = <1350000>;
 130                 regulator-always-on;
 131                 regulator-boot-on;
 132                 enable-active-high;
 133                 vin-supply = <&sysen2>;
 134                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
 135         };
 136
 137         aliases {
 138                 display0 = &hdmi0;
 139                 sound0 = &primary_sound;
 140                 sound1 = &hdmi;
 141         };
 142
 143         hdmi0: connector@1 {
 144                 compatible = "hdmi-connector";
 145                 label = "hdmi";
 146
 147                 type = "a";
 148
 149                 port {
 150                         hdmi_connector_in: endpoint {
 151                                 remote-endpoint = <&tpd12s015_out>;
 152                         };
 153                 };
 154         };
 155
 156         tpd12s015: encoder@1 {
 157                 compatible = "ti,dra7evm-tpd12s015";
 158
 159                 gpios = <&pcf_hdmi 4 0>,        /* P4, CT CP HPD */
 160                         <&pcf_hdmi 5 0>,        /* P5, LS OE */
 161                         <&gpio7 12 0>;  /* gpio7_12/sp1_cs2, HPD */
 162
 163                 ports {
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166
 167                         port@0 {
 168                                 reg = <0>;
 169
 170                                 tpd12s015_in: endpoint@0 {
 171                                         remote-endpoint = <&hdmi_out>;
 172                                 };
 173                         };
 174
 175                         port@1 {
 176                                 reg = <1>;
 177
 178                                 tpd12s015_out: endpoint@0 {
 179                                         remote-endpoint = <&hdmi_connector_in>;
 180                                 };
 181                         };
 182                 };
 183         };
 184
 185     ocp {
 186         gpu: gpu@0x56000000 {
 187             gpu0-voltdm = <&voltdm_gpu>;
 188         };
 189     };
 190
 191         primary_sound: primary_sound {
 192                 compatible = "ti,dra7xx-evm-audio";
 193                 ti,model = "DRA7xx-EVM";
 194                 ti,always-on;
 195                 ti,audio-codec = <&tlv320aic3106>;
 196                 ti,mcasp-controller = <&mcasp3>;
 197                 ti,codec-clock-rate = <11289600>;
 198                 clocks = <&atl_clkin2_ck>;
 199                 clock-names = "mclk";
 200                 ti,audio-routing =
 201                         "Headphone Jack",       "HPLOUT",
 202                         "Headphone Jack",       "HPROUT",
 203                         "Line Out",             "LLOUT",
 204                         "Line Out",             "RLOUT",
 205                         "MIC3L",                "Mic Jack",
 206                         "MIC3R",                "Mic Jack",
 207                         "Mic Jack",             "Mic Bias",
 208                         "LINE1L",               "Line In",
 209                         "LINE1R",               "Line In";
 210         };
 211
 212
 213         btwilink_sound: btwilink_sound {
 214                 #sound-dai-cells = <0>;
 215                 compatible = "linux,bt-sco-audio";
 216                 status = "okay";
 217         };
 218
 219         simple_bt_sco_card: bt_sco_card {
 220                 compatible = "simple-audio-card";
 221                 simple-audio-card,name = "DRA7xx-WiLink";
 222                 simple-audio-card,format = "dsp_a";
 223                 simple-audio-card,frame-master = <&btwilink_codec>;
 224                 simple-audio-card,bitclock-master = <&btwilink_codec>;
 225                 simple-audio-card,frame-inversion;
 226
 227                 simple-audio-card,cpu {
 228                         sound-dai = <&mcasp7>;
 229                 };
 230
 231                 btwilink_codec: simple-audio-card,codec {
 232                         sound-dai = <&btwilink_sound>;
 233                 };
 234         };
 235
 236         radio {
 237                 compatible = "ti,dra7xx_radio";
 238                 gpios = <&gpio6 20 0>;
 239         };
 240 };
 241
 242 &dra7_pmx_core {
 243         i2c2_pins: pinmux_i2c2_pins {
 244                 pinctrl-single,pins = <
 245                         0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
 246                         0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
 247                 >;
 248         };
 249
 250         dcan1_pins_default: dcan1_pins_default {
 251                 pinctrl-single,pins = <
 252                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 253                         0x418   (PULL_UP | MUX_MODE1)           /* wakeup0.dcan1_rx */
 254                 >;
 255         };
 256
 257         dcan1_pins_sleep: dcan1_pins_sleep {
 258                 pinctrl-single,pins = <
 259                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
 260                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
 261                 >;
 262         };
 263
 264         mmc1_pins_default: pinmux_mmc1_default_pins {
 265                 pinctrl-single,pins = <
 266                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_clk.clk */
 267                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_cmd.cmd */
 268                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat0.dat0 */
 269                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat1.dat1 */
 270                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat2.dat2 */
 271                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat3.dat3 */
 272                         0x36c (PIN_INPUT | MUX_MODE14)          /* mmc1sdcd.gpio187 */
 273                 >;
 274         };
 275
 276         mmc1_pins_hs: pinmux_mmc1_hs_pins {
 277                 pinctrl-single,pins = <
 278                         0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_clk.clk */
 279                         0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_cmd.cmd */
 280                         0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat0.dat0 */
 281                         0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat1.dat1 */
 282                         0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat2.dat2 */
 283                         0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat3.dat3 */
 284                 >;
 285         };
 286
 287         mmc2_pins_default: mmc2_pins_default {
 288                 pinctrl-single,pins = <
 289                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 290                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 291                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 292                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 293                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 294                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 295                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 296                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 297                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 298                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 299                 >;
 300         };
 301
 302         mmc2_pins_hs: pinmux_mmc2_hs_pins {
 303                 pinctrl-single,pins = <
 304                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 305                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 306                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 307                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 308                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 309                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 310                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 311                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 312                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 313                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 314                 >;
 315         };
 316 };
 317
 318 &i2c1 {
 319         status = "okay";
 320         clock-frequency = <400000>;
 321
 322         tps659038: tps659038@58 {
 323                 compatible = "ti,tps659038";
 324                 reg = <0x58>;
 325
 326                 tps659038_pmic {
 327                         compatible = "ti,tps659038-pmic";
 328
 329                         regulators {
 330                                 smps123_reg: smps123 {
 331                                         /* VDD_MPU */
 332                                         regulator-name = "smps123";
 333                                         regulator-min-microvolt = < 850000>;
 334                                         regulator-max-microvolt = <1250000>;
 335                                         regulator-always-on;
 336                                         regulator-boot-on;
 337                                 };
 338
 339                                 smps45_reg: smps45 {
 340                                         /* VDD_DSPEVE */
 341                                         regulator-name = "smps45";
 342                                         regulator-min-microvolt = < 850000>;
 343                                         regulator-max-microvolt = <1150000>;
 344                                         regulator-boot-on;
 345                                         regulator-always-on;
 346                                 };
 347
 348                                 smps6_reg: smps6 {
 349                                         /* VDD_GPU - over VDD_SMPS6 */
 350                                         regulator-name = "smps6";
 351                                         regulator-min-microvolt = <850000>;
 352                                         regulator-max-microvolt = <1250000>;
 353                                         regulator-boot-on;
 354                                         regulator-always-on;
 355                                 };
 356
 357                                 smps7_reg: smps7 {
 358                                         /* CORE_VDD */
 359                                         regulator-name = "smps7";
 360                                         regulator-min-microvolt = <850000>;
 361                                         regulator-max-microvolt = <1060000>;
 362                                         regulator-always-on;
 363                                         regulator-boot-on;
 364                                 };
 365
 366                                 smps8_reg: smps8 {
 367                                         /* VDD_IVAHD */
 368                                         regulator-name = "smps8";
 369                                         regulator-min-microvolt = < 850000>;
 370                                         regulator-max-microvolt = <1250000>;
 371                                         regulator-boot-on;
 372                                         regulator-always-on;
 373                                 };
 374
 375                                 smps9_reg: smps9 {
 376                                         /* VDDS1V8 */
 377                                         regulator-name = "smps9";
 378                                         regulator-min-microvolt = <1800000>;
 379                                         regulator-max-microvolt = <1800000>;
 380                                         regulator-always-on;
 381                                         regulator-boot-on;
 382                                 };
 383
 384                                 ldo1_reg: ldo1 {
 385                                         /* LDO1_OUT --> SDIO  */
 386                                         regulator-name = "ldo1";
 387                                         regulator-min-microvolt = <1800000>;
 388                                         regulator-max-microvolt = <3300000>;
 389                                         regulator-boot-on;
 390                                         regulator-always-on;
 391                                 };
 392
 393                                 ldo2_reg: ldo2 {
 394                                         /* VDD_RTCIO */
 395                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 396                                         regulator-name = "ldo2";
 397                                         regulator-min-microvolt = <3300000>;
 398                                         regulator-max-microvolt = <3300000>;
 399                                         regulator-boot-on;
 400                                         regulator-always-on;
 401                                 };
 402
 403                                 ldo3_reg: ldo3 {
 404                                         /* VDDA_1V8_PHY */
 405                                         regulator-name = "ldo3";
 406                                         regulator-min-microvolt = <1800000>;
 407                                         regulator-max-microvolt = <1800000>;
 408                                         regulator-always-on;
 409                                         regulator-boot-on;
 410                                 };
 411
 412                                 ldo9_reg: ldo9 {
 413                                         /* VDD_RTC */
 414                                         regulator-name = "ldo9";
 415                                         regulator-min-microvolt = <1050000>;
 416                                         regulator-max-microvolt = <1050000>;
 417                                         regulator-boot-on;
 418                                         regulator-always-on;
 419                                 };
 420
 421                                 ldoln_reg: ldoln {
 422                                         /* VDDA_1V8_PLL */
 423                                         regulator-name = "ldoln";
 424                                         regulator-min-microvolt = <1800000>;
 425                                         regulator-max-microvolt = <1800000>;
 426                                         regulator-always-on;
 427                                         regulator-boot-on;
 428                                 };
 429
 430                                 ldousb_reg: ldousb {
 431                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 432                                         regulator-name = "ldousb";
 433                                         regulator-min-microvolt = <3300000>;
 434                                         regulator-max-microvolt = <3300000>;
 435                                         regulator-boot-on;
 436                                         regulator-always-on;
 437                                 };
 438
 439                                 /* REGEN1 is unused */
 440
 441                                 regen2: regen2 {
 442                                         /* Needed for PMIC internal resources */
 443                                         regulator-name = "regen2";
 444                                         regulator-boot-on;
 445                                         regulator-always-on;
 446                                 };
 447
 448                                 /* REGEN3 is unused */
 449
 450                                 sysen1: sysen1 {
 451                                         /* PMIC_REGEN_3V3 */
 452                                         regulator-name = "sysen1";
 453                                         regulator-boot-on;
 454                                         regulator-always-on;
 455                                 };
 456
 457                                 sysen2: sysen2 {
 458                                         /* PMIC_REGEN_DDR */
 459                                         regulator-name = "sysen2";
 460                                         regulator-boot-on;
 461                                         regulator-always-on;
 462                                 };
 463                         };
 464                 };
 465         };
 466
 467         pcf_lcd: gpio@20 {
 468                 compatible = "nxp,pcf8575";
 469                 reg = <0x20>;
 470                 gpio-controller;
 471                 #gpio-cells = <2>;
 472         };
 473
 474         pcf_gpio_21: gpio@21 {
 475                 compatible = "ti,pcf8575";
 476                 reg = <0x21>;
 477                 lines-initial-states = <0x1408>;
 478                 gpio-controller;
 479                 #gpio-cells = <2>;
 480                 interrupt-parent = <&gpio6>;
 481                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 482                 interrupt-controller;
 483                 #interrupt-cells = <2>;
 484         };
 485
 486         mxt244: touchscreen@4a {
 487                 compatible = "atmel,mXT244";
 488                 status = "okay";
 489                 reg = <0x4a>;
 490                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 491
 492                 atmel,config = <
 493                         /* MXT244_GEN_COMMAND(6) */
 494                         0x00 0x00 0x00 0x00 0x00 0x00
 495                         /* MXT244_GEN_POWER(7) */
 496                         0x20 0xff 0x32
 497                         /* MXT244_GEN_ACQUIRE(8) */
 498                         0x0a 0x00 0x05 0x00 0x00 0x00 0x09 0x23
 499                         /* MXT244_TOUCH_MULTI(9) */
 500                         0x00 0x00 0x00 0x13 0x0b 0x00 0x00 0x00 0x02 0x00
 501                         0x00 0x01 0x01 0x0e 0x0a 0x0a 0x0a 0x0a 0x00 0x00
 502                         0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
 503                         0x00
 504                         /* MXT244_TOUCH_KEYARRAY(15) */
 505                         0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
 506                         0x00
 507                         /* MXT244_COMMSCONFIG_T18(2) */
 508                         0x00 0x00
 509                         /* MXT244_SPT_GPIOPWM(19) */
 510                         0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
 511                         0x00 0x00 0x00 0x00 0x00 0x00
 512                         /* MXT244_PROCI_GRIPFACE(20) */
 513                         0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x28 0x04
 514                         0x0f 0x0a
 515                         /* MXT244_PROCG_NOISE(22) */
 516                         0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x23 0x00
 517                         0x00 0x05 0x0f 0x19 0x23 0x2d 0x03
 518                         /* MXT244_TOUCH_PROXIMITY(23) */
 519                         0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
 520                         0x00 0x00 0x00 0x00 0x00
 521                         /* MXT244_PROCI_ONETOUCH(24) */
 522                         0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
 523                         0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
 524                         /* MXT244_SPT_SELFTEST(25) */
 525                         0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
 526                         0x00 0x00 0x00 0x00
 527                         /* MXT244_PROCI_TWOTOUCH(27) */
 528                         0x00 0x00 0x00 0x00 0x00 0x00 0x00
 529                         /* MXT244_SPT_CTECONFIG(28) */
 530                         0x00 0x00 0x02 0x08 0x10 0x00
 531                 >;
 532
 533                 atmel,x_line = <18>;
 534                 atmel,y_line = <12>;
 535                 atmel,x_size = <800>;
 536                 atmel,y_size = <480>;
 537                 atmel,blen = <0x01>;
 538                 atmel,threshold = <30>;
 539                 atmel,voltage = <2800000>;
 540                 atmel,orient = <0x4>;
 541         };
 542
 543         tlv320aic3106: tlv320aic3106@18 {
 544                 compatible = "ti,tlv320aic3106";
 545                 reg = <0x18>;
 546                 adc-settle-ms = <40>;
 547                 ai3x-micbias-vg = <1>;          /* 2.0V */
 548                 status = "okay";
 549
 550                 /* Regulators */
 551                 AVDD-supply = <&evm_3v3_sw>;
 552                 IOVDD-supply = <&evm_3v3_sw>;
 553                 DRVDD-supply = <&evm_3v3_sw>;
 554                 DVDD-supply = <&aic_dvdd>;
 555         };
 556 };
 557
 558 &i2c2 {
 559         status = "okay";
 560         pinctrl-names = "default";
 561         pinctrl-0 = <&i2c2_pins>;
 562         clock-frequency = <400000>;
 563
 564         pcf_hdmi: gpio@26 {
 565                 compatible = "nxp,pcf8575";
 566                 reg = <0x26>;
 567                 lines-initial-states = <0xffeb>;
 568                 gpio-controller;
 569                 #gpio-cells = <2>;
 570         };
 571
 572         ov10633@37 {
 573                 compatible = "ovti,ov10633";
 574                 reg = <0x37>;
 575
 576                 mux-gpios = <&pcf_hdmi 3        GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
 577                 port {
 578                         onboardLI: endpoint {
 579                                 remote-endpoint = <&vin1a>;
 580                                 hsync-active = <1>;
 581                                 vsync-active = <1>;
 582                                 pclk-sample = <1>;
 583                         };
 584                 };
 585         };
 586 };
 587
 588 &i2c3 {
 589         status = "okay";
 590         clock-frequency = <3400000>;
 591 };
 592
 593 &mcspi1 {
 594         status = "okay";
 595 };
 596
 597 &mcspi2 {
 598         status = "okay";
 599 };
 600
 601 &uart1 {
 602         status = "okay";
 603         interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
 604                                &dra7_pmx_core 0x3e0>;
 605 };
 606
 607 &uart2 {
 608         status = "okay";
 609 };
 610
 611 &uart3 {
 612         status = "okay";
 613         gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
 614 };
 615
 616 &mmc1 {
 617         status = "okay";
 618         pbias-supply = <&pbias_mmc_reg>;
 619         vmmc-supply = <&evm_3v3_sd>;
 620         vmmc_aux-supply = <&ldo1_reg>;
 621         bus-width = <4>;
 622         /*
 623          * SDCD signal is not being used here - using the fact that GPIO mode
 624          * is always hardwired.
 625          */
 626         cd-gpios = <&gpio6 27 0>;
 627         pinctrl-names = "default", "hs";
 628         pinctrl-0 = <&mmc1_pins_default>;
 629         pinctrl-1 = <&mmc1_pins_hs>;
 630 };
 631
 632 &mmc2 {
 633         status = "okay";
 634         vmmc-supply = <&evm_3v3_sw>;
 635         bus-width = <8>;
 636         pinctrl-names = "default", "hs";
 637         pinctrl-0 = <&mmc2_pins_default>;
 638         pinctrl-1 = <&mmc2_pins_hs>;
 639 };
 640
 641 &mmc4 {
 642         status = "okay";
 643         vmmc-supply = <&vmmcwl_fixed>;
 644         bus-width = <4>;
 645         cap-power-off-card;
 646         keep-power-in-suspend;
 647         ti,non-removable;
 648
 649         #address-cells = <1>;
 650         #size-cells = <0>;
 651         wlcore: wlcore@0 {
 652                 compatible = "ti,wlcore";
 653                 reg = <2>;
 654                 interrupt-parent = <&gpio5>;
 655                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 656         };
 657 };
 658
 659 &cpu0 {
 660         cpu0-voltdm = <&voltdm_mpu>;
 661         voltage-tolerance = <1>;
 662 };
 663
 664 &voltdm_mpu {
 665         vdd-supply = <&smps123_reg>;
 666 };
 667
 668 &voltdm_dspeve {
 669         vdd-supply = <&smps45_reg>;
 670 };
 671
 672 &voltdm_gpu {
 673         vdd-supply = <&smps6_reg>;
 674 };
 675
 676 &voltdm_ivahd {
 677         vdd-supply = <&smps8_reg>;
 678 };
 679
 680 &voltdm_core {
 681         vdd-supply = <&smps7_reg>;
 682 };
 683
 684 &qspi {
 685         status = "okay";
 686
 687         spi-max-frequency = <48000000>;
 688         m25p80@0 {
 689                 compatible = "s25fl256s1";
 690                 spi-max-frequency = <48000000>;
 691                 reg = <0>;
 692                 spi-tx-bus-width = <1>;
 693                 spi-rx-bus-width = <4>;
 694                 spi-cpol;
 695                 spi-cpha;
 696                 #address-cells = <1>;
 697                 #size-cells = <1>;
 698
 699                 /* MTD partition table.
 700                  * The ROM checks the first four physical blocks
 701                  * for a valid file to boot and the flash here is
 702                  * 64KiB block size.
 703                  */
 704                 partition@0 {
 705                         label = "QSPI.SPL";
 706                         reg = <0x00000000 0x000010000>;
 707                 };
 708                 partition@1 {
 709                         label = "QSPI.SPL.backup1";
 710                         reg = <0x00010000 0x00010000>;
 711                 };
 712                 partition@2 {
 713                         label = "QSPI.SPL.backup2";
 714                         reg = <0x00020000 0x00010000>;
 715                 };
 716                 partition@3 {
 717                         label = "QSPI.SPL.backup3";
 718                         reg = <0x00030000 0x00010000>;
 719                 };
 720                 partition@4 {
 721                         label = "QSPI.u-boot";
 722                         reg = <0x00040000 0x00100000>;
 723                 };
 724                 partition@5 {
 725                         label = "QSPI.u-boot-spl-os";
 726                         reg = <0x00140000 0x00080000>;
 727                 };
 728                 partition@6 {
 729                         label = "QSPI.u-boot-env";
 730                         reg = <0x001c0000 0x00010000>;
 731                 };
 732                 partition@7 {
 733                         label = "QSPI.u-boot-env.backup1";
 734                         reg = <0x001d0000 0x0010000>;
 735                 };
 736                 partition@8 {
 737                         label = "QSPI.kernel";
 738                         reg = <0x001e0000 0x0800000>;
 739                 };
 740                 partition@9 {
 741                         label = "QSPI.file-system";
 742                         reg = <0x009e0000 0x01620000>;
 743                 };
 744         };
 745 };
 746
 747 &omap_dwc3_1 {
 748         extcon = <&extcon1>;
 749 };
 750
 751 &omap_dwc3_2 {
 752         extcon = <&extcon2>;
 753 };
 754
 755 &usb1 {
 756         dr_mode = "peripheral";
 757 };
 758
 759 &usb2 {
 760         dr_mode = "host";
 761 };
 762
 763 &mac {
 764         status = "okay";
 765         dual_emac;
 766 };
 767
 768 &cpsw_emac0 {
 769         phy_id = <&davinci_mdio>, <2>;
 770         phy-mode = "rgmii";
 771         dual_emac_res_vlan = <1>;
 772 };
 773
 774 &cpsw_emac1 {
 775         phy_id = <&davinci_mdio>, <3>;
 776         phy-mode = "rgmii";
 777         dual_emac_res_vlan = <2>;
 778 };
 779
 780 &elm {
 781         status = "okay";
 782 };
 783
 784 &gpmc {
 785         status = "disabled";
 786         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 787         nand@0,0 {
 788                 reg = <0 0 4>;          /* device IO registers */
 789                 ti,nand-ecc-opt = "bch8";
 790                 ti,elm-id = <&elm>;
 791                 nand-bus-width = <16>;
 792                 gpmc,device-width = <2>;
 793                 gpmc,sync-clk-ps = <0>;
 794                 gpmc,cs-on-ns = <0>;
 795                 gpmc,cs-rd-off-ns = <80>;
 796                 gpmc,cs-wr-off-ns = <80>;
 797                 gpmc,adv-on-ns = <0>;
 798                 gpmc,adv-rd-off-ns = <60>;
 799                 gpmc,adv-wr-off-ns = <60>;
 800                 gpmc,we-on-ns = <10>;
 801                 gpmc,we-off-ns = <50>;
 802                 gpmc,oe-on-ns = <4>;
 803                 gpmc,oe-off-ns = <40>;
 804                 gpmc,access-ns = <40>;
 805                 gpmc,wr-access-ns = <80>;
 806                 gpmc,rd-cycle-ns = <80>;
 807                 gpmc,wr-cycle-ns = <80>;
 808                 gpmc,bus-turnaround-ns = <0>;
 809                 gpmc,cycle2cycle-delay-ns = <0>;
 810                 gpmc,clk-activation-ns = <0>;
 811                 gpmc,wait-monitoring-ns = <0>;
 812                 gpmc,wr-data-mux-bus-ns = <0>;
 813                 /* MTD partition table */
 814                 /* All SPL-* partitions are sized to minimal length
 815                  * which can be independently programmable. For
 816                  * NAND flash this is equal to size of erase-block */
 817                 #address-cells = <1>;
 818                 #size-cells = <1>;
 819                 partition@0 {
 820                         label = "NAND.SPL";
 821                         reg = <0x00000000 0x000020000>;
 822                 };
 823                 partition@1 {
 824                         label = "NAND.SPL.backup1";
 825                         reg = <0x00020000 0x00020000>;
 826                 };
 827                 partition@2 {
 828                         label = "NAND.SPL.backup2";
 829                         reg = <0x00040000 0x00020000>;
 830                 };
 831                 partition@3 {
 832                         label = "NAND.SPL.backup3";
 833                         reg = <0x00060000 0x00020000>;
 834                 };
 835                 partition@4 {
 836                         label = "NAND.u-boot-spl-os";
 837                         reg = <0x00080000 0x00040000>;
 838                 };
 839                 partition@5 {
 840                         label = "NAND.u-boot";
 841                         reg = <0x000c0000 0x00100000>;
 842                 };
 843                 partition@6 {
 844                         label = "NAND.u-boot-env";
 845                         reg = <0x001c0000 0x00020000>;
 846                 };
 847                 partition@7 {
 848                         label = "NAND.u-boot-env.backup1";
 849                         reg = <0x001e0000 0x00020000>;
 850                 };
 851                 partition@8 {
 852                         label = "NAND.kernel";
 853                         reg = <0x00200000 0x00800000>;
 854                 };
 855                 partition@9 {
 856                         label = "NAND.file-system";
 857                         reg = <0x00a00000 0x0f600000>;
 858                 };
 859         };
 860 };
 861
 862 &gpio7 {
 863         ti,no-reset-on-init;
 864         ti,no-idle-on-init;
 865 };
 866
 867 &dss {
 868         status = "ok";
 869
 870         vdda_video-supply = <&ldoln_reg>;
 871 };
 872
 873 &hdmi {
 874         status = "ok";
 875         vdda-supply = <&ldo3_reg>;
 876
 877         port {
 878                 hdmi_out: endpoint {
 879                         remote-endpoint = <&tpd12s015_in>;
 880                 };
 881         };
 882 };
 883
 884 &dcan1 {
 885         status = "ok";
 886         pinctrl-names = "default", "sleep";
 887         pinctrl-0 = <&dcan1_pins_default>;
 888         pinctrl-1 = <&dcan1_pins_sleep>;
 889 };
 890
 891 &mailbox5 {
 892         status = "okay";
 893         mbox_ipu1_legacy: mbox_ipu1_legacy {
 894                 status = "okay";
 895         };
 896         mbox_dsp1_legacy: mbox_dsp1_legacy {
 897                 status = "okay";
 898         };
 899 };
 900
 901 &mailbox6 {
 902         status = "okay";
 903         mbox_ipu2_legacy: mbox_ipu2_legacy {
 904                 status = "okay";
 905         };
 906         mbox_dsp2_legacy: mbox_dsp2_legacy {
 907                 status = "okay";
 908         };
 909 };
 910
 911 &mmu0_dsp1 {
 912         status = "okay";
 913 };
 914
 915 &mmu1_dsp1 {
 916         status = "okay";
 917 };
 918
 919 &mmu0_dsp2 {
 920         status = "okay";
 921 };
 922
 923 &mmu1_dsp2 {
 924         status = "okay";
 925 };
 926
 927 &mmu_ipu1 {
 928         status = "okay";
 929 };
 930
 931 &mmu_ipu2 {
 932         status = "okay";
 933 };
 934
 935 &ipu2 {
 936         status = "okay";
 937         memory-region = <&ipu2_cma_pool>;
 938         mboxes = <&mailbox6 &mbox_ipu2_legacy>;
 939         timers = <&timer3>;
 940         watchdog-timers = <&timer4>, <&timer9>;
 941 };
 942
 943 &ipu1 {
 944         status = "okay";
 945         memory-region = <&ipu1_cma_pool>;
 946         mboxes = <&mailbox5 &mbox_ipu1_legacy>;
 947         timers = <&timer11>;
 948         watchdog-timers = <&timer7>, <&timer8>;
 949 };
 950
 951 &dsp1 {
 952         status = "okay";
 953         memory-region = <&dsp1_cma_pool>;
 954         mboxes = <&mailbox5 &mbox_dsp1_legacy>;
 955         timers = <&timer5>;
 956         watchdog-timers = <&timer10>;
 957 };
 958
 959 &dsp2 {
 960         status = "okay";
 961         memory-region = <&dsp2_cma_pool>;
 962         mboxes = <&mailbox6 &mbox_dsp2_legacy>;
 963         timers = <&timer6>;
 964 };
 965
 966 &atl {
 967         status = "okay";
 968
 969         atl1 {
 970                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 971                 aws = <DRA7_ATL_WS_MCASP6_FSX>;
 972         };
 973
 974         atl2 {
 975                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 976                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 977         };
 978 };
 979
 980 &mcasp2 {
 981         fck_parent = "atl_clkin2_ck";
 982
 983         status = "okay";
 984
 985         op-mode = <0>;  /* MCASP_IIS_MODE */
 986         tdm-slots = <2>;
 987         /* 8 serializer */
 988         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 989                 1 1 1 1 1 1 1 1
 990         >;
 991 };
 992
 993 &mcasp3 {
 994         fck_parent = "atl_clkin2_ck";
 995
 996         status = "okay";
 997
 998         op-mode = <0>;          /* MCASP_IIS_MODE */
 999         tdm-slots = <2>;
1000         /* 4 serializer */
1001         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
1002                 1 2 0 0
1003         >;
1004 };
1005
1006 &mcasp6 {
1007         fck_parent = "atl_clkin1_ck";
1008
1009         status = "okay";
1010
1011         op-mode = <0>;  /* MCASP_IIS_MODE */
1012         tdm-slots = <8>;
1013         /* 4 serializer */
1014         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
1015                 1 2 0 0
1016         >;
1017         tx-num-evt = <8>;
1018         rx-num-evt = <8>;
1019 };
1020
1021 &mcasp7 {
1022         #sound-dai-cells = <0>;
1023
1024         status = "okay";
1025
1026         op-mode = <0>;  /* MCASP_IIS_MODE */
1027         tdm-slots = <4>;
1028         /* 4 serializer */
1029         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
1030                 2 1 0 0
1031         >;
1032         tx-num-evt = <8>;
1033         rx-num-evt = <8>;
1034 };
1035
1036 &usb2_phy1 {
1037         phy-supply = <&ldousb_reg>;
1038 };
1039
1040 &usb2_phy2 {
1041         phy-supply = <&ldousb_reg>;
1042 };
1043
1044 &vip1 {
1045         status = "okay";
1046 };
1047
1048 &vin1a {
1049         endpoint@0 {
1050                 slave-mode;
1051                 remote-endpoint = <&onboardLI>;
1052         };
1053 };