1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clk/ti-dra7-atl.h>
15 / {
16 model = "TI DRA742";
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
19 memory {
20 device_type = "memory";
21 reg = <0x80000000 0x60000000>; /* 1536 MB */
22 };
24 reserved-memory {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
29 ipu2_cma_pool: ipu2_cma@95800000 {
30 compatible = "shared-dma-pool";
31 reg = <0x95800000 0x3800000>;
32 reusable;
33 status = "okay";
34 };
36 dsp1_cma_pool: dsp1_cma@99000000 {
37 compatible = "shared-dma-pool";
38 reg = <0x99000000 0x4000000>;
39 reusable;
40 status = "okay";
41 };
43 ipu1_cma_pool: ipu1_cma@9d000000 {
44 compatible = "shared-dma-pool";
45 reg = <0x9d000000 0x2000000>;
46 reusable;
47 status = "okay";
48 };
50 dsp2_cma_pool: dsp2_cma@9f000000 {
51 compatible = "shared-dma-pool";
52 reg = <0x9f000000 0x800000>;
53 reusable;
54 status = "okay";
55 };
56 };
58 extcon1: dra7x_usbid_extcon1 {
59 compatible = "linux,extcon-gpio";
60 gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_LOW>;
61 cable-name = "USB-HOST";
62 };
64 extcon2: dra7x_usbid_extcon2 {
65 compatible = "linux,extcon-gpio";
66 gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_LOW>;
67 cable-name = "USB-HOST";
68 };
70 evm_3v3_sd: fixedregulator-sd {
71 compatible = "regulator-fixed";
72 regulator-name = "evm_3v3_sd";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 enable-active-high;
76 gpio = <&pcf_gpio_21 5 0>;
77 };
79 evm_3v3_sw: fixedregulator-evm_3v3_sw {
80 compatible = "regulator-fixed";
81 regulator-name = "evm_3v3_sw";
82 vin-supply = <&sysen1>;
83 regulator-min-microvolt = <3300000>;
84 regulator-max-microvolt = <3300000>;
85 };
87 aic_dvdd: fixedregulator-aic_dvdd {
88 /* TPS77018DBVT */
89 compatible = "regulator-fixed";
90 regulator-name = "aic_dvdd";
91 vin-supply = <&evm_3v3_sw>;
92 regulator-min-microvolt = <1800000>;
93 regulator-max-microvolt = <1800000>;
94 };
96 vmmcwl_fixed: fixedregulator-mmcwl {
97 compatible = "regulator-fixed";
98 regulator-name = "vmmcwl_fixed";
99 regulator-min-microvolt = <1800000>;
100 regulator-max-microvolt = <1800000>;
101 gpio = <&gpio5 8 0>; /* gpio5_8 */
102 startup-delay-us = <70000>;
103 enable-active-high;
104 };
106 kim {
107 compatible = "kim";
108 nshutdown_gpio = <132>;
109 dev_name = "/dev/ttyS2";
110 flow_cntrl = <1>;
111 baud_rate = <3686400>;
112 };
114 btwilink {
115 compatible = "btwilink";
116 };
118 vtt_fixed: fixedregulator-vtt {
119 compatible = "regulator-fixed";
120 regulator-name = "vtt_fixed";
121 regulator-min-microvolt = <1350000>;
122 regulator-max-microvolt = <1350000>;
123 regulator-always-on;
124 regulator-boot-on;
125 enable-active-high;
126 vin-supply = <&sysen2>;
127 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
128 };
130 aliases {
131 display0 = &hdmi0;
132 sound0 = &primary_sound;
133 sound1 = &hdmi;
134 };
136 hdmi0: connector@1 {
137 compatible = "hdmi-connector";
138 label = "hdmi";
140 type = "a";
142 port {
143 hdmi_connector_in: endpoint {
144 remote-endpoint = <&tpd12s015_out>;
145 };
146 };
147 };
149 tpd12s015: encoder@1 {
150 compatible = "ti,dra7evm-tpd12s015";
152 pinctrl-names = "default";
153 pinctrl-0 = <&hpd_pin>;
155 gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
156 <&pcf_hdmi 5 0>, /* P5, LS OE */
157 <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
159 ports {
160 #address-cells = <1>;
161 #size-cells = <0>;
163 port@0 {
164 reg = <0>;
166 tpd12s015_in: endpoint@0 {
167 remote-endpoint = <&hdmi_out>;
168 };
169 };
171 port@1 {
172 reg = <1>;
174 tpd12s015_out: endpoint@0 {
175 remote-endpoint = <&hdmi_connector_in>;
176 };
177 };
178 };
179 };
181 primary_sound: primary_sound {
182 compatible = "ti,dra7xx-evm-audio";
183 ti,model = "DRA7xx-EVM";
184 ti,audio-codec = <&tlv320aic3106>;
185 ti,mcasp-controller = <&mcasp3>;
186 ti,codec-clock-rate = <5644800>;
187 clocks = <&atl_clkin2_ck>;
188 clock-names = "mclk";
189 ti,audio-routing =
190 "Headphone Jack", "HPLOUT",
191 "Headphone Jack", "HPROUT",
192 "Line Out", "LLOUT",
193 "Line Out", "RLOUT",
194 "MIC3L", "Mic Jack",
195 "MIC3R", "Mic Jack",
196 "Mic Jack", "Mic Bias",
197 "LINE1L", "Line In",
198 "LINE1R", "Line In";
199 };
200 };
202 &dra7_pmx_core {
203 wlan_pins: pinmux_wlan_pins {
204 pinctrl-single,pins = <
205 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
206 0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
207 0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
208 0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
209 0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
210 0x3fc (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
211 0x2cc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr6.gpio5_8 - WLAN_EN */
212 >;
213 };
215 wlirq_pins: pinmux_wlirq_pins {
216 pinctrl-single,pins = <
217 0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */
218 >;
219 };
221 vout1_pins: pinmux_vout1_pins {
222 pinctrl-single,pins = <
223 0x1C8 (PIN_OUTPUT | MUX_MODE0) /* vout1_clk */
224 0x1CC (PIN_OUTPUT | MUX_MODE0) /* vout1_de */
225 0x1D0 (PIN_OUTPUT | MUX_MODE0) /* vout1_fld */
226 0x1D4 (PIN_OUTPUT | MUX_MODE0) /* vout1_hsync */
227 0x1D8 (PIN_OUTPUT | MUX_MODE0) /* vout1_vsync */
228 0x1DC (PIN_OUTPUT | MUX_MODE0) /* vout1_d0 */
229 0x1E0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d1 */
230 0x1E4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d2 */
231 0x1E8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d3 */
232 0x1EC (PIN_OUTPUT | MUX_MODE0) /* vout1_d4 */
233 0x1F0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d5 */
234 0x1F4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d6 */
235 0x1F8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d7 */
236 0x1FC (PIN_OUTPUT | MUX_MODE0) /* vout1_d8 */
237 0x200 (PIN_OUTPUT | MUX_MODE0) /* vout1_d9 */
238 0x204 (PIN_OUTPUT | MUX_MODE0) /* vout1_d10 */
239 0x208 (PIN_OUTPUT | MUX_MODE0) /* vout1_d11 */
240 0x20C (PIN_OUTPUT | MUX_MODE0) /* vout1_d12 */
241 0x210 (PIN_OUTPUT | MUX_MODE0) /* vout1_d13 */
242 0x214 (PIN_OUTPUT | MUX_MODE0) /* vout1_d14 */
243 0x218 (PIN_OUTPUT | MUX_MODE0) /* vout1_d15 */
244 0x21C (PIN_OUTPUT | MUX_MODE0) /* vout1_d16 */
245 0x220 (PIN_OUTPUT | MUX_MODE0) /* vout1_d17 */
246 0x224 (PIN_OUTPUT | MUX_MODE0) /* vout1_d18 */
247 0x228 (PIN_OUTPUT | MUX_MODE0) /* vout1_d19 */
248 0x22C (PIN_OUTPUT | MUX_MODE0) /* vout1_d20 */
249 0x230 (PIN_OUTPUT | MUX_MODE0) /* vout1_d21 */
250 0x234 (PIN_OUTPUT | MUX_MODE0) /* vout1_d22 */
251 0x238 (PIN_OUTPUT | MUX_MODE0) /* vout1_d23 */
252 >;
253 };
255 hpd_pin: pinmux_hpd_pin {
256 pinctrl-single,pins = <
257 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 */
258 >;
259 };
261 dcan1_pins_default: dcan1_pins_default {
262 pinctrl-single,pins = <
263 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
264 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
265 >;
266 };
268 dcan1_pins_sleep: dcan1_pins_sleep {
269 pinctrl-single,pins = <
270 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
271 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
272 >;
273 };
275 atl_pins: pinmux_atl_pins {
276 pinctrl-single,pins = <
277 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
278 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
279 >;
280 };
282 mcasp3_pins: pinmux_mcasp3_pins {
283 pinctrl-single,pins = <
284 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
285 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
286 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
287 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
288 >;
289 };
291 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
292 pinctrl-single,pins = <
293 0x324 (PIN_OFF_NONE)
294 0x328 (PIN_OFF_NONE)
295 0x32c (PIN_OFF_NONE)
296 0x330 (PIN_OFF_NONE)
297 >;
298 };
300 mmc1_pins_default: pinmux_mmc1_default_pins {
301 pinctrl-single,pins = <
302 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
303 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
304 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
305 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
306 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
307 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
308 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio187 */
309 >;
310 };
312 mmc1_pins_hs: pinmux_mmc1_hs_pins {
313 pinctrl-single,pins = <
314 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
315 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
316 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
317 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
318 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
319 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
320 >;
321 };
323 mmc2_pins_default: mmc2_pins_default {
324 pinctrl-single,pins = <
325 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
326 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
327 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
328 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
329 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
330 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
331 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
332 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
333 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
334 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
335 >;
336 };
338 mmc2_pins_hs: pinmux_mmc2_hs_pins {
339 pinctrl-single,pins = <
340 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
341 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
342 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
343 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
344 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
345 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
346 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
347 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
348 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
349 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
350 >;
351 };
352 };
354 &i2c1 {
355 status = "okay";
356 clock-frequency = <400000>;
358 tps659038: tps659038@58 {
359 compatible = "ti,tps659038";
360 reg = <0x58>;
362 tps659038_pmic {
363 compatible = "ti,tps659038-pmic";
365 regulators {
366 smps123_reg: smps123 {
367 /* VDD_MPU */
368 regulator-name = "smps123";
369 regulator-min-microvolt = < 850000>;
370 regulator-max-microvolt = <1250000>;
371 regulator-always-on;
372 regulator-boot-on;
373 };
375 smps45_reg: smps45 {
376 /* VDD_DSPEVE */
377 regulator-name = "smps45";
378 regulator-min-microvolt = < 850000>;
379 regulator-max-microvolt = <1150000>;
380 regulator-boot-on;
381 regulator-always-on;
382 };
384 smps6_reg: smps6 {
385 /* VDD_GPU - over VDD_SMPS6 */
386 regulator-name = "smps6";
387 regulator-min-microvolt = <850000>;
388 regulator-max-microvolt = <1250000>;
389 regulator-boot-on;
390 regulator-always-on;
391 };
393 smps7_reg: smps7 {
394 /* CORE_VDD */
395 regulator-name = "smps7";
396 regulator-min-microvolt = <850000>;
397 regulator-max-microvolt = <1060000>;
398 regulator-always-on;
399 regulator-boot-on;
400 };
402 smps8_reg: smps8 {
403 /* VDD_IVAHD */
404 regulator-name = "smps8";
405 regulator-min-microvolt = < 850000>;
406 regulator-max-microvolt = <1250000>;
407 regulator-boot-on;
408 regulator-always-on;
409 };
411 smps9_reg: smps9 {
412 /* VDDS1V8 */
413 regulator-name = "smps9";
414 regulator-min-microvolt = <1800000>;
415 regulator-max-microvolt = <1800000>;
416 regulator-always-on;
417 regulator-boot-on;
418 };
420 ldo1_reg: ldo1 {
421 /* LDO1_OUT --> SDIO */
422 regulator-name = "ldo1";
423 regulator-min-microvolt = <1800000>;
424 regulator-max-microvolt = <3300000>;
425 regulator-boot-on;
426 regulator-always-on;
427 };
429 ldo2_reg: ldo2 {
430 /* VDD_RTCIO */
431 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
432 regulator-name = "ldo2";
433 regulator-min-microvolt = <3300000>;
434 regulator-max-microvolt = <3300000>;
435 regulator-boot-on;
436 regulator-always-on;
437 };
439 ldo3_reg: ldo3 {
440 /* VDDA_1V8_PHY */
441 regulator-name = "ldo3";
442 regulator-min-microvolt = <1800000>;
443 regulator-max-microvolt = <1800000>;
444 regulator-always-on;
445 regulator-boot-on;
446 };
448 ldo9_reg: ldo9 {
449 /* VDD_RTC */
450 regulator-name = "ldo9";
451 regulator-min-microvolt = <1050000>;
452 regulator-max-microvolt = <1050000>;
453 regulator-boot-on;
454 regulator-always-on;
455 };
457 ldoln_reg: ldoln {
458 /* VDDA_1V8_PLL */
459 regulator-name = "ldoln";
460 regulator-min-microvolt = <1800000>;
461 regulator-max-microvolt = <1800000>;
462 regulator-always-on;
463 regulator-boot-on;
464 };
466 ldousb_reg: ldousb {
467 /* VDDA_3V_USB: VDDA_USBHS33 */
468 regulator-name = "ldousb";
469 regulator-min-microvolt = <3300000>;
470 regulator-max-microvolt = <3300000>;
471 regulator-boot-on;
472 regulator-always-on;
473 };
475 /* REGEN1 is unused */
477 regen2: regen2 {
478 /* Needed for PMIC internal resources */
479 regulator-name = "regen2";
480 regulator-boot-on;
481 regulator-always-on;
482 };
484 /* REGEN3 is unused */
486 sysen1: sysen1 {
487 /* PMIC_REGEN_3V3 */
488 regulator-name = "sysen1";
489 regulator-boot-on;
490 regulator-always-on;
491 };
493 sysen2: sysen2 {
494 /* PMIC_REGEN_DDR */
495 regulator-name = "sysen2";
496 regulator-boot-on;
497 regulator-always-on;
498 };
499 };
500 };
501 };
503 pcf_lcd: gpio@20 {
504 compatible = "nxp,pcf8575";
505 reg = <0x20>;
506 gpio-controller;
507 #gpio-cells = <2>;
508 };
510 pcf_gpio_21: gpio@21 {
511 compatible = "ti,pcf8575";
512 reg = <0x21>;
513 lines-initial-states = <0x1408>;
514 gpio-controller;
515 #gpio-cells = <2>;
516 interrupt-parent = <&gpio6>;
517 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
518 interrupt-controller;
519 #interrupt-cells = <2>;
520 };
522 mxt244: touchscreen@4a {
523 compatible = "atmel,mXT244";
524 status = "okay";
525 reg = <0x4a>;
526 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
528 atmel,config = <
529 /* MXT244_GEN_COMMAND(6) */
530 0x00 0x00 0x00 0x00 0x00 0x00
531 /* MXT244_GEN_POWER(7) */
532 0x20 0xff 0x32
533 /* MXT244_GEN_ACQUIRE(8) */
534 0x0a 0x00 0x05 0x00 0x00 0x00 0x09 0x23
535 /* MXT244_TOUCH_MULTI(9) */
536 0x00 0x00 0x00 0x13 0x0b 0x00 0x00 0x00 0x02 0x00
537 0x00 0x01 0x01 0x0e 0x0a 0x0a 0x0a 0x0a 0x00 0x00
538 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
539 0x00
540 /* MXT244_TOUCH_KEYARRAY(15) */
541 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
542 0x00
543 /* MXT244_COMMSCONFIG_T18(2) */
544 0x00 0x00
545 /* MXT244_SPT_GPIOPWM(19) */
546 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
547 0x00 0x00 0x00 0x00 0x00 0x00
548 /* MXT244_PROCI_GRIPFACE(20) */
549 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x28 0x04
550 0x0f 0x0a
551 /* MXT244_PROCG_NOISE(22) */
552 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x23 0x00
553 0x00 0x05 0x0f 0x19 0x23 0x2d 0x03
554 /* MXT244_TOUCH_PROXIMITY(23) */
555 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
556 0x00 0x00 0x00 0x00 0x00
557 /* MXT244_PROCI_ONETOUCH(24) */
558 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
559 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
560 /* MXT244_SPT_SELFTEST(25) */
561 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
562 0x00 0x00 0x00 0x00
563 /* MXT244_PROCI_TWOTOUCH(27) */
564 0x00 0x00 0x00 0x00 0x00 0x00 0x00
565 /* MXT244_SPT_CTECONFIG(28) */
566 0x00 0x00 0x02 0x08 0x10 0x00
567 >;
569 atmel,x_line = <18>;
570 atmel,y_line = <12>;
571 atmel,x_size = <800>;
572 atmel,y_size = <480>;
573 atmel,blen = <0x01>;
574 atmel,threshold = <30>;
575 atmel,voltage = <2800000>;
576 atmel,orient = <0x4>;
577 };
579 tlv320aic3106: tlv320aic3106@18 {
580 compatible = "ti,tlv320aic3106";
581 reg = <0x18>;
582 adc-settle-ms = <40>;
583 ai3x-micbias-vg = <1>; /* 2.0V */
584 status = "okay";
586 /* Regulators */
587 AVDD-supply = <&evm_3v3_sw>;
588 IOVDD-supply = <&evm_3v3_sw>;
589 DRVDD-supply = <&evm_3v3_sw>;
590 DVDD-supply = <&aic_dvdd>;
591 };
592 };
594 &i2c2 {
595 status = "okay";
596 clock-frequency = <400000>;
598 pcf_hdmi: gpio@26 {
599 compatible = "nxp,pcf8575";
600 reg = <0x26>;
601 lines-initial-states = <0xffeb>;
602 gpio-controller;
603 #gpio-cells = <2>;
604 };
605 };
607 &i2c3 {
608 status = "okay";
609 clock-frequency = <3400000>;
610 };
612 &mcspi1 {
613 status = "okay";
614 };
616 &mcspi2 {
617 status = "okay";
618 };
620 &uart1 {
621 status = "okay";
622 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
623 &dra7_pmx_core 0x3e0>;
624 };
626 &uart2 {
627 status = "okay";
628 };
630 &uart3 {
631 status = "okay";
632 gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
633 };
635 &mmc1 {
636 status = "okay";
637 pbias-supply = <&pbias_mmc_reg>;
638 vmmc-supply = <&evm_3v3_sd>;
639 vmmc_aux-supply = <&ldo1_reg>;
640 bus-width = <4>;
641 /*
642 * SDCD signal is not being used here - using the fact that GPIO mode
643 * is always hardwired.
644 */
645 cd-gpios = <&gpio6 27 0>;
646 pinctrl-names = "default", "hs";
647 pinctrl-0 = <&mmc1_pins_default>;
648 pinctrl-1 = <&mmc1_pins_hs>;
649 };
651 &mmc2 {
652 status = "okay";
653 vmmc-supply = <&evm_3v3_sw>;
654 bus-width = <8>;
655 pinctrl-names = "default", "hs";
656 pinctrl-0 = <&mmc2_pins_default>;
657 pinctrl-1 = <&mmc2_pins_hs>;
658 };
660 &mmc4 {
661 status = "okay";
662 vmmc-supply = <&vmmcwl_fixed>;
663 bus-width = <4>;
664 pinctrl-names = "default";
665 pinctrl-0 = <&wlan_pins &wlirq_pins>;
666 cap-power-off-card;
667 keep-power-in-suspend;
668 ti,non-removable;
670 #address-cells = <1>;
671 #size-cells = <0>;
672 wlcore: wlcore@0 {
673 compatible = "ti,wlcore";
674 reg = <2>;
675 interrupt-parent = <&gpio5>;
676 interrupts = <7 IRQ_TYPE_NONE>;
677 };
678 };
680 &cpu0 {
681 cpu0-voltdm = <&voltdm_mpu>;
682 voltage-tolerance = <1>;
683 };
685 &voltdm_mpu {
686 vdd-supply = <&smps123_reg>;
687 };
689 &voltdm_dspeve {
690 vdd-supply = <&smps45_reg>;
691 };
693 &voltdm_gpu {
694 vdd-supply = <&smps6_reg>;
695 };
697 &voltdm_ivahd {
698 vdd-supply = <&smps8_reg>;
699 };
701 &voltdm_core {
702 vdd-supply = <&smps7_reg>;
703 };
705 &qspi {
706 status = "okay";
708 spi-max-frequency = <48000000>;
709 m25p80@0 {
710 compatible = "s25fl256s1";
711 spi-max-frequency = <48000000>;
712 reg = <0>;
713 spi-tx-bus-width = <1>;
714 spi-rx-bus-width = <4>;
715 spi-cpol;
716 spi-cpha;
717 #address-cells = <1>;
718 #size-cells = <1>;
720 /* MTD partition table.
721 * The ROM checks the first four physical blocks
722 * for a valid file to boot and the flash here is
723 * 64KiB block size.
724 */
725 partition@0 {
726 label = "QSPI.SPL";
727 reg = <0x00000000 0x000010000>;
728 };
729 partition@1 {
730 label = "QSPI.SPL.backup1";
731 reg = <0x00010000 0x00010000>;
732 };
733 partition@2 {
734 label = "QSPI.SPL.backup2";
735 reg = <0x00020000 0x00010000>;
736 };
737 partition@3 {
738 label = "QSPI.SPL.backup3";
739 reg = <0x00030000 0x00010000>;
740 };
741 partition@4 {
742 label = "QSPI.u-boot";
743 reg = <0x00040000 0x00100000>;
744 };
745 partition@5 {
746 label = "QSPI.u-boot-spl-os";
747 reg = <0x00140000 0x00080000>;
748 };
749 partition@6 {
750 label = "QSPI.u-boot-env";
751 reg = <0x001c0000 0x00010000>;
752 };
753 partition@7 {
754 label = "QSPI.u-boot-env.backup1";
755 reg = <0x001d0000 0x0010000>;
756 };
757 partition@8 {
758 label = "QSPI.kernel";
759 reg = <0x001e0000 0x0800000>;
760 };
761 partition@9 {
762 label = "QSPI.file-system";
763 reg = <0x009e0000 0x01620000>;
764 };
765 };
766 };
768 &omap_dwc3_1 {
769 extcon = <&extcon1>;
770 };
772 &omap_dwc3_2 {
773 extcon = <&extcon2>;
774 };
776 &usb1 {
777 dr_mode = "peripheral";
778 };
780 &usb2 {
781 dr_mode = "host";
782 };
784 &mac {
785 status = "okay";
786 dual_emac;
787 };
789 &cpsw_emac0 {
790 phy_id = <&davinci_mdio>, <2>;
791 phy-mode = "rgmii";
792 dual_emac_res_vlan = <1>;
793 };
795 &cpsw_emac1 {
796 phy_id = <&davinci_mdio>, <3>;
797 phy-mode = "rgmii";
798 dual_emac_res_vlan = <2>;
799 };
801 &elm {
802 status = "okay";
803 };
805 &gpmc {
806 status = "disabled";
807 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
808 nand@0,0 {
809 reg = <0 0 4>; /* device IO registers */
810 ti,nand-ecc-opt = "bch8";
811 ti,elm-id = <&elm>;
812 nand-bus-width = <16>;
813 gpmc,device-width = <2>;
814 gpmc,sync-clk-ps = <0>;
815 gpmc,cs-on-ns = <0>;
816 gpmc,cs-rd-off-ns = <80>;
817 gpmc,cs-wr-off-ns = <80>;
818 gpmc,adv-on-ns = <0>;
819 gpmc,adv-rd-off-ns = <60>;
820 gpmc,adv-wr-off-ns = <60>;
821 gpmc,we-on-ns = <10>;
822 gpmc,we-off-ns = <50>;
823 gpmc,oe-on-ns = <4>;
824 gpmc,oe-off-ns = <40>;
825 gpmc,access-ns = <40>;
826 gpmc,wr-access-ns = <80>;
827 gpmc,rd-cycle-ns = <80>;
828 gpmc,wr-cycle-ns = <80>;
829 gpmc,bus-turnaround-ns = <0>;
830 gpmc,cycle2cycle-delay-ns = <0>;
831 gpmc,clk-activation-ns = <0>;
832 gpmc,wait-monitoring-ns = <0>;
833 gpmc,wr-data-mux-bus-ns = <0>;
834 /* MTD partition table */
835 /* All SPL-* partitions are sized to minimal length
836 * which can be independently programmable. For
837 * NAND flash this is equal to size of erase-block */
838 #address-cells = <1>;
839 #size-cells = <1>;
840 partition@0 {
841 label = "NAND.SPL";
842 reg = <0x00000000 0x000020000>;
843 };
844 partition@1 {
845 label = "NAND.SPL.backup1";
846 reg = <0x00020000 0x00020000>;
847 };
848 partition@2 {
849 label = "NAND.SPL.backup2";
850 reg = <0x00040000 0x00020000>;
851 };
852 partition@3 {
853 label = "NAND.SPL.backup3";
854 reg = <0x00060000 0x00020000>;
855 };
856 partition@4 {
857 label = "NAND.u-boot-spl-os";
858 reg = <0x00080000 0x00040000>;
859 };
860 partition@5 {
861 label = "NAND.u-boot";
862 reg = <0x000c0000 0x00100000>;
863 };
864 partition@6 {
865 label = "NAND.u-boot-env";
866 reg = <0x001c0000 0x00020000>;
867 };
868 partition@7 {
869 label = "NAND.u-boot-env.backup1";
870 reg = <0x001e0000 0x00020000>;
871 };
872 partition@8 {
873 label = "NAND.kernel";
874 reg = <0x00200000 0x00800000>;
875 };
876 partition@9 {
877 label = "NAND.file-system";
878 reg = <0x00a00000 0x0f600000>;
879 };
880 };
881 };
883 &gpio7 {
884 ti,no-reset-on-init;
885 ti,no-idle-on-init;
886 };
888 &dss {
889 status = "ok";
891 vdda_video-supply = <&ldoln_reg>;
892 };
894 &hdmi {
895 status = "ok";
896 vdda-supply = <&ldo3_reg>;
898 port {
899 hdmi_out: endpoint {
900 remote-endpoint = <&tpd12s015_in>;
901 };
902 };
903 };
905 &dcan1 {
906 status = "ok";
907 pinctrl-names = "default", "sleep";
908 pinctrl-0 = <&dcan1_pins_default>;
909 pinctrl-1 = <&dcan1_pins_sleep>;
910 };
912 &mailbox5 {
913 status = "okay";
914 mbox_ipu1_legacy: mbox_ipu1_legacy {
915 status = "okay";
916 };
917 mbox_dsp1_legacy: mbox_dsp1_legacy {
918 status = "okay";
919 };
920 };
922 &mailbox6 {
923 status = "okay";
924 mbox_ipu2_legacy: mbox_ipu2_legacy {
925 status = "okay";
926 };
927 mbox_dsp2_legacy: mbox_dsp2_legacy {
928 status = "okay";
929 };
930 };
932 &mmu0_dsp1 {
933 status = "okay";
934 };
936 &mmu1_dsp1 {
937 status = "okay";
938 };
940 &mmu0_dsp2 {
941 status = "okay";
942 };
944 &mmu1_dsp2 {
945 status = "okay";
946 };
948 &mmu_ipu1 {
949 status = "okay";
950 };
952 &mmu_ipu2 {
953 status = "okay";
954 };
956 &ipu2 {
957 status = "okay";
958 memory-region = <&ipu2_cma_pool>;
959 mboxes = <&mailbox6 &mbox_ipu2_legacy>;
960 timers = <&timer3>;
961 watchdog-timers = <&timer4>, <&timer9>;
962 };
964 &ipu1 {
965 status = "okay";
966 memory-region = <&ipu1_cma_pool>;
967 mboxes = <&mailbox5 &mbox_ipu1_legacy>;
968 timers = <&timer11>;
969 };
971 &dsp1 {
972 status = "okay";
973 memory-region = <&dsp1_cma_pool>;
974 mboxes = <&mailbox5 &mbox_dsp1_legacy>;
975 timers = <&timer5>;
976 };
978 &dsp2 {
979 status = "okay";
980 memory-region = <&dsp2_cma_pool>;
981 mboxes = <&mailbox6 &mbox_dsp2_legacy>;
982 timers = <&timer6>;
983 };
985 &atl {
986 pinctrl-names = "default";
987 pinctrl-0 = <&atl_pins>;
989 status = "okay";
991 atl2 {
992 bws = <DRA7_ATL_WS_MCASP2_FSX>;
993 aws = <DRA7_ATL_WS_MCASP3_FSX>;
994 };
995 };
997 &mcasp3 {
998 pinctrl-names = "default", "sleep";
999 pinctrl-0 = <&mcasp3_pins>;
1000 pinctrl-1 = <&mcasp3_sleep_pins>;
1002 fck_parent = "atl_clkin2_ck";
1004 status = "okay";
1006 op-mode = <0>; /* MCASP_IIS_MODE */
1007 tdm-slots = <2>;
1008 /* 4 serializer */
1009 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1010 1 2 0 0
1011 >;
1012 };
1014 &usb2_phy1 {
1015 phy-supply = <&ldousb_reg>;
1016 };
1018 &usb2_phy2 {
1019 phy-supply = <&ldousb_reg>;
1020 };