1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clk/ti-dra7-atl.h>
15 / {
16 model = "TI DRA742";
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
19 memory {
20 device_type = "memory";
21 reg = <0x80000000 0x60000000>; /* 1536 MB */
22 };
24 reserved-memory {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
29 ipu2_cma_pool: ipu2_cma@95800000 {
30 compatible = "shared-dma-pool";
31 reg = <0x95800000 0x3800000>;
32 reusable;
33 status = "okay";
34 };
36 dsp1_cma_pool: dsp1_cma@99000000 {
37 compatible = "shared-dma-pool";
38 reg = <0x99000000 0x4000000>;
39 reusable;
40 status = "okay";
41 };
43 ipu1_cma_pool: ipu1_cma@9d000000 {
44 compatible = "shared-dma-pool";
45 reg = <0x9d000000 0x2000000>;
46 reusable;
47 status = "okay";
48 };
50 dsp2_cma_pool: dsp2_cma@9f000000 {
51 compatible = "shared-dma-pool";
52 reg = <0x9f000000 0x800000>;
53 reusable;
54 status = "okay";
55 };
56 };
58 extcon_usb1: extcon_usb1 {
59 compatible = "linux,extcon-usb-gpio";
60 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
61 };
63 extcon_usb2: extcon_usb2 {
64 compatible = "linux,extcon-usb-gpio";
65 id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
66 };
68 evm_3v3_sd: fixedregulator-sd {
69 compatible = "regulator-fixed";
70 regulator-name = "evm_3v3_sd";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 enable-active-high;
74 gpio = <&pcf_gpio_21 5 0>;
75 };
77 evm_3v3_sw: fixedregulator-evm_3v3_sw {
78 compatible = "regulator-fixed";
79 regulator-name = "evm_3v3_sw";
80 vin-supply = <&sysen1>;
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 };
85 aic_dvdd: fixedregulator-aic_dvdd {
86 /* TPS77018DBVT */
87 compatible = "regulator-fixed";
88 regulator-name = "aic_dvdd";
89 vin-supply = <&evm_3v3_sw>;
90 regulator-min-microvolt = <1800000>;
91 regulator-max-microvolt = <1800000>;
92 };
94 vmmcwl_fixed: fixedregulator-mmcwl {
95 compatible = "regulator-fixed";
96 regulator-name = "vmmcwl_fixed";
97 regulator-min-microvolt = <1800000>;
98 regulator-max-microvolt = <1800000>;
99 gpio = <&gpio5 8 0>; /* gpio5_8 */
100 startup-delay-us = <70000>;
101 enable-active-high;
102 };
104 kim {
105 compatible = "kim";
106 nshutdown_gpio = <132>;
107 dev_name = "/dev/ttyS2";
108 flow_cntrl = <1>;
109 baud_rate = <3686400>;
110 };
112 btwilink {
113 compatible = "btwilink";
114 };
116 vtt_fixed: fixedregulator-vtt {
117 compatible = "regulator-fixed";
118 regulator-name = "vtt_fixed";
119 regulator-min-microvolt = <1350000>;
120 regulator-max-microvolt = <1350000>;
121 regulator-always-on;
122 regulator-boot-on;
123 enable-active-high;
124 vin-supply = <&sysen2>;
125 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
126 };
128 aliases {
129 display0 = &hdmi0;
130 sound0 = &primary_sound;
131 sound1 = &hdmi;
132 };
134 hdmi0: connector@1 {
135 compatible = "hdmi-connector";
136 label = "hdmi";
138 type = "a";
140 port {
141 hdmi_connector_in: endpoint {
142 remote-endpoint = <&tpd12s015_out>;
143 };
144 };
145 };
147 tpd12s015: encoder@1 {
148 compatible = "ti,dra7evm-tpd12s015";
150 gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
151 <&pcf_hdmi 5 0>, /* P5, LS OE */
152 <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
154 ports {
155 #address-cells = <1>;
156 #size-cells = <0>;
158 port@0 {
159 reg = <0>;
161 tpd12s015_in: endpoint@0 {
162 remote-endpoint = <&hdmi_out>;
163 };
164 };
166 port@1 {
167 reg = <1>;
169 tpd12s015_out: endpoint@0 {
170 remote-endpoint = <&hdmi_connector_in>;
171 };
172 };
173 };
174 };
176 primary_sound: primary_sound {
177 compatible = "ti,dra7xx-evm-audio";
178 ti,model = "DRA7xx-EVM";
179 ti,audio-codec = <&tlv320aic3106>;
180 ti,mcasp-controller = <&mcasp3>;
181 ti,codec-clock-rate = <5644800>;
182 clocks = <&atl_clkin2_ck>;
183 clock-names = "mclk";
184 ti,audio-routing =
185 "Headphone Jack", "HPLOUT",
186 "Headphone Jack", "HPROUT",
187 "Line Out", "LLOUT",
188 "Line Out", "RLOUT",
189 "MIC3L", "Mic Jack",
190 "MIC3R", "Mic Jack",
191 "Mic Jack", "Mic Bias",
192 "LINE1L", "Line In",
193 "LINE1R", "Line In";
194 };
195 };
197 &dra7_pmx_core {
198 dcan1_pins_default: dcan1_pins_default {
199 pinctrl-single,pins = <
200 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
201 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
202 >;
203 };
205 dcan1_pins_sleep: dcan1_pins_sleep {
206 pinctrl-single,pins = <
207 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
208 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
209 >;
210 };
212 mmc1_pins_default: pinmux_mmc1_default_pins {
213 pinctrl-single,pins = <
214 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
215 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
216 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
217 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
218 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
219 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
220 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio187 */
221 >;
222 };
224 mmc1_pins_hs: pinmux_mmc1_hs_pins {
225 pinctrl-single,pins = <
226 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
227 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
228 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
229 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
230 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
231 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
232 >;
233 };
235 mmc2_pins_default: mmc2_pins_default {
236 pinctrl-single,pins = <
237 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
238 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
239 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
240 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
241 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
242 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
243 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
244 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
245 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
246 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
247 >;
248 };
250 mmc2_pins_hs: pinmux_mmc2_hs_pins {
251 pinctrl-single,pins = <
252 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
253 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
254 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
255 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
256 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
257 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
258 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
259 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
260 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
261 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
262 >;
263 };
264 };
266 &i2c1 {
267 status = "okay";
268 clock-frequency = <400000>;
270 tps659038: tps659038@58 {
271 compatible = "ti,tps659038";
272 reg = <0x58>;
274 tps659038_pmic {
275 compatible = "ti,tps659038-pmic";
277 regulators {
278 smps123_reg: smps123 {
279 /* VDD_MPU */
280 regulator-name = "smps123";
281 regulator-min-microvolt = < 850000>;
282 regulator-max-microvolt = <1250000>;
283 regulator-always-on;
284 regulator-boot-on;
285 };
287 smps45_reg: smps45 {
288 /* VDD_DSPEVE */
289 regulator-name = "smps45";
290 regulator-min-microvolt = < 850000>;
291 regulator-max-microvolt = <1150000>;
292 regulator-boot-on;
293 regulator-always-on;
294 };
296 smps6_reg: smps6 {
297 /* VDD_GPU - over VDD_SMPS6 */
298 regulator-name = "smps6";
299 regulator-min-microvolt = <850000>;
300 regulator-max-microvolt = <1250000>;
301 regulator-boot-on;
302 regulator-always-on;
303 };
305 smps7_reg: smps7 {
306 /* CORE_VDD */
307 regulator-name = "smps7";
308 regulator-min-microvolt = <850000>;
309 regulator-max-microvolt = <1060000>;
310 regulator-always-on;
311 regulator-boot-on;
312 };
314 smps8_reg: smps8 {
315 /* VDD_IVAHD */
316 regulator-name = "smps8";
317 regulator-min-microvolt = < 850000>;
318 regulator-max-microvolt = <1250000>;
319 regulator-boot-on;
320 regulator-always-on;
321 };
323 smps9_reg: smps9 {
324 /* VDDS1V8 */
325 regulator-name = "smps9";
326 regulator-min-microvolt = <1800000>;
327 regulator-max-microvolt = <1800000>;
328 regulator-always-on;
329 regulator-boot-on;
330 };
332 ldo1_reg: ldo1 {
333 /* LDO1_OUT --> SDIO */
334 regulator-name = "ldo1";
335 regulator-min-microvolt = <1800000>;
336 regulator-max-microvolt = <3300000>;
337 regulator-boot-on;
338 regulator-always-on;
339 };
341 ldo2_reg: ldo2 {
342 /* VDD_RTCIO */
343 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
344 regulator-name = "ldo2";
345 regulator-min-microvolt = <3300000>;
346 regulator-max-microvolt = <3300000>;
347 regulator-boot-on;
348 regulator-always-on;
349 };
351 ldo3_reg: ldo3 {
352 /* VDDA_1V8_PHY */
353 regulator-name = "ldo3";
354 regulator-min-microvolt = <1800000>;
355 regulator-max-microvolt = <1800000>;
356 regulator-always-on;
357 regulator-boot-on;
358 };
360 ldo9_reg: ldo9 {
361 /* VDD_RTC */
362 regulator-name = "ldo9";
363 regulator-min-microvolt = <1050000>;
364 regulator-max-microvolt = <1050000>;
365 regulator-boot-on;
366 regulator-always-on;
367 };
369 ldoln_reg: ldoln {
370 /* VDDA_1V8_PLL */
371 regulator-name = "ldoln";
372 regulator-min-microvolt = <1800000>;
373 regulator-max-microvolt = <1800000>;
374 regulator-always-on;
375 regulator-boot-on;
376 };
378 ldousb_reg: ldousb {
379 /* VDDA_3V_USB: VDDA_USBHS33 */
380 regulator-name = "ldousb";
381 regulator-min-microvolt = <3300000>;
382 regulator-max-microvolt = <3300000>;
383 regulator-boot-on;
384 regulator-always-on;
385 };
387 /* REGEN1 is unused */
389 regen2: regen2 {
390 /* Needed for PMIC internal resources */
391 regulator-name = "regen2";
392 regulator-boot-on;
393 regulator-always-on;
394 };
396 /* REGEN3 is unused */
398 sysen1: sysen1 {
399 /* PMIC_REGEN_3V3 */
400 regulator-name = "sysen1";
401 regulator-boot-on;
402 regulator-always-on;
403 };
405 sysen2: sysen2 {
406 /* PMIC_REGEN_DDR */
407 regulator-name = "sysen2";
408 regulator-boot-on;
409 regulator-always-on;
410 };
411 };
412 };
413 };
415 pcf_lcd: gpio@20 {
416 compatible = "nxp,pcf8575";
417 reg = <0x20>;
418 gpio-controller;
419 #gpio-cells = <2>;
420 };
422 pcf_gpio_21: gpio@21 {
423 compatible = "nxp,pcf8575";
424 reg = <0x21>;
425 lines-initial-states = <0x1408>;
426 gpio-controller;
427 #gpio-cells = <2>;
428 interrupt-parent = <&gpio6>;
429 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 };
434 tlv320aic3106: tlv320aic3106@18 {
435 compatible = "ti,tlv320aic3106";
436 reg = <0x18>;
437 adc-settle-ms = <40>;
438 ai3x-micbias-vg = <1>; /* 2.0V */
439 status = "okay";
441 /* Regulators */
442 AVDD-supply = <&evm_3v3_sw>;
443 IOVDD-supply = <&evm_3v3_sw>;
444 DRVDD-supply = <&evm_3v3_sw>;
445 DVDD-supply = <&aic_dvdd>;
446 };
447 };
449 &i2c2 {
450 status = "okay";
451 clock-frequency = <400000>;
453 pcf_hdmi: gpio@26 {
454 compatible = "nxp,pcf8575";
455 reg = <0x26>;
456 lines-initial-states = <0xffeb>;
457 gpio-controller;
458 #gpio-cells = <2>;
459 };
461 ov10633@37 {
462 compatible = "ovti,ov10633";
463 reg = <0x37>;
465 mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
466 port {
467 onboardLI: endpoint {
468 remote-endpoint = <&vin1a>;
469 hsync-active = <1>;
470 vsync-active = <1>;
471 pclk-sample = <1>;
472 };
473 };
474 };
475 };
477 &i2c3 {
478 status = "okay";
479 clock-frequency = <3400000>;
480 };
482 &mcspi1 {
483 status = "okay";
484 };
486 &mcspi2 {
487 status = "okay";
488 };
490 &uart1 {
491 status = "okay";
492 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
493 &dra7_pmx_core 0x3e0>;
494 };
496 &uart2 {
497 status = "okay";
498 };
500 &uart3 {
501 status = "okay";
502 gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
503 };
505 &mmc1 {
506 status = "okay";
507 pbias-supply = <&pbias_mmc_reg>;
508 vmmc-supply = <&evm_3v3_sd>;
509 vmmc_aux-supply = <&ldo1_reg>;
510 bus-width = <4>;
511 /*
512 * SDCD signal is not being used here - using the fact that GPIO mode
513 * is always hardwired.
514 */
515 cd-gpios = <&gpio6 27 0>;
516 pinctrl-names = "default", "hs";
517 pinctrl-0 = <&mmc1_pins_default>;
518 pinctrl-1 = <&mmc1_pins_hs>;
519 };
521 &mmc2 {
522 status = "okay";
523 vmmc-supply = <&evm_3v3_sw>;
524 bus-width = <8>;
525 pinctrl-names = "default", "hs";
526 pinctrl-0 = <&mmc2_pins_default>;
527 pinctrl-1 = <&mmc2_pins_hs>;
528 };
530 &mmc4 {
531 status = "okay";
532 vmmc-supply = <&vmmcwl_fixed>;
533 bus-width = <4>;
534 cap-power-off-card;
535 keep-power-in-suspend;
536 ti,non-removable;
538 #address-cells = <1>;
539 #size-cells = <0>;
540 wlcore: wlcore@0 {
541 compatible = "ti,wlcore";
542 reg = <2>;
543 interrupt-parent = <&gpio5>;
544 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
545 };
546 };
548 &cpu0 {
549 cpu0-voltdm = <&voltdm_mpu>;
550 voltage-tolerance = <1>;
551 };
553 &voltdm_mpu {
554 vdd-supply = <&smps123_reg>;
555 };
557 &voltdm_dspeve {
558 vdd-supply = <&smps45_reg>;
559 };
561 &voltdm_gpu {
562 vdd-supply = <&smps6_reg>;
563 };
565 &voltdm_ivahd {
566 vdd-supply = <&smps8_reg>;
567 };
569 &voltdm_core {
570 vdd-supply = <&smps7_reg>;
571 };
573 &qspi {
574 status = "okay";
576 spi-max-frequency = <48000000>;
577 m25p80@0 {
578 compatible = "s25fl256s1";
579 spi-max-frequency = <48000000>;
580 reg = <0>;
581 spi-tx-bus-width = <1>;
582 spi-rx-bus-width = <4>;
583 spi-cpol;
584 spi-cpha;
585 #address-cells = <1>;
586 #size-cells = <1>;
588 /* MTD partition table.
589 * The ROM checks the first four physical blocks
590 * for a valid file to boot and the flash here is
591 * 64KiB block size.
592 */
593 partition@0 {
594 label = "QSPI.SPL";
595 reg = <0x00000000 0x000010000>;
596 };
597 partition@1 {
598 label = "QSPI.SPL.backup1";
599 reg = <0x00010000 0x00010000>;
600 };
601 partition@2 {
602 label = "QSPI.SPL.backup2";
603 reg = <0x00020000 0x00010000>;
604 };
605 partition@3 {
606 label = "QSPI.SPL.backup3";
607 reg = <0x00030000 0x00010000>;
608 };
609 partition@4 {
610 label = "QSPI.u-boot";
611 reg = <0x00040000 0x00100000>;
612 };
613 partition@5 {
614 label = "QSPI.u-boot-spl-os";
615 reg = <0x00140000 0x00080000>;
616 };
617 partition@6 {
618 label = "QSPI.u-boot-env";
619 reg = <0x001c0000 0x00010000>;
620 };
621 partition@7 {
622 label = "QSPI.u-boot-env.backup1";
623 reg = <0x001d0000 0x0010000>;
624 };
625 partition@8 {
626 label = "QSPI.kernel";
627 reg = <0x001e0000 0x0800000>;
628 };
629 partition@9 {
630 label = "QSPI.file-system";
631 reg = <0x009e0000 0x01620000>;
632 };
633 };
634 };
636 &omap_dwc3_1 {
637 extcon = <&extcon_usb1>;
638 };
640 &omap_dwc3_2 {
641 extcon = <&extcon_usb2>;
642 };
644 &usb1 {
645 dr_mode = "otg";
646 };
648 &usb2 {
649 dr_mode = "host";
650 };
652 &mac {
653 status = "okay";
654 dual_emac;
655 };
657 &cpsw_emac0 {
658 phy_id = <&davinci_mdio>, <2>;
659 phy-mode = "rgmii";
660 dual_emac_res_vlan = <1>;
661 };
663 &cpsw_emac1 {
664 phy_id = <&davinci_mdio>, <3>;
665 phy-mode = "rgmii";
666 dual_emac_res_vlan = <2>;
667 };
669 &elm {
670 status = "okay";
671 };
673 &gpmc {
674 status = "disabled";
675 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
676 nand@0,0 {
677 reg = <0 0 4>; /* device IO registers */
678 ti,nand-ecc-opt = "bch8";
679 ti,elm-id = <&elm>;
680 nand-bus-width = <16>;
681 gpmc,device-width = <2>;
682 gpmc,sync-clk-ps = <0>;
683 gpmc,cs-on-ns = <0>;
684 gpmc,cs-rd-off-ns = <80>;
685 gpmc,cs-wr-off-ns = <80>;
686 gpmc,adv-on-ns = <0>;
687 gpmc,adv-rd-off-ns = <60>;
688 gpmc,adv-wr-off-ns = <60>;
689 gpmc,we-on-ns = <10>;
690 gpmc,we-off-ns = <50>;
691 gpmc,oe-on-ns = <4>;
692 gpmc,oe-off-ns = <40>;
693 gpmc,access-ns = <40>;
694 gpmc,wr-access-ns = <80>;
695 gpmc,rd-cycle-ns = <80>;
696 gpmc,wr-cycle-ns = <80>;
697 gpmc,bus-turnaround-ns = <0>;
698 gpmc,cycle2cycle-delay-ns = <0>;
699 gpmc,clk-activation-ns = <0>;
700 gpmc,wait-monitoring-ns = <0>;
701 gpmc,wr-data-mux-bus-ns = <0>;
702 /* MTD partition table */
703 /* All SPL-* partitions are sized to minimal length
704 * which can be independently programmable. For
705 * NAND flash this is equal to size of erase-block */
706 #address-cells = <1>;
707 #size-cells = <1>;
708 partition@0 {
709 label = "NAND.SPL";
710 reg = <0x00000000 0x000020000>;
711 };
712 partition@1 {
713 label = "NAND.SPL.backup1";
714 reg = <0x00020000 0x00020000>;
715 };
716 partition@2 {
717 label = "NAND.SPL.backup2";
718 reg = <0x00040000 0x00020000>;
719 };
720 partition@3 {
721 label = "NAND.SPL.backup3";
722 reg = <0x00060000 0x00020000>;
723 };
724 partition@4 {
725 label = "NAND.u-boot-spl-os";
726 reg = <0x00080000 0x00040000>;
727 };
728 partition@5 {
729 label = "NAND.u-boot";
730 reg = <0x000c0000 0x00100000>;
731 };
732 partition@6 {
733 label = "NAND.u-boot-env";
734 reg = <0x001c0000 0x00020000>;
735 };
736 partition@7 {
737 label = "NAND.u-boot-env.backup1";
738 reg = <0x001e0000 0x00020000>;
739 };
740 partition@8 {
741 label = "NAND.kernel";
742 reg = <0x00200000 0x00800000>;
743 };
744 partition@9 {
745 label = "NAND.file-system";
746 reg = <0x00a00000 0x0f600000>;
747 };
748 };
749 };
751 &gpio7 {
752 ti,no-reset-on-init;
753 ti,no-idle-on-init;
754 };
756 &dss {
757 status = "ok";
759 vdda_video-supply = <&ldoln_reg>;
760 };
762 &hdmi {
763 status = "ok";
764 vdda-supply = <&ldo3_reg>;
766 port {
767 hdmi_out: endpoint {
768 remote-endpoint = <&tpd12s015_in>;
769 };
770 };
771 };
773 &dcan1 {
774 status = "ok";
775 pinctrl-names = "default", "sleep";
776 pinctrl-0 = <&dcan1_pins_default>;
777 pinctrl-1 = <&dcan1_pins_sleep>;
778 };
780 &mailbox5 {
781 status = "okay";
782 mbox_ipu1_legacy: mbox_ipu1_legacy {
783 status = "okay";
784 };
785 mbox_dsp1_legacy: mbox_dsp1_legacy {
786 status = "okay";
787 };
788 };
790 &mailbox6 {
791 status = "okay";
792 mbox_ipu2_legacy: mbox_ipu2_legacy {
793 status = "okay";
794 };
795 mbox_dsp2_legacy: mbox_dsp2_legacy {
796 status = "okay";
797 };
798 };
800 &mmu0_dsp1 {
801 status = "okay";
802 };
804 &mmu1_dsp1 {
805 status = "okay";
806 };
808 &mmu0_dsp2 {
809 status = "okay";
810 };
812 &mmu1_dsp2 {
813 status = "okay";
814 };
816 &mmu_ipu1 {
817 status = "okay";
818 };
820 &mmu_ipu2 {
821 status = "okay";
822 };
824 &ipu2 {
825 status = "okay";
826 memory-region = <&ipu2_cma_pool>;
827 mboxes = <&mailbox6 &mbox_ipu2_legacy>;
828 timers = <&timer3>;
829 watchdog-timers = <&timer4>, <&timer9>;
830 };
832 &ipu1 {
833 status = "okay";
834 memory-region = <&ipu1_cma_pool>;
835 mboxes = <&mailbox5 &mbox_ipu1_legacy>;
836 timers = <&timer11>;
837 watchdog-timers = <&timer7>, <&timer8>;
838 };
840 &dsp1 {
841 status = "okay";
842 memory-region = <&dsp1_cma_pool>;
843 mboxes = <&mailbox5 &mbox_dsp1_legacy>;
844 timers = <&timer5>;
845 watchdog-timers = <&timer10>;
846 };
848 &dsp2 {
849 status = "okay";
850 memory-region = <&dsp2_cma_pool>;
851 mboxes = <&mailbox6 &mbox_dsp2_legacy>;
852 timers = <&timer6>;
853 };
855 &atl {
856 status = "okay";
858 atl2 {
859 bws = <DRA7_ATL_WS_MCASP2_FSX>;
860 aws = <DRA7_ATL_WS_MCASP3_FSX>;
861 };
862 };
864 &mcasp3 {
865 fck_parent = "atl_clkin2_ck";
867 status = "okay";
869 op-mode = <0>; /* MCASP_IIS_MODE */
870 tdm-slots = <2>;
871 /* 4 serializer */
872 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
873 1 2 0 0
874 >;
875 };
877 &usb2_phy1 {
878 phy-supply = <&ldousb_reg>;
879 };
881 &usb2_phy2 {
882 phy-supply = <&ldousb_reg>;
883 };
885 &vip1 {
886 status = "okay";
887 };
889 &vin1a {
890 endpoint@0 {
891 slave-mode;
892 remote-endpoint = <&onboardLI>;
893 };
894 };