arch/arm/boot/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/clk/ti-dra7-atl.h>
  14
  15 / {
  16         model = "TI DRA742";
  17         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  18
  19         memory {
  20                 device_type = "memory";
  21                 reg = <0x80000000 0x60000000>; /* 1536 MB */
  22         };
  23
  24         reserved_mem: reserved-memory {
  25                 #address-cells = <1>;
  26                 #size-cells = <1>;
  27                 ranges;
  28
  29                 ipu2_cma_pool: ipu2_cma@95800000 {
  30                         compatible = "shared-dma-pool";
  31                         reg = <0x95800000 0x3800000>;
  32                         reusable;
  33                         status = "okay";
  34                 };
  35
  36                 dsp1_cma_pool: dsp1_cma@99000000 {
  37                         compatible = "shared-dma-pool";
  38                         reg = <0x99000000 0x4000000>;
  39                         reusable;
  40                         status = "okay";
  41                 };
  42
  43                 ipu1_cma_pool: ipu1_cma@9d000000 {
  44                         compatible = "shared-dma-pool";
  45                         reg = <0x9d000000 0x2000000>;
  46                         reusable;
  47                         status = "okay";
  48                 };
  49
  50                 dsp2_cma_pool: dsp2_cma@9f000000 {
  51                         compatible = "shared-dma-pool";
  52                         reg = <0x9f000000 0x800000>;
  53                         reusable;
  54                         status = "okay";
  55                 };
  56         };
  57
  58         extcon_usb1: extcon_usb1 {
  59                 compatible = "linux,extcon-usb-gpio";
  60                 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  61         };
  62
  63         extcon_usb2: extcon_usb2 {
  64                 compatible = "linux,extcon-usb-gpio";
  65                 id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  66         };
  67
  68         evm_3v3_sd: fixedregulator-sd {
  69                 compatible = "regulator-fixed";
  70                 regulator-name = "evm_3v3_sd";
  71                 regulator-min-microvolt = <3300000>;
  72                 regulator-max-microvolt = <3300000>;
  73                 enable-active-high;
  74                 gpio = <&pcf_gpio_21 5 0>;
  75         };
  76
  77         evm_3v3_sw: fixedregulator-evm_3v3_sw {
  78                 compatible = "regulator-fixed";
  79                 regulator-name = "evm_3v3_sw";
  80                 vin-supply = <&sysen1>;
  81                 regulator-min-microvolt = <3300000>;
  82                 regulator-max-microvolt = <3300000>;
  83         };
  84
  85         aic_dvdd: fixedregulator-aic_dvdd {
  86                 /* TPS77018DBVT */
  87                 compatible = "regulator-fixed";
  88                 regulator-name = "aic_dvdd";
  89                 vin-supply = <&evm_3v3_sw>;
  90                 regulator-min-microvolt = <1800000>;
  91                 regulator-max-microvolt = <1800000>;
  92         };
  93
  94         vmmcwl_fixed: fixedregulator-mmcwl {
  95                 compatible = "regulator-fixed";
  96                 regulator-name = "vmmcwl_fixed";
  97                 regulator-min-microvolt = <1800000>;
  98                 regulator-max-microvolt = <1800000>;
  99                 gpio = <&gpio5 8 0>;    /* gpio5_8 */
 100                 startup-delay-us = <70000>;
 101                 enable-active-high;
 102         };
 103
 104         kim {
 105                 compatible = "kim";
 106                 nshutdown_gpio = <132>;
 107                 dev_name = "/dev/ttyS2";
 108                 flow_cntrl = <1>;
 109                 baud_rate = <3686400>;
 110         };
 111
 112         btwilink {
 113                 compatible = "btwilink";
 114         };
 115
 116         vtt_fixed: fixedregulator-vtt {
 117                 compatible = "regulator-fixed";
 118                 regulator-name = "vtt_fixed";
 119                 regulator-min-microvolt = <1350000>;
 120                 regulator-max-microvolt = <1350000>;
 121                 regulator-always-on;
 122                 regulator-boot-on;
 123                 enable-active-high;
 124                 vin-supply = <&sysen2>;
 125                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
 126         };
 127
 128         aliases {
 129                 display0 = &hdmi0;
 130                 sound0 = &primary_sound;
 131                 sound1 = &hdmi;
 132         };
 133
 134         hdmi0: connector@1 {
 135                 compatible = "hdmi-connector";
 136                 label = "hdmi";
 137
 138                 type = "a";
 139
 140                 port {
 141                         hdmi_connector_in: endpoint {
 142                                 remote-endpoint = <&tpd12s015_out>;
 143                         };
 144                 };
 145         };
 146
 147         tpd12s015: encoder@1 {
 148                 compatible = "ti,dra7evm-tpd12s015";
 149
 150                 gpios = <&pcf_hdmi 4 0>,        /* P4, CT CP HPD */
 151                         <&pcf_hdmi 5 0>,        /* P5, LS OE */
 152                         <&gpio7 12 0>;  /* gpio7_12/sp1_cs2, HPD */
 153
 154                 ports {
 155                         #address-cells = <1>;
 156                         #size-cells = <0>;
 157
 158                         port@0 {
 159                                 reg = <0>;
 160
 161                                 tpd12s015_in: endpoint@0 {
 162                                         remote-endpoint = <&hdmi_out>;
 163                                 };
 164                         };
 165
 166                         port@1 {
 167                                 reg = <1>;
 168
 169                                 tpd12s015_out: endpoint@0 {
 170                                         remote-endpoint = <&hdmi_connector_in>;
 171                                 };
 172                         };
 173                 };
 174         };
 175
 176     ocp {
 177         gpu: gpu@0x56000000 {
 178             gpu0-voltdm = <&voltdm_gpu>;
 179         };
 180     };
 181
 182         primary_sound: primary_sound {
 183                 compatible = "ti,dra7xx-evm-audio";
 184                 ti,model = "DRA7xx-EVM";
 185                 ti,always-on;
 186                 ti,audio-codec = <&tlv320aic3106>;
 187                 ti,mcasp-controller = <&mcasp3>;
 188                 ti,codec-clock-rate = <11289600>;
 189                 clocks = <&atl_clkin2_ck>;
 190                 clock-names = "mclk";
 191                 ti,audio-routing =
 192                         "Headphone Jack",       "HPLOUT",
 193                         "Headphone Jack",       "HPROUT",
 194                         "Line Out",             "LLOUT",
 195                         "Line Out",             "RLOUT",
 196                         "MIC3L",                "Mic Jack",
 197                         "MIC3R",                "Mic Jack",
 198                         "Mic Jack",             "Mic Bias",
 199                         "LINE1L",               "Line In",
 200                         "LINE1R",               "Line In";
 201         };
 202
 203         btwilink_sound: btwilink_sound {
 204                 #sound-dai-cells = <0>;
 205                 compatible = "linux,bt-sco-audio";
 206                 status = "okay";
 207         };
 208
 209         simple_bt_sco_card: bt_sco_card {
 210                 compatible = "simple-audio-card";
 211                 simple-audio-card,name = "DRA7xx-WiLink";
 212                 simple-audio-card,format = "dsp_a";
 213                 simple-audio-card,frame-master = <&btwilink_codec>;
 214                 simple-audio-card,bitclock-master = <&btwilink_codec>;
 215                 simple-audio-card,frame-inversion;
 216
 217                 simple-audio-card,cpu {
 218                         sound-dai = <&mcasp7>;
 219                 };
 220
 221                 btwilink_codec: simple-audio-card,codec {
 222                         sound-dai = <&btwilink_sound>;
 223                 };
 224         };
 225 };
 226
 227 &dra7_pmx_core {
 228         i2c2_pins: pinmux_i2c2_pins {
 229                 pinctrl-single,pins = <
 230                         0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
 231                         0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
 232                 >;
 233         };
 234
 235         dcan1_pins_default: dcan1_pins_default {
 236                 pinctrl-single,pins = <
 237                         0x3d0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 238                         0x418   (PULL_UP | MUX_MODE1)           /* wakeup0.dcan1_rx */
 239                 >;
 240         };
 241
 242         dcan1_pins_sleep: dcan1_pins_sleep {
 243                 pinctrl-single,pins = <
 244                         0x3d0   (MUX_MODE15 | PULL_UP)  /* dcan1_tx.off */
 245                         0x418   (MUX_MODE15 | PULL_UP)  /* wakeup0.off */
 246                 >;
 247         };
 248
 249         mmc1_pins_default: pinmux_mmc1_default_pins {
 250                 pinctrl-single,pins = <
 251                         0x354 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_clk.clk */
 252                         0x358 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_cmd.cmd */
 253                         0x35c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat0.dat0 */
 254                         0x360 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat1.dat1 */
 255                         0x364 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat2.dat2 */
 256                         0x368 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc1_dat3.dat3 */
 257                         0x36c (PIN_INPUT | MUX_MODE14)          /* mmc1sdcd.gpio187 */
 258                 >;
 259         };
 260
 261         mmc1_pins_hs: pinmux_mmc1_hs_pins {
 262                 pinctrl-single,pins = <
 263                         0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_clk.clk */
 264                         0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_cmd.cmd */
 265                         0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat0.dat0 */
 266                         0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat1.dat1 */
 267                         0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat2.dat2 */
 268                         0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)       /* mmc1_dat3.dat3 */
 269                 >;
 270         };
 271
 272         mmc2_pins_default: mmc2_pins_default {
 273                 pinctrl-single,pins = <
 274                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 275                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 276                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 277                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 278                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 279                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 280                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 281                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 282                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 283                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 284                 >;
 285         };
 286
 287         mmc2_pins_hs: pinmux_mmc2_hs_pins {
 288                 pinctrl-single,pins = <
 289                         0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 290                         0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 291                         0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 292                         0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 293                         0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 294                         0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 295                         0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 296                         0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 297                         0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 298                         0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 299                 >;
 300         };
 301 };
 302
 303 &i2c1 {
 304         status = "okay";
 305         clock-frequency = <400000>;
 306
 307         tps659038: tps659038@58 {
 308                 compatible = "ti,tps659038";
 309                 reg = <0x58>;
 310
 311                 tps659038_pmic {
 312                         compatible = "ti,tps659038-pmic";
 313
 314                         regulators {
 315                                 smps123_reg: smps123 {
 316                                         /* VDD_MPU */
 317                                         regulator-name = "smps123";
 318                                         regulator-min-microvolt = < 850000>;
 319                                         regulator-max-microvolt = <1250000>;
 320                                         regulator-always-on;
 321                                         regulator-boot-on;
 322                                 };
 323
 324                                 smps45_reg: smps45 {
 325                                         /* VDD_DSPEVE */
 326                                         regulator-name = "smps45";
 327                                         regulator-min-microvolt = < 850000>;
 328                                         regulator-max-microvolt = <1150000>;
 329                                         regulator-boot-on;
 330                                         regulator-always-on;
 331                                 };
 332
 333                                 smps6_reg: smps6 {
 334                                         /* VDD_GPU - over VDD_SMPS6 */
 335                                         regulator-name = "smps6";
 336                                         regulator-min-microvolt = <850000>;
 337                                         regulator-max-microvolt = <1250000>;
 338                                         regulator-boot-on;
 339                                         regulator-always-on;
 340                                 };
 341
 342                                 smps7_reg: smps7 {
 343                                         /* CORE_VDD */
 344                                         regulator-name = "smps7";
 345                                         regulator-min-microvolt = <850000>;
 346                                         regulator-max-microvolt = <1060000>;
 347                                         regulator-always-on;
 348                                         regulator-boot-on;
 349                                 };
 350
 351                                 smps8_reg: smps8 {
 352                                         /* VDD_IVAHD */
 353                                         regulator-name = "smps8";
 354                                         regulator-min-microvolt = < 850000>;
 355                                         regulator-max-microvolt = <1250000>;
 356                                         regulator-boot-on;
 357                                         regulator-always-on;
 358                                 };
 359
 360                                 smps9_reg: smps9 {
 361                                         /* VDDS1V8 */
 362                                         regulator-name = "smps9";
 363                                         regulator-min-microvolt = <1800000>;
 364                                         regulator-max-microvolt = <1800000>;
 365                                         regulator-always-on;
 366                                         regulator-boot-on;
 367                                 };
 368
 369                                 ldo1_reg: ldo1 {
 370                                         /* LDO1_OUT --> SDIO  */
 371                                         regulator-name = "ldo1";
 372                                         regulator-min-microvolt = <1800000>;
 373                                         regulator-max-microvolt = <3300000>;
 374                                         regulator-boot-on;
 375                                         regulator-always-on;
 376                                 };
 377
 378                                 ldo2_reg: ldo2 {
 379                                         /* VDD_RTCIO */
 380                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 381                                         regulator-name = "ldo2";
 382                                         regulator-min-microvolt = <3300000>;
 383                                         regulator-max-microvolt = <3300000>;
 384                                         regulator-boot-on;
 385                                         regulator-always-on;
 386                                 };
 387
 388                                 ldo3_reg: ldo3 {
 389                                         /* VDDA_1V8_PHY */
 390                                         regulator-name = "ldo3";
 391                                         regulator-min-microvolt = <1800000>;
 392                                         regulator-max-microvolt = <1800000>;
 393                                         regulator-always-on;
 394                                         regulator-boot-on;
 395                                 };
 396
 397                                 ldo9_reg: ldo9 {
 398                                         /* VDD_RTC */
 399                                         regulator-name = "ldo9";
 400                                         regulator-min-microvolt = <1050000>;
 401                                         regulator-max-microvolt = <1050000>;
 402                                         regulator-boot-on;
 403                                         regulator-always-on;
 404                                 };
 405
 406                                 ldoln_reg: ldoln {
 407                                         /* VDDA_1V8_PLL */
 408                                         regulator-name = "ldoln";
 409                                         regulator-min-microvolt = <1800000>;
 410                                         regulator-max-microvolt = <1800000>;
 411                                         regulator-always-on;
 412                                         regulator-boot-on;
 413                                 };
 414
 415                                 ldousb_reg: ldousb {
 416                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 417                                         regulator-name = "ldousb";
 418                                         regulator-min-microvolt = <3300000>;
 419                                         regulator-max-microvolt = <3300000>;
 420                                         regulator-boot-on;
 421                                         regulator-always-on;
 422                                 };
 423
 424                                 /* REGEN1 is unused */
 425
 426                                 regen2: regen2 {
 427                                         /* Needed for PMIC internal resources */
 428                                         regulator-name = "regen2";
 429                                         regulator-boot-on;
 430                                         regulator-always-on;
 431                                 };
 432
 433                                 /* REGEN3 is unused */
 434
 435                                 sysen1: sysen1 {
 436                                         /* PMIC_REGEN_3V3 */
 437                                         regulator-name = "sysen1";
 438                                         regulator-boot-on;
 439                                         regulator-always-on;
 440                                 };
 441
 442                                 sysen2: sysen2 {
 443                                         /* PMIC_REGEN_DDR */
 444                                         regulator-name = "sysen2";
 445                                         regulator-boot-on;
 446                                         regulator-always-on;
 447                                 };
 448                         };
 449                 };
 450         };
 451
 452         pcf_lcd: gpio@20 {
 453                 compatible = "nxp,pcf8575";
 454                 reg = <0x20>;
 455                 gpio-controller;
 456                 #gpio-cells = <2>;
 457         };
 458
 459         pcf_gpio_21: gpio@21 {
 460                 compatible = "nxp,pcf8575";
 461                 reg = <0x21>;
 462                 lines-initial-states = <0x1408>;
 463                 gpio-controller;
 464                 #gpio-cells = <2>;
 465                 interrupt-parent = <&gpio6>;
 466                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 467                 interrupt-controller;
 468                 #interrupt-cells = <2>;
 469         };
 470
 471
 472         tlv320aic3106: tlv320aic3106@18 {
 473                 compatible = "ti,tlv320aic3106";
 474                 reg = <0x18>;
 475                 adc-settle-ms = <40>;
 476                 ai3x-micbias-vg = <1>;          /* 2.0V */
 477                 status = "okay";
 478
 479                 /* Regulators */
 480                 AVDD-supply = <&evm_3v3_sw>;
 481                 IOVDD-supply = <&evm_3v3_sw>;
 482                 DRVDD-supply = <&evm_3v3_sw>;
 483                 DVDD-supply = <&aic_dvdd>;
 484         };
 485 };
 486
 487 i2c_p3_exp: &i2c2 {
 488         status = "okay";
 489         pinctrl-names = "default";
 490         pinctrl-0 = <&i2c2_pins>;
 491         clock-frequency = <400000>;
 492
 493         pcf_hdmi: gpio@26 {
 494                 compatible = "nxp,pcf8575";
 495                 reg = <0x26>;
 496                 lines-initial-states = <0xffeb>;
 497                 gpio-controller;
 498                 #gpio-cells = <2>;
 499         };
 500
 501         ov10633@37 {
 502                 compatible = "ovti,ov10633";
 503                 reg = <0x37>;
 504
 505                 mux-gpios = <&pcf_hdmi 3        GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
 506                 port {
 507                         onboardLI: endpoint {
 508                                 remote-endpoint = <&vin1a>;
 509                                 hsync-active = <1>;
 510                                 vsync-active = <1>;
 511                                 pclk-sample = <0>;
 512                         };
 513                 };
 514         };
 515 };
 516
 517 &i2c3 {
 518         status = "okay";
 519         clock-frequency = <3400000>;
 520 };
 521
 522 &mcspi1 {
 523         status = "okay";
 524 };
 525
 526 &mcspi2 {
 527         status = "okay";
 528 };
 529
 530 &uart1 {
 531         status = "okay";
 532         interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
 533                                &dra7_pmx_core 0x3e0>;
 534 };
 535
 536 &uart2 {
 537         status = "okay";
 538 };
 539
 540 &uart3 {
 541         status = "okay";
 542         gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
 543 };
 544
 545 &mmc1 {
 546         status = "okay";
 547         pbias-supply = <&pbias_mmc_reg>;
 548         vmmc-supply = <&evm_3v3_sd>;
 549         vmmc_aux-supply = <&ldo1_reg>;
 550         bus-width = <4>;
 551         /*
 552          * SDCD signal is not being used here - using the fact that GPIO mode
 553          * is always hardwired.
 554          */
 555         cd-gpios = <&gpio6 27 0>;
 556         pinctrl-names = "default", "hs";
 557         pinctrl-0 = <&mmc1_pins_default>;
 558         pinctrl-1 = <&mmc1_pins_hs>;
 559 };
 560
 561 &mmc2 {
 562         status = "okay";
 563         vmmc-supply = <&evm_3v3_sw>;
 564         bus-width = <8>;
 565         pinctrl-names = "default", "hs";
 566         pinctrl-0 = <&mmc2_pins_default>;
 567         pinctrl-1 = <&mmc2_pins_hs>;
 568 };
 569
 570 &mmc4 {
 571         status = "okay";
 572         vmmc-supply = <&vmmcwl_fixed>;
 573         bus-width = <4>;
 574         cap-power-off-card;
 575         keep-power-in-suspend;
 576         ti,non-removable;
 577
 578         #address-cells = <1>;
 579         #size-cells = <0>;
 580         wlcore: wlcore@0 {
 581                 compatible = "ti,wlcore";
 582                 reg = <2>;
 583                 interrupt-parent = <&gpio5>;
 584                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 585         };
 586 };
 587
 588 &cpu0 {
 589         cpu0-voltdm = <&voltdm_mpu>;
 590         voltage-tolerance = <1>;
 591 };
 592
 593 &voltdm_mpu {
 594         vdd-supply = <&smps123_reg>;
 595 };
 596
 597 &voltdm_dspeve {
 598         vdd-supply = <&smps45_reg>;
 599 };
 600
 601 &voltdm_gpu {
 602         vdd-supply = <&smps6_reg>;
 603 };
 604
 605 &voltdm_ivahd {
 606         vdd-supply = <&smps8_reg>;
 607 };
 608
 609 &voltdm_core {
 610         vdd-supply = <&smps7_reg>;
 611 };
 612
 613 &qspi {
 614         status = "okay";
 615
 616         spi-max-frequency = <48000000>;
 617         m25p80@0 {
 618                 compatible = "s25fl256s1";
 619                 spi-max-frequency = <48000000>;
 620                 reg = <0>;
 621                 spi-tx-bus-width = <1>;
 622                 spi-rx-bus-width = <4>;
 623                 spi-cpol;
 624                 spi-cpha;
 625                 #address-cells = <1>;
 626                 #size-cells = <1>;
 627
 628                 /* MTD partition table.
 629                  * The ROM checks the first four physical blocks
 630                  * for a valid file to boot and the flash here is
 631                  * 64KiB block size.
 632                  */
 633                 partition@0 {
 634                         label = "QSPI.SPL";
 635                         reg = <0x00000000 0x000010000>;
 636                 };
 637                 partition@1 {
 638                         label = "QSPI.SPL.backup1";
 639                         reg = <0x00010000 0x00010000>;
 640                 };
 641                 partition@2 {
 642                         label = "QSPI.SPL.backup2";
 643                         reg = <0x00020000 0x00010000>;
 644                 };
 645                 partition@3 {
 646                         label = "QSPI.SPL.backup3";
 647                         reg = <0x00030000 0x00010000>;
 648                 };
 649                 partition@4 {
 650                         label = "QSPI.u-boot";
 651                         reg = <0x00040000 0x00100000>;
 652                 };
 653                 partition@5 {
 654                         label = "QSPI.u-boot-spl-os";
 655                         reg = <0x00140000 0x00080000>;
 656                 };
 657                 partition@6 {
 658                         label = "QSPI.u-boot-env";
 659                         reg = <0x001c0000 0x00010000>;
 660                 };
 661                 partition@7 {
 662                         label = "QSPI.u-boot-env.backup1";
 663                         reg = <0x001d0000 0x0010000>;
 664                 };
 665                 partition@8 {
 666                         label = "QSPI.kernel";
 667                         reg = <0x001e0000 0x0800000>;
 668                 };
 669                 partition@9 {
 670                         label = "QSPI.file-system";
 671                         reg = <0x009e0000 0x01620000>;
 672                 };
 673         };
 674 };
 675
 676 &omap_dwc3_1 {
 677         extcon = <&extcon_usb1>;
 678 };
 679
 680 &omap_dwc3_2 {
 681         extcon = <&extcon_usb2>;
 682 };
 683
 684 &usb1 {
 685         dr_mode = "otg";
 686 };
 687
 688 &usb2 {
 689         dr_mode = "host";
 690 };
 691
 692 &mac {
 693         status = "okay";
 694         dual_emac;
 695 };
 696
 697 &cpsw_emac0 {
 698         phy_id = <&davinci_mdio>, <2>;
 699         phy-mode = "rgmii";
 700         dual_emac_res_vlan = <1>;
 701 };
 702
 703 &cpsw_emac1 {
 704         phy_id = <&davinci_mdio>, <3>;
 705         phy-mode = "rgmii";
 706         dual_emac_res_vlan = <2>;
 707 };
 708
 709 &elm {
 710         status = "okay";
 711 };
 712
 713 &gpmc {
 714         status = "disabled";
 715         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 716         nand@0,0 {
 717                 reg = <0 0 4>;          /* device IO registers */
 718                 ti,nand-ecc-opt = "bch8";
 719                 ti,elm-id = <&elm>;
 720                 nand-bus-width = <16>;
 721                 gpmc,device-width = <2>;
 722                 gpmc,sync-clk-ps = <0>;
 723                 gpmc,cs-on-ns = <0>;
 724                 gpmc,cs-rd-off-ns = <80>;
 725                 gpmc,cs-wr-off-ns = <80>;
 726                 gpmc,adv-on-ns = <0>;
 727                 gpmc,adv-rd-off-ns = <60>;
 728                 gpmc,adv-wr-off-ns = <60>;
 729                 gpmc,we-on-ns = <10>;
 730                 gpmc,we-off-ns = <50>;
 731                 gpmc,oe-on-ns = <4>;
 732                 gpmc,oe-off-ns = <40>;
 733                 gpmc,access-ns = <40>;
 734                 gpmc,wr-access-ns = <80>;
 735                 gpmc,rd-cycle-ns = <80>;
 736                 gpmc,wr-cycle-ns = <80>;
 737                 gpmc,bus-turnaround-ns = <0>;
 738                 gpmc,cycle2cycle-delay-ns = <0>;
 739                 gpmc,clk-activation-ns = <0>;
 740                 gpmc,wait-monitoring-ns = <0>;
 741                 gpmc,wr-data-mux-bus-ns = <0>;
 742                 /* MTD partition table */
 743                 /* All SPL-* partitions are sized to minimal length
 744                  * which can be independently programmable. For
 745                  * NAND flash this is equal to size of erase-block */
 746                 #address-cells = <1>;
 747                 #size-cells = <1>;
 748                 partition@0 {
 749                         label = "NAND.SPL";
 750                         reg = <0x00000000 0x000020000>;
 751                 };
 752                 partition@1 {
 753                         label = "NAND.SPL.backup1";
 754                         reg = <0x00020000 0x00020000>;
 755                 };
 756                 partition@2 {
 757                         label = "NAND.SPL.backup2";
 758                         reg = <0x00040000 0x00020000>;
 759                 };
 760                 partition@3 {
 761                         label = "NAND.SPL.backup3";
 762                         reg = <0x00060000 0x00020000>;
 763                 };
 764                 partition@4 {
 765                         label = "NAND.u-boot-spl-os";
 766                         reg = <0x00080000 0x00040000>;
 767                 };
 768                 partition@5 {
 769                         label = "NAND.u-boot";
 770                         reg = <0x000c0000 0x00100000>;
 771                 };
 772                 partition@6 {
 773                         label = "NAND.u-boot-env";
 774                         reg = <0x001c0000 0x00020000>;
 775                 };
 776                 partition@7 {
 777                         label = "NAND.u-boot-env.backup1";
 778                         reg = <0x001e0000 0x00020000>;
 779                 };
 780                 partition@8 {
 781                         label = "NAND.kernel";
 782                         reg = <0x00200000 0x00800000>;
 783                 };
 784                 partition@9 {
 785                         label = "NAND.file-system";
 786                         reg = <0x00a00000 0x0f600000>;
 787                 };
 788         };
 789 };
 790
 791 &gpio7 {
 792         ti,no-reset-on-init;
 793         ti,no-idle-on-init;
 794 };
 795
 796 &dss {
 797         status = "ok";
 798
 799         vdda_video-supply = <&ldoln_reg>;
 800 };
 801
 802 &hdmi {
 803         status = "ok";
 804         vdda-supply = <&ldo3_reg>;
 805
 806         port {
 807                 hdmi_out: endpoint {
 808                         remote-endpoint = <&tpd12s015_in>;
 809                 };
 810         };
 811 };
 812
 813 &dcan1 {
 814         status = "ok";
 815         pinctrl-names = "default", "sleep";
 816         pinctrl-0 = <&dcan1_pins_default>;
 817         pinctrl-1 = <&dcan1_pins_sleep>;
 818 };
 819
 820 &mailbox5 {
 821         status = "okay";
 822         mbox_ipu1_legacy: mbox_ipu1_legacy {
 823                 status = "okay";
 824         };
 825         mbox_dsp1_legacy: mbox_dsp1_legacy {
 826                 status = "okay";
 827         };
 828 };
 829
 830 &mailbox6 {
 831         status = "okay";
 832         mbox_ipu2_legacy: mbox_ipu2_legacy {
 833                 status = "okay";
 834         };
 835         mbox_dsp2_legacy: mbox_dsp2_legacy {
 836                 status = "okay";
 837         };
 838 };
 839
 840 &mmu0_dsp1 {
 841         status = "okay";
 842 };
 843
 844 &mmu1_dsp1 {
 845         status = "okay";
 846 };
 847
 848 &mmu0_dsp2 {
 849         status = "okay";
 850 };
 851
 852 &mmu1_dsp2 {
 853         status = "okay";
 854 };
 855
 856 &mmu_ipu1 {
 857         status = "okay";
 858 };
 859
 860 &mmu_ipu2 {
 861         status = "okay";
 862 };
 863
 864 &ipu2 {
 865         status = "okay";
 866         memory-region = <&ipu2_cma_pool>;
 867         mboxes = <&mailbox6 &mbox_ipu2_legacy>;
 868         timers = <&timer3>;
 869         watchdog-timers = <&timer4>, <&timer9>;
 870 };
 871
 872 &ipu1 {
 873         status = "okay";
 874         memory-region = <&ipu1_cma_pool>;
 875         mboxes = <&mailbox5 &mbox_ipu1_legacy>;
 876         timers = <&timer11>;
 877         watchdog-timers = <&timer7>, <&timer8>;
 878 };
 879
 880 &dsp1 {
 881         status = "okay";
 882         memory-region = <&dsp1_cma_pool>;
 883         mboxes = <&mailbox5 &mbox_dsp1_legacy>;
 884         timers = <&timer5>;
 885         watchdog-timers = <&timer10>;
 886 };
 887
 888 &dsp2 {
 889         status = "okay";
 890         memory-region = <&dsp2_cma_pool>;
 891         mboxes = <&mailbox6 &mbox_dsp2_legacy>;
 892         timers = <&timer6>;
 893 };
 894
 895 &atl {
 896         status = "okay";
 897
 898         atl2 {
 899                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 900                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 901         };
 902 };
 903
 904 &mcasp3 {
 905         fck_parent = "atl_clkin2_ck";
 906
 907         status = "okay";
 908
 909         op-mode = <0>;          /* MCASP_IIS_MODE */
 910         tdm-slots = <2>;
 911         /* 4 serializer */
 912         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 913                 1 2 0 0
 914         >;
 915 };
 916
 917 &mcasp7 {
 918         #sound-dai-cells = <0>;
 919
 920         status = "okay";
 921
 922         op-mode = <0>;  /* MCASP_IIS_MODE */
 923         tdm-slots = <4>;
 924         /* 4 serializer */
 925         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 926                 2 1 0 0
 927         >;
 928         tx-num-evt = <8>;
 929         rx-num-evt = <8>;
 930 };
 931
 932 &usb2_phy1 {
 933         phy-supply = <&ldousb_reg>;
 934 };
 935
 936 &usb2_phy2 {
 937         phy-supply = <&ldousb_reg>;
 938 };
 939
 940 &vip1 {
 941         status = "okay";
 942 };
 943
 944 &vin1a {
 945         endpoint@0 {
 946                 slave-mode;
 947                 remote-endpoint = <&onboardLI>;
 948         };
 949 };
 950
 951 #include "dra7xx-jamr3.dtsi"