1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clk/ti-dra7-atl.h>
15 / {
16 model = "TI DRA742";
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
19 memory {
20 device_type = "memory";
21 reg = <0x80000000 0x60000000>; /* 1536 MB */
22 };
24 reserved_mem: reserved-memory {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
29 ipu2_cma_pool: ipu2_cma@95800000 {
30 compatible = "shared-dma-pool";
31 reg = <0x95800000 0x3800000>;
32 reusable;
33 status = "okay";
34 };
36 dsp1_cma_pool: dsp1_cma@99000000 {
37 compatible = "shared-dma-pool";
38 reg = <0x99000000 0x4000000>;
39 reusable;
40 status = "okay";
41 };
43 ipu1_cma_pool: ipu1_cma@9d000000 {
44 compatible = "shared-dma-pool";
45 reg = <0x9d000000 0x2000000>;
46 reusable;
47 status = "okay";
48 };
50 dsp2_cma_pool: dsp2_cma@9f000000 {
51 compatible = "shared-dma-pool";
52 reg = <0x9f000000 0x800000>;
53 reusable;
54 status = "okay";
55 };
56 };
58 extcon_usb1: extcon_usb1 {
59 compatible = "linux,extcon-usb-gpio";
60 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
61 };
63 extcon_usb2: extcon_usb2 {
64 compatible = "linux,extcon-usb-gpio";
65 id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
66 };
68 evm_3v3_sd: fixedregulator-sd {
69 compatible = "regulator-fixed";
70 regulator-name = "evm_3v3_sd";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 enable-active-high;
74 gpio = <&pcf_gpio_21 5 0>;
75 };
77 evm_3v3_sw: fixedregulator-evm_3v3_sw {
78 compatible = "regulator-fixed";
79 regulator-name = "evm_3v3_sw";
80 vin-supply = <&sysen1>;
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 };
85 aic_dvdd: fixedregulator-aic_dvdd {
86 /* TPS77018DBVT */
87 compatible = "regulator-fixed";
88 regulator-name = "aic_dvdd";
89 vin-supply = <&evm_3v3_sw>;
90 regulator-min-microvolt = <1800000>;
91 regulator-max-microvolt = <1800000>;
92 };
94 vmmcwl_fixed: fixedregulator-mmcwl {
95 compatible = "regulator-fixed";
96 regulator-name = "vmmcwl_fixed";
97 regulator-min-microvolt = <1800000>;
98 regulator-max-microvolt = <1800000>;
99 gpio = <&gpio5 8 0>; /* gpio5_8 */
100 startup-delay-us = <70000>;
101 enable-active-high;
102 };
104 kim {
105 compatible = "kim";
106 nshutdown_gpio = <132>;
107 dev_name = "/dev/ttyS2";
108 flow_cntrl = <1>;
109 baud_rate = <3686400>;
110 };
112 btwilink {
113 compatible = "btwilink";
114 };
116 vtt_fixed: fixedregulator-vtt {
117 compatible = "regulator-fixed";
118 regulator-name = "vtt_fixed";
119 regulator-min-microvolt = <1350000>;
120 regulator-max-microvolt = <1350000>;
121 regulator-always-on;
122 regulator-boot-on;
123 enable-active-high;
124 vin-supply = <&sysen2>;
125 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
126 };
128 aliases {
129 display0 = &hdmi0;
130 sound0 = &primary_sound;
131 sound1 = &hdmi;
132 };
134 hdmi0: connector@1 {
135 compatible = "hdmi-connector";
136 label = "hdmi";
138 type = "a";
140 port {
141 hdmi_connector_in: endpoint {
142 remote-endpoint = <&tpd12s015_out>;
143 };
144 };
145 };
147 tpd12s015: encoder@1 {
148 compatible = "ti,dra7evm-tpd12s015";
150 gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
151 <&pcf_hdmi 5 0>, /* P5, LS OE */
152 <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
154 ports {
155 #address-cells = <1>;
156 #size-cells = <0>;
158 port@0 {
159 reg = <0>;
161 tpd12s015_in: endpoint@0 {
162 remote-endpoint = <&hdmi_out>;
163 };
164 };
166 port@1 {
167 reg = <1>;
169 tpd12s015_out: endpoint@0 {
170 remote-endpoint = <&hdmi_connector_in>;
171 };
172 };
173 };
174 };
176 ocp {
177 gpu: gpu@0x56000000 {
178 gpu0-voltdm = <&voltdm_gpu>;
179 };
180 };
182 primary_sound: primary_sound {
183 compatible = "ti,dra7xx-evm-audio";
184 ti,model = "DRA7xx-EVM";
185 ti,always-on;
186 ti,audio-codec = <&tlv320aic3106>;
187 ti,mcasp-controller = <&mcasp3>;
188 ti,codec-clock-rate = <11289600>;
189 clocks = <&atl_clkin2_ck>;
190 clock-names = "mclk";
191 ti,audio-routing =
192 "Headphone Jack", "HPLOUT",
193 "Headphone Jack", "HPROUT",
194 "Line Out", "LLOUT",
195 "Line Out", "RLOUT",
196 "MIC3L", "Mic Jack",
197 "MIC3R", "Mic Jack",
198 "Mic Jack", "Mic Bias",
199 "LINE1L", "Line In",
200 "LINE1R", "Line In";
201 };
203 btwilink_sound: btwilink_sound {
204 #sound-dai-cells = <0>;
205 compatible = "linux,bt-sco-audio";
206 status = "okay";
207 };
209 simple_bt_sco_card: bt_sco_card {
210 compatible = "simple-audio-card";
211 simple-audio-card,name = "DRA7xx-WiLink";
212 simple-audio-card,format = "dsp_a";
213 simple-audio-card,frame-master = <&btwilink_codec>;
214 simple-audio-card,bitclock-master = <&btwilink_codec>;
215 simple-audio-card,frame-inversion;
217 simple-audio-card,cpu {
218 sound-dai = <&mcasp7>;
219 };
221 btwilink_codec: simple-audio-card,codec {
222 sound-dai = <&btwilink_sound>;
223 };
224 };
225 };
227 &dra7_pmx_core {
228 i2c2_pins: pinmux_i2c2_pins {
229 pinctrl-single,pins = <
230 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
231 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
232 >;
233 };
235 dcan1_pins_default: dcan1_pins_default {
236 pinctrl-single,pins = <
237 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
238 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
239 >;
240 };
242 dcan1_pins_sleep: dcan1_pins_sleep {
243 pinctrl-single,pins = <
244 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
245 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
246 >;
247 };
249 mmc1_pins_default: pinmux_mmc1_default_pins {
250 pinctrl-single,pins = <
251 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
252 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
253 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
254 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
255 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
256 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
257 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio187 */
258 >;
259 };
261 mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
262 pinctrl-single,pins = <
263 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
264 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
265 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
266 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
267 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
268 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
269 >;
270 };
272 mmc1_pins_hs: pinmux_mmc1_hs_pins {
273 pinctrl-single,pins = <
274 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
275 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
276 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
277 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
278 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
279 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
280 >;
281 };
283 mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
284 pinctrl-single,pins = <
285 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
286 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
287 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
288 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
289 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
290 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
291 >;
292 };
294 mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
295 pinctrl-single,pins = <
296 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.clk */
297 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.cmd */
298 0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.dat0 */
299 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.dat1 */
300 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.dat2 */
301 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.dat3 */
302 >;
303 };
305 mmc2_pins_default: mmc2_pins_default {
306 pinctrl-single,pins = <
307 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
308 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
309 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
310 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
311 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
312 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
313 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
314 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
315 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
316 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
317 >;
318 };
320 mmc2_pins_hs: pinmux_mmc2_hs_pins {
321 pinctrl-single,pins = <
322 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
323 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
324 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
325 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
326 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
327 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
328 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
329 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
330 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
331 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
332 >;
333 };
335 mmc2_pins_ddr_3_3v: pinmux_mmc2_ddr_3_3v_pins {
336 pinctrl-single,pins = <
337 0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
338 0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
339 0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
340 0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
341 0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
342 0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
343 0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
344 0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
345 0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
346 0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
347 >;
348 };
349 };
351 &dra7_iodelay_core {
352 mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
353 pinctrl-single,pins = <
354 0x618 (A_DELAY(572) | G_DELAY(540)) /* CFG_MMC1_CLK_IN */
355 0x624 (A_DELAY(0) | G_DELAY(600)) /* CFG_MMC1_CMD_IN */
356 0x630 (A_DELAY(403) | G_DELAY(120)) /* CFG_MMC1_DAT0_IN */
357 0x63c (A_DELAY(23) | G_DELAY(60)) /* CFG_MMC1_DAT1_IN */
358 0x648 (A_DELAY(25) | G_DELAY(60)) /* CFG_MMC1_DAT2_IN */
359 0x654 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */
360 0x620 (A_DELAY(1525) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */
361 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
362 0x62c (A_DELAY(55) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
363 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
364 0x638 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
365 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
366 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
367 0x64c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
368 0x650 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
369 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
370 0x65c (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
371 >;
372 };
374 mmc2_iodelay_ddr_3_3v_conf: mmc2_iodelay_ddr_3_3v_conf {
375 pinctrl-single,pins = <
376 0x18c (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A19_IN */
377 0x1a4 (A_DELAY(265) | G_DELAY(360)) /* CFG_GPMC_A20_IN */
378 0x1b0 (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A21_IN */
379 0x1bc (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A22_IN */
380 0x1c8 (A_DELAY(287) | G_DELAY(420)) /* CFG_GPMC_A23_IN */
381 0x1d4 (A_DELAY(144) | G_DELAY(240)) /* CFG_GPMC_A24_IN */
382 0x1e0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */
383 0x1ec (A_DELAY(0) | G_DELAY(120)) /* CFG_GPMC_A26_IN */
384 0x1f8 (A_DELAY(120) | G_DELAY(180)) /* CFG_GPMC_A27_IN */
385 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */
386 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
387 0x194 (A_DELAY(174) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
388 0x1a8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
389 0x1ac (A_DELAY(168) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
390 0x1b4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
391 0x1b8 (A_DELAY(136) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
392 0x1c0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
393 0x1c4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
394 0x1d0 (A_DELAY(879) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */
395 0x1d8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
396 0x1dc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
397 0x1e4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
398 0x1e8 (A_DELAY(34) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
399 0x1f0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
400 0x1f4 (A_DELAY(120) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
401 0x1fc (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
402 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
403 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
404 0x368 (A_DELAY(11) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
405 >;
406 };
407 };
409 &i2c1 {
410 status = "okay";
411 clock-frequency = <400000>;
413 tps659038: tps659038@58 {
414 compatible = "ti,tps659038";
415 reg = <0x58>;
417 tps659038_pmic {
418 compatible = "ti,tps659038-pmic";
420 regulators {
421 smps123_reg: smps123 {
422 /* VDD_MPU */
423 regulator-name = "smps123";
424 regulator-min-microvolt = < 850000>;
425 regulator-max-microvolt = <1250000>;
426 regulator-always-on;
427 regulator-boot-on;
428 };
430 smps45_reg: smps45 {
431 /* VDD_DSPEVE */
432 regulator-name = "smps45";
433 regulator-min-microvolt = < 850000>;
434 regulator-max-microvolt = <1150000>;
435 regulator-boot-on;
436 regulator-always-on;
437 };
439 smps6_reg: smps6 {
440 /* VDD_GPU - over VDD_SMPS6 */
441 regulator-name = "smps6";
442 regulator-min-microvolt = <850000>;
443 regulator-max-microvolt = <1250000>;
444 regulator-boot-on;
445 regulator-always-on;
446 };
448 smps7_reg: smps7 {
449 /* CORE_VDD */
450 regulator-name = "smps7";
451 regulator-min-microvolt = <850000>;
452 regulator-max-microvolt = <1060000>;
453 regulator-always-on;
454 regulator-boot-on;
455 };
457 smps8_reg: smps8 {
458 /* VDD_IVAHD */
459 regulator-name = "smps8";
460 regulator-min-microvolt = < 850000>;
461 regulator-max-microvolt = <1250000>;
462 regulator-boot-on;
463 regulator-always-on;
464 };
466 smps9_reg: smps9 {
467 /* VDDS1V8 */
468 regulator-name = "smps9";
469 regulator-min-microvolt = <1800000>;
470 regulator-max-microvolt = <1800000>;
471 regulator-always-on;
472 regulator-boot-on;
473 };
475 ldo1_reg: ldo1 {
476 /* LDO1_OUT --> SDIO */
477 regulator-name = "ldo1";
478 regulator-min-microvolt = <1800000>;
479 regulator-max-microvolt = <3300000>;
480 regulator-boot-on;
481 regulator-always-on;
482 };
484 ldo2_reg: ldo2 {
485 /* VDD_RTCIO */
486 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
487 regulator-name = "ldo2";
488 regulator-min-microvolt = <3300000>;
489 regulator-max-microvolt = <3300000>;
490 regulator-boot-on;
491 regulator-always-on;
492 };
494 ldo3_reg: ldo3 {
495 /* VDDA_1V8_PHY */
496 regulator-name = "ldo3";
497 regulator-min-microvolt = <1800000>;
498 regulator-max-microvolt = <1800000>;
499 regulator-always-on;
500 regulator-boot-on;
501 };
503 ldo9_reg: ldo9 {
504 /* VDD_RTC */
505 regulator-name = "ldo9";
506 regulator-min-microvolt = <1050000>;
507 regulator-max-microvolt = <1050000>;
508 regulator-boot-on;
509 regulator-always-on;
510 };
512 ldoln_reg: ldoln {
513 /* VDDA_1V8_PLL */
514 regulator-name = "ldoln";
515 regulator-min-microvolt = <1800000>;
516 regulator-max-microvolt = <1800000>;
517 regulator-always-on;
518 regulator-boot-on;
519 };
521 ldousb_reg: ldousb {
522 /* VDDA_3V_USB: VDDA_USBHS33 */
523 regulator-name = "ldousb";
524 regulator-min-microvolt = <3300000>;
525 regulator-max-microvolt = <3300000>;
526 regulator-boot-on;
527 regulator-always-on;
528 };
530 /* REGEN1 is unused */
532 regen2: regen2 {
533 /* Needed for PMIC internal resources */
534 regulator-name = "regen2";
535 regulator-boot-on;
536 regulator-always-on;
537 };
539 /* REGEN3 is unused */
541 sysen1: sysen1 {
542 /* PMIC_REGEN_3V3 */
543 regulator-name = "sysen1";
544 regulator-boot-on;
545 regulator-always-on;
546 };
548 sysen2: sysen2 {
549 /* PMIC_REGEN_DDR */
550 regulator-name = "sysen2";
551 regulator-boot-on;
552 regulator-always-on;
553 };
554 };
555 };
556 };
558 pcf_lcd: gpio@20 {
559 compatible = "nxp,pcf8575";
560 reg = <0x20>;
561 gpio-controller;
562 #gpio-cells = <2>;
563 };
565 pcf_gpio_21: gpio@21 {
566 compatible = "nxp,pcf8575";
567 reg = <0x21>;
568 lines-initial-states = <0x1408>;
569 gpio-controller;
570 #gpio-cells = <2>;
571 interrupt-parent = <&gpio6>;
572 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 };
578 tlv320aic3106: tlv320aic3106@18 {
579 compatible = "ti,tlv320aic3106";
580 reg = <0x18>;
581 adc-settle-ms = <40>;
582 ai3x-micbias-vg = <1>; /* 2.0V */
583 status = "okay";
585 /* Regulators */
586 AVDD-supply = <&evm_3v3_sw>;
587 IOVDD-supply = <&evm_3v3_sw>;
588 DRVDD-supply = <&evm_3v3_sw>;
589 DVDD-supply = <&aic_dvdd>;
590 };
591 };
593 i2c_p3_exp: &i2c2 {
594 status = "okay";
595 pinctrl-names = "default";
596 pinctrl-0 = <&i2c2_pins>;
597 clock-frequency = <400000>;
599 pcf_hdmi: gpio@26 {
600 compatible = "nxp,pcf8575";
601 reg = <0x26>;
602 lines-initial-states = <0xffeb>;
603 gpio-controller;
604 #gpio-cells = <2>;
605 };
607 ov10633@37 {
608 compatible = "ovti,ov10633";
609 reg = <0x37>;
611 mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
612 port {
613 onboardLI: endpoint {
614 remote-endpoint = <&vin1a>;
615 hsync-active = <1>;
616 vsync-active = <1>;
617 pclk-sample = <0>;
618 };
619 };
620 };
621 };
623 &i2c3 {
624 status = "okay";
625 clock-frequency = <3400000>;
626 };
628 &mcspi1 {
629 status = "okay";
630 };
632 &mcspi2 {
633 status = "okay";
634 };
636 &uart1 {
637 status = "okay";
638 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
639 &dra7_pmx_core 0x3e0>;
640 };
642 &uart2 {
643 status = "okay";
644 };
646 &uart3 {
647 status = "okay";
648 gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
649 };
651 &mmc1 {
652 status = "okay";
653 pbias-supply = <&pbias_mmc_reg>;
654 vmmc-supply = <&evm_3v3_sd>;
655 vmmc_aux-supply = <&ldo1_reg>;
656 bus-width = <4>;
657 /*
658 * SDCD signal is not being used here - using the fact that GPIO mode
659 * is always hardwired.
660 */
661 cd-gpios = <&gpio6 27 0>;
662 pinctrl-names = "default", "hs", "sdr12", "sdr25", "ddr50";
663 pinctrl-0 = <&mmc1_pins_default>;
664 pinctrl-1 = <&mmc1_pins_hs>;
665 pinctrl-2 = <&mmc1_pins_sdr12>;
666 pinctrl-3 = <&mmc1_pins_sdr25>;
667 pinctrl-4 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>;
668 sd-uhs-ddr50;
669 sd-uhs-sdr25;
670 sd-uhs-sdr12;
671 };
673 &mmc2 {
674 status = "okay";
675 vmmc-supply = <&evm_3v3_sw>;
676 bus-width = <8>;
677 pinctrl-names = "default", "hs", "ddr_3_3v";
678 pinctrl-0 = <&mmc2_pins_default>;
679 pinctrl-1 = <&mmc2_pins_hs>;
680 pinctrl-2 = <&mmc2_pins_ddr_3_3v &mmc2_iodelay_ddr_3_3v_conf>;
681 mmc-ddr-1_8v;
682 };
684 &mmc4 {
685 status = "okay";
686 vmmc-supply = <&vmmcwl_fixed>;
687 bus-width = <4>;
688 cap-power-off-card;
689 keep-power-in-suspend;
690 ti,non-removable;
692 #address-cells = <1>;
693 #size-cells = <0>;
694 wlcore: wlcore@0 {
695 compatible = "ti,wlcore";
696 reg = <2>;
697 interrupt-parent = <&gpio5>;
698 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
699 };
700 };
702 &cpu0 {
703 cpu0-voltdm = <&voltdm_mpu>;
704 voltage-tolerance = <1>;
705 };
707 &voltdm_mpu {
708 vdd-supply = <&smps123_reg>;
709 };
711 &voltdm_dspeve {
712 vdd-supply = <&smps45_reg>;
713 };
715 &voltdm_gpu {
716 vdd-supply = <&smps6_reg>;
717 };
719 &voltdm_ivahd {
720 vdd-supply = <&smps8_reg>;
721 };
723 &voltdm_core {
724 vdd-supply = <&smps7_reg>;
725 };
727 &qspi {
728 status = "okay";
730 spi-max-frequency = <48000000>;
731 m25p80@0 {
732 compatible = "s25fl256s1";
733 spi-max-frequency = <48000000>;
734 reg = <0>;
735 spi-tx-bus-width = <1>;
736 spi-rx-bus-width = <4>;
737 spi-cpol;
738 spi-cpha;
739 #address-cells = <1>;
740 #size-cells = <1>;
742 /* MTD partition table.
743 * The ROM checks the first four physical blocks
744 * for a valid file to boot and the flash here is
745 * 64KiB block size.
746 */
747 partition@0 {
748 label = "QSPI.SPL";
749 reg = <0x00000000 0x000010000>;
750 };
751 partition@1 {
752 label = "QSPI.SPL.backup1";
753 reg = <0x00010000 0x00010000>;
754 };
755 partition@2 {
756 label = "QSPI.SPL.backup2";
757 reg = <0x00020000 0x00010000>;
758 };
759 partition@3 {
760 label = "QSPI.SPL.backup3";
761 reg = <0x00030000 0x00010000>;
762 };
763 partition@4 {
764 label = "QSPI.u-boot";
765 reg = <0x00040000 0x00100000>;
766 };
767 partition@5 {
768 label = "QSPI.u-boot-spl-os";
769 reg = <0x00140000 0x00080000>;
770 };
771 partition@6 {
772 label = "QSPI.u-boot-env";
773 reg = <0x001c0000 0x00010000>;
774 };
775 partition@7 {
776 label = "QSPI.u-boot-env.backup1";
777 reg = <0x001d0000 0x0010000>;
778 };
779 partition@8 {
780 label = "QSPI.kernel";
781 reg = <0x001e0000 0x0800000>;
782 };
783 partition@9 {
784 label = "QSPI.file-system";
785 reg = <0x009e0000 0x01620000>;
786 };
787 };
788 };
790 &omap_dwc3_1 {
791 extcon = <&extcon_usb1>;
792 };
794 &omap_dwc3_2 {
795 extcon = <&extcon_usb2>;
796 };
798 &usb1 {
799 dr_mode = "otg";
800 };
802 &usb2 {
803 dr_mode = "host";
804 };
806 &mac {
807 status = "okay";
808 dual_emac;
809 };
811 &cpsw_emac0 {
812 phy_id = <&davinci_mdio>, <2>;
813 phy-mode = "rgmii";
814 dual_emac_res_vlan = <1>;
815 };
817 &cpsw_emac1 {
818 phy_id = <&davinci_mdio>, <3>;
819 phy-mode = "rgmii";
820 dual_emac_res_vlan = <2>;
821 };
823 &elm {
824 status = "okay";
825 };
827 &gpmc {
828 status = "disabled";
829 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
830 nand@0,0 {
831 reg = <0 0 4>; /* device IO registers */
832 ti,nand-ecc-opt = "bch8";
833 ti,elm-id = <&elm>;
834 nand-bus-width = <16>;
835 gpmc,device-width = <2>;
836 gpmc,sync-clk-ps = <0>;
837 gpmc,cs-on-ns = <0>;
838 gpmc,cs-rd-off-ns = <80>;
839 gpmc,cs-wr-off-ns = <80>;
840 gpmc,adv-on-ns = <0>;
841 gpmc,adv-rd-off-ns = <60>;
842 gpmc,adv-wr-off-ns = <60>;
843 gpmc,we-on-ns = <10>;
844 gpmc,we-off-ns = <50>;
845 gpmc,oe-on-ns = <4>;
846 gpmc,oe-off-ns = <40>;
847 gpmc,access-ns = <40>;
848 gpmc,wr-access-ns = <80>;
849 gpmc,rd-cycle-ns = <80>;
850 gpmc,wr-cycle-ns = <80>;
851 gpmc,bus-turnaround-ns = <0>;
852 gpmc,cycle2cycle-delay-ns = <0>;
853 gpmc,clk-activation-ns = <0>;
854 gpmc,wait-monitoring-ns = <0>;
855 gpmc,wr-data-mux-bus-ns = <0>;
856 /* MTD partition table */
857 /* All SPL-* partitions are sized to minimal length
858 * which can be independently programmable. For
859 * NAND flash this is equal to size of erase-block */
860 #address-cells = <1>;
861 #size-cells = <1>;
862 partition@0 {
863 label = "NAND.SPL";
864 reg = <0x00000000 0x000020000>;
865 };
866 partition@1 {
867 label = "NAND.SPL.backup1";
868 reg = <0x00020000 0x00020000>;
869 };
870 partition@2 {
871 label = "NAND.SPL.backup2";
872 reg = <0x00040000 0x00020000>;
873 };
874 partition@3 {
875 label = "NAND.SPL.backup3";
876 reg = <0x00060000 0x00020000>;
877 };
878 partition@4 {
879 label = "NAND.u-boot-spl-os";
880 reg = <0x00080000 0x00040000>;
881 };
882 partition@5 {
883 label = "NAND.u-boot";
884 reg = <0x000c0000 0x00100000>;
885 };
886 partition@6 {
887 label = "NAND.u-boot-env";
888 reg = <0x001c0000 0x00020000>;
889 };
890 partition@7 {
891 label = "NAND.u-boot-env.backup1";
892 reg = <0x001e0000 0x00020000>;
893 };
894 partition@8 {
895 label = "NAND.kernel";
896 reg = <0x00200000 0x00800000>;
897 };
898 partition@9 {
899 label = "NAND.file-system";
900 reg = <0x00a00000 0x0f600000>;
901 };
902 };
903 };
905 &gpio7 {
906 ti,no-reset-on-init;
907 ti,no-idle-on-init;
908 };
910 &dss {
911 status = "ok";
913 vdda_video-supply = <&ldoln_reg>;
914 };
916 &hdmi {
917 status = "ok";
918 vdda-supply = <&ldo3_reg>;
920 port {
921 hdmi_out: endpoint {
922 remote-endpoint = <&tpd12s015_in>;
923 };
924 };
925 };
927 &dcan1 {
928 status = "ok";
929 pinctrl-names = "default", "sleep";
930 pinctrl-0 = <&dcan1_pins_default>;
931 pinctrl-1 = <&dcan1_pins_sleep>;
932 };
934 &mailbox5 {
935 status = "okay";
936 mbox_ipu1_legacy: mbox_ipu1_legacy {
937 status = "okay";
938 };
939 mbox_dsp1_legacy: mbox_dsp1_legacy {
940 status = "okay";
941 };
942 };
944 &mailbox6 {
945 status = "okay";
946 mbox_ipu2_legacy: mbox_ipu2_legacy {
947 status = "okay";
948 };
949 mbox_dsp2_legacy: mbox_dsp2_legacy {
950 status = "okay";
951 };
952 };
954 &mmu0_dsp1 {
955 status = "okay";
956 };
958 &mmu1_dsp1 {
959 status = "okay";
960 };
962 &mmu0_dsp2 {
963 status = "okay";
964 };
966 &mmu1_dsp2 {
967 status = "okay";
968 };
970 &mmu_ipu1 {
971 status = "okay";
972 };
974 &mmu_ipu2 {
975 status = "okay";
976 };
978 &ipu2 {
979 status = "okay";
980 memory-region = <&ipu2_cma_pool>;
981 mboxes = <&mailbox6 &mbox_ipu2_legacy>;
982 timers = <&timer3>;
983 watchdog-timers = <&timer4>, <&timer9>;
984 };
986 &ipu1 {
987 status = "okay";
988 memory-region = <&ipu1_cma_pool>;
989 mboxes = <&mailbox5 &mbox_ipu1_legacy>;
990 timers = <&timer11>;
991 watchdog-timers = <&timer7>, <&timer8>;
992 };
994 &dsp1 {
995 status = "okay";
996 memory-region = <&dsp1_cma_pool>;
997 mboxes = <&mailbox5 &mbox_dsp1_legacy>;
998 timers = <&timer5>;
999 watchdog-timers = <&timer10>;
1000 };
1002 &dsp2 {
1003 status = "okay";
1004 memory-region = <&dsp2_cma_pool>;
1005 mboxes = <&mailbox6 &mbox_dsp2_legacy>;
1006 timers = <&timer6>;
1007 };
1009 &atl {
1010 status = "okay";
1012 atl2 {
1013 bws = <DRA7_ATL_WS_MCASP2_FSX>;
1014 aws = <DRA7_ATL_WS_MCASP3_FSX>;
1015 };
1016 };
1018 &mcasp3 {
1019 fck_parent = "atl_clkin2_ck";
1021 status = "okay";
1023 op-mode = <0>; /* MCASP_IIS_MODE */
1024 tdm-slots = <2>;
1025 /* 4 serializer */
1026 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1027 1 2 0 0
1028 >;
1029 };
1031 &mcasp7 {
1032 #sound-dai-cells = <0>;
1034 status = "okay";
1036 op-mode = <0>; /* MCASP_IIS_MODE */
1037 tdm-slots = <4>;
1038 /* 4 serializer */
1039 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1040 2 1 0 0
1041 >;
1042 tx-num-evt = <8>;
1043 rx-num-evt = <8>;
1044 };
1046 &usb2_phy1 {
1047 phy-supply = <&ldousb_reg>;
1048 };
1050 &usb2_phy2 {
1051 phy-supply = <&ldousb_reg>;
1052 };
1054 &vip1 {
1055 status = "okay";
1056 };
1058 &vin1a {
1059 endpoint@0 {
1060 slave-mode;
1061 remote-endpoint = <&onboardLI>;
1062 };
1063 };
1065 #include "dra7xx-jamr3.dtsi"