1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra74x.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/clk/ti-dra7-atl.h>
15 / {
16 model = "TI DRA742";
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
19 memory {
20 device_type = "memory";
21 reg = <0x80000000 0x60000000>; /* 1536 MB */
22 };
24 reserved_mem: reserved-memory {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges;
29 ipu2_cma_pool: ipu2_cma@95800000 {
30 compatible = "shared-dma-pool";
31 reg = <0x95800000 0x3800000>;
32 reusable;
33 status = "okay";
34 };
36 dsp1_cma_pool: dsp1_cma@99000000 {
37 compatible = "shared-dma-pool";
38 reg = <0x99000000 0x4000000>;
39 reusable;
40 status = "okay";
41 };
43 ipu1_cma_pool: ipu1_cma@9d000000 {
44 compatible = "shared-dma-pool";
45 reg = <0x9d000000 0x2000000>;
46 reusable;
47 status = "okay";
48 };
50 dsp2_cma_pool: dsp2_cma@9f000000 {
51 compatible = "shared-dma-pool";
52 reg = <0x9f000000 0x800000>;
53 reusable;
54 status = "okay";
55 };
56 };
58 extcon_usb1: extcon_usb1 {
59 compatible = "linux,extcon-usb-gpio";
60 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
61 };
63 extcon_usb2: extcon_usb2 {
64 compatible = "linux,extcon-usb-gpio";
65 id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
66 };
68 evm_3v3_sd: fixedregulator-sd {
69 compatible = "regulator-fixed";
70 regulator-name = "evm_3v3_sd";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 enable-active-high;
74 gpio = <&pcf_gpio_21 5 0>;
75 };
77 evm_3v3_sw: fixedregulator-evm_3v3_sw {
78 compatible = "regulator-fixed";
79 regulator-name = "evm_3v3_sw";
80 vin-supply = <&sysen1>;
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 };
85 aic_dvdd: fixedregulator-aic_dvdd {
86 /* TPS77018DBVT */
87 compatible = "regulator-fixed";
88 regulator-name = "aic_dvdd";
89 vin-supply = <&evm_3v3_sw>;
90 regulator-min-microvolt = <1800000>;
91 regulator-max-microvolt = <1800000>;
92 };
94 vmmcwl_fixed: fixedregulator-mmcwl {
95 compatible = "regulator-fixed";
96 regulator-name = "vmmcwl_fixed";
97 regulator-min-microvolt = <1800000>;
98 regulator-max-microvolt = <1800000>;
99 gpio = <&gpio5 8 0>; /* gpio5_8 */
100 startup-delay-us = <70000>;
101 enable-active-high;
102 };
104 kim {
105 compatible = "kim";
106 nshutdown_gpio = <132>;
107 dev_name = "/dev/ttyS2";
108 flow_cntrl = <1>;
109 baud_rate = <3686400>;
110 };
112 btwilink {
113 compatible = "btwilink";
114 };
116 vtt_fixed: fixedregulator-vtt {
117 compatible = "regulator-fixed";
118 regulator-name = "vtt_fixed";
119 regulator-min-microvolt = <1350000>;
120 regulator-max-microvolt = <1350000>;
121 regulator-always-on;
122 regulator-boot-on;
123 enable-active-high;
124 vin-supply = <&sysen2>;
125 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
126 };
128 aliases {
129 display0 = &hdmi0;
130 sound0 = &primary_sound;
131 sound1 = &hdmi;
132 };
134 hdmi0: connector@1 {
135 compatible = "hdmi-connector";
136 label = "hdmi";
138 type = "a";
140 port {
141 hdmi_connector_in: endpoint {
142 remote-endpoint = <&tpd12s015_out>;
143 };
144 };
145 };
147 tpd12s015: encoder@1 {
148 compatible = "ti,dra7evm-tpd12s015";
150 gpios = <&pcf_hdmi 4 0>, /* P4, CT CP HPD */
151 <&pcf_hdmi 5 0>, /* P5, LS OE */
152 <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
154 ports {
155 #address-cells = <1>;
156 #size-cells = <0>;
158 port@0 {
159 reg = <0>;
161 tpd12s015_in: endpoint@0 {
162 remote-endpoint = <&hdmi_out>;
163 };
164 };
166 port@1 {
167 reg = <1>;
169 tpd12s015_out: endpoint@0 {
170 remote-endpoint = <&hdmi_connector_in>;
171 };
172 };
173 };
174 };
176 ocp {
177 gpu: gpu@0x56000000 {
178 gpu0-voltdm = <&voltdm_gpu>;
179 };
180 };
182 primary_sound: primary_sound {
183 compatible = "ti,dra7xx-evm-audio";
184 ti,model = "DRA7xx-EVM";
185 ti,always-on;
186 ti,audio-codec = <&tlv320aic3106>;
187 ti,mcasp-controller = <&mcasp3>;
188 ti,codec-clock-rate = <11289600>;
189 clocks = <&atl_clkin2_ck>;
190 clock-names = "mclk";
191 ti,audio-routing =
192 "Headphone Jack", "HPLOUT",
193 "Headphone Jack", "HPROUT",
194 "Line Out", "LLOUT",
195 "Line Out", "RLOUT",
196 "MIC3L", "Mic Jack",
197 "MIC3R", "Mic Jack",
198 "Mic Jack", "Mic Bias",
199 "LINE1L", "Line In",
200 "LINE1R", "Line In";
201 };
203 btwilink_sound: btwilink_sound {
204 #sound-dai-cells = <0>;
205 compatible = "linux,bt-sco-audio";
206 status = "okay";
207 };
209 simple_bt_sco_card: bt_sco_card {
210 compatible = "simple-audio-card";
211 simple-audio-card,name = "DRA7xx-WiLink";
212 simple-audio-card,format = "dsp_a";
213 simple-audio-card,frame-master = <&btwilink_codec>;
214 simple-audio-card,bitclock-master = <&btwilink_codec>;
215 simple-audio-card,frame-inversion;
217 simple-audio-card,cpu {
218 sound-dai = <&mcasp7>;
219 };
221 btwilink_codec: simple-audio-card,codec {
222 sound-dai = <&btwilink_sound>;
223 };
224 };
225 };
227 &dra7_pmx_core {
228 i2c2_pins: pinmux_i2c2_pins {
229 pinctrl-single,pins = <
230 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
231 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
232 >;
233 };
235 dcan1_pins_default: dcan1_pins_default {
236 pinctrl-single,pins = <
237 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
238 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
239 >;
240 };
242 dcan1_pins_sleep: dcan1_pins_sleep {
243 pinctrl-single,pins = <
244 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
245 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
246 >;
247 };
249 mmc1_pins_default: pinmux_mmc1_default_pins {
250 pinctrl-single,pins = <
251 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
252 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
253 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
254 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
255 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
256 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
257 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio187 */
258 >;
259 };
261 mmc1_pins_hs: pinmux_mmc1_hs_pins {
262 pinctrl-single,pins = <
263 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
264 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
265 0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
266 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
267 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
268 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
269 >;
270 };
272 mmc2_pins_default: mmc2_pins_default {
273 pinctrl-single,pins = <
274 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
275 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
276 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
277 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
278 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
279 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
280 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
281 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
282 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
283 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
284 >;
285 };
287 mmc2_pins_hs: pinmux_mmc2_hs_pins {
288 pinctrl-single,pins = <
289 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
290 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
291 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
292 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
293 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
294 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
295 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
296 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
297 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
298 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
299 >;
300 };
301 };
303 &i2c1 {
304 status = "okay";
305 clock-frequency = <400000>;
307 tps659038: tps659038@58 {
308 compatible = "ti,tps659038";
309 reg = <0x58>;
311 tps659038_pmic {
312 compatible = "ti,tps659038-pmic";
314 regulators {
315 smps123_reg: smps123 {
316 /* VDD_MPU */
317 regulator-name = "smps123";
318 regulator-min-microvolt = < 850000>;
319 regulator-max-microvolt = <1250000>;
320 regulator-always-on;
321 regulator-boot-on;
322 };
324 smps45_reg: smps45 {
325 /* VDD_DSPEVE */
326 regulator-name = "smps45";
327 regulator-min-microvolt = < 850000>;
328 regulator-max-microvolt = <1150000>;
329 regulator-boot-on;
330 regulator-always-on;
331 };
333 smps6_reg: smps6 {
334 /* VDD_GPU - over VDD_SMPS6 */
335 regulator-name = "smps6";
336 regulator-min-microvolt = <850000>;
337 regulator-max-microvolt = <1250000>;
338 regulator-boot-on;
339 regulator-always-on;
340 };
342 smps7_reg: smps7 {
343 /* CORE_VDD */
344 regulator-name = "smps7";
345 regulator-min-microvolt = <850000>;
346 regulator-max-microvolt = <1060000>;
347 regulator-always-on;
348 regulator-boot-on;
349 };
351 smps8_reg: smps8 {
352 /* VDD_IVAHD */
353 regulator-name = "smps8";
354 regulator-min-microvolt = < 850000>;
355 regulator-max-microvolt = <1250000>;
356 regulator-boot-on;
357 regulator-always-on;
358 };
360 smps9_reg: smps9 {
361 /* VDDS1V8 */
362 regulator-name = "smps9";
363 regulator-min-microvolt = <1800000>;
364 regulator-max-microvolt = <1800000>;
365 regulator-always-on;
366 regulator-boot-on;
367 };
369 ldo1_reg: ldo1 {
370 /* LDO1_OUT --> SDIO */
371 regulator-name = "ldo1";
372 regulator-min-microvolt = <1800000>;
373 regulator-max-microvolt = <3300000>;
374 regulator-boot-on;
375 regulator-always-on;
376 };
378 ldo2_reg: ldo2 {
379 /* VDD_RTCIO */
380 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
381 regulator-name = "ldo2";
382 regulator-min-microvolt = <3300000>;
383 regulator-max-microvolt = <3300000>;
384 regulator-boot-on;
385 regulator-always-on;
386 };
388 ldo3_reg: ldo3 {
389 /* VDDA_1V8_PHY */
390 regulator-name = "ldo3";
391 regulator-min-microvolt = <1800000>;
392 regulator-max-microvolt = <1800000>;
393 regulator-always-on;
394 regulator-boot-on;
395 };
397 ldo9_reg: ldo9 {
398 /* VDD_RTC */
399 regulator-name = "ldo9";
400 regulator-min-microvolt = <1050000>;
401 regulator-max-microvolt = <1050000>;
402 regulator-boot-on;
403 regulator-always-on;
404 };
406 ldoln_reg: ldoln {
407 /* VDDA_1V8_PLL */
408 regulator-name = "ldoln";
409 regulator-min-microvolt = <1800000>;
410 regulator-max-microvolt = <1800000>;
411 regulator-always-on;
412 regulator-boot-on;
413 };
415 ldousb_reg: ldousb {
416 /* VDDA_3V_USB: VDDA_USBHS33 */
417 regulator-name = "ldousb";
418 regulator-min-microvolt = <3300000>;
419 regulator-max-microvolt = <3300000>;
420 regulator-boot-on;
421 regulator-always-on;
422 };
424 /* REGEN1 is unused */
426 regen2: regen2 {
427 /* Needed for PMIC internal resources */
428 regulator-name = "regen2";
429 regulator-boot-on;
430 regulator-always-on;
431 };
433 /* REGEN3 is unused */
435 sysen1: sysen1 {
436 /* PMIC_REGEN_3V3 */
437 regulator-name = "sysen1";
438 regulator-boot-on;
439 regulator-always-on;
440 };
442 sysen2: sysen2 {
443 /* PMIC_REGEN_DDR */
444 regulator-name = "sysen2";
445 regulator-boot-on;
446 regulator-always-on;
447 };
448 };
449 };
450 };
452 pcf_lcd: gpio@20 {
453 compatible = "nxp,pcf8575";
454 reg = <0x20>;
455 gpio-controller;
456 #gpio-cells = <2>;
457 };
459 pcf_gpio_21: gpio@21 {
460 compatible = "nxp,pcf8575";
461 reg = <0x21>;
462 lines-initial-states = <0x1408>;
463 gpio-controller;
464 #gpio-cells = <2>;
465 interrupt-parent = <&gpio6>;
466 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
467 interrupt-controller;
468 #interrupt-cells = <2>;
469 };
471 mxt244: touchscreen@4a {
472 compatible = "atmel,mXT244";
473 status = "okay";
474 reg = <0x4a>;
475 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
477 atmel,config = <
478 /* MXT244_GEN_COMMAND(6) */
479 0x00 0x00 0x00 0x00 0x00 0x00
480 /* MXT244_GEN_POWER(7) */
481 0x20 0xff 0x32
482 /* MXT244_GEN_ACQUIRE(8) */
483 0x0a 0x00 0x05 0x00 0x00 0x00 0x09 0x23
484 /* MXT244_TOUCH_MULTI(9) */
485 0x00 0x00 0x00 0x13 0x0b 0x00 0x00 0x00 0x02 0x00
486 0x00 0x01 0x01 0x0e 0x0a 0x0a 0x0a 0x0a 0x00 0x00
487 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
488 0x00
489 /* MXT244_TOUCH_KEYARRAY(15) */
490 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
491 0x00
492 /* MXT244_COMMSCONFIG_T18(2) */
493 0x00 0x00
494 /* MXT244_SPT_GPIOPWM(19) */
495 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
496 0x00 0x00 0x00 0x00 0x00 0x00
497 /* MXT244_PROCI_GRIPFACE(20) */
498 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x28 0x04
499 0x0f 0x0a
500 /* MXT244_PROCG_NOISE(22) */
501 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0x23 0x00
502 0x00 0x05 0x0f 0x19 0x23 0x2d 0x03
503 /* MXT244_TOUCH_PROXIMITY(23) */
504 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
505 0x00 0x00 0x00 0x00 0x00
506 /* MXT244_PROCI_ONETOUCH(24) */
507 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
508 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
509 /* MXT244_SPT_SELFTEST(25) */
510 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
511 0x00 0x00 0x00 0x00
512 /* MXT244_PROCI_TWOTOUCH(27) */
513 0x00 0x00 0x00 0x00 0x00 0x00 0x00
514 /* MXT244_SPT_CTECONFIG(28) */
515 0x00 0x00 0x02 0x08 0x10 0x00
516 >;
518 atmel,x_line = <18>;
519 atmel,y_line = <12>;
520 atmel,x_size = <800>;
521 atmel,y_size = <480>;
522 atmel,blen = <0x01>;
523 atmel,threshold = <30>;
524 atmel,voltage = <2800000>;
525 atmel,orient = <0x4>;
526 };
528 tlv320aic3106: tlv320aic3106@18 {
529 compatible = "ti,tlv320aic3106";
530 reg = <0x18>;
531 adc-settle-ms = <40>;
532 ai3x-micbias-vg = <1>; /* 2.0V */
533 status = "okay";
535 /* Regulators */
536 AVDD-supply = <&evm_3v3_sw>;
537 IOVDD-supply = <&evm_3v3_sw>;
538 DRVDD-supply = <&evm_3v3_sw>;
539 DVDD-supply = <&aic_dvdd>;
540 };
541 };
543 i2c_p3_exp: &i2c2 {
544 status = "okay";
545 pinctrl-names = "default";
546 pinctrl-0 = <&i2c2_pins>;
547 clock-frequency = <400000>;
549 pcf_hdmi: gpio@26 {
550 compatible = "nxp,pcf8575";
551 reg = <0x26>;
552 lines-initial-states = <0xffeb>;
553 gpio-controller;
554 #gpio-cells = <2>;
555 };
557 ov10633@37 {
558 compatible = "ovti,ov10633";
559 reg = <0x37>;
561 mux-gpios = <&pcf_hdmi 3 GPIO_ACTIVE_LOW>; /* CAM_FPD_MUX_S0 */
562 port {
563 onboardLI: endpoint {
564 remote-endpoint = <&vin1a>;
565 hsync-active = <1>;
566 vsync-active = <1>;
567 pclk-sample = <1>;
568 };
569 };
570 };
571 };
573 &i2c3 {
574 status = "okay";
575 clock-frequency = <3400000>;
576 };
578 &mcspi1 {
579 status = "okay";
580 };
582 &mcspi2 {
583 status = "okay";
584 };
586 &uart1 {
587 status = "okay";
588 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
589 &dra7_pmx_core 0x3e0>;
590 };
592 &uart2 {
593 status = "okay";
594 };
596 &uart3 {
597 status = "okay";
598 gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
599 };
601 &mmc1 {
602 status = "okay";
603 pbias-supply = <&pbias_mmc_reg>;
604 vmmc-supply = <&evm_3v3_sd>;
605 vmmc_aux-supply = <&ldo1_reg>;
606 bus-width = <4>;
607 /*
608 * SDCD signal is not being used here - using the fact that GPIO mode
609 * is always hardwired.
610 */
611 cd-gpios = <&gpio6 27 0>;
612 pinctrl-names = "default", "hs";
613 pinctrl-0 = <&mmc1_pins_default>;
614 pinctrl-1 = <&mmc1_pins_hs>;
615 };
617 &mmc2 {
618 status = "okay";
619 vmmc-supply = <&evm_3v3_sw>;
620 bus-width = <8>;
621 pinctrl-names = "default", "hs";
622 pinctrl-0 = <&mmc2_pins_default>;
623 pinctrl-1 = <&mmc2_pins_hs>;
624 };
626 &mmc4 {
627 status = "okay";
628 vmmc-supply = <&vmmcwl_fixed>;
629 bus-width = <4>;
630 cap-power-off-card;
631 keep-power-in-suspend;
632 ti,non-removable;
634 #address-cells = <1>;
635 #size-cells = <0>;
636 wlcore: wlcore@0 {
637 compatible = "ti,wlcore";
638 reg = <2>;
639 interrupt-parent = <&gpio5>;
640 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
641 };
642 };
644 &cpu0 {
645 cpu0-voltdm = <&voltdm_mpu>;
646 voltage-tolerance = <1>;
647 };
649 &voltdm_mpu {
650 vdd-supply = <&smps123_reg>;
651 };
653 &voltdm_dspeve {
654 vdd-supply = <&smps45_reg>;
655 };
657 &voltdm_gpu {
658 vdd-supply = <&smps6_reg>;
659 };
661 &voltdm_ivahd {
662 vdd-supply = <&smps8_reg>;
663 };
665 &voltdm_core {
666 vdd-supply = <&smps7_reg>;
667 };
669 &qspi {
670 status = "okay";
672 spi-max-frequency = <48000000>;
673 m25p80@0 {
674 compatible = "s25fl256s1";
675 spi-max-frequency = <48000000>;
676 reg = <0>;
677 spi-tx-bus-width = <1>;
678 spi-rx-bus-width = <4>;
679 spi-cpol;
680 spi-cpha;
681 #address-cells = <1>;
682 #size-cells = <1>;
684 /* MTD partition table.
685 * The ROM checks the first four physical blocks
686 * for a valid file to boot and the flash here is
687 * 64KiB block size.
688 */
689 partition@0 {
690 label = "QSPI.SPL";
691 reg = <0x00000000 0x000010000>;
692 };
693 partition@1 {
694 label = "QSPI.SPL.backup1";
695 reg = <0x00010000 0x00010000>;
696 };
697 partition@2 {
698 label = "QSPI.SPL.backup2";
699 reg = <0x00020000 0x00010000>;
700 };
701 partition@3 {
702 label = "QSPI.SPL.backup3";
703 reg = <0x00030000 0x00010000>;
704 };
705 partition@4 {
706 label = "QSPI.u-boot";
707 reg = <0x00040000 0x00100000>;
708 };
709 partition@5 {
710 label = "QSPI.u-boot-spl-os";
711 reg = <0x00140000 0x00080000>;
712 };
713 partition@6 {
714 label = "QSPI.u-boot-env";
715 reg = <0x001c0000 0x00010000>;
716 };
717 partition@7 {
718 label = "QSPI.u-boot-env.backup1";
719 reg = <0x001d0000 0x0010000>;
720 };
721 partition@8 {
722 label = "QSPI.kernel";
723 reg = <0x001e0000 0x0800000>;
724 };
725 partition@9 {
726 label = "QSPI.file-system";
727 reg = <0x009e0000 0x01620000>;
728 };
729 };
730 };
732 &omap_dwc3_1 {
733 extcon = <&extcon_usb1>;
734 };
736 &omap_dwc3_2 {
737 extcon = <&extcon_usb2>;
738 };
740 &usb1 {
741 dr_mode = "peripheral";
742 };
744 &usb2 {
745 dr_mode = "host";
746 };
748 &mac {
749 status = "okay";
750 dual_emac;
751 };
753 &cpsw_emac0 {
754 phy_id = <&davinci_mdio>, <2>;
755 phy-mode = "rgmii";
756 dual_emac_res_vlan = <1>;
757 };
759 &cpsw_emac1 {
760 phy_id = <&davinci_mdio>, <3>;
761 phy-mode = "rgmii";
762 dual_emac_res_vlan = <2>;
763 };
765 &elm {
766 status = "okay";
767 };
769 &gpmc {
770 status = "disabled";
771 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
772 nand@0,0 {
773 reg = <0 0 4>; /* device IO registers */
774 ti,nand-ecc-opt = "bch8";
775 ti,elm-id = <&elm>;
776 nand-bus-width = <16>;
777 gpmc,device-width = <2>;
778 gpmc,sync-clk-ps = <0>;
779 gpmc,cs-on-ns = <0>;
780 gpmc,cs-rd-off-ns = <80>;
781 gpmc,cs-wr-off-ns = <80>;
782 gpmc,adv-on-ns = <0>;
783 gpmc,adv-rd-off-ns = <60>;
784 gpmc,adv-wr-off-ns = <60>;
785 gpmc,we-on-ns = <10>;
786 gpmc,we-off-ns = <50>;
787 gpmc,oe-on-ns = <4>;
788 gpmc,oe-off-ns = <40>;
789 gpmc,access-ns = <40>;
790 gpmc,wr-access-ns = <80>;
791 gpmc,rd-cycle-ns = <80>;
792 gpmc,wr-cycle-ns = <80>;
793 gpmc,bus-turnaround-ns = <0>;
794 gpmc,cycle2cycle-delay-ns = <0>;
795 gpmc,clk-activation-ns = <0>;
796 gpmc,wait-monitoring-ns = <0>;
797 gpmc,wr-data-mux-bus-ns = <0>;
798 /* MTD partition table */
799 /* All SPL-* partitions are sized to minimal length
800 * which can be independently programmable. For
801 * NAND flash this is equal to size of erase-block */
802 #address-cells = <1>;
803 #size-cells = <1>;
804 partition@0 {
805 label = "NAND.SPL";
806 reg = <0x00000000 0x000020000>;
807 };
808 partition@1 {
809 label = "NAND.SPL.backup1";
810 reg = <0x00020000 0x00020000>;
811 };
812 partition@2 {
813 label = "NAND.SPL.backup2";
814 reg = <0x00040000 0x00020000>;
815 };
816 partition@3 {
817 label = "NAND.SPL.backup3";
818 reg = <0x00060000 0x00020000>;
819 };
820 partition@4 {
821 label = "NAND.u-boot-spl-os";
822 reg = <0x00080000 0x00040000>;
823 };
824 partition@5 {
825 label = "NAND.u-boot";
826 reg = <0x000c0000 0x00100000>;
827 };
828 partition@6 {
829 label = "NAND.u-boot-env";
830 reg = <0x001c0000 0x00020000>;
831 };
832 partition@7 {
833 label = "NAND.u-boot-env.backup1";
834 reg = <0x001e0000 0x00020000>;
835 };
836 partition@8 {
837 label = "NAND.kernel";
838 reg = <0x00200000 0x00800000>;
839 };
840 partition@9 {
841 label = "NAND.file-system";
842 reg = <0x00a00000 0x0f600000>;
843 };
844 };
845 };
847 &gpio7 {
848 ti,no-reset-on-init;
849 ti,no-idle-on-init;
850 };
852 &dss {
853 status = "ok";
855 vdda_video-supply = <&ldoln_reg>;
856 };
858 &hdmi {
859 status = "ok";
860 vdda-supply = <&ldo3_reg>;
862 port {
863 hdmi_out: endpoint {
864 remote-endpoint = <&tpd12s015_in>;
865 };
866 };
867 };
869 &dcan1 {
870 status = "ok";
871 pinctrl-names = "default", "sleep";
872 pinctrl-0 = <&dcan1_pins_default>;
873 pinctrl-1 = <&dcan1_pins_sleep>;
874 };
876 &mailbox5 {
877 status = "okay";
878 mbox_ipu1_legacy: mbox_ipu1_legacy {
879 status = "okay";
880 };
881 mbox_dsp1_legacy: mbox_dsp1_legacy {
882 status = "okay";
883 };
884 };
886 &mailbox6 {
887 status = "okay";
888 mbox_ipu2_legacy: mbox_ipu2_legacy {
889 status = "okay";
890 };
891 mbox_dsp2_legacy: mbox_dsp2_legacy {
892 status = "okay";
893 };
894 };
896 &mmu0_dsp1 {
897 status = "okay";
898 };
900 &mmu1_dsp1 {
901 status = "okay";
902 };
904 &mmu0_dsp2 {
905 status = "okay";
906 };
908 &mmu1_dsp2 {
909 status = "okay";
910 };
912 &mmu_ipu1 {
913 status = "okay";
914 };
916 &mmu_ipu2 {
917 status = "okay";
918 };
920 &ipu2 {
921 status = "okay";
922 memory-region = <&ipu2_cma_pool>;
923 mboxes = <&mailbox6 &mbox_ipu2_legacy>;
924 timers = <&timer3>;
925 watchdog-timers = <&timer4>, <&timer9>;
926 };
928 &ipu1 {
929 status = "okay";
930 memory-region = <&ipu1_cma_pool>;
931 mboxes = <&mailbox5 &mbox_ipu1_legacy>;
932 timers = <&timer11>;
933 watchdog-timers = <&timer7>, <&timer8>;
934 };
936 &dsp1 {
937 status = "okay";
938 memory-region = <&dsp1_cma_pool>;
939 mboxes = <&mailbox5 &mbox_dsp1_legacy>;
940 timers = <&timer5>;
941 watchdog-timers = <&timer10>;
942 };
944 &dsp2 {
945 status = "okay";
946 memory-region = <&dsp2_cma_pool>;
947 mboxes = <&mailbox6 &mbox_dsp2_legacy>;
948 timers = <&timer6>;
949 };
951 &atl {
952 status = "okay";
954 atl2 {
955 bws = <DRA7_ATL_WS_MCASP2_FSX>;
956 aws = <DRA7_ATL_WS_MCASP3_FSX>;
957 };
958 };
960 &mcasp3 {
961 fck_parent = "atl_clkin2_ck";
963 status = "okay";
965 op-mode = <0>; /* MCASP_IIS_MODE */
966 tdm-slots = <2>;
967 /* 4 serializer */
968 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
969 1 2 0 0
970 >;
971 };
973 &mcasp7 {
974 #sound-dai-cells = <0>;
976 status = "okay";
978 op-mode = <0>; /* MCASP_IIS_MODE */
979 tdm-slots = <4>;
980 /* 4 serializer */
981 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
982 2 1 0 0
983 >;
984 tx-num-evt = <8>;
985 rx-num-evt = <8>;
986 };
988 &usb2_phy1 {
989 phy-supply = <&ldousb_reg>;
990 };
992 &usb2_phy2 {
993 phy-supply = <&ldousb_reg>;
994 };
996 &vip1 {
997 status = "okay";
998 };
1000 &vin1a {
1001 endpoint@0 {
1002 slave-mode;
1003 remote-endpoint = <&onboardLI>;
1004 };
1005 };
1007 #include "dra7xx-jamr3.dtsi"