3259f2b5c9e47d927b9807f55ca4ebfd88977cf6
1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
10 /include/ "skeleton.dtsi"
12 / {
13 compatible = "ti,dra7xx";
14 interrupt-parent = <&gic>;
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
22 serial5 = &uart6;
23 };
25 cpus {
26 cpu@0 {
27 compatible = "arm,cortex-a15";
28 operating-points = <
29 /* kHz uV */
30 /* The OPP_HIGH Only for DVFS enabled Samples */
31 1000000 1090000
32 1176000 1210000
33 >;
34 clocks = <&dpll_mpu>;
35 clock-names = "cpu";
36 timer {
37 compatible = "arm,armv7-timer";
38 /*
39 * PPI secure/nonsecure IRQ,
40 * active low level-sensitive
41 */
42 interrupts = <1 13 0x308>,
43 <1 14 0x308>;
44 clock-frequency = <6144000>;
45 };
46 };
47 cpu@1 {
48 compatible = "arm,cortex-a15";
49 timer {
50 compatible = "arm,armv7-timer";
51 /*
52 * PPI secure/nonsecure IRQ,
53 * active low level-sensitive
54 */
55 interrupts = <1 13 0x308>,
56 <1 14 0x308>;
57 clock-frequency = <6144000>;
58 };
59 };
60 };
62 gic: interrupt-controller@48211000 {
63 compatible = "arm,cortex-a15-gic";
64 interrupt-controller;
65 #interrupt-cells = <3>;
66 reg = <0x48211000 0x1000>,
67 <0x48212000 0x1000>;
68 };
70 /*
71 * The soc node represents the soc top level view. It is uses for IPs
72 * that are not memory mapped in the MPU view or for the MPU itself.
73 */
74 soc {
75 compatible = "ti,omap-infra";
76 mpu {
77 compatible = "ti,omap5-mpu";
78 ti,hwmods = "mpu";
79 };
80 };
82 /*
83 * XXX: Use a flat representation of the SOC interconnect.
84 * The real OMAP interconnect network is quite complex.
85 * Since that will not bring real advantage to represent that in DT for
86 * the moment, just use a fake OCP bus entry to represent the whole bus
87 * hierarchy.
88 */
89 ocp {
90 compatible = "ti,omap4-l3-noc", "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <1>;
93 ranges;
94 ti,hwmods = "l3_main_1", "l3_main_2";
96 counter32k: counter@4ae04000 {
97 compatible = "ti,omap-counter32k";
98 reg = <0x4ae04000 0x40>;
99 ti,hwmods = "counter_32k";
100 };
102 dra7_pmx_core: pinmux@4a003400 {
103 compatible = "pinctrl-single";
104 reg = <0x4a003400 0x0464>;
105 #address-cells = <1>;
106 #size-cells = <0>;
107 pinctrl-single,register-width = <32>;
108 pinctrl-single,function-mask = <0x3fffffff>;
109 };
111 dpll_mpu: dpll_mpu {
112 #clock-cells = <0>;
113 compatible = "ti,omap-clock";
114 };
116 dpll_gpu_m2_ck: dpll_gpu_m2_ck {
117 #clock-cells = <0>;
118 compatible = "ti,omap-clock";
119 };
121 dpll_core_h14x2_ck: dpll_core_h14x2_ck {
122 #clock-cells = <0>;
123 compatible = "ti,omap-clock";
124 };
126 dpll_per_h14x2_ck: dpll_per_h14x2_ck {
127 #clock-cells = <0>;
128 compatible = "ti,omap-clock";
129 };
131 gpu_core_gclk_mux: gpu_core_gclk_mux {
132 #clock-cells = <0>;
133 compatible = "ti,omap-clock";
134 };
136 gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
137 #clock-cells = <0>;
138 compatible = "ti,omap-clock";
139 };
141 sdma: dma-controller@4a056000 {
142 compatible = "ti,omap4430-sdma";
143 reg = <0x4a056000 0x1000>;
144 interrupts = <0 12 0x4>,
145 <0 13 0x4>,
146 <0 14 0x4>,
147 <0 15 0x4>;
148 #dma-cells = <1>;
149 #dma-channels = <32>;
150 #dma-requests = <127>;
151 };
153 gpio1: gpio@4ae10000 {
154 compatible = "ti,omap4-gpio";
155 reg = <0x4ae10000 0x200>;
156 interrupts = <0 29 0x4>;
157 ti,hwmods = "gpio1";
158 gpio-controller;
159 #gpio-cells = <2>;
160 interrupt-controller;
161 #interrupt-cells = <1>;
162 };
164 gpio2: gpio@48055000 {
165 compatible = "ti,omap4-gpio";
166 reg = <0x48055000 0x200>;
167 interrupts = <0 30 0x4>;
168 ti,hwmods = "gpio2";
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
172 #interrupt-cells = <1>;
173 };
175 gpio3: gpio@48057000 {
176 compatible = "ti,omap4-gpio";
177 reg = <0x48057000 0x200>;
178 interrupts = <0 31 0x4>;
179 ti,hwmods = "gpio3";
180 gpio-controller;
181 #gpio-cells = <2>;
182 interrupt-controller;
183 #interrupt-cells = <1>;
184 };
186 gpio4: gpio@48059000 {
187 compatible = "ti,omap4-gpio";
188 reg = <0x48059000 0x200>;
189 interrupts = <0 32 0x4>;
190 ti,hwmods = "gpio4";
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
194 #interrupt-cells = <1>;
195 };
197 gpio5: gpio@4805b000 {
198 compatible = "ti,omap4-gpio";
199 reg = <0x4805b000 0x200>;
200 interrupts = <0 33 0x4>;
201 ti,hwmods = "gpio5";
202 gpio-controller;
203 #gpio-cells = <2>;
204 interrupt-controller;
205 #interrupt-cells = <1>;
206 };
208 gpio6: gpio@4805d000 {
209 compatible = "ti,omap4-gpio";
210 reg = <0x4805d000 0x200>;
211 interrupts = <0 34 0x4>;
212 ti,hwmods = "gpio6";
213 gpio-controller;
214 #gpio-cells = <2>;
215 interrupt-controller;
216 #interrupt-cells = <1>;
217 };
219 gpio7: gpio@48051000 {
220 compatible = "ti,omap4-gpio";
221 reg = <0x48051000 0x200>;
222 interrupts = <0 35 0x4>;
223 ti,hwmods = "gpio7";
224 gpio-controller;
225 #gpio-cells = <2>;
226 interrupt-controller;
227 #interrupt-cells = <1>;
228 };
230 gpio8: gpio@48053000 {
231 compatible = "ti,omap4-gpio";
232 reg = <0x48053000 0x200>;
233 interrupts = <0 121 0x4>;
234 ti,hwmods = "gpio8";
235 gpio-controller;
236 #gpio-cells = <2>;
237 interrupt-controller;
238 #interrupt-cells = <1>;
239 };
241 uart1: serial@4806a000 {
242 compatible = "ti,omap4-uart";
243 reg = <0x4806a000 0x100>;
244 interrupts = <0 72 0x4>;
245 ti,hwmods = "uart1";
246 clock-frequency = <48000000>;
247 };
249 uart2: serial@4806c000 {
250 compatible = "ti,omap4-uart";
251 reg = <0x4806c000 0x100>;
252 interrupts = <0 73 0x4>;
253 ti,hwmods = "uart2";
254 clock-frequency = <48000000>;
255 };
257 uart3: serial@48020000 {
258 compatible = "ti,omap4-uart";
259 reg = <0x48020000 0x100>;
260 interrupts = <0 74 0x4>;
261 ti,hwmods = "uart3";
262 clock-frequency = <48000000>;
263 };
265 uart4: serial@4806e000 {
266 compatible = "ti,omap4-uart";
267 reg = <0x4806e000 0x100>;
268 interrupts = <0 70 0x4>;
269 ti,hwmods = "uart4";
270 clock-frequency = <48000000>;
271 };
273 uart5: serial@48066000 {
274 compatible = "ti,omap4-uart";
275 reg = <0x48066000 0x100>;
276 interrupts = <0 105 0x4>;
277 ti,hwmods = "uart5";
278 clock-frequency = <48000000>;
279 };
281 uart6: serial@48068000 {
282 compatible = "ti,omap4-uart";
283 reg = <0x48068000 0x100>;
284 interrupts = <0 106 0x4>;
285 ti,hwmods = "uart6";
286 clock-frequency = <48000000>;
287 };
289 timer1: timer@4ae18000 {
290 compatible = "ti,omap2-timer";
291 reg = <0x4ae18000 0x80>;
292 interrupts = <0 37 0x4>;
293 ti,hwmods = "timer1";
294 ti,timer-alwon;
295 };
297 timer2: timer@48032000 {
298 compatible = "ti,omap2-timer";
299 reg = <0x48032000 0x80>;
300 interrupts = <0 38 0x4>;
301 ti,hwmods = "timer2";
302 };
304 timer3: timer@48034000 {
305 compatible = "ti,omap2-timer";
306 reg = <0x48034000 0x80>;
307 interrupts = <0 39 0x4>;
308 ti,hwmods = "timer3";
309 };
311 timer4: timer@48036000 {
312 compatible = "ti,omap2-timer";
313 reg = <0x48036000 0x80>;
314 interrupts = <0 40 0x4>;
315 ti,hwmods = "timer4";
316 };
318 timer5: timer@48820000 {
319 compatible = "ti,omap2-timer";
320 reg = <0x48820000 0x80>;
321 interrupts = <0 41 0x4>;
322 ti,hwmods = "timer5";
323 ti,timer-dsp;
324 };
326 timer6: timer@48822000 {
327 compatible = "ti,omap2-timer";
328 reg = <0x48822000 0x80>;
329 interrupts = <0 42 0x4>;
330 ti,hwmods = "timer6";
331 ti,timer-dsp;
332 ti,timer-pwm;
333 };
335 timer7: timer@48824000 {
336 compatible = "ti,omap2-timer";
337 reg = <0x48824000 0x80>;
338 interrupts = <0 43 0x4>;
339 ti,hwmods = "timer7";
340 ti,timer-dsp;
341 };
343 timer8: timer@48826000 {
344 compatible = "ti,omap2-timer";
345 reg = <0x48826000 0x80>;
346 interrupts = <0 44 0x4>;
347 ti,hwmods = "timer8";
348 ti,timer-dsp;
349 ti,timer-pwm;
350 };
352 timer9: timer@4803e000 {
353 compatible = "ti,omap2-timer";
354 reg = <0x4803e000 0x80>;
355 interrupts = <0 45 0x4>;
356 ti,hwmods = "timer9";
357 };
359 timer10: timer@48086000 {
360 compatible = "ti,omap2-timer";
361 reg = <0x48086000 0x80>;
362 interrupts = <0 46 0x4>;
363 ti,hwmods = "timer10";
364 };
366 timer11: timer@48088000 {
367 compatible = "ti,omap2-timer";
368 reg = <0x48088000 0x80>;
369 interrupts = <0 47 0x4>;
370 ti,hwmods = "timer11";
371 ti,timer-pwm;
372 };
374 wdt2: wdt@4ae14000 {
375 compatible = "ti,omap4-wdt";
376 reg = <0x4ae14000 0x80>;
377 interrupts = <0 80 0x4>;
378 ti,hwmods = "wd_timer2";
379 };
381 dmm: dmm@4e000000 {
382 compatible = "ti,omap5-dmm";
383 reg = <0x4e000000 0x800>;
384 interrupts = <0 113 0x4>;
385 ti,hwmods = "dmm";
386 };
388 gpu: gpu@0x56000000 {
389 compatible = "ti,omap4-gpu";
390 reg = <0x56000000 0xffff>;
391 interrupts = <0 21 0x4>;
392 ti,hwmods = "gpu";
393 operating-points = <
394 /* kHz uV */
395 425600 1090000
396 500000 1210000
397 532000 1280000
398 >;
399 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>,
400 <&dpll_gpu_m2_ck>, <&gpu_core_gclk_mux>,
401 <&gpu_hyd_gclk_mux>;
402 clock-names = "core", "per", "gpu", "gpu_core", "gpu_hyd";
403 };
405 bandgap {
406 reg = <0x4a0021e0 0xc
407 0x4a00232c 0xc
408 0x4a002380 0x2c
409 0x4a0023C0 0x3c
410 0x4a002564 0x8
411 0x4a002574 0x50>;
412 compatible = "ti,dra752-bandgap";
413 interrupts = <0 126 4>; /* talert */
414 };
416 i2c1: i2c@48070000 {
417 compatible = "ti,omap4-i2c";
418 reg = <0x48070000 0x100>;
419 interrupts = <0 56 0x4>;
420 #address-cells = <1>;
421 #size-cells = <0>;
422 ti,hwmods = "i2c1";
423 };
425 i2c2: i2c@48072000 {
426 compatible = "ti,omap4-i2c";
427 reg = <0x48072000 0x100>;
428 interrupts = <0 57 0x4>;
429 #address-cells = <1>;
430 #size-cells = <0>;
431 ti,hwmods = "i2c2";
432 };
434 i2c3: i2c@48060000 {
435 compatible = "ti,omap4-i2c";
436 reg = <0x48060000 0x100>;
437 interrupts = <0 61 0x4>;
438 #address-cells = <1>;
439 #size-cells = <0>;
440 ti,hwmods = "i2c3";
441 };
443 i2c4: i2c@4807a000 {
444 compatible = "ti,omap4-i2c";
445 reg = <0x4807a000 0x100>;
446 interrupts = <0 62 0x4>;
447 #address-cells = <1>;
448 #size-cells = <0>;
449 ti,hwmods = "i2c4";
450 };
452 i2c5: i2c@4807c000 {
453 compatible = "ti,omap4-i2c";
454 reg = <0x4807c000 0x100>;
455 interrupts = <0 60 0x4>;
456 #address-cells = <1>;
457 #size-cells = <0>;
458 ti,hwmods = "i2c5";
459 };
461 mmc1: mmc@4809c000 {
462 compatible = "ti,omap4-hsmmc";
463 reg = <0x4809c000 0x400>;
464 interrupts = <0 83 0x4>;
465 ti,hwmods = "mmc1";
466 ti,dual-volt;
467 ti,needs-special-reset;
468 dmas = <&sdma 61>, <&sdma 62>;
469 dma-names = "tx", "rx";
470 };
472 mmc2: mmc@480b4000 {
473 compatible = "ti,omap4-hsmmc";
474 reg = <0x480b4000 0x400>;
475 interrupts = <0 86 0x4>;
476 ti,hwmods = "mmc2";
477 ti,needs-special-reset;
478 dmas = <&sdma 47>, <&sdma 48>;
479 dma-names = "tx", "rx";
480 };
482 mmc3: mmc@480ad000 {
483 compatible = "ti,omap4-hsmmc";
484 reg = <0x480ad000 0x400>;
485 interrupts = <0 94 0x4>;
486 ti,hwmods = "mmc3";
487 ti,needs-special-reset;
488 dmas = <&sdma 77>, <&sdma 78>;
489 dma-names = "tx", "rx";
490 };
492 mmc4: mmc@480d1000 {
493 compatible = "ti,omap4-hsmmc";
494 reg = <0x480d1000 0x400>;
495 interrupts = <0 96 0x4>;
496 ti,hwmods = "mmc4";
497 ti,needs-special-reset;
498 dmas = <&sdma 57>, <&sdma 58>;
499 dma-names = "tx", "rx";
500 };
502 avs_mpu: regulator-avs@0x4A003B18 {
503 compatible = "ti,avsclass0";
504 reg = <0x4A003B18 0x20>;
505 efuse-settings = <1090000 8
506 1210000 12
507 1280000 16>;
508 };
510 avs_core: regulator-avs@0x4A0025EC {
511 compatible = "ti,avsclass0";
512 reg = <0x4A0025EC 0x20>;
513 efuse-settings = <1030000 8>;
514 };
516 avs_gpu: regulator-avs@0x4A003B00 {
517 compatible = "ti,avsclass0";
518 reg = <0x4A003B00 0x20>;
519 efuse-settings = <1090000 8
520 1210000 12
521 1280000 16>;
522 };
524 avs_dspeve: regulator-avs@0x4A0025D8 {
525 compatible = "ti,avsclass0";
526 reg = <0x4A0025D8 0x20>;
527 efuse-settings = <1055000 8
528 1150000 12
529 1250000 16>;
530 };
532 avs_iva: regulator-avs@0x4A0025C4 {
533 compatible = "ti,avsclass0";
534 reg = <0x4A0025C4 0x20>;
535 efuse-settings = <1055000 8
536 1150000 12
537 1250000 16>;
538 };
540 dss {
541 compatible = "ti,omap4-dss";
542 ti,hwmods = "dss_core";
543 #address-cells = <1>;
544 #size-cells = <0>;
545 vdda_video-supply = <&ldoln_reg>;
547 dispc {
548 compatible = "ti,omap4-dispc";
549 ti,hwmods = "dss_dispc";
550 };
552 dpi1: dpi@1 {
553 compatible = "ti,dra7xx-dpi";
554 reg = <0>;
555 video-source = <0>;
556 };
558 dpi2: dpi@2 {
559 compatible = "ti,dra7xx-dpi";
560 reg = <1>;
561 video-source = <2>;
562 };
564 dpi3: dpi@3 {
565 compatible = "ti,dra7xx-dpi";
566 reg = <2>;
567 video-source = <3>;
568 };
570 hdmi: hdmi {
571 compatible = "ti,omap4-hdmi", "simple-bus";
572 ti,hwmods = "dss_hdmi";
573 vdda_hdmi_dac-supply = <&ldo3_reg>;
574 video-source = <1>;
575 };
576 };
577 };
578 };