1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
10 /include/ "skeleton.dtsi"
12 / {
13 compatible = "ti,dra7xx";
14 interrupt-parent = <&gic>;
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
22 serial5 = &uart6;
23 };
25 cpus {
26 cpu@0 {
27 compatible = "arm,cortex-a15";
28 operating-points = <
29 /* kHz uV */
30 /* The OPP_HIGH Only for DVFS enabled Samples Hence commenting*/
31 1000000 1090000
32 /* 1176000 1210000 */
33 >;
34 clocks = <&dpll_mpu>;
35 clock-names = "cpu";
36 timer {
37 compatible = "arm,armv7-timer";
38 /*
39 * PPI secure/nonsecure IRQ,
40 * active low level-sensitive
41 */
42 interrupts = <1 13 0x308>,
43 <1 14 0x308>;
44 clock-frequency = <6144000>;
45 };
46 };
47 cpu@1 {
48 compatible = "arm,cortex-a15";
49 timer {
50 compatible = "arm,armv7-timer";
51 /*
52 * PPI secure/nonsecure IRQ,
53 * active low level-sensitive
54 */
55 interrupts = <1 13 0x308>,
56 <1 14 0x308>;
57 clock-frequency = <6144000>;
58 };
59 };
60 };
62 gic: interrupt-controller@48211000 {
63 compatible = "arm,cortex-a15-gic";
64 interrupt-controller;
65 #interrupt-cells = <3>;
66 reg = <0x48211000 0x1000>,
67 <0x48212000 0x1000>;
68 };
70 /*
71 * The soc node represents the soc top level view. It is uses for IPs
72 * that are not memory mapped in the MPU view or for the MPU itself.
73 */
74 soc {
75 compatible = "ti,omap-infra";
76 mpu {
77 compatible = "ti,omap5-mpu";
78 ti,hwmods = "mpu";
79 };
80 };
82 /*
83 * XXX: Use a flat representation of the SOC interconnect.
84 * The real OMAP interconnect network is quite complex.
85 * Since that will not bring real advantage to represent that in DT for
86 * the moment, just use a fake OCP bus entry to represent the whole bus
87 * hierarchy.
88 */
89 ocp {
90 compatible = "ti,omap4-l3-noc", "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <1>;
93 ranges;
94 ti,hwmods = "l3_main_1", "l3_main_2";
96 counter32k: counter@4ae04000 {
97 compatible = "ti,omap-counter32k";
98 reg = <0x4ae04000 0x40>;
99 ti,hwmods = "counter_32k";
100 };
102 dra7_pmx_core: pinmux@4a003400 {
103 compatible = "pinctrl-single";
104 reg = <0x4a003400 0x0464>;
105 #address-cells = <1>;
106 #size-cells = <0>;
107 pinctrl-single,register-width = <32>;
108 pinctrl-single,function-mask = <0x3fffffff>;
109 };
111 dpll_mpu: dpll_mpu {
112 #clock-cells = <0>;
113 compatible = "ti,omap-clock";
114 };
116 sdma: dma-controller@4a056000 {
117 compatible = "ti,omap4430-sdma";
118 reg = <0x4a056000 0x1000>;
119 interrupts = <0 12 0x4>,
120 <0 13 0x4>,
121 <0 14 0x4>,
122 <0 15 0x4>;
123 #dma-cells = <1>;
124 #dma-channels = <32>;
125 #dma-requests = <127>;
126 };
128 gpio1: gpio@4ae10000 {
129 compatible = "ti,omap4-gpio";
130 reg = <0x4ae10000 0x200>;
131 interrupts = <0 29 0x4>;
132 ti,hwmods = "gpio1";
133 gpio-controller;
134 #gpio-cells = <2>;
135 interrupt-controller;
136 #interrupt-cells = <1>;
137 };
139 gpio2: gpio@48055000 {
140 compatible = "ti,omap4-gpio";
141 reg = <0x48055000 0x200>;
142 interrupts = <0 30 0x4>;
143 ti,hwmods = "gpio2";
144 gpio-controller;
145 #gpio-cells = <2>;
146 interrupt-controller;
147 #interrupt-cells = <1>;
148 };
150 gpio3: gpio@48057000 {
151 compatible = "ti,omap4-gpio";
152 reg = <0x48057000 0x200>;
153 interrupts = <0 31 0x4>;
154 ti,hwmods = "gpio3";
155 gpio-controller;
156 #gpio-cells = <2>;
157 interrupt-controller;
158 #interrupt-cells = <1>;
159 };
161 gpio4: gpio@48059000 {
162 compatible = "ti,omap4-gpio";
163 reg = <0x48059000 0x200>;
164 interrupts = <0 32 0x4>;
165 ti,hwmods = "gpio4";
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
169 #interrupt-cells = <1>;
170 };
172 gpio5: gpio@4805b000 {
173 compatible = "ti,omap4-gpio";
174 reg = <0x4805b000 0x200>;
175 interrupts = <0 33 0x4>;
176 ti,hwmods = "gpio5";
177 gpio-controller;
178 #gpio-cells = <2>;
179 interrupt-controller;
180 #interrupt-cells = <1>;
181 };
183 gpio6: gpio@4805d000 {
184 compatible = "ti,omap4-gpio";
185 reg = <0x4805d000 0x200>;
186 interrupts = <0 34 0x4>;
187 ti,hwmods = "gpio6";
188 gpio-controller;
189 #gpio-cells = <2>;
190 interrupt-controller;
191 #interrupt-cells = <1>;
192 };
194 gpio7: gpio@48051000 {
195 compatible = "ti,omap4-gpio";
196 reg = <0x48051000 0x200>;
197 interrupts = <0 35 0x4>;
198 ti,hwmods = "gpio7";
199 gpio-controller;
200 #gpio-cells = <2>;
201 interrupt-controller;
202 #interrupt-cells = <1>;
203 };
205 gpio8: gpio@48053000 {
206 compatible = "ti,omap4-gpio";
207 reg = <0x48053000 0x200>;
208 interrupts = <0 121 0x4>;
209 ti,hwmods = "gpio8";
210 gpio-controller;
211 #gpio-cells = <2>;
212 interrupt-controller;
213 #interrupt-cells = <1>;
214 };
216 uart1: serial@4806a000 {
217 compatible = "ti,omap4-uart";
218 reg = <0x4806a000 0x100>;
219 interrupts = <0 72 0x4>;
220 ti,hwmods = "uart1";
221 clock-frequency = <48000000>;
222 };
224 uart2: serial@4806c000 {
225 compatible = "ti,omap4-uart";
226 reg = <0x4806c000 0x100>;
227 interrupts = <0 73 0x4>;
228 ti,hwmods = "uart2";
229 clock-frequency = <48000000>;
230 };
232 uart3: serial@48020000 {
233 compatible = "ti,omap4-uart";
234 reg = <0x48020000 0x100>;
235 interrupts = <0 74 0x4>;
236 ti,hwmods = "uart3";
237 clock-frequency = <48000000>;
238 };
240 uart4: serial@4806e000 {
241 compatible = "ti,omap4-uart";
242 reg = <0x4806e000 0x100>;
243 interrupts = <0 70 0x4>;
244 ti,hwmods = "uart4";
245 clock-frequency = <48000000>;
246 };
248 uart5: serial@48066000 {
249 compatible = "ti,omap4-uart";
250 reg = <0x48066000 0x100>;
251 interrupts = <0 105 0x4>;
252 ti,hwmods = "uart5";
253 clock-frequency = <48000000>;
254 };
256 uart6: serial@48068000 {
257 compatible = "ti,omap4-uart";
258 reg = <0x48068000 0x100>;
259 interrupts = <0 106 0x4>;
260 ti,hwmods = "uart6";
261 clock-frequency = <48000000>;
262 };
264 timer1: timer@4ae18000 {
265 compatible = "ti,omap2-timer";
266 reg = <0x4ae18000 0x80>;
267 interrupts = <0 37 0x4>;
268 ti,hwmods = "timer1";
269 ti,timer-alwon;
270 };
272 timer2: timer@48032000 {
273 compatible = "ti,omap2-timer";
274 reg = <0x48032000 0x80>;
275 interrupts = <0 38 0x4>;
276 ti,hwmods = "timer2";
277 };
279 timer3: timer@48034000 {
280 compatible = "ti,omap2-timer";
281 reg = <0x48034000 0x80>;
282 interrupts = <0 39 0x4>;
283 ti,hwmods = "timer3";
284 };
286 timer4: timer@48036000 {
287 compatible = "ti,omap2-timer";
288 reg = <0x48036000 0x80>;
289 interrupts = <0 40 0x4>;
290 ti,hwmods = "timer4";
291 };
293 timer5: timer@48820000 {
294 compatible = "ti,omap2-timer";
295 reg = <0x48820000 0x80>;
296 interrupts = <0 41 0x4>;
297 ti,hwmods = "timer5";
298 ti,timer-dsp;
299 };
301 timer6: timer@48822000 {
302 compatible = "ti,omap2-timer";
303 reg = <0x48822000 0x80>;
304 interrupts = <0 42 0x4>;
305 ti,hwmods = "timer6";
306 ti,timer-dsp;
307 ti,timer-pwm;
308 };
310 timer7: timer@48824000 {
311 compatible = "ti,omap2-timer";
312 reg = <0x48824000 0x80>;
313 interrupts = <0 43 0x4>;
314 ti,hwmods = "timer7";
315 ti,timer-dsp;
316 };
318 timer8: timer@48826000 {
319 compatible = "ti,omap2-timer";
320 reg = <0x48826000 0x80>;
321 interrupts = <0 44 0x4>;
322 ti,hwmods = "timer8";
323 ti,timer-dsp;
324 ti,timer-pwm;
325 };
327 timer9: timer@4803e000 {
328 compatible = "ti,omap2-timer";
329 reg = <0x4803e000 0x80>;
330 interrupts = <0 45 0x4>;
331 ti,hwmods = "timer9";
332 };
334 timer10: timer@48086000 {
335 compatible = "ti,omap2-timer";
336 reg = <0x48086000 0x80>;
337 interrupts = <0 46 0x4>;
338 ti,hwmods = "timer10";
339 };
341 timer11: timer@48088000 {
342 compatible = "ti,omap2-timer";
343 reg = <0x48088000 0x80>;
344 interrupts = <0 47 0x4>;
345 ti,hwmods = "timer11";
346 ti,timer-pwm;
347 };
349 wdt2: wdt@4ae14000 {
350 compatible = "ti,omap4-wdt";
351 reg = <0x4ae14000 0x80>;
352 interrupts = <0 80 0x4>;
353 ti,hwmods = "wd_timer2";
354 };
356 dmm: dmm@4e000000 {
357 compatible = "ti,omap5-dmm";
358 reg = <0x4e000000 0x800>;
359 interrupts = <0 113 0x4>;
360 ti,hwmods = "dmm";
361 };
363 bandgap {
364 reg = <0x4a0021e0 0xc
365 0x4a00232c 0xc
366 0x4a002380 0x2c
367 0x4a0023C0 0x3c
368 0x4a002564 0x8
369 0x4a002574 0x50>;
370 compatible = "ti,dra752-bandgap";
371 interrupts = <0 126 4>; /* talert */
372 };
374 i2c1: i2c@48070000 {
375 compatible = "ti,omap4-i2c";
376 reg = <0x48070000 0x100>;
377 interrupts = <0 56 0x4>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380 ti,hwmods = "i2c1";
381 };
383 i2c2: i2c@48072000 {
384 compatible = "ti,omap4-i2c";
385 reg = <0x48072000 0x100>;
386 interrupts = <0 57 0x4>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389 ti,hwmods = "i2c2";
390 };
392 i2c3: i2c@48060000 {
393 compatible = "ti,omap4-i2c";
394 reg = <0x48060000 0x100>;
395 interrupts = <0 61 0x4>;
396 #address-cells = <1>;
397 #size-cells = <0>;
398 ti,hwmods = "i2c3";
399 };
401 i2c4: i2c@4807a000 {
402 compatible = "ti,omap4-i2c";
403 reg = <0x4807a000 0x100>;
404 interrupts = <0 62 0x4>;
405 #address-cells = <1>;
406 #size-cells = <0>;
407 ti,hwmods = "i2c4";
408 };
410 i2c5: i2c@4807c000 {
411 compatible = "ti,omap4-i2c";
412 reg = <0x4807c000 0x100>;
413 interrupts = <0 60 0x4>;
414 #address-cells = <1>;
415 #size-cells = <0>;
416 ti,hwmods = "i2c5";
417 };
419 mmc1: mmc@4809c000 {
420 compatible = "ti,omap4-hsmmc";
421 reg = <0x4809c000 0x400>;
422 interrupts = <0 83 0x4>;
423 ti,hwmods = "mmc1";
424 ti,dual-volt;
425 ti,needs-special-reset;
426 dmas = <&sdma 61>, <&sdma 62>;
427 dma-names = "tx", "rx";
428 };
430 mmc2: mmc@480b4000 {
431 compatible = "ti,omap4-hsmmc";
432 reg = <0x480b4000 0x400>;
433 interrupts = <0 86 0x4>;
434 ti,hwmods = "mmc2";
435 ti,needs-special-reset;
436 dmas = <&sdma 47>, <&sdma 48>;
437 dma-names = "tx", "rx";
438 };
440 mmc3: mmc@480ad000 {
441 compatible = "ti,omap4-hsmmc";
442 reg = <0x480ad000 0x400>;
443 interrupts = <0 94 0x4>;
444 ti,hwmods = "mmc3";
445 ti,needs-special-reset;
446 dmas = <&sdma 77>, <&sdma 78>;
447 dma-names = "tx", "rx";
448 };
450 mmc4: mmc@480d1000 {
451 compatible = "ti,omap4-hsmmc";
452 reg = <0x480d1000 0x400>;
453 interrupts = <0 96 0x4>;
454 ti,hwmods = "mmc4";
455 ti,needs-special-reset;
456 dmas = <&sdma 57>, <&sdma 58>;
457 dma-names = "tx", "rx";
458 };
460 avs_mpu: regulator-avs@0x4A003B18 {
461 compatible = "ti,avsclass0";
462 reg = <0x4A003B18 0x20>;
463 efuse-settings = <1090000 8
464 1210000 12
465 1280000 16>;
466 };
468 avs_core: regulator-avs@0x4A0025EC {
469 compatible = "ti,avsclass0";
470 reg = <0x4A0025EC 0x20>;
471 efuse-settings = <1030000 8>;
472 };
474 avs_gpu: regulator-avs@0x4A003B00 {
475 compatible = "ti,avsclass0";
476 reg = <0x4A003B00 0x20>;
477 efuse-settings = <1090000 8
478 1210000 12
479 1280000 16>;
480 };
482 avs_dspeve: regulator-avs@0x4A0025D8 {
483 compatible = "ti,avsclass0";
484 reg = <0x4A0025D8 0x20>;
485 efuse-settings = <1055000 8
486 1150000 12
487 1250000 16>;
488 };
490 avs_iva: regulator-avs@0x4A0025C4 {
491 compatible = "ti,avsclass0";
492 reg = <0x4A0025C4 0x20>;
493 efuse-settings = <1055000 8
494 1150000 12
495 1250000 16>;
496 };
498 dss {
499 compatible = "ti,omap4-dss";
500 ti,hwmods = "dss_core";
501 #address-cells = <1>;
502 #size-cells = <0>;
503 vdda_video-supply = <&ldoln_reg>;
505 dispc {
506 compatible = "ti,omap4-dispc";
507 ti,hwmods = "dss_dispc";
508 };
510 dpi1: dpi@1 {
511 compatible = "ti,dra7xx-dpi";
512 reg = <0>;
513 video-source = <0>;
514 };
516 dpi2: dpi@2 {
517 compatible = "ti,dra7xx-dpi";
518 reg = <1>;
519 video-source = <2>;
520 };
522 dpi3: dpi@3 {
523 compatible = "ti,dra7xx-dpi";
524 reg = <2>;
525 video-source = <3>;
526 };
528 hdmi: hdmi {
529 compatible = "ti,omap4-hdmi", "simple-bus";
530 ti,hwmods = "dss_hdmi";
531 vdda_hdmi_dac-supply = <&ldo3_reg>;
532 video-source = <1>;
533 };
534 };
535 };
536 };