65d8c44b71f873dede8f4f3fd6694afed8c1f4f0
1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
10 /include/ "skeleton.dtsi"
12 / {
13 compatible = "ti,dra7xx";
14 interrupt-parent = <&gic>;
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
22 serial5 = &uart6;
23 };
25 cpus {
26 cpu@0 {
27 compatible = "arm,cortex-a15";
28 operating-points = <
29 /* kHz uV */
30 /* The OPP_HIGH Only for DVFS enabled Samples Hence commenting*/
31 1000000 1090000
32 /* 1176000 1210000 */
33 >;
34 clocks = <&dpll_mpu>;
35 clock-names = "cpu";
36 timer {
37 compatible = "arm,armv7-timer";
38 /*
39 * PPI secure/nonsecure IRQ,
40 * active low level-sensitive
41 */
42 interrupts = <1 13 0x308>,
43 <1 14 0x308>;
44 clock-frequency = <6144000>;
45 };
46 };
47 cpu@1 {
48 compatible = "arm,cortex-a15";
49 timer {
50 compatible = "arm,armv7-timer";
51 /*
52 * PPI secure/nonsecure IRQ,
53 * active low level-sensitive
54 */
55 interrupts = <1 13 0x308>,
56 <1 14 0x308>;
57 clock-frequency = <6144000>;
58 };
59 };
60 };
62 gic: interrupt-controller@48211000 {
63 compatible = "arm,cortex-a15-gic";
64 interrupt-controller;
65 #interrupt-cells = <3>;
66 reg = <0x48211000 0x1000>,
67 <0x48212000 0x1000>;
68 };
70 /*
71 * The soc node represents the soc top level view. It is uses for IPs
72 * that are not memory mapped in the MPU view or for the MPU itself.
73 */
74 soc {
75 compatible = "ti,omap-infra";
76 mpu {
77 compatible = "ti,omap5-mpu";
78 ti,hwmods = "mpu";
79 };
80 };
82 /*
83 * XXX: Use a flat representation of the SOC interconnect.
84 * The real OMAP interconnect network is quite complex.
85 * Since that will not bring real advantage to represent that in DT for
86 * the moment, just use a fake OCP bus entry to represent the whole bus
87 * hierarchy.
88 */
89 ocp {
90 compatible = "ti,omap4-l3-noc", "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <1>;
93 ranges;
94 ti,hwmods = "l3_main_1", "l3_main_2";
96 counter32k: counter@4ae04000 {
97 compatible = "ti,omap-counter32k";
98 reg = <0x4ae04000 0x40>;
99 ti,hwmods = "counter_32k";
100 };
102 dra7_pmx_core: pinmux@4a003400 {
103 compatible = "pinctrl-single";
104 reg = <0x4a003400 0x0464>;
105 #address-cells = <1>;
106 #size-cells = <0>;
107 pinctrl-single,register-width = <32>;
108 pinctrl-single,function-mask = <0x3fffffff>;
109 };
111 dpll_mpu: dpll_mpu {
112 #clock-cells = <0>;
113 compatible = "ti,omap-clock";
114 };
116 gpio1: gpio@4ae10000 {
117 compatible = "ti,omap4-gpio";
118 reg = <0x4ae10000 0x200>;
119 interrupts = <0 29 0x4>;
120 ti,hwmods = "gpio1";
121 gpio-controller;
122 #gpio-cells = <2>;
123 interrupt-controller;
124 #interrupt-cells = <1>;
125 };
127 gpio2: gpio@48055000 {
128 compatible = "ti,omap4-gpio";
129 reg = <0x48055000 0x200>;
130 interrupts = <0 30 0x4>;
131 ti,hwmods = "gpio2";
132 gpio-controller;
133 #gpio-cells = <2>;
134 interrupt-controller;
135 #interrupt-cells = <1>;
136 };
138 gpio3: gpio@48057000 {
139 compatible = "ti,omap4-gpio";
140 reg = <0x48057000 0x200>;
141 interrupts = <0 31 0x4>;
142 ti,hwmods = "gpio3";
143 gpio-controller;
144 #gpio-cells = <2>;
145 interrupt-controller;
146 #interrupt-cells = <1>;
147 };
149 gpio4: gpio@48059000 {
150 compatible = "ti,omap4-gpio";
151 reg = <0x48059000 0x200>;
152 interrupts = <0 32 0x4>;
153 ti,hwmods = "gpio4";
154 gpio-controller;
155 #gpio-cells = <2>;
156 interrupt-controller;
157 #interrupt-cells = <1>;
158 };
160 gpio5: gpio@4805b000 {
161 compatible = "ti,omap4-gpio";
162 reg = <0x4805b000 0x200>;
163 interrupts = <0 33 0x4>;
164 ti,hwmods = "gpio5";
165 gpio-controller;
166 #gpio-cells = <2>;
167 interrupt-controller;
168 #interrupt-cells = <1>;
169 };
171 gpio6: gpio@4805d000 {
172 compatible = "ti,omap4-gpio";
173 reg = <0x4805d000 0x200>;
174 interrupts = <0 34 0x4>;
175 ti,hwmods = "gpio6";
176 gpio-controller;
177 #gpio-cells = <2>;
178 interrupt-controller;
179 #interrupt-cells = <1>;
180 };
182 gpio7: gpio@48051000 {
183 compatible = "ti,omap4-gpio";
184 reg = <0x48051000 0x200>;
185 interrupts = <0 35 0x4>;
186 ti,hwmods = "gpio7";
187 gpio-controller;
188 #gpio-cells = <2>;
189 interrupt-controller;
190 #interrupt-cells = <1>;
191 };
193 gpio8: gpio@48053000 {
194 compatible = "ti,omap4-gpio";
195 reg = <0x48053000 0x200>;
196 interrupts = <0 121 0x4>;
197 ti,hwmods = "gpio8";
198 gpio-controller;
199 #gpio-cells = <2>;
200 interrupt-controller;
201 #interrupt-cells = <1>;
202 };
204 uart1: serial@4806a000 {
205 compatible = "ti,omap4-uart";
206 reg = <0x4806a000 0x100>;
207 interrupts = <0 72 0x4>;
208 ti,hwmods = "uart1";
209 clock-frequency = <48000000>;
210 };
212 uart2: serial@4806c000 {
213 compatible = "ti,omap4-uart";
214 reg = <0x4806c000 0x100>;
215 interrupts = <0 73 0x4>;
216 ti,hwmods = "uart2";
217 clock-frequency = <48000000>;
218 };
220 uart3: serial@48020000 {
221 compatible = "ti,omap4-uart";
222 reg = <0x48020000 0x100>;
223 interrupts = <0 74 0x4>;
224 ti,hwmods = "uart3";
225 clock-frequency = <48000000>;
226 };
228 uart4: serial@4806e000 {
229 compatible = "ti,omap4-uart";
230 reg = <0x4806e000 0x100>;
231 interrupts = <0 70 0x4>;
232 ti,hwmods = "uart4";
233 clock-frequency = <48000000>;
234 };
236 uart5: serial@48066000 {
237 compatible = "ti,omap4-uart";
238 reg = <0x48066000 0x100>;
239 interrupts = <0 105 0x4>;
240 ti,hwmods = "uart5";
241 clock-frequency = <48000000>;
242 };
244 uart6: serial@48068000 {
245 compatible = "ti,omap4-uart";
246 reg = <0x48068000 0x100>;
247 interrupts = <0 106 0x4>;
248 ti,hwmods = "uart6";
249 clock-frequency = <48000000>;
250 };
252 timer1: timer@4ae18000 {
253 compatible = "ti,omap2-timer";
254 reg = <0x4ae18000 0x80>;
255 interrupts = <0 37 0x4>;
256 ti,hwmods = "timer1";
257 ti,timer-alwon;
258 };
260 timer2: timer@48032000 {
261 compatible = "ti,omap2-timer";
262 reg = <0x48032000 0x80>;
263 interrupts = <0 38 0x4>;
264 ti,hwmods = "timer2";
265 };
267 timer3: timer@48034000 {
268 compatible = "ti,omap2-timer";
269 reg = <0x48034000 0x80>;
270 interrupts = <0 39 0x4>;
271 ti,hwmods = "timer3";
272 };
274 timer4: timer@48036000 {
275 compatible = "ti,omap2-timer";
276 reg = <0x48036000 0x80>;
277 interrupts = <0 40 0x4>;
278 ti,hwmods = "timer4";
279 };
281 timer5: timer@48820000 {
282 compatible = "ti,omap2-timer";
283 reg = <0x48820000 0x80>;
284 interrupts = <0 41 0x4>;
285 ti,hwmods = "timer5";
286 ti,timer-dsp;
287 };
289 timer6: timer@48822000 {
290 compatible = "ti,omap2-timer";
291 reg = <0x48822000 0x80>;
292 interrupts = <0 42 0x4>;
293 ti,hwmods = "timer6";
294 ti,timer-dsp;
295 ti,timer-pwm;
296 };
298 timer7: timer@48824000 {
299 compatible = "ti,omap2-timer";
300 reg = <0x48824000 0x80>;
301 interrupts = <0 43 0x4>;
302 ti,hwmods = "timer7";
303 ti,timer-dsp;
304 };
306 timer8: timer@48826000 {
307 compatible = "ti,omap2-timer";
308 reg = <0x48826000 0x80>;
309 interrupts = <0 44 0x4>;
310 ti,hwmods = "timer8";
311 ti,timer-dsp;
312 ti,timer-pwm;
313 };
315 timer9: timer@4803e000 {
316 compatible = "ti,omap2-timer";
317 reg = <0x4803e000 0x80>;
318 interrupts = <0 45 0x4>;
319 ti,hwmods = "timer9";
320 };
322 timer10: timer@48086000 {
323 compatible = "ti,omap2-timer";
324 reg = <0x48086000 0x80>;
325 interrupts = <0 46 0x4>;
326 ti,hwmods = "timer10";
327 };
329 timer11: timer@48088000 {
330 compatible = "ti,omap2-timer";
331 reg = <0x48088000 0x80>;
332 interrupts = <0 47 0x4>;
333 ti,hwmods = "timer11";
334 ti,timer-pwm;
335 };
337 wdt2: wdt@4ae14000 {
338 compatible = "ti,omap4-wdt";
339 reg = <0x4ae14000 0x80>;
340 interrupts = <0 80 0x4>;
341 ti,hwmods = "wd_timer2";
342 };
344 bandgap {
345 reg = <0x4a0021e0 0xc
346 0x4a00232c 0xc
347 0x4a002380 0x2c
348 0x4a0023C0 0x3c
349 0x4a002564 0x8
350 0x4a002574 0x50>;
351 compatible = "ti,dra752-bandgap";
352 interrupts = <0 126 4>; /* talert */
353 };
355 i2c1: i2c@48070000 {
356 compatible = "ti,omap4-i2c";
357 reg = <0x48070000 0x100>;
358 interrupts = <0 56 0x4>;
359 #address-cells = <1>;
360 #size-cells = <0>;
361 ti,hwmods = "i2c1";
362 };
364 i2c2: i2c@48072000 {
365 compatible = "ti,omap4-i2c";
366 reg = <0x48072000 0x100>;
367 interrupts = <0 57 0x4>;
368 #address-cells = <1>;
369 #size-cells = <0>;
370 ti,hwmods = "i2c2";
371 };
373 i2c3: i2c@48060000 {
374 compatible = "ti,omap4-i2c";
375 reg = <0x48060000 0x100>;
376 interrupts = <0 61 0x4>;
377 #address-cells = <1>;
378 #size-cells = <0>;
379 ti,hwmods = "i2c3";
380 };
382 i2c4: i2c@4807a000 {
383 compatible = "ti,omap4-i2c";
384 reg = <0x4807a000 0x100>;
385 interrupts = <0 62 0x4>;
386 #address-cells = <1>;
387 #size-cells = <0>;
388 ti,hwmods = "i2c4";
389 };
391 i2c5: i2c@4807c000 {
392 compatible = "ti,omap4-i2c";
393 reg = <0x4807c000 0x100>;
394 interrupts = <0 60 0x4>;
395 #address-cells = <1>;
396 #size-cells = <0>;
397 ti,hwmods = "i2c5";
398 };
400 avs_mpu: regulator-avs@0x4A003B18 {
401 compatible = "ti,avsclass0";
402 reg = <0x4A003B18 0x20>;
403 efuse-settings = <1090000 8
404 1210000 12
405 1280000 16>;
406 };
408 avs_core: regulator-avs@0x4A0025EC {
409 compatible = "ti,avsclass0";
410 reg = <0x4A0025EC 0x20>;
411 efuse-settings = <1030000 8>;
412 };
414 avs_gpu: regulator-avs@0x4A003B00 {
415 compatible = "ti,avsclass0";
416 reg = <0x4A003B00 0x20>;
417 efuse-settings = <1090000 8
418 1210000 12
419 1280000 16>;
420 };
422 avs_dspeve: regulator-avs@0x4A0025D8 {
423 compatible = "ti,avsclass0";
424 reg = <0x4A0025D8 0x20>;
425 efuse-settings = <1055000 8
426 1150000 12
427 1250000 16>;
428 };
430 avs_iva: regulator-avs@0x4A0025C4 {
431 compatible = "ti,avsclass0";
432 reg = <0x4A0025C4 0x20>;
433 efuse-settings = <1055000 8
434 1150000 12
435 1250000 16>;
436 };
438 };
439 };