1 /*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra72x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/clk/ti-dra7-atl.h>
14 / {
15 model = "TI DRA722";
16 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
18 aliases {
19 display0 = &hdmi0;
20 sound0 = &primary_sound;
21 sound1 = &hdmi;
22 };
24 memory {
25 device_type = "memory";
26 reg = <0x80000000 0x40000000>; /* 1024 MB */
27 };
29 tpd12s015: encoder@0 {
30 compatible = "ti,tpd12s015";
32 pinctrl-names = "default";
33 pinctrl-0 = <&hpd_pin>;
35 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
36 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
37 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
39 ports {
40 #address-cells = <1>;
41 #size-cells = <0>;
43 port@0 {
44 reg = <0>;
46 tpd12s015_in: endpoint@0 {
47 remote-endpoint = <&hdmi_out>;
48 };
49 };
51 port@1 {
52 reg = <1>;
54 tpd12s015_out: endpoint@0 {
55 remote-endpoint = <&hdmi_connector_in>;
56 };
57 };
58 };
59 };
61 hdmi0: connector@0 {
62 compatible = "hdmi-connector";
63 label = "hdmi";
65 type = "a";
67 port {
68 hdmi_connector_in: endpoint {
69 remote-endpoint = <&tpd12s015_out>;
70 };
71 };
72 };
74 reserved_mem: reserved-memory {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges;
79 ipu2_cma_pool: ipu2_cma@95800000 {
80 compatible = "shared-dma-pool";
81 reg = <0x95800000 0x3800000>;
82 reusable;
83 status = "okay";
84 };
86 dsp1_cma_pool: dsp1_cma@99000000 {
87 compatible = "shared-dma-pool";
88 reg = <0x99000000 0x4000000>;
89 reusable;
90 status = "okay";
91 };
93 ipu1_cma_pool: ipu1_cma@9d000000 {
94 compatible = "shared-dma-pool";
95 reg = <0x9d000000 0x2000000>;
96 reusable;
97 status = "okay";
98 };
99 };
101 extcon_usb1: extcon_usb1 {
102 compatible = "linux,extcon-usb-gpio";
103 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
104 };
106 extcon_usb2: extcon_usb2 {
107 compatible = "linux,extcon-usb-gpio";
108 id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
109 };
111 evm_3v3_sd: fixedregulator-sd {
112 compatible = "regulator-fixed";
113 regulator-name = "evm_3v3_sd";
114 regulator-min-microvolt = <3300000>;
115 regulator-max-microvolt = <3300000>;
116 enable-active-high;
117 gpio = <&pcf_gpio_21 5 0>;
118 };
120 evm_3v3_sw: fixedregulator-evm_3v3 {
121 compatible = "regulator-fixed";
122 regulator-name = "evm_3v3";
123 regulator-min-microvolt = <3300000>;
124 regulator-max-microvolt = <3300000>;
125 };
127 aic_dvdd: fixedregulator-aic_dvdd {
128 /* TPS77018DBVT */
129 compatible = "regulator-fixed";
130 regulator-name = "aic_dvdd";
131 vin-supply = <&evm_3v3_sw>;
132 regulator-min-microvolt = <1800000>;
133 regulator-max-microvolt = <1800000>;
134 };
136 primary_sound: primary_sound {
137 compatible = "ti,dra7xx-evm-audio";
138 ti,model = "DRA7xx-EVM";
139 ti,always-on;
140 ti,audio-codec = <&tlv320aic3106>;
141 ti,mcasp-controller = <&mcasp3>;
142 ti,codec-clock-rate = <11289600>;
143 clocks = <&atl_clkin2_ck>;
144 clock-names = "mclk";
145 ti,audio-routing =
146 "Headphone Jack", "HPLOUT",
147 "Headphone Jack", "HPROUT",
148 "Line Out", "LLOUT",
149 "Line Out", "RLOUT",
150 "MIC3L", "Mic Jack",
151 "MIC3R", "Mic Jack",
152 "Mic Jack", "Mic Bias",
153 "LINE1L", "Line In",
154 "LINE1R", "Line In";
155 };
157 btwilink_sound: btwilink_sound {
158 #sound-dai-cells = <0>;
159 compatible = "linux,bt-sco-audio";
160 status = "okay";
161 };
163 simple_bt_sco_card: bt_sco_card {
164 compatible = "simple-audio-card";
165 simple-audio-card,name = "DRA7xx-WiLink";
166 simple-audio-card,format = "dsp_a";
167 simple-audio-card,frame-master = <&btwilink_codec>;
168 simple-audio-card,bitclock-master = <&btwilink_codec>;
169 simple-audio-card,frame-inversion;
171 simple-audio-card,cpu {
172 sound-dai = <&mcasp7>;
173 };
175 btwilink_codec: simple-audio-card,codec {
176 sound-dai = <&btwilink_sound>;
177 };
178 };
180 vmmcwl_fixed: fixedregulator-mmcwl {
181 compatible = "regulator-fixed";
182 regulator-name = "vmmcwl_fixed";
183 regulator-min-microvolt = <1800000>;
184 regulator-max-microvolt = <1800000>;
185 gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; /* gpio5_8 */
186 enable-active-high;
187 };
189 kim {
190 compatible = "kim";
191 nshutdown_gpio = <132>;
192 dev_name = "/dev/ttyS2";
193 flow_cntrl = <1>;
194 baud_rate = <3686400>;
195 };
197 btwilink {
198 compatible = "btwilink";
199 };
200 };
202 &dra7_pmx_core {
203 bt_uart3_pins: pinmux_uart3_pins {
204 pinctrl-single,pins = <
205 0x3c0 (PIN_INPUT_PULLUP | MUX_MODE1) /* uart3_rxd */
206 0x3c4 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* uart3_txd */
207 0x3c8 (PIN_INPUT | MUX_MODE1) /* uart3_ctsn */
208 0x3cc (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* uart3_rtsn */
209 0x2bc (PIN_OUTPUT | MUX_MODE14) /* gpio5_4 */
210 >;
211 };
213 i2c1_pins: pinmux_i2c1_pins {
214 pinctrl-single,pins = <
215 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
216 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
217 >;
218 };
220 uart1_pins: pinmix_uart1_pins {
221 pinctrl-single,pins = <
222 0x3e0 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd */
223 0x3e4 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_txd */
224 >;
225 };
227 i2c2_pins: pinmux_i2c2_pins {
228 pinctrl-single,pins = <
229 0x408 (PIN_INPUT | MUX_MODE1) /* hdmi1_ddc_scl */
230 0x40c (PIN_INPUT | MUX_MODE1) /* hdmi1_ddc_sda */
231 >;
232 };
234 cpsw_default: cpsw_default {
235 pinctrl-single,pins = <
236 /* Slave 2 */
237 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
238 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
239 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
240 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
241 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
242 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
243 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
244 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
245 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
246 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
247 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
248 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
249 >;
251 };
253 cpsw_sleep: cpsw_sleep {
254 pinctrl-single,pins = <
255 /* Slave 1 */
256 0x198 (PIN_OFF_NONE)
257 0x19c (PIN_OFF_NONE)
258 0x1a0 (PIN_OFF_NONE)
259 0x1a4 (PIN_OFF_NONE)
260 0x1a8 (PIN_OFF_NONE)
261 0x1ac (PIN_OFF_NONE)
262 0x1b0 (PIN_OFF_NONE)
263 0x1b4 (PIN_OFF_NONE)
264 0x1b8 (PIN_OFF_NONE)
265 0x1bc (PIN_OFF_NONE)
266 0x1c0 (PIN_OFF_NONE)
267 0x1c4 (PIN_OFF_NONE)
268 >;
269 };
271 davinci_mdio_default: davinci_mdio_default {
272 pinctrl-single,pins = <
273 /* MDIO */
274 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */
275 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk */
276 >;
277 };
279 davinci_mdio_sleep: davinci_mdio_sleep {
280 pinctrl-single,pins = <
281 0x23c (PIN_OFF_NONE)
282 0x240 (PIN_OFF_NONE)
283 >;
284 };
286 tps65917_pins_default: tps65917_pins_default {
287 pinctrl-single,pins = <
288 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
289 >;
290 };
292 nand_default: nand_default {
293 pinctrl-single,pins = <
294 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
295 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
296 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
297 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
298 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
299 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
300 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
301 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
302 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
303 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
304 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
305 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
306 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
307 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
308 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
309 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
310 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
311 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
312 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
313 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
314 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
315 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
316 >;
317 };
319 vout1_pins: pinmux_vout1_pins {
320 pinctrl-single,pins = <
321 0x1C8 (PIN_OUTPUT | MUX_MODE0) /* vout1_clk */
322 0x1CC (PIN_OUTPUT | MUX_MODE0) /* vout1_de */
323 0x1D0 (PIN_OUTPUT | MUX_MODE0) /* vout1_fld */
324 0x1D4 (PIN_OUTPUT | MUX_MODE0) /* vout1_hsync */
325 0x1D8 (PIN_OUTPUT | MUX_MODE0) /* vout1_vsync */
326 0x1DC (PIN_OUTPUT | MUX_MODE0) /* vout1_d0 */
327 0x1E0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d1 */
328 0x1E4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d2 */
329 0x1E8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d3 */
330 0x1EC (PIN_OUTPUT | MUX_MODE0) /* vout1_d4 */
331 0x1F0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d5 */
332 0x1F4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d6 */
333 0x1F8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d7 */
334 0x1FC (PIN_OUTPUT | MUX_MODE0) /* vout1_d8 */
335 0x200 (PIN_OUTPUT | MUX_MODE0) /* vout1_d9 */
336 0x204 (PIN_OUTPUT | MUX_MODE0) /* vout1_d10 */
337 0x208 (PIN_OUTPUT | MUX_MODE0) /* vout1_d11 */
338 0x20C (PIN_OUTPUT | MUX_MODE0) /* vout1_d12 */
339 0x210 (PIN_OUTPUT | MUX_MODE0) /* vout1_d13 */
340 0x214 (PIN_OUTPUT | MUX_MODE0) /* vout1_d14 */
341 0x218 (PIN_OUTPUT | MUX_MODE0) /* vout1_d15 */
342 0x21C (PIN_OUTPUT | MUX_MODE0) /* vout1_d16 */
343 0x220 (PIN_OUTPUT | MUX_MODE0) /* vout1_d17 */
344 0x224 (PIN_OUTPUT | MUX_MODE0) /* vout1_d18 */
345 0x228 (PIN_OUTPUT | MUX_MODE0) /* vout1_d19 */
346 0x22C (PIN_OUTPUT | MUX_MODE0) /* vout1_d20 */
347 0x230 (PIN_OUTPUT | MUX_MODE0) /* vout1_d21 */
348 0x234 (PIN_OUTPUT | MUX_MODE0) /* vout1_d22 */
349 0x238 (PIN_OUTPUT | MUX_MODE0) /* vout1_d23 */
350 >;
351 };
353 hpd_pin: pinmux_hpd_pin {
354 pinctrl-single,pins = <
355 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 */
356 >;
357 };
359 atl_pins: pinmux_atl_pins {
360 pinctrl-single,pins = <
361 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
362 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
363 >;
364 };
366 mcasp2_pins: pinmux_mcasp2_pins {
367 pinctrl-single,pins = <
368 0x02F4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_aclkx */
369 0x02F8 (PIN_INPUT_SLEW | MUX_MODE0) /* mcasp2_afsx */
370 0x0304 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr0 */
371 0x0308 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr1 */
372 0x030C (PIN_INPUT_SLEW | MUX_MODE0) /* mcasp2_axr2 */
373 0x0310 (PIN_INPUT_SLEW | MUX_MODE0) /* mcasp2_axr3 */
374 0x0314 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr4 */
375 0x0318 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr5 */
376 0x031c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr6 */
377 0x0320 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr7 */
378 >;
379 };
381 mcasp3_pins: pinmux_mcasp3_pins {
382 pinctrl-single,pins = <
383 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
384 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
385 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
386 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
387 >;
388 };
390 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
391 pinctrl-single,pins = <
392 0x324 (PIN_OFF_NONE)
393 0x328 (PIN_OFF_NONE)
394 0x32c (PIN_OFF_NONE)
395 0x330 (PIN_OFF_NONE)
396 >;
397 };
399 mcasp6_pins: pinmux_mcasp6_pins {
400 pinctrl-single,pins = <
401 0x2d4 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mcasp6_axr0 */
402 0x2d8 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp6_axr1 */
403 0x2dc (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mcasp6_clkx */
404 0x2e0 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp6_fsx */
405 >;
406 };
408 mcasp7_pins: pinmux_mcasp7_pins {
409 pinctrl-single,pins = <
410 0x2e4 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp7_axr0 */
411 0x2e8 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mcasp7_axr1 */
412 0x2ec (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp7_clkx */
413 0x2f0 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp7_fsx */
414 >;
415 };
417 mcasp7_sleep_pins: pinmux_mcasp7_sleep_pins {
418 pinctrl-single,pins = <
419 0x2e4 (PIN_OFF_NONE)
420 0x2e8 (PIN_OFF_NONE)
421 0x2ec (PIN_OFF_NONE)
422 0x2f0 (PIN_OFF_NONE)
423 >;
424 };
426 usb1_pins: pinmux_usb1_pins {
427 pinctrl-single,pins = <
428 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
429 >;
430 };
432 usb2_pins: pinmux_usb2_pins {
433 pinctrl-single,pins = <
434 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
435 >;
436 };
438 tsc_pins: pinmux_tsc_pins {
439 pinctrl-single,pins = <
440 0x3D4 (PIN_INPUT_PULLUP | MUX_MODE14) /* dcan1_rx -> gpio1_15 */
441 >;
442 };
444 qspi1_pins: pinmux_qspi1_pins {
445 pinctrl-single,pins = <
446 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
447 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
448 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
449 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
450 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
451 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
452 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
453 >;
454 };
456 dcan1_pins_default: dcan1_pins_default {
457 pinctrl-single,pins = <
458 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
459 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
460 >;
461 };
463 dcan1_pins_sleep: dcan1_pins_sleep {
464 pinctrl-single,pins = <
465 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
466 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
467 >;
468 };
470 radio_pins: pinmux_radio_pins {
471 pinctrl-single,pins = <
472 0x0334 (PIN_INPUT | MUX_MODE4) /* i2c4_sda */
473 0x0338 (PIN_INPUT | MUX_MODE4) /* i2c4_scl */
474 0x02A0 (PIN_INPUT | MUX_MODE14) /* gpio6_20 */
475 >;
476 };
478 wlan_pins: pinmux_wlan_pins {
479 pinctrl-single,pins = <
480 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
481 0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
482 0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
483 0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
484 0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
485 0x3fc (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
486 0x2cc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr6.gpio5_8 - WLAN_EN */
487 >;
488 };
490 wlirq_pins: pinmux_wlirq_pins {
491 pinctrl-single,pins = <
492 0x2c8 (PIN_INPUT_PULLDOWN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */
493 >;
494 };
496 vin1a_pins: pinmux_vin1a_pins {
497 pinctrl-single,pins = <
498 0x0DC (PIN_INPUT | MUX_MODE0) /* vin1a_clk0 */
499 0x0E4 (PIN_INPUT | MUX_MODE0) /* vin1a_de0 */
500 0x0E8 (PIN_INPUT | MUX_MODE0) /* vin1a_fld0 */
501 0x0EC (PIN_INPUT | MUX_MODE0) /* vin1a_hsync0 */
502 0x0F0 (PIN_INPUT | MUX_MODE0) /* vin1a_vsync0 */
503 0x0F4 (PIN_INPUT | MUX_MODE0) /* vin1a_d0 */
504 0x0F8 (PIN_INPUT | MUX_MODE0) /* vin1a_d1 */
505 0x0FC (PIN_INPUT | MUX_MODE0) /* vin1a_d2 */
506 0x100 (PIN_INPUT | MUX_MODE0) /* vin1a_d3 */
507 0x104 (PIN_INPUT | MUX_MODE0) /* vin1a_d4 */
508 0x108 (PIN_INPUT | MUX_MODE0) /* vin1a_d5 */
509 0x10C (PIN_INPUT | MUX_MODE0) /* vin1a_d6 */
510 0x110 (PIN_INPUT | MUX_MODE0) /* vin1a_d7 */
511 0x114 (PIN_INPUT | MUX_MODE0) /* vin1a_d8 */
512 0x118 (PIN_INPUT | MUX_MODE0) /* vin1a_d9 */
513 0x11C (PIN_INPUT | MUX_MODE0) /* vin1a_d10 */
514 0x120 (PIN_INPUT | MUX_MODE0) /* vin1a_d11 */
515 0x124 (PIN_INPUT | MUX_MODE0) /* vin1a_d12 */
516 0x128 (PIN_INPUT | MUX_MODE0) /* vin1a_d13 */
517 0x12C (PIN_INPUT | MUX_MODE0) /* vin1a_d14 */
518 0x130 (PIN_INPUT | MUX_MODE0) /* vin1a_d15 */
519 >;
520 };
522 vin1a_d16_d23_pins: pinmux_vin1a_d16_d23_pins {
523 pinctrl-single,pins = <
524 0x134 (PIN_INPUT | MUX_MODE0) /* vin1a_d16 */
525 0x138 (PIN_INPUT | MUX_MODE0) /* vin1a_d17 */
526 0x13C (PIN_INPUT | MUX_MODE0) /* vin1a_d18 */
527 0x140 (PIN_INPUT | MUX_MODE0) /* vin1a_d19 */
528 0x144 (PIN_INPUT | MUX_MODE0) /* vin1a_d20 */
529 0x148 (PIN_INPUT | MUX_MODE0) /* vin1a_d21 */
530 0x14C (PIN_INPUT | MUX_MODE0) /* vin1a_d22 */
531 0x150 (PIN_INPUT | MUX_MODE0) /* vin1a_d23 */
533 >;
534 };
536 vin2a_pins: pinmux_vin2a_pins {
537 pinctrl-single,pins = <
538 0x154 (PIN_INPUT | MUX_MODE0) /* vin2a_clk0 */
539 0x160 (PIN_INPUT | MUX_MODE0) /* vin2a_hsync0 */
540 0x164 (PIN_INPUT | MUX_MODE0) /* vin2a_vsync0 */
541 0x168 (PIN_INPUT | MUX_MODE0) /* vin2a_d0 */
542 0x16c (PIN_INPUT | MUX_MODE0) /* vin2a_d1 */
543 0x170 (PIN_INPUT | MUX_MODE0) /* vin2a_d2 */
544 0x174 (PIN_INPUT | MUX_MODE0) /* vin2a_d3 */
545 0x178 (PIN_INPUT | MUX_MODE0) /* vin2a_d4 */
546 0x17c (PIN_INPUT | MUX_MODE0) /* vin2a_d5 */
547 0x180 (PIN_INPUT | MUX_MODE0) /* vin2a_d6 */
548 0x184 (PIN_INPUT | MUX_MODE0) /* vin2a_d7 */
549 >;
550 };
552 };
554 &i2c1 {
555 status = "okay";
556 pinctrl-names = "default";
557 pinctrl-0 = <&i2c1_pins>;
558 clock-frequency = <400000>;
560 tps65917: tps65917@58 {
561 compatible = "ti,tps65917";
562 reg = <0x58>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&tps65917_pins_default>;
566 interrupts-extended = <&gic GIC_SPI 2 IRQ_TYPE_NONE
567 &dra7_pmx_core 0x424>;
568 interrupt-parent = <&gic>;
569 interrupt-controller;
570 #interrupt-cells = <2>;
572 ti,system-power-controller;
574 tps65917_pmic {
575 compatible = "ti,tps65917-pmic";
577 regulators {
578 smps1_reg: smps1 {
579 /* VDD_MPU */
580 regulator-name = "smps1";
581 regulator-min-microvolt = <850000>;
582 regulator-max-microvolt = <1250000>;
583 regulator-always-on;
584 regulator-boot-on;
585 };
587 smps2_reg: smps2 {
588 /* VDD_CORE */
589 regulator-name = "smps2";
590 regulator-min-microvolt = <850000>;
591 regulator-max-microvolt = <1060000>;
592 regulator-boot-on;
593 regulator-always-on;
594 };
596 smps3_reg: smps3 {
597 /* VDD_GPU IVA DSPEVE */
598 regulator-name = "smps3";
599 regulator-min-microvolt = <850000>;
600 regulator-max-microvolt = <1250000>;
601 regulator-boot-on;
602 regulator-always-on;
603 };
605 smps4_reg: smps4 {
606 /* VDDS1V8 */
607 regulator-name = "smps4";
608 regulator-min-microvolt = <1800000>;
609 regulator-max-microvolt = <1800000>;
610 regulator-always-on;
611 regulator-boot-on;
612 };
614 smps5_reg: smps5 {
615 /* VDD_DDR */
616 regulator-name = "smps5";
617 regulator-min-microvolt = <1350000>;
618 regulator-max-microvolt = <1350000>;
619 regulator-boot-on;
620 regulator-always-on;
621 };
623 ldo1_reg: ldo1 {
624 /* LDO1_OUT --> SDIO */
625 regulator-name = "ldo1";
626 regulator-min-microvolt = <1800000>;
627 regulator-max-microvolt = <3300000>;
628 regulator-always-on;
629 regulator-boot-on;
630 };
632 ldo2_reg: ldo2 {
633 /* LDO2_OUT --> TP1017 (UNUSED) */
634 regulator-name = "ldo2";
635 regulator-min-microvolt = <1800000>;
636 regulator-max-microvolt = <3300000>;
637 };
639 ldo3_reg: ldo3 {
640 /* VDDA_1V8_PHY */
641 regulator-name = "ldo3";
642 regulator-min-microvolt = <1800000>;
643 regulator-max-microvolt = <1800000>;
644 regulator-boot-on;
645 regulator-always-on;
646 };
648 ldo5_reg: ldo5 {
649 /* VDDA_1V8_PLL */
650 regulator-name = "ldo5";
651 regulator-min-microvolt = <1800000>;
652 regulator-max-microvolt = <1800000>;
653 regulator-always-on;
654 regulator-boot-on;
655 };
657 ldo4_reg: ldo4 {
658 /* VDDA_3V_USB: VDDA_USBHS33 */
659 regulator-name = "ldo4";
660 regulator-min-microvolt = <3300000>;
661 regulator-max-microvolt = <3300000>;
662 regulator-boot-on;
663 };
664 };
665 };
667 tps65917_power_button {
668 compatible = "ti,palmas-pwrbutton";
669 interrupt-parent = <&tps65917>;
670 interrupts = <1 IRQ_TYPE_NONE>;
671 wakeup-source;
672 ti,palmas-long-press-seconds = <6>;
673 };
674 };
676 pcf_lcd: gpio@20 {
677 compatible = "nxp,pcf8575";
678 reg = <0x20>;
679 gpio-controller;
680 #gpio-cells = <2>;
681 };
683 pcf_gpio_21: gpio@21 {
684 compatible = "nxp,pcf8575";
685 reg = <0x21>;
686 lines-initial-states = <0x1408>;
687 gpio-controller;
688 #gpio-cells = <2>;
689 interrupt-parent = <&gpio6>;
690 interrupts = <11 2>;
691 interrupt-controller;
692 #interrupt-cells = <2>;
694 };
696 tlv320aic3106: tlv320aic3106@19 {
697 compatible = "ti,tlv320aic3106";
698 reg = <0x19>;
699 adc-settle-ms = <40>;
700 ai3x-micbias-vg = <1>; /* 2.0V */
701 status = "okay";
703 /* Regulators */
704 AVDD-supply = <&evm_3v3_sw>;
705 IOVDD-supply = <&evm_3v3_sw>;
706 DRVDD-supply = <&evm_3v3_sw>;
707 DVDD-supply = <&aic_dvdd>;
708 };
709 };
711 &dra7_pmx_core {
712 i2c5_pins: pinmux_i2c5_pins {
713 pinctrl-single,pins = <
714 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
715 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
716 >;
717 };
718 };
720 i2c_p3_exp: &i2c5 {
721 status = "okay";
722 pinctrl-names = "default";
723 pinctrl-0 = <&i2c5_pins>;
724 clock-frequency = <400000>;
726 pcf_hdmi: pcf8575@26 {
727 compatible = "nxp,pcf8575";
728 reg = <0x26>;
729 gpio-controller;
730 #gpio-cells = <2>;
731 /*
732 * initial state is used here to keep the mdio interface
733 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
734 * VIN2_S0 driven high otherwise Ethernet stops working
735 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
736 */
737 lines-initial-states = <0x0f2b>;
738 };
740 ov10633@37 {
741 compatible = "ovti,ov10633";
742 reg = <0x37>;
744 mux-gpios = <&pcf_hdmi 2 GPIO_ACTIVE_HIGH>, /* VIN2_S0 */
745 <&pcf_hdmi 6 GPIO_ACTIVE_LOW>; /* VIN2_S2 */
746 port {
747 onboardLI: endpoint {
748 remote-endpoint = <&vin2a>;
749 hsync-active = <1>;
750 vsync-active = <1>;
751 pclk-sample = <0>;
752 };
753 };
754 };
755 };
757 &uart1 {
758 pinctrl-names = "default";
759 pinctrl-0 = <&uart1_pins>;
761 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
762 &dra7_pmx_core 0x3e0>;
763 status = "okay";
764 };
766 &uart3 {
767 status = "okay";
768 gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
769 pinctrl-names = "default";
770 pinctrl-0 = <&bt_uart3_pins>;
771 };
773 &mmc1 {
774 /* Using default configured pins */
775 status = "okay";
776 pbias-supply = <&pbias_mmc_reg>;
777 vmmc-supply = <&evm_3v3_sd>;
778 vmmc_aux-supply = <&ldo1_reg>;
779 bus-width = <4>;
780 /*
781 * SDCD signal is not being used here - using the fact that GPIO mode
782 * is always hardwired.
783 */
784 cd-gpios = <&gpio6 27 0>;
785 sd-uhs-sdr104;
786 sd-uhs-sdr50;
787 sd-uhs-ddr50;
788 sd-uhs-sdr25;
789 sd-uhs-sdr12;
790 max-frequency = <192000000>;
791 };
793 &mmc2 {
794 /* Using default configured pins */
795 status = "okay";
796 vmmc-supply = <&evm_3v3_sw>;
797 bus-width = <8>;
798 ti,non-removable;
799 mmc-hs200-1_8v;
800 max-frequency = <192000000>;
801 };
803 &mmc4 {
804 status = "okay";
805 vmmc-supply = <&vmmcwl_fixed>;
806 bus-width = <4>;
807 pinctrl-names = "default";
808 pinctrl-0 = <&wlan_pins &wlirq_pins>;
809 cap-power-off-card;
810 keep-power-in-suspend;
811 ti,non-removable;
813 #address-cells = <1>;
814 #size-cells = <0>;
815 wlcore: wlcore@0 {
816 compatible = "ti,wlcore";
817 reg = <2>;
818 interrupt-parent = <&gpio5>;
819 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
820 };
821 };
823 &mac {
824 status = "okay";
825 pinctrl-names = "default", "sleep";
826 pinctrl-0 = <&cpsw_default>;
827 pinctrl-1 = <&cpsw_sleep>;
828 slaves = <1>;
829 ti,no-idle;
830 };
832 &cpsw_emac0 {
833 phy_id = <&davinci_mdio>, <3>;
834 phy-mode = "rgmii";
835 };
837 &davinci_mdio {
838 pinctrl-names = "default", "sleep";
839 pinctrl-0 = <&davinci_mdio_default>;
840 pinctrl-1 = <&davinci_mdio_sleep>;
841 };
843 &cpu0 {
844 cpu0-voltdm = <&voltdm_mpu>;
845 voltage-tolerance = <1>;
846 };
848 &voltdm_mpu {
849 vdd-supply = <&smps1_reg>;
850 };
852 &voltdm_core {
853 vdd-supply = <&smps2_reg>;
854 };
856 &voltdm_dspeve {
857 vdd-supply = <&smps3_reg>;
858 };
860 &voltdm_gpu {
861 vdd-supply = <&smps3_reg>;
862 };
864 &voltdm_ivahd {
865 vdd-supply = <&smps3_reg>;
866 };
868 &elm {
869 status = "okay";
870 };
872 &gpmc {
873 status = "okay";
874 pinctrl-names = "default";
875 pinctrl-0 = <&nand_default>;
876 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
877 nand@0,0 {
878 /* To use NAND, DIP switch SW5 must be set like so:
879 * SW5.1 (NAND_SELn) = ON (LOW)
880 * SW5.9 (GPMC_WPN) = OFF (HIGH)
881 */
882 reg = <0 0 4>; /* device IO registers */
883 ti,nand-ecc-opt = "bch8";
884 ti,elm-id = <&elm>;
885 nand-bus-width = <16>;
886 gpmc,device-width = <2>;
887 gpmc,sync-clk-ps = <0>;
888 gpmc,cs-on-ns = <0>;
889 gpmc,cs-rd-off-ns = <80>;
890 gpmc,cs-wr-off-ns = <80>;
891 gpmc,adv-on-ns = <0>;
892 gpmc,adv-rd-off-ns = <60>;
893 gpmc,adv-wr-off-ns = <60>;
894 gpmc,we-on-ns = <10>;
895 gpmc,we-off-ns = <50>;
896 gpmc,oe-on-ns = <4>;
897 gpmc,oe-off-ns = <40>;
898 gpmc,access-ns = <40>;
899 gpmc,wr-access-ns = <80>;
900 gpmc,rd-cycle-ns = <80>;
901 gpmc,wr-cycle-ns = <80>;
902 gpmc,bus-turnaround-ns = <0>;
903 gpmc,cycle2cycle-delay-ns = <0>;
904 gpmc,clk-activation-ns = <0>;
905 gpmc,wait-monitoring-ns = <0>;
906 gpmc,wr-data-mux-bus-ns = <0>;
907 /* MTD partition table */
908 /* All SPL-* partitions are sized to minimal length
909 * which can be independently programmable. For
910 * NAND flash this is equal to size of erase-block */
911 #address-cells = <1>;
912 #size-cells = <1>;
913 partition@0 {
914 label = "NAND.SPL";
915 reg = <0x00000000 0x000020000>;
916 };
917 partition@1 {
918 label = "NAND.SPL.backup1";
919 reg = <0x00020000 0x00020000>;
920 };
921 partition@2 {
922 label = "NAND.SPL.backup2";
923 reg = <0x00040000 0x00020000>;
924 };
925 partition@3 {
926 label = "NAND.SPL.backup3";
927 reg = <0x00060000 0x00020000>;
928 };
929 partition@4 {
930 label = "NAND.u-boot-spl-os";
931 reg = <0x00080000 0x00040000>;
932 };
933 partition@5 {
934 label = "NAND.u-boot";
935 reg = <0x000c0000 0x00100000>;
936 };
937 partition@6 {
938 label = "NAND.u-boot-env";
939 reg = <0x001c0000 0x00020000>;
940 };
941 partition@7 {
942 label = "NAND.u-boot-env.backup1";
943 reg = <0x001e0000 0x00020000>;
944 };
945 partition@8 {
946 label = "NAND.kernel";
947 reg = <0x00200000 0x00800000>;
948 };
949 partition@9 {
950 label = "NAND.file-system";
951 reg = <0x00a00000 0x0f600000>;
952 };
953 };
954 };
956 &dss {
957 status = "ok";
959 vdda_video-supply = <&ldo5_reg>;
960 };
962 &hdmi {
963 status = "ok";
964 vdda-supply = <&ldo3_reg>;
965 pinctrl-names = "default";
966 pinctrl-0 = <&i2c2_pins>;
968 port {
969 hdmi_out: endpoint {
970 remote-endpoint = <&tpd12s015_in>;
971 };
972 };
973 };
975 &mailbox5 {
976 status = "okay";
977 mbox_ipu1_legacy: mbox_ipu1_legacy {
978 status = "okay";
979 };
980 mbox_dsp1_legacy: mbox_dsp1_legacy {
981 status = "okay";
982 };
983 };
985 &mailbox6 {
986 status = "okay";
987 mbox_ipu2_legacy: mbox_ipu2_legacy {
988 status = "okay";
989 };
990 };
992 &mmu0_dsp1 {
993 status = "okay";
994 };
996 &mmu1_dsp1 {
997 status = "okay";
998 };
1000 &mmu_ipu1 {
1001 status = "okay";
1002 };
1004 &mmu_ipu2 {
1005 status = "okay";
1006 };
1008 &ipu2 {
1009 status = "okay";
1010 memory-region = <&ipu2_cma_pool>;
1011 mboxes = <&mailbox6 &mbox_ipu2_legacy>;
1012 timers = <&timer3>;
1013 watchdog-timers = <&timer4>, <&timer9>;
1014 };
1016 &ipu1 {
1017 status = "okay";
1018 memory-region = <&ipu1_cma_pool>;
1019 mboxes = <&mailbox5 &mbox_ipu1_legacy>;
1020 timers = <&timer11>;
1021 watchdog-timers = <&timer7>, <&timer8>;
1022 };
1024 &dsp1 {
1025 status = "okay";
1026 memory-region = <&dsp1_cma_pool>;
1027 mboxes = <&mailbox5 &mbox_dsp1_legacy>;
1028 timers = <&timer5>;
1029 watchdog-timers = <&timer10>;
1030 };
1032 &atl {
1033 pinctrl-names = "default";
1034 pinctrl-0 = <&atl_pins>;
1036 status = "okay";
1038 atl2 {
1039 bws = <DRA7_ATL_WS_MCASP2_FSX>;
1040 aws = <DRA7_ATL_WS_MCASP3_FSX>;
1041 };
1042 };
1044 &mcasp2 {
1045 pinctrl-names = "default";
1046 pinctrl-0 = <&mcasp2_pins>;
1047 };
1049 &mcasp3 {
1050 pinctrl-names = "default", "sleep";
1051 pinctrl-0 = <&mcasp3_pins>;
1052 pinctrl-1 = <&mcasp3_sleep_pins>;
1054 fck_parent = "atl_clkin2_ck";
1056 status = "okay";
1058 op-mode = <0>; /* MCASP_IIS_MODE */
1059 tdm-slots = <2>;
1060 /* 4 serializer */
1061 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1062 1 2 0 0
1063 >;
1064 tx-num-evt = <8>;
1065 rx-num-evt = <8>;
1066 };
1068 &mcasp6 {
1069 pinctrl-names = "default";
1070 pinctrl-0 = <&mcasp6_pins>;
1071 };
1073 &mcasp7 {
1074 #sound-dai-cells = <0>;
1075 pinctrl-names = "default", "sleep";
1076 pinctrl-0 = <&mcasp7_pins>;
1077 pinctrl-1 = <&mcasp7_sleep_pins>;
1079 status = "okay";
1081 op-mode = <0>; /* MCASP_IIS_MODE */
1082 tdm-slots = <4>;
1083 /* 4 serializer */
1084 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1085 2 1 0 0
1086 >;
1087 tx-num-evt = <8>;
1088 rx-num-evt = <8>;
1089 };
1091 &omap_dwc3_1 {
1092 extcon = <&extcon_usb1>;
1093 };
1095 &omap_dwc3_2 {
1096 extcon = <&extcon_usb2>;
1097 };
1099 &usb2_phy1 {
1100 phy-supply = <&ldo4_reg>;
1101 };
1103 &usb2_phy2 {
1104 phy-supply = <&ldo4_reg>;
1105 };
1107 &usb1 {
1108 dr_mode = "otg";
1109 pinctrl-names = "default";
1110 pinctrl-0 = <&usb1_pins>;
1111 };
1113 &usb2 {
1114 dr_mode = "host";
1115 pinctrl-names = "default";
1116 pinctrl-0 = <&usb2_pins>;
1117 };
1119 &qspi {
1120 status = "okay";
1121 pinctrl-names = "default";
1122 pinctrl-0 = <&qspi1_pins>;
1124 spi-max-frequency = <48000000>;
1125 m25p80@0 {
1126 compatible = "s25fl256s1";
1127 spi-max-frequency = <48000000>;
1128 reg = <0>;
1129 spi-tx-bus-width = <1>;
1130 spi-rx-bus-width = <4>;
1131 spi-cpol;
1132 spi-cpha;
1133 #address-cells = <1>;
1134 #size-cells = <1>;
1136 /* MTD partition table.
1137 * The ROM checks the first four physical blocks
1138 * for a valid file to boot and the flash here is
1139 * 64KiB block size.
1140 */
1141 partition@0 {
1142 label = "QSPI.SPL";
1143 reg = <0x00000000 0x000010000>;
1144 };
1145 partition@1 {
1146 label = "QSPI.SPL.backup1";
1147 reg = <0x00010000 0x00010000>;
1148 };
1149 partition@2 {
1150 label = "QSPI.SPL.backup2";
1151 reg = <0x00020000 0x00010000>;
1152 };
1153 partition@3 {
1154 label = "QSPI.SPL.backup3";
1155 reg = <0x00030000 0x00010000>;
1156 };
1157 partition@4 {
1158 label = "QSPI.u-boot";
1159 reg = <0x00040000 0x00100000>;
1160 };
1161 partition@5 {
1162 label = "QSPI.u-boot-spl-os";
1163 reg = <0x00140000 0x00080000>;
1164 };
1165 partition@6 {
1166 label = "QSPI.u-boot-env";
1167 reg = <0x001c0000 0x00010000>;
1168 };
1169 partition@7 {
1170 label = "QSPI.u-boot-env.backup1";
1171 reg = <0x001d0000 0x0010000>;
1172 };
1173 partition@8 {
1174 label = "QSPI.kernel";
1175 reg = <0x001e0000 0x0800000>;
1176 };
1177 partition@9 {
1178 label = "QSPI.file-system";
1179 reg = <0x009e0000 0x01620000>;
1180 };
1181 };
1182 };
1184 &dcan1 {
1185 status = "ok";
1186 pinctrl-names = "default", "sleep";
1187 pinctrl-0 = <&dcan1_pins_default>;
1188 pinctrl-1 = <&dcan1_pins_sleep>;
1189 };
1191 &vip1 {
1192 pinctrl-names = "default";
1193 pinctrl-0 = <&vin2a_pins>;
1194 status = "okay";
1195 };
1197 video_in: &vin2a {
1198 status = "okay";
1199 endpoint@0 {
1200 slave-mode;
1201 remote-endpoint = <&onboardLI>;
1202 };
1203 };
1205 #include "dra7xx-jamr3.dtsi"
1206 &cal {
1207 status = "okay";
1208 };
1210 &dsp_radio {
1211 pinctrl-names = "default";
1212 pinctrl-0 = <&radio_pins>;
1213 };
1215 &tvp_5158{
1216 mux-gpios = <&pcf_hdmi 2 GPIO_ACTIVE_LOW>, /*VIN2_S0*/
1217 <&pcf_jamr3_21 8 GPIO_ACTIVE_LOW>, /*SEL_TVP_FPD*/
1218 <&pcf_hdmi 6 GPIO_ACTIVE_HIGH>; /*VIN2_S2*/
1219 };