1 /*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra72x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/clk/ti-dra7-atl.h>
14 / {
15 model = "TI DRA722";
16 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
18 aliases {
19 display0 = &hdmi0;
20 sound0 = &primary_sound;
21 sound1 = &hdmi;
22 i2c7 = &disp_ser;
23 };
25 memory {
26 device_type = "memory";
27 reg = <0x80000000 0x40000000>; /* 1024 MB */
28 };
30 tpd12s015: encoder@0 {
31 compatible = "ti,tpd12s015";
33 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
34 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
35 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
37 ports {
38 #address-cells = <1>;
39 #size-cells = <0>;
41 port@0 {
42 reg = <0>;
44 tpd12s015_in: endpoint@0 {
45 remote-endpoint = <&hdmi_out>;
46 };
47 };
49 port@1 {
50 reg = <1>;
52 tpd12s015_out: endpoint@0 {
53 remote-endpoint = <&hdmi_connector_in>;
54 };
55 };
56 };
57 };
59 hdmi0: connector@0 {
60 compatible = "hdmi-connector";
61 label = "hdmi";
63 type = "a";
65 port {
66 hdmi_connector_in: endpoint {
67 remote-endpoint = <&tpd12s015_out>;
68 };
69 };
70 };
72 reserved_mem: reserved-memory {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
77 ipu2_cma_pool: ipu2_cma@95800000 {
78 compatible = "shared-dma-pool";
79 reg = <0x95800000 0x3800000>;
80 reusable;
81 status = "okay";
82 };
84 dsp1_cma_pool: dsp1_cma@99000000 {
85 compatible = "shared-dma-pool";
86 reg = <0x99000000 0x4000000>;
87 reusable;
88 status = "okay";
89 };
91 ipu1_cma_pool: ipu1_cma@9d000000 {
92 compatible = "shared-dma-pool";
93 reg = <0x9d000000 0x2000000>;
94 reusable;
95 status = "okay";
96 };
97 };
99 extcon_usb1: extcon_usb1 {
100 compatible = "linux,extcon-usb-gpio";
101 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
102 };
104 extcon_usb2: extcon_usb2 {
105 compatible = "linux,extcon-usb-gpio";
106 id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
107 };
109 evm_3v3_sd: fixedregulator-sd {
110 compatible = "regulator-fixed";
111 regulator-name = "evm_3v3_sd";
112 regulator-min-microvolt = <3300000>;
113 regulator-max-microvolt = <3300000>;
114 enable-active-high;
115 gpio = <&pcf_gpio_21 5 0>;
116 };
118 evm_3v3_sw: fixedregulator-evm_3v3 {
119 compatible = "regulator-fixed";
120 regulator-name = "evm_3v3";
121 regulator-min-microvolt = <3300000>;
122 regulator-max-microvolt = <3300000>;
123 };
125 aic_dvdd: fixedregulator-aic_dvdd {
126 /* TPS77018DBVT */
127 compatible = "regulator-fixed";
128 regulator-name = "aic_dvdd";
129 vin-supply = <&evm_3v3_sw>;
130 regulator-min-microvolt = <1800000>;
131 regulator-max-microvolt = <1800000>;
132 };
134 primary_sound: primary_sound {
135 compatible = "ti,dra7xx-evm-audio";
136 ti,model = "DRA7xx-EVM";
137 ti,always-on;
138 ti,audio-codec = <&tlv320aic3106>;
139 ti,mcasp-controller = <&mcasp3>;
140 ti,codec-clock-rate = <11289600>;
141 clocks = <&atl_clkin2_ck>;
142 clock-names = "mclk";
143 ti,audio-routing =
144 "Headphone Jack", "HPLOUT",
145 "Headphone Jack", "HPROUT",
146 "Line Out", "LLOUT",
147 "Line Out", "RLOUT",
148 "MIC3L", "Mic Jack",
149 "MIC3R", "Mic Jack",
150 "Mic Jack", "Mic Bias",
151 "LINE1L", "Line In",
152 "LINE1R", "Line In";
153 };
155 btwilink_sound: btwilink_sound {
156 #sound-dai-cells = <0>;
157 compatible = "linux,bt-sco-audio";
158 status = "okay";
159 };
161 simple_bt_sco_card: bt_sco_card {
162 compatible = "simple-audio-card";
163 simple-audio-card,name = "DRA7xx-WiLink";
164 simple-audio-card,format = "dsp_a";
165 simple-audio-card,frame-master = <&btwilink_codec>;
166 simple-audio-card,bitclock-master = <&btwilink_codec>;
167 simple-audio-card,frame-inversion;
169 simple-audio-card,cpu {
170 sound-dai = <&mcasp7>;
171 };
173 btwilink_codec: simple-audio-card,codec {
174 sound-dai = <&btwilink_sound>;
175 };
176 };
178 vmmcwl_fixed: fixedregulator-mmcwl {
179 compatible = "regulator-fixed";
180 regulator-name = "vmmcwl_fixed";
181 regulator-min-microvolt = <1800000>;
182 regulator-max-microvolt = <1800000>;
183 gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; /* gpio5_8 */
184 enable-active-high;
185 };
187 kim {
188 compatible = "kim";
189 nshutdown_gpio = <132>;
190 dev_name = "/dev/ttyS2";
191 flow_cntrl = <1>;
192 baud_rate = <3686400>;
193 };
195 btwilink {
196 compatible = "btwilink";
197 };
198 };
200 &dra7_pmx_core {
201 tps65917_pins_default: tps65917_pins_default {
202 pinctrl-single,pins = <
203 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
204 >;
205 };
207 mmc1_pins_default: mmc1_pins_default {
208 pinctrl-single,pins = <
209 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
210 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
211 0x35C (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
212 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
213 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
214 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
215 0x36C (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_sdcd.mmc1_sdcd */
216 >;
217 };
219 mmc1_pins_virtual1: mmc1_pins_virtual1 {
220 pinctrl-single,pins = <
221 0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_clk.mmc1_clk */
222 0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
223 0x35C (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
224 0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
225 0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
226 0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
227 0x36C (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_sdcd.mmc1_sdcd */
228 >;
229 };
231 mmc1_pins_manual1: mmc1_pins_manual1 {
232 pinctrl-single,pins = <
233 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.mmc1_clk */
234 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
235 0x35C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
236 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
237 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
238 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
239 0x36C (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_sdcd.mmc1_sdcd */
240 >;
241 };
243 mmc1_pins_manual2: mmc1_pins_manual2 {
244 pinctrl-single,pins = <
245 0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_clk.mmc1_clk */
246 0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
247 0x35C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
248 0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
249 0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
250 0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
251 0x36C (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_sdcd.mmc1_sdcd */
252 >;
253 };
255 mmc2_pins_default: mmc2_pins_default {
256 pinctrl-single,pins = <
257 0x08C (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
258 0x090 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
259 0x094 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
260 0x098 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
261 0x09C (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
262 0x0A0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
263 0x0A4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
264 0x0A8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
265 0x0AC (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
266 0x0B0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
267 >;
268 };
270 mmc2_pins_manual1: mmc2_pins_manual1 {
271 pinctrl-single,pins = <
272 0x08C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
273 0x090 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
274 0x094 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
275 0x098 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
276 0x09C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
277 0x0A0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
278 0x0A4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
279 0x0A8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
280 0x0AC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
281 0x0B0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
282 >;
283 };
285 mmc2_pins_manual3: mmc2_pins_manual3 {
286 pinctrl-single,pins = <
287 0x08C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
288 0x090 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
289 0x094 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
290 0x098 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
291 0x09C (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
292 0x0A0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
293 0x0A4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
294 0x0A8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
295 0x0AC (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
296 0x0B0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
297 >;
298 };
300 mmc4_pins_default: mmc4_pins_default {
301 pinctrl-single,pins = <
302 0x3E8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
303 0x3EC (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
304 0x3F0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
305 0x3F4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
306 0x3F8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
307 0x3FC (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
308 >;
309 };
310 };
312 &dra7_iodelay_core {
313 mmc1_iodelay_manual1_conf: mmc1_iodelay_manual1_conf {
314 pinctrl-single,pins = <
315 0x618 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CLK_IN */
316 0x620 (A_DELAY(1353) | G_DELAY(0)) /* CFG_MMC1_CLK_OUT */
317 0x624 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_IN */
318 0x62C (A_DELAY(1) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
319 0x628 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
320 0x630 (A_DELAY(483) | G_DELAY(0)) /* CFG_MMC1_DAT0_IN */
321 0x638 (A_DELAY(16) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
322 0x634 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
323 0x63C (A_DELAY(126) | G_DELAY(0)) /* CFG_MMC1_DAT1_IN */
324 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
325 0x640 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
326 0x648 (A_DELAY(104) | G_DELAY(0)) /* CFG_MMC1_DAT2_IN */
327 0x650 (A_DELAY(34) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
328 0x64C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
329 0x654 (A_DELAY(33) | G_DELAY(0)) /* CFG_MMC1_DAT3_IN */
330 0x65C (A_DELAY(18) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
331 0x658 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
332 >;
333 };
335 mmc1_iodelay_manual2_conf: mmc1_iodelay_manual2_conf {
336 pinctrl-single,pins = <
337 0x620 (A_DELAY(560) | G_DELAY(365)) /* CFG_MMC1_CLK_OUT */
338 0x62C (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_CMD_OUT */
339 0x628 (A_DELAY(125) | G_DELAY(0)) /* CFG_MMC1_CMD_OEN */
340 0x638 (A_DELAY(29) | G_DELAY(0)) /* CFG_MMC1_DAT0_OUT */
341 0x634 (A_DELAY(43) | G_DELAY(0)) /* CFG_MMC1_DAT0_OEN */
342 0x644 (A_DELAY(0) | G_DELAY(0)) /* CFG_MMC1_DAT1_OUT */
343 0x640 (A_DELAY(433) | G_DELAY(0)) /* CFG_MMC1_DAT1_OEN */
344 0x650 (A_DELAY(47) | G_DELAY(0)) /* CFG_MMC1_DAT2_OUT */
345 0x64C (A_DELAY(287) | G_DELAY(0)) /* CFG_MMC1_DAT2_OEN */
346 0x65C (A_DELAY(30) | G_DELAY(0)) /* CFG_MMC1_DAT3_OUT */
347 0x658 (A_DELAY(351) | G_DELAY(0)) /* CFG_MMC1_DAT3_OEN */
348 >;
349 };
351 mmc2_iodelay_manual1_conf: mmc2_iodelay_manual1_conf {
352 pinctrl-single,pins = <
353 0x18C (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_IN */
354 0x194 (A_DELAY(100) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
355 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
356 0x1A4 (A_DELAY(391) | G_DELAY(0)) /* CFG_GPMC_A20_IN */
357 0x1AC (A_DELAY(219) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
358 0x1A8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
359 0x1B0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_IN */
360 0x1B8 (A_DELAY(24) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
361 0x1B4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
362 0x1BC (A_DELAY(211) | G_DELAY(0)) /* CFG_GPMC_A22_IN */
363 0x1C4 (A_DELAY(88) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
364 0x1C0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
365 0x1C8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A23_IN */
366 0x1D0 (A_DELAY(626) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */
367 0x1D4 (A_DELAY(320) | G_DELAY(0)) /* CFG_GPMC_A24_IN */
368 0x1DC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
369 0x1D8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
370 0x1E0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */
371 0x1E8 (A_DELAY(172) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
372 0x1E4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
373 0x1EC (A_DELAY(159) | G_DELAY(0)) /* CFG_GPMC_A26_IN */
374 0x1F4 (A_DELAY(177) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
375 0x1F0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
376 0x1F8 (A_DELAY(232) | G_DELAY(0)) /* CFG_GPMC_A27_IN */
377 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
378 0x1FC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
379 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */
380 0x368 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
381 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
382 >;
383 };
385 mmc2_iodelay_manual2_conf: mmc2_iodelay_manual2_conf {
386 pinctrl-single,pins = <
387 0x18C (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_IN */
388 0x194 (A_DELAY(100) | G_DELAY(0)) /* CFG_GPMC_A19_OUT */
389 0x190 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
390 0x1A4 (A_DELAY(173) | G_DELAY(0)) /* CFG_GPMC_A20_IN */
391 0x1AC (A_DELAY(219) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
392 0x1A8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
393 0x1B0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_IN */
394 0x1B8 (A_DELAY(24) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
395 0x1B4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
396 0x1BC (A_DELAY(40) | G_DELAY(0)) /* CFG_GPMC_A22_IN */
397 0x1C4 (A_DELAY(88) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
398 0x1C0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
399 0x1C8 (A_DELAY(716) | G_DELAY(2726)) /* CFG_GPMC_A23_IN */
400 0x1D0 (A_DELAY(626) | G_DELAY(0)) /* CFG_GPMC_A23_OUT */
401 0x1D4 (A_DELAY(133) | G_DELAY(0)) /* CFG_GPMC_A24_IN */
402 0x1DC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
403 0x1D8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
404 0x1E0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_IN */
405 0x1E8 (A_DELAY(172) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
406 0x1E4 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
407 0x1EC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_IN */
408 0x1F4 (A_DELAY(177) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
409 0x1F0 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
410 0x1F8 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_IN */
411 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
412 0x1FC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
413 0x360 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_IN */
414 0x368 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
415 0x364 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
416 >;
417 };
419 mmc2_iodelay_manual3_conf: mmc2_iodelay_manual3_conf {
420 pinctrl-single,pins = <
421 0x194 (A_DELAY(0) | G_DELAY(95)) /* CFG_GPMC_A19_OUT */
422 0x190 (A_DELAY(695) | G_DELAY(0)) /* CFG_GPMC_A19_OEN */
423 0x1AC (A_DELAY(214) | G_DELAY(0)) /* CFG_GPMC_A20_OUT */
424 0x1A8 (A_DELAY(924) | G_DELAY(0)) /* CFG_GPMC_A20_OEN */
425 0x1B8 (A_DELAY(19) | G_DELAY(0)) /* CFG_GPMC_A21_OUT */
426 0x1B4 (A_DELAY(719) | G_DELAY(0)) /* CFG_GPMC_A21_OEN */
427 0x1C4 (A_DELAY(83) | G_DELAY(0)) /* CFG_GPMC_A22_OUT */
428 0x1C0 (A_DELAY(824) | G_DELAY(0)) /* CFG_GPMC_A22_OEN */
429 0x1D0 (A_DELAY(1020) | G_DELAY(416)) /* CFG_GPMC_A23_OUT */
430 0x1DC (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A24_OUT */
431 0x1D8 (A_DELAY(877) | G_DELAY(0)) /* CFG_GPMC_A24_OEN */
432 0x1E8 (A_DELAY(167) | G_DELAY(0)) /* CFG_GPMC_A25_OUT */
433 0x1E4 (A_DELAY(446) | G_DELAY(0)) /* CFG_GPMC_A25_OEN */
434 0x1F4 (A_DELAY(172) | G_DELAY(0)) /* CFG_GPMC_A26_OUT */
435 0x1F0 (A_DELAY(847) | G_DELAY(0)) /* CFG_GPMC_A26_OEN */
436 0x200 (A_DELAY(0) | G_DELAY(0)) /* CFG_GPMC_A27_OUT */
437 0x1FC (A_DELAY(586) | G_DELAY(0)) /* CFG_GPMC_A27_OEN */
438 0x368 (A_DELAY(40) | G_DELAY(0)) /* CFG_GPMC_CS1_OUT */
439 0x364 (A_DELAY(1039) | G_DELAY(0)) /* CFG_GPMC_CS1_OEN */
440 >;
441 };
443 };
445 &i2c1 {
446 status = "okay";
447 clock-frequency = <400000>;
449 tps65917: tps65917@58 {
450 compatible = "ti,tps65917";
451 reg = <0x58>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&tps65917_pins_default>;
455 interrupts-extended = <&gic GIC_SPI 2 IRQ_TYPE_NONE
456 &dra7_pmx_core 0x424>;
457 interrupt-parent = <&gic>;
458 interrupt-controller;
459 #interrupt-cells = <2>;
461 ti,system-power-controller;
463 tps65917_pmic {
464 compatible = "ti,tps65917-pmic";
466 regulators {
467 smps1_reg: smps1 {
468 /* VDD_MPU */
469 regulator-name = "smps1";
470 regulator-min-microvolt = <850000>;
471 regulator-max-microvolt = <1500000>;
472 regulator-always-on;
473 regulator-boot-on;
474 };
476 smps2_reg: smps2 {
477 /* VDD_CORE */
478 regulator-name = "smps2";
479 regulator-min-microvolt = <850000>;
480 regulator-max-microvolt = <1500000>;
481 regulator-boot-on;
482 regulator-always-on;
483 };
485 smps3_reg: smps3 {
486 /* VDD_GPU IVA DSPEVE */
487 regulator-name = "smps3";
488 regulator-min-microvolt = <850000>;
489 regulator-max-microvolt = <1500000>;
490 regulator-boot-on;
491 regulator-always-on;
492 };
494 smps4_reg: smps4 {
495 /* VDDS1V8 */
496 regulator-name = "smps4";
497 regulator-min-microvolt = <1800000>;
498 regulator-max-microvolt = <1800000>;
499 regulator-always-on;
500 regulator-boot-on;
501 };
503 smps5_reg: smps5 {
504 /* VDD_DDR */
505 regulator-name = "smps5";
506 regulator-min-microvolt = <1350000>;
507 regulator-max-microvolt = <1350000>;
508 regulator-boot-on;
509 regulator-always-on;
510 };
512 ldo1_reg: ldo1 {
513 /* LDO1_OUT --> SDIO */
514 regulator-name = "ldo1";
515 regulator-min-microvolt = <1800000>;
516 regulator-max-microvolt = <3300000>;
517 regulator-always-on;
518 regulator-boot-on;
519 };
521 ldo2_reg: ldo2 {
522 /* LDO2_OUT --> TP1017 (UNUSED) */
523 regulator-name = "ldo2";
524 regulator-min-microvolt = <1800000>;
525 regulator-max-microvolt = <3300000>;
526 };
528 ldo3_reg: ldo3 {
529 /* VDDA_1V8_PHY */
530 regulator-name = "ldo3";
531 regulator-min-microvolt = <1800000>;
532 regulator-max-microvolt = <1800000>;
533 regulator-boot-on;
534 regulator-always-on;
535 };
537 ldo5_reg: ldo5 {
538 /* VDDA_1V8_PLL */
539 regulator-name = "ldo5";
540 regulator-min-microvolt = <1800000>;
541 regulator-max-microvolt = <1800000>;
542 regulator-always-on;
543 regulator-boot-on;
544 };
546 ldo4_reg: ldo4 {
547 /* VDDA_3V_USB: VDDA_USBHS33 */
548 regulator-name = "ldo4";
549 regulator-min-microvolt = <3300000>;
550 regulator-max-microvolt = <3300000>;
551 regulator-boot-on;
552 };
553 };
554 };
556 tps65917_power_button {
557 compatible = "ti,palmas-pwrbutton";
558 interrupt-parent = <&tps65917>;
559 interrupts = <1 IRQ_TYPE_NONE>;
560 wakeup-source;
561 ti,palmas-long-press-seconds = <6>;
562 };
563 };
565 pcf_lcd: gpio@20 {
566 compatible = "nxp,pcf8575";
567 reg = <0x20>;
568 gpio-controller;
569 #gpio-cells = <2>;
570 };
572 pcf_lcd_tc3587x: gpio@27 {
573 compatible = "nxp,pcf8575";
574 reg = <0x27>;
575 gpio-controller;
576 #gpio-cells = <2>;
577 };
579 pcf_gpio_21: gpio@21 {
580 compatible = "nxp,pcf8575";
581 reg = <0x21>;
582 lines-initial-states = <0x1408>;
583 gpio-controller;
584 #gpio-cells = <2>;
585 interrupt-parent = <&gpio6>;
586 interrupts = <11 2>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
590 sel_enet_mux_hog: cpsw_sel_s0 {
591 gpio-hog;
592 gpios = <4 GPIO_ACTIVE_HIGH>;
593 output-low;
594 };
595 };
597 tlv320aic3106: tlv320aic3106@19 {
598 compatible = "ti,tlv320aic3106";
599 reg = <0x19>;
600 adc-settle-ms = <40>;
601 ai3x-micbias-vg = <1>; /* 2.0V */
602 status = "okay";
604 /* Regulators */
605 AVDD-supply = <&evm_3v3_sw>;
606 IOVDD-supply = <&evm_3v3_sw>;
607 DRVDD-supply = <&evm_3v3_sw>;
608 DVDD-supply = <&aic_dvdd>;
609 };
610 };
612 i2c_p3_exp: &i2c5 {
613 status = "okay";
614 clock-frequency = <400000>;
616 pcf_hdmi: pcf8575@26 {
617 compatible = "nxp,pcf8575";
618 reg = <0x26>;
619 gpio-controller;
620 #gpio-cells = <2>;
621 /*
622 * initial state is used here to keep the mdio interface
623 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
624 * VIN2_S0 driven high otherwise Ethernet stops working
625 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
626 */
627 lines-initial-states = <0x0f2b>;
628 };
630 ov10633@37 {
631 compatible = "ovti,ov10633";
632 reg = <0x37>;
634 mux-gpios = <&pcf_hdmi 2 GPIO_ACTIVE_HIGH>, /* VIN2_S0 */
635 <&pcf_hdmi 6 GPIO_ACTIVE_LOW>; /* VIN2_S2 */
636 port {
637 onboardLI: endpoint {
638 remote-endpoint = <&vin2a>;
639 hsync-active = <1>;
640 vsync-active = <1>;
641 pclk-sample = <0>;
642 };
643 };
644 };
646 disp_ser: serializer@1b {
647 status = "disabled";
648 compatible = "ti,ds90uh925q";
649 reg = <0x1b>;
651 #address-cells = <1>;
652 #size-cells = <0>;
653 ranges = <0x2c 0x2c>,
654 <0x1c 0x1c>;
656 disp_des: deserializer@2c {
657 compatible = "ti,ds90uh928q";
658 reg = <0x2c>;
659 slave-mode;
660 };
662 /* TLC chip for LCD panel power and backlight */
663 fpd_disp: tlc59108@1c {
664 reg = <0x1c>;
665 compatible = "ti,tlc59108-fpddisp";
666 enable-gpios = <&pcf_gpio_21 0 GPIO_ACTIVE_LOW>;
667 /* P0, SEL_GPMC_AD_VID_S0 */
669 port@lcd3 {
670 fpd_in: endpoint {
671 remote-endpoint = <&dpi_out3>;
672 };
673 };
674 };
675 };
676 };
678 &uart1 {
679 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
680 &dra7_pmx_core 0x3e0>;
681 status = "okay";
682 };
684 &uart3 {
685 status = "okay";
686 gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
687 };
689 &mmc1 {
690 status = "okay";
691 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
692 pinctrl-0 = <&mmc1_pins_default>;
693 pinctrl-1 = <&mmc1_pins_default>;
694 pinctrl-2 = <&mmc1_pins_default>;
695 pinctrl-3 = <&mmc1_pins_default>;
696 pinctrl-4 = <&mmc1_pins_virtual1>;
697 pinctrl-5 = <&mmc1_pins_manual1 &mmc1_iodelay_manual1_conf>;
698 pinctrl-6 = <&mmc1_pins_manual2 &mmc1_iodelay_manual2_conf>;
699 pbias-supply = <&pbias_mmc_reg>;
700 vmmc-supply = <&evm_3v3_sd>;
701 vmmc_aux-supply = <&ldo1_reg>;
702 bus-width = <4>;
703 /*
704 * SDCD signal is not being used here - using the fact that GPIO mode
705 * is always hardwired.
706 */
707 cd-gpios = <&gpio6 27 0>;
708 sd-uhs-sdr104;
709 sd-uhs-sdr50;
710 sd-uhs-ddr50;
711 sd-uhs-sdr25;
712 sd-uhs-sdr12;
713 max-frequency = <192000000>;
714 };
716 &mmc2 {
717 status = "okay";
718 pinctrl-names = "default", "hs", "ddr_3_3v", "hs200";
719 pinctrl-0 = <&mmc2_pins_default>;
720 pinctrl-1 = <&mmc2_pins_default>;
721 pinctrl-2 = <&mmc2_pins_manual1 &mmc2_iodelay_manual1_conf>;
722 pinctrl-3 = <&mmc2_pins_manual3 &mmc2_iodelay_manual3_conf>;
723 vmmc-supply = <&evm_3v3_sw>;
724 bus-width = <8>;
725 ti,non-removable;
726 mmc-hs200-1_8v;
727 max-frequency = <192000000>;
728 };
730 &mmc4 {
731 status = "okay";
732 pinctrl-names = "default";
733 pinctrl-0 = <&mmc4_pins_default>;
734 vmmc-supply = <&vmmcwl_fixed>;
735 bus-width = <4>;
736 cap-power-off-card;
737 keep-power-in-suspend;
738 ti,non-removable;
740 #address-cells = <1>;
741 #size-cells = <0>;
742 wlcore: wlcore@0 {
743 compatible = "ti,wlcore";
744 reg = <2>;
745 interrupt-parent = <&gpio5>;
746 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
747 };
748 };
750 &mac {
751 status = "okay";
752 slaves = <1>;
753 ti,no-idle;
754 };
756 &cpsw_emac0 {
757 phy_id = <&davinci_mdio>, <3>;
758 phy-mode = "rgmii";
759 };
761 &cpu0 {
762 cpu0-voltdm = <&voltdm_mpu>;
763 voltage-tolerance = <1>;
764 };
766 &voltdm_mpu {
767 vdd-supply = <&smps1_reg>;
768 };
770 &voltdm_core {
771 vdd-supply = <&smps2_reg>;
772 };
774 &voltdm_dspeve {
775 vdd-supply = <&smps3_reg>;
776 };
778 &voltdm_gpu {
779 vdd-supply = <&smps3_reg>;
780 };
782 &voltdm_ivahd {
783 vdd-supply = <&smps3_reg>;
784 };
786 &elm {
787 status = "okay";
788 };
790 &gpmc {
791 status = "okay";
792 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
793 nand@0,0 {
794 /* To use NAND, DIP switch SW5 must be set like so:
795 * SW5.1 (NAND_SELn) = ON (LOW)
796 * SW5.9 (GPMC_WPN) = OFF (HIGH)
797 */
798 reg = <0 0 4>; /* device IO registers */
799 ti,nand-ecc-opt = "bch8";
800 ti,elm-id = <&elm>;
801 nand-bus-width = <16>;
802 gpmc,device-width = <2>;
803 gpmc,sync-clk-ps = <0>;
804 gpmc,cs-on-ns = <0>;
805 gpmc,cs-rd-off-ns = <80>;
806 gpmc,cs-wr-off-ns = <80>;
807 gpmc,adv-on-ns = <0>;
808 gpmc,adv-rd-off-ns = <60>;
809 gpmc,adv-wr-off-ns = <60>;
810 gpmc,we-on-ns = <10>;
811 gpmc,we-off-ns = <50>;
812 gpmc,oe-on-ns = <4>;
813 gpmc,oe-off-ns = <40>;
814 gpmc,access-ns = <40>;
815 gpmc,wr-access-ns = <80>;
816 gpmc,rd-cycle-ns = <80>;
817 gpmc,wr-cycle-ns = <80>;
818 gpmc,bus-turnaround-ns = <0>;
819 gpmc,cycle2cycle-delay-ns = <0>;
820 gpmc,clk-activation-ns = <0>;
821 gpmc,wait-monitoring-ns = <0>;
822 gpmc,wr-data-mux-bus-ns = <0>;
823 /* MTD partition table */
824 /* All SPL-* partitions are sized to minimal length
825 * which can be independently programmable. For
826 * NAND flash this is equal to size of erase-block */
827 #address-cells = <1>;
828 #size-cells = <1>;
829 partition@0 {
830 label = "NAND.SPL";
831 reg = <0x00000000 0x000020000>;
832 };
833 partition@1 {
834 label = "NAND.SPL.backup1";
835 reg = <0x00020000 0x00020000>;
836 };
837 partition@2 {
838 label = "NAND.SPL.backup2";
839 reg = <0x00040000 0x00020000>;
840 };
841 partition@3 {
842 label = "NAND.SPL.backup3";
843 reg = <0x00060000 0x00020000>;
844 };
845 partition@4 {
846 label = "NAND.u-boot-spl-os";
847 reg = <0x00080000 0x00040000>;
848 };
849 partition@5 {
850 label = "NAND.u-boot";
851 reg = <0x000c0000 0x00100000>;
852 };
853 partition@6 {
854 label = "NAND.u-boot-env";
855 reg = <0x001c0000 0x00020000>;
856 };
857 partition@7 {
858 label = "NAND.u-boot-env.backup1";
859 reg = <0x001e0000 0x00020000>;
860 };
861 partition@8 {
862 label = "NAND.kernel";
863 reg = <0x00200000 0x00800000>;
864 };
865 partition@9 {
866 label = "NAND.file-system";
867 reg = <0x00a00000 0x0f600000>;
868 };
869 };
870 };
872 &dss {
873 status = "ok";
875 vdda_video-supply = <&ldo5_reg>;
877 ports {
878 #address-cells = <1>;
879 #size-cells = <0>;
880 status = "disabled";
882 port@lcd3 {
883 reg = <2>;
885 dpi_out3: endpoint {
886 remote-endpoint = <&fpd_in>;
887 data-lines = <24>;
888 };
889 };
890 };
891 };
893 &hdmi {
894 status = "ok";
895 vdda-supply = <&ldo3_reg>;
897 port {
898 hdmi_out: endpoint {
899 remote-endpoint = <&tpd12s015_in>;
900 };
901 };
902 };
904 &mailbox5 {
905 status = "okay";
906 mbox_ipu1_legacy: mbox_ipu1_legacy {
907 status = "okay";
908 };
909 mbox_dsp1_legacy: mbox_dsp1_legacy {
910 status = "okay";
911 };
912 };
914 &mailbox6 {
915 status = "okay";
916 mbox_ipu2_legacy: mbox_ipu2_legacy {
917 status = "okay";
918 };
919 };
921 &mmu0_dsp1 {
922 status = "okay";
923 };
925 &mmu1_dsp1 {
926 status = "okay";
927 };
929 &mmu_ipu1 {
930 status = "okay";
931 };
933 &mmu_ipu2 {
934 status = "okay";
935 };
937 &ipu2 {
938 status = "okay";
939 memory-region = <&ipu2_cma_pool>;
940 mboxes = <&mailbox6 &mbox_ipu2_legacy>;
941 timers = <&timer3>;
942 watchdog-timers = <&timer4>, <&timer9>;
943 };
945 &ipu1 {
946 status = "okay";
947 memory-region = <&ipu1_cma_pool>;
948 mboxes = <&mailbox5 &mbox_ipu1_legacy>;
949 timers = <&timer11>;
950 watchdog-timers = <&timer7>, <&timer8>;
951 };
953 &dsp1 {
954 status = "okay";
955 memory-region = <&dsp1_cma_pool>;
956 mboxes = <&mailbox5 &mbox_dsp1_legacy>;
957 timers = <&timer5>;
958 watchdog-timers = <&timer10>;
959 };
961 &atl {
962 status = "okay";
964 atl2 {
965 bws = <DRA7_ATL_WS_MCASP2_FSX>;
966 aws = <DRA7_ATL_WS_MCASP3_FSX>;
967 };
968 };
970 &mcasp3 {
971 fck_parent = "atl_clkin2_ck";
973 status = "okay";
975 op-mode = <0>; /* MCASP_IIS_MODE */
976 tdm-slots = <2>;
977 /* 4 serializer */
978 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
979 1 2 0 0
980 >;
981 tx-num-evt = <8>;
982 rx-num-evt = <8>;
983 };
985 &mcasp7 {
986 #sound-dai-cells = <0>;
988 status = "okay";
990 op-mode = <0>; /* MCASP_IIS_MODE */
991 tdm-slots = <4>;
992 /* 4 serializer */
993 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
994 2 1 0 0
995 >;
996 tx-num-evt = <8>;
997 rx-num-evt = <8>;
998 };
1000 &omap_dwc3_1 {
1001 extcon = <&extcon_usb1>;
1002 };
1004 &omap_dwc3_2 {
1005 extcon = <&extcon_usb2>;
1006 };
1008 &usb2_phy1 {
1009 phy-supply = <&ldo4_reg>;
1010 };
1012 &usb2_phy2 {
1013 phy-supply = <&ldo4_reg>;
1014 };
1016 &usb1 {
1017 dr_mode = "otg";
1018 };
1020 &usb2 {
1021 dr_mode = "host";
1022 };
1024 &qspi {
1025 status = "okay";
1027 spi-max-frequency = <48000000>;
1028 m25p80@0 {
1029 compatible = "s25fl256s1";
1030 spi-max-frequency = <48000000>;
1031 reg = <0>;
1032 spi-tx-bus-width = <1>;
1033 spi-rx-bus-width = <4>;
1034 spi-cpol;
1035 spi-cpha;
1036 #address-cells = <1>;
1037 #size-cells = <1>;
1039 /* MTD partition table.
1040 * The ROM checks the first four physical blocks
1041 * for a valid file to boot and the flash here is
1042 * 64KiB block size.
1043 */
1044 partition@0 {
1045 label = "QSPI.SPL";
1046 reg = <0x00000000 0x000010000>;
1047 };
1048 partition@1 {
1049 label = "QSPI.SPL.backup1";
1050 reg = <0x00010000 0x00010000>;
1051 };
1052 partition@2 {
1053 label = "QSPI.SPL.backup2";
1054 reg = <0x00020000 0x00010000>;
1055 };
1056 partition@3 {
1057 label = "QSPI.SPL.backup3";
1058 reg = <0x00030000 0x00010000>;
1059 };
1060 partition@4 {
1061 label = "QSPI.u-boot";
1062 reg = <0x00040000 0x00100000>;
1063 };
1064 partition@5 {
1065 label = "QSPI.u-boot-spl-os";
1066 reg = <0x00140000 0x00080000>;
1067 };
1068 partition@6 {
1069 label = "QSPI.u-boot-env";
1070 reg = <0x001c0000 0x00010000>;
1071 };
1072 partition@7 {
1073 label = "QSPI.u-boot-env.backup1";
1074 reg = <0x001d0000 0x0010000>;
1075 };
1076 partition@8 {
1077 label = "QSPI.kernel";
1078 reg = <0x001e0000 0x0800000>;
1079 };
1080 partition@9 {
1081 label = "QSPI.file-system";
1082 reg = <0x009e0000 0x01620000>;
1083 };
1084 };
1085 };
1087 &dcan1 {
1088 status = "ok";
1089 };
1091 &vip1 {
1092 status = "okay";
1093 };
1095 video_in: &vin2a {
1096 status = "okay";
1097 endpoint@0 {
1098 slave-mode;
1099 remote-endpoint = <&onboardLI>;
1100 };
1101 };
1103 #include "dra7xx-jamr3.dtsi"
1104 &cal {
1105 status = "okay";
1106 };
1108 &tvp_5158{
1109 mux-gpios = <&pcf_hdmi 2 GPIO_ACTIVE_LOW>, /*VIN2_S0*/
1110 <&pcf_jamr3_21 8 GPIO_ACTIVE_LOW>, /*SEL_TVP_FPD*/
1111 <&pcf_hdmi 6 GPIO_ACTIVE_HIGH>; /*VIN2_S2*/
1112 };