1 /*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra72x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/clk/ti-dra7-atl.h>
14 / {
15 model = "TI DRA722";
16 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
18 aliases {
19 display0 = &hdmi0;
20 sound0 = &primary_sound;
21 sound1 = &hdmi;
22 };
24 memory {
25 device_type = "memory";
26 reg = <0x80000000 0x40000000>; /* 1024 MB */
27 };
29 tpd12s015: encoder@0 {
30 compatible = "ti,tpd12s015";
32 pinctrl-names = "default";
33 pinctrl-0 = <&hpd_pin>;
35 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
36 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
37 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
39 ports {
40 #address-cells = <1>;
41 #size-cells = <0>;
43 port@0 {
44 reg = <0>;
46 tpd12s015_in: endpoint@0 {
47 remote-endpoint = <&hdmi_out>;
48 };
49 };
51 port@1 {
52 reg = <1>;
54 tpd12s015_out: endpoint@0 {
55 remote-endpoint = <&hdmi_connector_in>;
56 };
57 };
58 };
59 };
61 hdmi0: connector@0 {
62 compatible = "hdmi-connector";
63 label = "hdmi";
65 type = "a";
67 port {
68 hdmi_connector_in: endpoint {
69 remote-endpoint = <&tpd12s015_out>;
70 };
71 };
72 };
74 reserved-memory {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges;
79 ipu2_cma_pool: ipu2_cma@95800000 {
80 compatible = "shared-dma-pool";
81 reg = <0x95800000 0x3800000>;
82 reusable;
83 status = "okay";
84 };
86 dsp1_cma_pool: dsp1_cma@99000000 {
87 compatible = "shared-dma-pool";
88 reg = <0x99000000 0x4000000>;
89 reusable;
90 status = "okay";
91 };
93 ipu1_cma_pool: ipu1_cma@9d000000 {
94 compatible = "shared-dma-pool";
95 reg = <0x9d000000 0x2000000>;
96 reusable;
97 status = "okay";
98 };
99 };
101 extcon_usb1: extcon_usb1 {
102 compatible = "linux,extcon-usb-gpio";
103 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
104 };
106 extcon_usb2: extcon_usb2 {
107 compatible = "linux,extcon-usb-gpio";
108 id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
109 };
111 evm_3v3_sd: fixedregulator-sd {
112 compatible = "regulator-fixed";
113 regulator-name = "evm_3v3_sd";
114 regulator-min-microvolt = <3300000>;
115 regulator-max-microvolt = <3300000>;
116 enable-active-high;
117 gpio = <&pcf_gpio_21 5 0>;
118 };
120 evm_3v3: fixedregulator-evm_3v3 {
121 compatible = "regulator-fixed";
122 regulator-name = "evm_3v3";
123 regulator-min-microvolt = <3300000>;
124 regulator-max-microvolt = <3300000>;
125 };
127 aic_dvdd: fixedregulator-aic_dvdd {
128 /* TPS77018DBVT */
129 compatible = "regulator-fixed";
130 regulator-name = "aic_dvdd";
131 vin-supply = <&evm_3v3>;
132 regulator-min-microvolt = <1800000>;
133 regulator-max-microvolt = <1800000>;
134 };
136 primary_sound: primary_sound {
137 compatible = "ti,dra7xx-evm-audio";
138 ti,model = "DRA7xx-EVM";
139 ti,audio-codec = <&tlv320aic3106>;
140 ti,mcasp-controller = <&mcasp3>;
141 ti,codec-clock-rate = <5644800>;
142 clocks = <&atl_clkin2_ck>;
143 clock-names = "mclk";
144 ti,audio-routing =
145 "Headphone Jack", "HPLOUT",
146 "Headphone Jack", "HPROUT",
147 "Line Out", "LLOUT",
148 "Line Out", "RLOUT",
149 "MIC3L", "Mic Jack",
150 "MIC3R", "Mic Jack",
151 "Mic Jack", "Mic Bias",
152 "LINE1L", "Line In",
153 "LINE1R", "Line In";
154 };
156 vmmcwl_fixed: fixedregulator-mmcwl {
157 compatible = "regulator-fixed";
158 regulator-name = "vmmcwl_fixed";
159 regulator-min-microvolt = <1800000>;
160 regulator-max-microvolt = <1800000>;
161 gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; /* gpio5_8 */
162 enable-active-high;
163 };
165 kim {
166 compatible = "kim";
167 nshutdown_gpio = <132>;
168 dev_name = "/dev/ttyS2";
169 flow_cntrl = <1>;
170 baud_rate = <3686400>;
171 };
173 btwilink {
174 compatible = "btwilink";
175 };
176 };
178 &dra7_pmx_core {
179 i2c1_pins: pinmux_i2c1_pins {
180 pinctrl-single,pins = <
181 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
182 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
183 >;
184 };
186 uart1_pins: pinmix_uart1_pins {
187 pinctrl-single,pins = <
188 0x3e0 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd */
189 0x3e4 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_txd */
190 >;
191 };
193 i2c2_pins: pinmux_i2c2_pins {
194 pinctrl-single,pins = <
195 0x408 (PIN_INPUT | MUX_MODE1) /* hdmi1_ddc_scl */
196 0x40c (PIN_INPUT | MUX_MODE1) /* hdmi1_ddc_sda */
197 >;
198 };
200 cpsw_default: cpsw_default {
201 pinctrl-single,pins = <
202 /* Slave 2 */
203 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
204 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
205 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
206 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
207 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
208 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
209 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
210 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
211 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
212 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
213 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
214 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
215 >;
217 };
219 cpsw_sleep: cpsw_sleep {
220 pinctrl-single,pins = <
221 /* Slave 1 */
222 0x198 (PIN_OFF_NONE)
223 0x19c (PIN_OFF_NONE)
224 0x1a0 (PIN_OFF_NONE)
225 0x1a4 (PIN_OFF_NONE)
226 0x1a8 (PIN_OFF_NONE)
227 0x1ac (PIN_OFF_NONE)
228 0x1b0 (PIN_OFF_NONE)
229 0x1b4 (PIN_OFF_NONE)
230 0x1b8 (PIN_OFF_NONE)
231 0x1bc (PIN_OFF_NONE)
232 0x1c0 (PIN_OFF_NONE)
233 0x1c4 (PIN_OFF_NONE)
234 >;
235 };
237 davinci_mdio_default: davinci_mdio_default {
238 pinctrl-single,pins = <
239 /* MDIO */
240 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */
241 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk */
242 >;
243 };
245 davinci_mdio_sleep: davinci_mdio_sleep {
246 pinctrl-single,pins = <
247 0x23c (PIN_OFF_NONE)
248 0x240 (PIN_OFF_NONE)
249 >;
250 };
252 tps65917_pins_default: tps65917_pins_default {
253 pinctrl-single,pins = <
254 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
255 >;
256 };
258 nand_default: nand_default {
259 pinctrl-single,pins = <
260 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
261 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
262 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
263 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
264 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
265 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
266 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
267 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
268 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
269 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
270 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
271 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
272 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
273 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
274 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
275 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
276 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
277 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
278 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
279 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
280 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
281 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
282 >;
283 };
285 vout1_pins: pinmux_vout1_pins {
286 pinctrl-single,pins = <
287 0x1C8 (PIN_OUTPUT | MUX_MODE0) /* vout1_clk */
288 0x1CC (PIN_OUTPUT | MUX_MODE0) /* vout1_de */
289 0x1D0 (PIN_OUTPUT | MUX_MODE0) /* vout1_fld */
290 0x1D4 (PIN_OUTPUT | MUX_MODE0) /* vout1_hsync */
291 0x1D8 (PIN_OUTPUT | MUX_MODE0) /* vout1_vsync */
292 0x1DC (PIN_OUTPUT | MUX_MODE0) /* vout1_d0 */
293 0x1E0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d1 */
294 0x1E4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d2 */
295 0x1E8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d3 */
296 0x1EC (PIN_OUTPUT | MUX_MODE0) /* vout1_d4 */
297 0x1F0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d5 */
298 0x1F4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d6 */
299 0x1F8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d7 */
300 0x1FC (PIN_OUTPUT | MUX_MODE0) /* vout1_d8 */
301 0x200 (PIN_OUTPUT | MUX_MODE0) /* vout1_d9 */
302 0x204 (PIN_OUTPUT | MUX_MODE0) /* vout1_d10 */
303 0x208 (PIN_OUTPUT | MUX_MODE0) /* vout1_d11 */
304 0x20C (PIN_OUTPUT | MUX_MODE0) /* vout1_d12 */
305 0x210 (PIN_OUTPUT | MUX_MODE0) /* vout1_d13 */
306 0x214 (PIN_OUTPUT | MUX_MODE0) /* vout1_d14 */
307 0x218 (PIN_OUTPUT | MUX_MODE0) /* vout1_d15 */
308 0x21C (PIN_OUTPUT | MUX_MODE0) /* vout1_d16 */
309 0x220 (PIN_OUTPUT | MUX_MODE0) /* vout1_d17 */
310 0x224 (PIN_OUTPUT | MUX_MODE0) /* vout1_d18 */
311 0x228 (PIN_OUTPUT | MUX_MODE0) /* vout1_d19 */
312 0x22C (PIN_OUTPUT | MUX_MODE0) /* vout1_d20 */
313 0x230 (PIN_OUTPUT | MUX_MODE0) /* vout1_d21 */
314 0x234 (PIN_OUTPUT | MUX_MODE0) /* vout1_d22 */
315 0x238 (PIN_OUTPUT | MUX_MODE0) /* vout1_d23 */
316 >;
317 };
319 hpd_pin: pinmux_hpd_pin {
320 pinctrl-single,pins = <
321 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 */
322 >;
323 };
325 atl_pins: pinmux_atl_pins {
326 pinctrl-single,pins = <
327 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
328 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
329 >;
330 };
332 mcasp3_pins: pinmux_mcasp3_pins {
333 pinctrl-single,pins = <
334 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
335 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
336 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
337 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
338 >;
339 };
341 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
342 pinctrl-single,pins = <
343 0x324 (PIN_OFF_NONE)
344 0x328 (PIN_OFF_NONE)
345 0x32c (PIN_OFF_NONE)
346 0x330 (PIN_OFF_NONE)
347 >;
348 };
350 usb1_pins: pinmux_usb1_pins {
351 pinctrl-single,pins = <
352 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
353 >;
354 };
356 usb2_pins: pinmux_usb2_pins {
357 pinctrl-single,pins = <
358 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
359 >;
360 };
362 qspi1_pins: pinmux_qspi1_pins {
363 pinctrl-single,pins = <
364 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
365 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
366 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
367 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
368 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
369 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
370 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
371 >;
372 };
374 dcan1_pins_default: dcan1_pins_default {
375 pinctrl-single,pins = <
376 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
377 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
378 >;
379 };
381 dcan1_pins_sleep: dcan1_pins_sleep {
382 pinctrl-single,pins = <
383 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
384 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
385 >;
386 };
388 wlan_pins: pinmux_wlan_pins {
389 pinctrl-single,pins = <
390 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
391 0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
392 0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
393 0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
394 0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
395 0x3fc (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
396 0x2cc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr6.gpio5_8 - WLAN_EN */
397 >;
398 };
400 wlirq_pins: pinmux_wlirq_pins {
401 pinctrl-single,pins = <
402 0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */
403 >;
404 };
406 vin1a_pins: pinmux_vin1a_pins {
407 pinctrl-single,pins = <
408 0x0DC (PIN_INPUT | MUX_MODE0) /* vin1a_clk0 */
409 0x0E4 (PIN_INPUT | MUX_MODE0) /* vin1a_de0 */
410 0x0E8 (PIN_INPUT | MUX_MODE0) /* vin1a_fld0 */
411 0x0EC (PIN_INPUT | MUX_MODE0) /* vin1a_hsync0 */
412 0x0F0 (PIN_INPUT | MUX_MODE0) /* vin1a_vsync0 */
413 0x0F4 (PIN_INPUT | MUX_MODE0) /* vin1a_d0 */
414 0x0F8 (PIN_INPUT | MUX_MODE0) /* vin1a_d1 */
415 0x0FC (PIN_INPUT | MUX_MODE0) /* vin1a_d2 */
416 0x100 (PIN_INPUT | MUX_MODE0) /* vin1a_d3 */
417 0x104 (PIN_INPUT | MUX_MODE0) /* vin1a_d4 */
418 0x108 (PIN_INPUT | MUX_MODE0) /* vin1a_d5 */
419 0x10C (PIN_INPUT | MUX_MODE0) /* vin1a_d6 */
420 0x110 (PIN_INPUT | MUX_MODE0) /* vin1a_d7 */
421 0x114 (PIN_INPUT | MUX_MODE0) /* vin1a_d8 */
422 0x118 (PIN_INPUT | MUX_MODE0) /* vin1a_d9 */
423 0x11C (PIN_INPUT | MUX_MODE0) /* vin1a_d10 */
424 0x120 (PIN_INPUT | MUX_MODE0) /* vin1a_d11 */
425 0x124 (PIN_INPUT | MUX_MODE0) /* vin1a_d12 */
426 0x128 (PIN_INPUT | MUX_MODE0) /* vin1a_d13 */
427 0x12C (PIN_INPUT | MUX_MODE0) /* vin1a_d14 */
428 0x130 (PIN_INPUT | MUX_MODE0) /* vin1a_d15 */
429 >;
430 };
432 vin1a_d16_d23_pins: pinmux_vin1a_d16_d23_pins {
433 pinctrl-single,pins = <
434 0x134 (PIN_INPUT | MUX_MODE0) /* vin1a_d16 */
435 0x138 (PIN_INPUT | MUX_MODE0) /* vin1a_d17 */
436 0x13C (PIN_INPUT | MUX_MODE0) /* vin1a_d18 */
437 0x140 (PIN_INPUT | MUX_MODE0) /* vin1a_d19 */
438 0x144 (PIN_INPUT | MUX_MODE0) /* vin1a_d20 */
439 0x148 (PIN_INPUT | MUX_MODE0) /* vin1a_d21 */
440 0x14C (PIN_INPUT | MUX_MODE0) /* vin1a_d22 */
441 0x150 (PIN_INPUT | MUX_MODE0) /* vin1a_d23 */
443 >;
444 };
446 vin2a_pins: pinmux_vin2a_pins {
447 pinctrl-single,pins = <
448 0x154 (PIN_INPUT | MUX_MODE0) /* vin2a_clk0 */
449 0x160 (PIN_INPUT | MUX_MODE0) /* vin2a_hsync0 */
450 0x164 (PIN_INPUT | MUX_MODE0) /* vin2a_vsync0 */
451 0x168 (PIN_INPUT | MUX_MODE0) /* vin2a_d0 */
452 0x16c (PIN_INPUT | MUX_MODE0) /* vin2a_d1 */
453 0x170 (PIN_INPUT | MUX_MODE0) /* vin2a_d2 */
454 0x174 (PIN_INPUT | MUX_MODE0) /* vin2a_d3 */
455 0x178 (PIN_INPUT | MUX_MODE0) /* vin2a_d4 */
456 0x17c (PIN_INPUT | MUX_MODE0) /* vin2a_d5 */
457 0x180 (PIN_INPUT | MUX_MODE0) /* vin2a_d6 */
458 0x184 (PIN_INPUT | MUX_MODE0) /* vin2a_d7 */
459 >;
460 };
462 };
464 &i2c1 {
465 status = "okay";
466 pinctrl-names = "default";
467 pinctrl-0 = <&i2c1_pins>;
468 clock-frequency = <400000>;
470 tps65917: tps65917@58 {
471 compatible = "ti,tps65917";
472 reg = <0x58>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&tps65917_pins_default>;
476 interrupts-extended = <&gic GIC_SPI 2 IRQ_TYPE_NONE
477 &dra7_pmx_core 0x424>;
478 interrupt-parent = <&gic>;
479 interrupt-controller;
480 #interrupt-cells = <2>;
482 ti,system-power-controller;
484 tps65917_pmic {
485 compatible = "ti,tps65917-pmic";
487 regulators {
488 smps1_reg: smps1 {
489 /* VDD_MPU */
490 regulator-name = "smps1";
491 regulator-min-microvolt = <850000>;
492 regulator-max-microvolt = <1250000>;
493 regulator-always-on;
494 regulator-boot-on;
495 };
497 smps2_reg: smps2 {
498 /* VDD_CORE */
499 regulator-name = "smps2";
500 regulator-min-microvolt = <850000>;
501 regulator-max-microvolt = <1060000>;
502 regulator-boot-on;
503 regulator-always-on;
504 };
506 smps3_reg: smps3 {
507 /* VDD_GPU IVA DSPEVE */
508 regulator-name = "smps3";
509 regulator-min-microvolt = <850000>;
510 regulator-max-microvolt = <1250000>;
511 regulator-boot-on;
512 regulator-always-on;
513 };
515 smps4_reg: smps4 {
516 /* VDDS1V8 */
517 regulator-name = "smps4";
518 regulator-min-microvolt = <1800000>;
519 regulator-max-microvolt = <1800000>;
520 regulator-always-on;
521 regulator-boot-on;
522 };
524 smps5_reg: smps5 {
525 /* VDD_DDR */
526 regulator-name = "smps5";
527 regulator-min-microvolt = <1350000>;
528 regulator-max-microvolt = <1350000>;
529 regulator-boot-on;
530 regulator-always-on;
531 };
533 ldo1_reg: ldo1 {
534 /* LDO1_OUT --> SDIO */
535 regulator-name = "ldo1";
536 regulator-min-microvolt = <1800000>;
537 regulator-max-microvolt = <3300000>;
538 regulator-boot-on;
539 };
541 ldo2_reg: ldo2 {
542 /* LDO2_OUT --> TP1017 (UNUSED) */
543 regulator-name = "ldo2";
544 regulator-min-microvolt = <1800000>;
545 regulator-max-microvolt = <3300000>;
546 };
548 ldo3_reg: ldo3 {
549 /* VDDA_1V8_PHY */
550 regulator-name = "ldo3";
551 regulator-min-microvolt = <1800000>;
552 regulator-max-microvolt = <1800000>;
553 regulator-boot-on;
554 regulator-always-on;
555 };
557 ldo5_reg: ldo5 {
558 /* VDDA_1V8_PLL */
559 regulator-name = "ldo5";
560 regulator-min-microvolt = <1800000>;
561 regulator-max-microvolt = <1800000>;
562 regulator-always-on;
563 regulator-boot-on;
564 };
566 ldo4_reg: ldo4 {
567 /* VDDA_3V_USB: VDDA_USBHS33 */
568 regulator-name = "ldo4";
569 regulator-min-microvolt = <3300000>;
570 regulator-max-microvolt = <3300000>;
571 regulator-boot-on;
572 };
573 };
574 };
576 tps65917_power_button {
577 compatible = "ti,palmas-pwrbutton";
578 interrupt-parent = <&tps65917>;
579 interrupts = <1 IRQ_TYPE_NONE>;
580 wakeup-source;
581 ti,palmas-long-press-seconds = <6>;
582 };
583 };
585 pcf_lcd: gpio@20 {
586 compatible = "nxp,pcf8575";
587 reg = <0x20>;
588 gpio-controller;
589 #gpio-cells = <2>;
590 };
592 pcf_gpio_21: gpio@21 {
593 compatible = "nxp,pcf8575";
594 reg = <0x21>;
595 lines-initial-states = <0x1408>;
596 gpio-controller;
597 #gpio-cells = <2>;
598 interrupt-parent = <&gpio6>;
599 interrupts = <11 2>;
600 interrupt-controller;
601 #interrupt-cells = <2>;
603 cpsw_sel_s0 {
604 gpio-hog;
605 gpios = <4 GPIO_ACTIVE_HIGH>;
606 output-low;
607 };
608 };
610 tlv320aic3106: tlv320aic3106@19 {
611 compatible = "ti,tlv320aic3106";
612 reg = <0x19>;
613 adc-settle-ms = <40>;
614 ai3x-micbias-vg = <1>; /* 2.0V */
615 status = "okay";
617 /* Regulators */
618 AVDD-supply = <&evm_3v3>;
619 IOVDD-supply = <&evm_3v3>;
620 DRVDD-supply = <&evm_3v3>;
621 DVDD-supply = <&aic_dvdd>;
622 };
623 };
625 &dra7_pmx_core {
626 i2c5_pins: pinmux_i2c5_pins {
627 pinctrl-single,pins = <
628 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
629 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
630 >;
631 };
632 };
634 &i2c5 {
635 status = "okay";
636 pinctrl-names = "default";
637 pinctrl-0 = <&i2c5_pins>;
638 clock-frequency = <400000>;
640 pcf_hdmi: pcf8575@26 {
641 compatible = "nxp,pcf8575";
642 reg = <0x26>;
643 gpio-controller;
644 #gpio-cells = <2>;
645 /*
646 * initial state is used here to keep the mdio interface
647 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
648 * VIN2_S0 driven high otherwise Ethernet stops working
649 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
650 */
651 lines-initial-states = <0x0f2b>;
652 };
654 ov10633@37 {
655 compatible = "ovti,ov10633";
656 reg = <0x37>;
658 mux-gpios = <&pcf_hdmi 2 GPIO_ACTIVE_HIGH>, /* VIN2_S0 */
659 <&pcf_hdmi 6 GPIO_ACTIVE_LOW>; /* VIN2_S2 */
660 port {
661 onboardLI: endpoint {
662 remote-endpoint = <&vin2a>;
663 hsync-active = <1>;
664 vsync-active = <1>;
665 pclk-sample = <1>;
666 };
667 };
668 };
669 };
671 &uart1 {
672 pinctrl-names = "default";
673 pinctrl-0 = <&uart1_pins>;
675 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
676 &dra7_pmx_core 0x3e0>;
677 status = "okay";
678 };
680 &uart3 {
681 status = "okay";
682 gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
683 };
685 &mmc1 {
686 /* Using default configured pins */
687 status = "okay";
688 pbias-supply = <&pbias_mmc_reg>;
689 vmmc-supply = <&evm_3v3_sd>;
690 vmmc_aux-supply = <&ldo1_reg>;
691 bus-width = <4>;
692 /*
693 * SDCD signal is not being used here - using the fact that GPIO mode
694 * is always hardwired.
695 */
696 cd-gpios = <&gpio6 27 0>;
697 sd-uhs-sdr104;
698 sd-uhs-sdr50;
699 sd-uhs-ddr50;
700 sd-uhs-sdr25;
701 sd-uhs-sdr12;
702 max-frequency = <192000000>;
703 };
705 &mmc2 {
706 /* Using default configured pins */
707 status = "okay";
708 vmmc-supply = <&evm_3v3>;
709 bus-width = <8>;
710 ti,non-removable;
711 mmc-hs200-1_8v;
712 max-frequency = <192000000>;
713 };
715 &mmc4 {
716 status = "okay";
717 vmmc-supply = <&vmmcwl_fixed>;
718 bus-width = <4>;
719 pinctrl-names = "default";
720 pinctrl-0 = <&wlan_pins &wlirq_pins>;
721 cap-power-off-card;
722 keep-power-in-suspend;
723 ti,non-removable;
725 #address-cells = <1>;
726 #size-cells = <0>;
727 wlcore: wlcore@0 {
728 compatible = "ti,wlcore";
729 reg = <2>;
730 interrupt-parent = <&gpio5>;
731 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
732 };
733 };
735 &mac {
736 status = "okay";
737 pinctrl-names = "default", "sleep";
738 pinctrl-0 = <&cpsw_default>;
739 pinctrl-1 = <&cpsw_sleep>;
740 slaves = <1>;
741 };
743 &cpsw_emac0 {
744 phy_id = <&davinci_mdio>, <3>;
745 phy-mode = "rgmii";
746 };
748 &davinci_mdio {
749 pinctrl-names = "default", "sleep";
750 pinctrl-0 = <&davinci_mdio_default>;
751 pinctrl-1 = <&davinci_mdio_sleep>;
752 };
754 &cpu0 {
755 cpu0-voltdm = <&voltdm_mpu>;
756 voltage-tolerance = <1>;
757 };
759 &voltdm_mpu {
760 vdd-supply = <&smps1_reg>;
761 };
763 &voltdm_core {
764 vdd-supply = <&smps2_reg>;
765 };
767 &voltdm_dspeve {
768 vdd-supply = <&smps3_reg>;
769 };
771 &voltdm_gpu {
772 vdd-supply = <&smps3_reg>;
773 };
775 &voltdm_ivahd {
776 vdd-supply = <&smps3_reg>;
777 };
779 &elm {
780 status = "okay";
781 };
783 &gpmc {
784 status = "okay";
785 pinctrl-names = "default";
786 pinctrl-0 = <&nand_default>;
787 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
788 nand@0,0 {
789 /* To use NAND, DIP switch SW5 must be set like so:
790 * SW5.1 (NAND_SELn) = ON (LOW)
791 * SW5.9 (GPMC_WPN) = OFF (HIGH)
792 */
793 reg = <0 0 4>; /* device IO registers */
794 ti,nand-ecc-opt = "bch8";
795 ti,elm-id = <&elm>;
796 nand-bus-width = <16>;
797 gpmc,device-width = <2>;
798 gpmc,sync-clk-ps = <0>;
799 gpmc,cs-on-ns = <0>;
800 gpmc,cs-rd-off-ns = <80>;
801 gpmc,cs-wr-off-ns = <80>;
802 gpmc,adv-on-ns = <0>;
803 gpmc,adv-rd-off-ns = <60>;
804 gpmc,adv-wr-off-ns = <60>;
805 gpmc,we-on-ns = <10>;
806 gpmc,we-off-ns = <50>;
807 gpmc,oe-on-ns = <4>;
808 gpmc,oe-off-ns = <40>;
809 gpmc,access-ns = <40>;
810 gpmc,wr-access-ns = <80>;
811 gpmc,rd-cycle-ns = <80>;
812 gpmc,wr-cycle-ns = <80>;
813 gpmc,bus-turnaround-ns = <0>;
814 gpmc,cycle2cycle-delay-ns = <0>;
815 gpmc,clk-activation-ns = <0>;
816 gpmc,wait-monitoring-ns = <0>;
817 gpmc,wr-data-mux-bus-ns = <0>;
818 /* MTD partition table */
819 /* All SPL-* partitions are sized to minimal length
820 * which can be independently programmable. For
821 * NAND flash this is equal to size of erase-block */
822 #address-cells = <1>;
823 #size-cells = <1>;
824 partition@0 {
825 label = "NAND.SPL";
826 reg = <0x00000000 0x000020000>;
827 };
828 partition@1 {
829 label = "NAND.SPL.backup1";
830 reg = <0x00020000 0x00020000>;
831 };
832 partition@2 {
833 label = "NAND.SPL.backup2";
834 reg = <0x00040000 0x00020000>;
835 };
836 partition@3 {
837 label = "NAND.SPL.backup3";
838 reg = <0x00060000 0x00020000>;
839 };
840 partition@4 {
841 label = "NAND.u-boot-spl-os";
842 reg = <0x00080000 0x00040000>;
843 };
844 partition@5 {
845 label = "NAND.u-boot";
846 reg = <0x000c0000 0x00100000>;
847 };
848 partition@6 {
849 label = "NAND.u-boot-env";
850 reg = <0x001c0000 0x00020000>;
851 };
852 partition@7 {
853 label = "NAND.u-boot-env.backup1";
854 reg = <0x001e0000 0x00020000>;
855 };
856 partition@8 {
857 label = "NAND.kernel";
858 reg = <0x00200000 0x00800000>;
859 };
860 partition@9 {
861 label = "NAND.file-system";
862 reg = <0x00a00000 0x0f600000>;
863 };
864 };
865 };
867 &dss {
868 status = "ok";
870 vdda_video-supply = <&ldo5_reg>;
871 };
873 &hdmi {
874 status = "ok";
875 vdda-supply = <&ldo3_reg>;
876 pinctrl-names = "default";
877 pinctrl-0 = <&i2c2_pins>;
879 port {
880 hdmi_out: endpoint {
881 remote-endpoint = <&tpd12s015_in>;
882 };
883 };
884 };
886 &mailbox5 {
887 status = "okay";
888 mbox_ipu1_legacy: mbox_ipu1_legacy {
889 status = "okay";
890 };
891 mbox_dsp1_legacy: mbox_dsp1_legacy {
892 status = "okay";
893 };
894 };
896 &mailbox6 {
897 status = "okay";
898 mbox_ipu2_legacy: mbox_ipu2_legacy {
899 status = "okay";
900 };
901 };
903 &mmu0_dsp1 {
904 status = "okay";
905 };
907 &mmu1_dsp1 {
908 status = "okay";
909 };
911 &mmu_ipu1 {
912 status = "okay";
913 };
915 &mmu_ipu2 {
916 status = "okay";
917 };
919 &ipu2 {
920 status = "okay";
921 memory-region = <&ipu2_cma_pool>;
922 mboxes = <&mailbox6 &mbox_ipu2_legacy>;
923 timers = <&timer3>;
924 watchdog-timers = <&timer4>, <&timer9>;
925 };
927 &ipu1 {
928 status = "okay";
929 memory-region = <&ipu1_cma_pool>;
930 mboxes = <&mailbox5 &mbox_ipu1_legacy>;
931 timers = <&timer11>;
932 watchdog-timers = <&timer7>, <&timer8>;
933 };
935 &dsp1 {
936 status = "okay";
937 memory-region = <&dsp1_cma_pool>;
938 mboxes = <&mailbox5 &mbox_dsp1_legacy>;
939 timers = <&timer5>;
940 watchdog-timers = <&timer10>;
941 };
943 &atl {
944 pinctrl-names = "default";
945 pinctrl-0 = <&atl_pins>;
947 status = "okay";
949 atl2 {
950 bws = <DRA7_ATL_WS_MCASP2_FSX>;
951 aws = <DRA7_ATL_WS_MCASP3_FSX>;
952 };
953 };
955 &mcasp3 {
956 pinctrl-names = "default", "sleep";
957 pinctrl-0 = <&mcasp3_pins>;
958 pinctrl-1 = <&mcasp3_sleep_pins>;
960 fck_parent = "atl_clkin2_ck";
962 status = "okay";
964 op-mode = <0>; /* MCASP_IIS_MODE */
965 tdm-slots = <2>;
966 /* 4 serializer */
967 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
968 1 2 0 0
969 >;
970 };
972 &omap_dwc3_1 {
973 extcon = <&extcon_usb1>;
974 };
976 &omap_dwc3_2 {
977 extcon = <&extcon_usb2>;
978 };
980 &usb2_phy1 {
981 phy-supply = <&ldo4_reg>;
982 };
984 &usb2_phy2 {
985 phy-supply = <&ldo4_reg>;
986 };
988 &usb1 {
989 dr_mode = "otg";
990 pinctrl-names = "default";
991 pinctrl-0 = <&usb1_pins>;
992 };
994 &usb2 {
995 dr_mode = "host";
996 pinctrl-names = "default";
997 pinctrl-0 = <&usb2_pins>;
998 };
1000 &qspi {
1001 status = "okay";
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&qspi1_pins>;
1005 spi-max-frequency = <48000000>;
1006 m25p80@0 {
1007 compatible = "s25fl256s1";
1008 spi-max-frequency = <48000000>;
1009 reg = <0>;
1010 spi-tx-bus-width = <1>;
1011 spi-rx-bus-width = <4>;
1012 spi-cpol;
1013 spi-cpha;
1014 #address-cells = <1>;
1015 #size-cells = <1>;
1017 /* MTD partition table.
1018 * The ROM checks the first four physical blocks
1019 * for a valid file to boot and the flash here is
1020 * 64KiB block size.
1021 */
1022 partition@0 {
1023 label = "QSPI.SPL";
1024 reg = <0x00000000 0x000010000>;
1025 };
1026 partition@1 {
1027 label = "QSPI.SPL.backup1";
1028 reg = <0x00010000 0x00010000>;
1029 };
1030 partition@2 {
1031 label = "QSPI.SPL.backup2";
1032 reg = <0x00020000 0x00010000>;
1033 };
1034 partition@3 {
1035 label = "QSPI.SPL.backup3";
1036 reg = <0x00030000 0x00010000>;
1037 };
1038 partition@4 {
1039 label = "QSPI.u-boot";
1040 reg = <0x00040000 0x00100000>;
1041 };
1042 partition@5 {
1043 label = "QSPI.u-boot-spl-os";
1044 reg = <0x00140000 0x00080000>;
1045 };
1046 partition@6 {
1047 label = "QSPI.u-boot-env";
1048 reg = <0x001c0000 0x00010000>;
1049 };
1050 partition@7 {
1051 label = "QSPI.u-boot-env.backup1";
1052 reg = <0x001d0000 0x0010000>;
1053 };
1054 partition@8 {
1055 label = "QSPI.kernel";
1056 reg = <0x001e0000 0x0800000>;
1057 };
1058 partition@9 {
1059 label = "QSPI.file-system";
1060 reg = <0x009e0000 0x01620000>;
1061 };
1062 };
1063 };
1065 &dcan1 {
1066 status = "ok";
1067 pinctrl-names = "default", "sleep";
1068 pinctrl-0 = <&dcan1_pins_default>;
1069 pinctrl-1 = <&dcan1_pins_sleep>;
1070 };
1072 &vip1 {
1073 pinctrl-names = "default";
1074 pinctrl-0 = <&vin2a_pins>;
1075 status = "okay";
1076 };
1078 &vin2a {
1079 endpoint@0 {
1080 slave-mode;
1081 remote-endpoint = <&onboardLI>;
1082 };
1083 };