1 /*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 /dts-v1/;
10 #include "dra72x.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/clk/ti-dra7-atl.h>
14 / {
15 model = "TI DRA722";
16 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
18 aliases {
19 display0 = &hdmi0;
20 sound0 = &primary_sound;
21 sound1 = &hdmi;
22 };
24 memory {
25 device_type = "memory";
26 reg = <0x80000000 0x40000000>; /* 1024 MB */
27 };
29 tpd12s015: encoder@0 {
30 compatible = "ti,tpd12s015";
32 pinctrl-names = "default";
33 pinctrl-0 = <&hpd_pin>;
35 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
36 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
37 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
39 ports {
40 #address-cells = <1>;
41 #size-cells = <0>;
43 port@0 {
44 reg = <0>;
46 tpd12s015_in: endpoint@0 {
47 remote-endpoint = <&hdmi_out>;
48 };
49 };
51 port@1 {
52 reg = <1>;
54 tpd12s015_out: endpoint@0 {
55 remote-endpoint = <&hdmi_connector_in>;
56 };
57 };
58 };
59 };
61 hdmi0: connector@0 {
62 compatible = "hdmi-connector";
63 label = "hdmi";
65 type = "a";
67 port {
68 hdmi_connector_in: endpoint {
69 remote-endpoint = <&tpd12s015_out>;
70 };
71 };
72 };
74 reserved_mem: reserved-memory {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges;
79 ipu2_cma_pool: ipu2_cma@95800000 {
80 compatible = "shared-dma-pool";
81 reg = <0x95800000 0x3800000>;
82 reusable;
83 status = "okay";
84 };
86 dsp1_cma_pool: dsp1_cma@99000000 {
87 compatible = "shared-dma-pool";
88 reg = <0x99000000 0x4000000>;
89 reusable;
90 status = "okay";
91 };
93 ipu1_cma_pool: ipu1_cma@9d000000 {
94 compatible = "shared-dma-pool";
95 reg = <0x9d000000 0x2000000>;
96 reusable;
97 status = "okay";
98 };
99 };
101 extcon_usb1: extcon_usb1 {
102 compatible = "linux,extcon-usb-gpio";
103 id-gpios = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
104 };
106 extcon_usb2: extcon_usb2 {
107 compatible = "linux,extcon-usb-gpio";
108 id-gpios = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
109 };
111 evm_3v3_sd: fixedregulator-sd {
112 compatible = "regulator-fixed";
113 regulator-name = "evm_3v3_sd";
114 regulator-min-microvolt = <3300000>;
115 regulator-max-microvolt = <3300000>;
116 enable-active-high;
117 gpio = <&pcf_gpio_21 5 0>;
118 };
120 evm_3v3_sw: fixedregulator-evm_3v3 {
121 compatible = "regulator-fixed";
122 regulator-name = "evm_3v3";
123 regulator-min-microvolt = <3300000>;
124 regulator-max-microvolt = <3300000>;
125 };
127 aic_dvdd: fixedregulator-aic_dvdd {
128 /* TPS77018DBVT */
129 compatible = "regulator-fixed";
130 regulator-name = "aic_dvdd";
131 vin-supply = <&evm_3v3_sw>;
132 regulator-min-microvolt = <1800000>;
133 regulator-max-microvolt = <1800000>;
134 };
136 primary_sound: primary_sound {
137 compatible = "ti,dra7xx-evm-audio";
138 ti,model = "DRA7xx-EVM";
139 ti,always-on;
140 ti,audio-codec = <&tlv320aic3106>;
141 ti,mcasp-controller = <&mcasp3>;
142 ti,codec-clock-rate = <11289600>;
143 clocks = <&atl_clkin2_ck>;
144 clock-names = "mclk";
145 ti,audio-routing =
146 "Headphone Jack", "HPLOUT",
147 "Headphone Jack", "HPROUT",
148 "Line Out", "LLOUT",
149 "Line Out", "RLOUT",
150 "MIC3L", "Mic Jack",
151 "MIC3R", "Mic Jack",
152 "Mic Jack", "Mic Bias",
153 "LINE1L", "Line In",
154 "LINE1R", "Line In";
155 };
157 btwilink_sound: btwilink_sound {
158 #sound-dai-cells = <0>;
159 compatible = "linux,bt-sco-audio";
160 status = "okay";
161 };
163 simple_bt_sco_card: bt_sco_card {
164 compatible = "simple-audio-card";
165 simple-audio-card,name = "DRA7xx-WiLink";
166 simple-audio-card,format = "dsp_a";
167 simple-audio-card,frame-master = <&btwilink_codec>;
168 simple-audio-card,bitclock-master = <&btwilink_codec>;
169 simple-audio-card,frame-inversion;
171 simple-audio-card,cpu {
172 sound-dai = <&mcasp7>;
173 };
175 btwilink_codec: simple-audio-card,codec {
176 sound-dai = <&btwilink_sound>;
177 };
178 };
180 vmmcwl_fixed: fixedregulator-mmcwl {
181 compatible = "regulator-fixed";
182 regulator-name = "vmmcwl_fixed";
183 regulator-min-microvolt = <1800000>;
184 regulator-max-microvolt = <1800000>;
185 gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; /* gpio5_8 */
186 enable-active-high;
187 };
189 kim {
190 compatible = "kim";
191 nshutdown_gpio = <132>;
192 dev_name = "/dev/ttyS2";
193 flow_cntrl = <1>;
194 baud_rate = <3686400>;
195 };
197 btwilink {
198 compatible = "btwilink";
199 };
200 };
202 &dra7_pmx_core {
203 i2c1_pins: pinmux_i2c1_pins {
204 pinctrl-single,pins = <
205 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
206 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
207 >;
208 };
210 uart1_pins: pinmix_uart1_pins {
211 pinctrl-single,pins = <
212 0x3e0 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd */
213 0x3e4 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_txd */
214 >;
215 };
217 i2c2_pins: pinmux_i2c2_pins {
218 pinctrl-single,pins = <
219 0x408 (PIN_INPUT | MUX_MODE1) /* hdmi1_ddc_scl */
220 0x40c (PIN_INPUT | MUX_MODE1) /* hdmi1_ddc_sda */
221 >;
222 };
224 cpsw_default: cpsw_default {
225 pinctrl-single,pins = <
226 /* Slave 2 */
227 0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
228 0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
229 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
230 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
231 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
232 0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
233 0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
234 0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
235 0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
236 0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
237 0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
238 0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
239 >;
241 };
243 cpsw_sleep: cpsw_sleep {
244 pinctrl-single,pins = <
245 /* Slave 1 */
246 0x198 (PIN_OFF_NONE)
247 0x19c (PIN_OFF_NONE)
248 0x1a0 (PIN_OFF_NONE)
249 0x1a4 (PIN_OFF_NONE)
250 0x1a8 (PIN_OFF_NONE)
251 0x1ac (PIN_OFF_NONE)
252 0x1b0 (PIN_OFF_NONE)
253 0x1b4 (PIN_OFF_NONE)
254 0x1b8 (PIN_OFF_NONE)
255 0x1bc (PIN_OFF_NONE)
256 0x1c0 (PIN_OFF_NONE)
257 0x1c4 (PIN_OFF_NONE)
258 >;
259 };
261 davinci_mdio_default: davinci_mdio_default {
262 pinctrl-single,pins = <
263 /* MDIO */
264 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_data */
265 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk */
266 >;
267 };
269 davinci_mdio_sleep: davinci_mdio_sleep {
270 pinctrl-single,pins = <
271 0x23c (PIN_OFF_NONE)
272 0x240 (PIN_OFF_NONE)
273 >;
274 };
276 tps65917_pins_default: tps65917_pins_default {
277 pinctrl-single,pins = <
278 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
279 >;
280 };
282 nand_default: nand_default {
283 pinctrl-single,pins = <
284 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
285 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
286 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
287 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
288 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
289 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
290 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
291 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
292 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
293 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
294 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
295 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
296 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
297 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
298 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
299 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
300 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
301 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
302 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
303 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
304 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
305 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
306 >;
307 };
309 vout1_pins: pinmux_vout1_pins {
310 pinctrl-single,pins = <
311 0x1C8 (PIN_OUTPUT | MUX_MODE0) /* vout1_clk */
312 0x1CC (PIN_OUTPUT | MUX_MODE0) /* vout1_de */
313 0x1D0 (PIN_OUTPUT | MUX_MODE0) /* vout1_fld */
314 0x1D4 (PIN_OUTPUT | MUX_MODE0) /* vout1_hsync */
315 0x1D8 (PIN_OUTPUT | MUX_MODE0) /* vout1_vsync */
316 0x1DC (PIN_OUTPUT | MUX_MODE0) /* vout1_d0 */
317 0x1E0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d1 */
318 0x1E4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d2 */
319 0x1E8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d3 */
320 0x1EC (PIN_OUTPUT | MUX_MODE0) /* vout1_d4 */
321 0x1F0 (PIN_OUTPUT | MUX_MODE0) /* vout1_d5 */
322 0x1F4 (PIN_OUTPUT | MUX_MODE0) /* vout1_d6 */
323 0x1F8 (PIN_OUTPUT | MUX_MODE0) /* vout1_d7 */
324 0x1FC (PIN_OUTPUT | MUX_MODE0) /* vout1_d8 */
325 0x200 (PIN_OUTPUT | MUX_MODE0) /* vout1_d9 */
326 0x204 (PIN_OUTPUT | MUX_MODE0) /* vout1_d10 */
327 0x208 (PIN_OUTPUT | MUX_MODE0) /* vout1_d11 */
328 0x20C (PIN_OUTPUT | MUX_MODE0) /* vout1_d12 */
329 0x210 (PIN_OUTPUT | MUX_MODE0) /* vout1_d13 */
330 0x214 (PIN_OUTPUT | MUX_MODE0) /* vout1_d14 */
331 0x218 (PIN_OUTPUT | MUX_MODE0) /* vout1_d15 */
332 0x21C (PIN_OUTPUT | MUX_MODE0) /* vout1_d16 */
333 0x220 (PIN_OUTPUT | MUX_MODE0) /* vout1_d17 */
334 0x224 (PIN_OUTPUT | MUX_MODE0) /* vout1_d18 */
335 0x228 (PIN_OUTPUT | MUX_MODE0) /* vout1_d19 */
336 0x22C (PIN_OUTPUT | MUX_MODE0) /* vout1_d20 */
337 0x230 (PIN_OUTPUT | MUX_MODE0) /* vout1_d21 */
338 0x234 (PIN_OUTPUT | MUX_MODE0) /* vout1_d22 */
339 0x238 (PIN_OUTPUT | MUX_MODE0) /* vout1_d23 */
340 >;
341 };
343 hpd_pin: pinmux_hpd_pin {
344 pinctrl-single,pins = <
345 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 */
346 >;
347 };
349 atl_pins: pinmux_atl_pins {
350 pinctrl-single,pins = <
351 0x298 (PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
352 0x29c (PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
353 >;
354 };
356 mcasp2_pins: pinmux_mcasp2_pins {
357 pinctrl-single,pins = <
358 0x02F4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_aclkx */
359 0x02F8 (PIN_INPUT_SLEW | MUX_MODE0) /* mcasp2_afsx */
360 0x0304 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr0 */
361 0x0308 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr1 */
362 0x030C (PIN_INPUT_SLEW | MUX_MODE0) /* mcasp2_axr2 */
363 0x0310 (PIN_INPUT_SLEW | MUX_MODE0) /* mcasp2_axr3 */
364 0x0314 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr4 */
365 0x0318 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr5 */
366 0x031c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr6 */
367 0x0320 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp2_axr7 */
368 >;
369 };
371 mcasp3_pins: pinmux_mcasp3_pins {
372 pinctrl-single,pins = <
373 0x324 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
374 0x328 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
375 0x32c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
376 0x330 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
377 >;
378 };
380 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
381 pinctrl-single,pins = <
382 0x324 (PIN_OFF_NONE)
383 0x328 (PIN_OFF_NONE)
384 0x32c (PIN_OFF_NONE)
385 0x330 (PIN_OFF_NONE)
386 >;
387 };
389 mcasp6_pins: pinmux_mcasp6_pins {
390 pinctrl-single,pins = <
391 0x2d4 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mcasp6_axr0 */
392 0x2d8 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp6_axr1 */
393 0x2dc (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mcasp6_clkx */
394 0x2e0 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp6_fsx */
395 >;
396 };
398 mcasp7_pins: pinmux_mcasp7_pins {
399 pinctrl-single,pins = <
400 0x2e4 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp7_axr0 */
401 0x2e8 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mcasp7_axr1 */
402 0x2ec (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp7_clkx */
403 0x2f0 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcasp7_fsx */
404 >;
405 };
407 mcasp7_sleep_pins: pinmux_mcasp7_sleep_pins {
408 pinctrl-single,pins = <
409 0x2e4 (PIN_OFF_NONE)
410 0x2e8 (PIN_OFF_NONE)
411 0x2ec (PIN_OFF_NONE)
412 0x2f0 (PIN_OFF_NONE)
413 >;
414 };
416 usb1_pins: pinmux_usb1_pins {
417 pinctrl-single,pins = <
418 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
419 >;
420 };
422 usb2_pins: pinmux_usb2_pins {
423 pinctrl-single,pins = <
424 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
425 >;
426 };
428 tsc_pins: pinmux_tsc_pins {
429 pinctrl-single,pins = <
430 0x3D4 (PIN_INPUT_PULLUP | MUX_MODE14) /* dcan1_rx -> gpio1_15 */
431 >;
432 };
434 qspi1_pins: pinmux_qspi1_pins {
435 pinctrl-single,pins = <
436 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
437 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
438 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
439 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
440 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
441 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
442 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
443 >;
444 };
446 dcan1_pins_default: dcan1_pins_default {
447 pinctrl-single,pins = <
448 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
449 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
450 >;
451 };
453 dcan1_pins_sleep: dcan1_pins_sleep {
454 pinctrl-single,pins = <
455 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
456 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */
457 >;
458 };
460 radio_pins: pinmux_radio_pins {
461 pinctrl-single,pins = <
462 0x0334 (PIN_INPUT | MUX_MODE4) /* i2c4_sda */
463 0x0338 (PIN_INPUT | MUX_MODE4) /* i2c4_scl */
464 0x02A0 (PIN_INPUT | MUX_MODE14) /* gpio6_20 */
465 >;
466 };
468 wlan_pins: pinmux_wlan_pins {
469 pinctrl-single,pins = <
470 0x3e8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
471 0x3ec (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
472 0x3f0 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
473 0x3f4 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
474 0x3f8 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
475 0x3fc (PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
476 0x2cc (PIN_OUTPUT | MUX_MODE14) /* mcasp1_axr6.gpio5_8 - WLAN_EN */
477 >;
478 };
480 wlirq_pins: pinmux_wlirq_pins {
481 pinctrl-single,pins = <
482 0x2c8 (PIN_INPUT_PULLUP | WAKEUP_EN | MUX_MODE14 ) /* mcasp1_axr5.gpio5_7 - WLAN_IRQ */
483 >;
484 };
486 vin1a_pins: pinmux_vin1a_pins {
487 pinctrl-single,pins = <
488 0x0DC (PIN_INPUT | MUX_MODE0) /* vin1a_clk0 */
489 0x0E4 (PIN_INPUT | MUX_MODE0) /* vin1a_de0 */
490 0x0E8 (PIN_INPUT | MUX_MODE0) /* vin1a_fld0 */
491 0x0EC (PIN_INPUT | MUX_MODE0) /* vin1a_hsync0 */
492 0x0F0 (PIN_INPUT | MUX_MODE0) /* vin1a_vsync0 */
493 0x0F4 (PIN_INPUT | MUX_MODE0) /* vin1a_d0 */
494 0x0F8 (PIN_INPUT | MUX_MODE0) /* vin1a_d1 */
495 0x0FC (PIN_INPUT | MUX_MODE0) /* vin1a_d2 */
496 0x100 (PIN_INPUT | MUX_MODE0) /* vin1a_d3 */
497 0x104 (PIN_INPUT | MUX_MODE0) /* vin1a_d4 */
498 0x108 (PIN_INPUT | MUX_MODE0) /* vin1a_d5 */
499 0x10C (PIN_INPUT | MUX_MODE0) /* vin1a_d6 */
500 0x110 (PIN_INPUT | MUX_MODE0) /* vin1a_d7 */
501 0x114 (PIN_INPUT | MUX_MODE0) /* vin1a_d8 */
502 0x118 (PIN_INPUT | MUX_MODE0) /* vin1a_d9 */
503 0x11C (PIN_INPUT | MUX_MODE0) /* vin1a_d10 */
504 0x120 (PIN_INPUT | MUX_MODE0) /* vin1a_d11 */
505 0x124 (PIN_INPUT | MUX_MODE0) /* vin1a_d12 */
506 0x128 (PIN_INPUT | MUX_MODE0) /* vin1a_d13 */
507 0x12C (PIN_INPUT | MUX_MODE0) /* vin1a_d14 */
508 0x130 (PIN_INPUT | MUX_MODE0) /* vin1a_d15 */
509 >;
510 };
512 vin1a_d16_d23_pins: pinmux_vin1a_d16_d23_pins {
513 pinctrl-single,pins = <
514 0x134 (PIN_INPUT | MUX_MODE0) /* vin1a_d16 */
515 0x138 (PIN_INPUT | MUX_MODE0) /* vin1a_d17 */
516 0x13C (PIN_INPUT | MUX_MODE0) /* vin1a_d18 */
517 0x140 (PIN_INPUT | MUX_MODE0) /* vin1a_d19 */
518 0x144 (PIN_INPUT | MUX_MODE0) /* vin1a_d20 */
519 0x148 (PIN_INPUT | MUX_MODE0) /* vin1a_d21 */
520 0x14C (PIN_INPUT | MUX_MODE0) /* vin1a_d22 */
521 0x150 (PIN_INPUT | MUX_MODE0) /* vin1a_d23 */
523 >;
524 };
526 vin2a_pins: pinmux_vin2a_pins {
527 pinctrl-single,pins = <
528 0x154 (PIN_INPUT | MUX_MODE0) /* vin2a_clk0 */
529 0x160 (PIN_INPUT | MUX_MODE0) /* vin2a_hsync0 */
530 0x164 (PIN_INPUT | MUX_MODE0) /* vin2a_vsync0 */
531 0x168 (PIN_INPUT | MUX_MODE0) /* vin2a_d0 */
532 0x16c (PIN_INPUT | MUX_MODE0) /* vin2a_d1 */
533 0x170 (PIN_INPUT | MUX_MODE0) /* vin2a_d2 */
534 0x174 (PIN_INPUT | MUX_MODE0) /* vin2a_d3 */
535 0x178 (PIN_INPUT | MUX_MODE0) /* vin2a_d4 */
536 0x17c (PIN_INPUT | MUX_MODE0) /* vin2a_d5 */
537 0x180 (PIN_INPUT | MUX_MODE0) /* vin2a_d6 */
538 0x184 (PIN_INPUT | MUX_MODE0) /* vin2a_d7 */
539 >;
540 };
542 };
544 &i2c1 {
545 status = "okay";
546 pinctrl-names = "default";
547 pinctrl-0 = <&i2c1_pins>;
548 clock-frequency = <400000>;
550 tps65917: tps65917@58 {
551 compatible = "ti,tps65917";
552 reg = <0x58>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&tps65917_pins_default>;
556 interrupts-extended = <&gic GIC_SPI 2 IRQ_TYPE_NONE
557 &dra7_pmx_core 0x424>;
558 interrupt-parent = <&gic>;
559 interrupt-controller;
560 #interrupt-cells = <2>;
562 ti,system-power-controller;
564 tps65917_pmic {
565 compatible = "ti,tps65917-pmic";
567 regulators {
568 smps1_reg: smps1 {
569 /* VDD_MPU */
570 regulator-name = "smps1";
571 regulator-min-microvolt = <850000>;
572 regulator-max-microvolt = <1250000>;
573 regulator-always-on;
574 regulator-boot-on;
575 };
577 smps2_reg: smps2 {
578 /* VDD_CORE */
579 regulator-name = "smps2";
580 regulator-min-microvolt = <850000>;
581 regulator-max-microvolt = <1060000>;
582 regulator-boot-on;
583 regulator-always-on;
584 };
586 smps3_reg: smps3 {
587 /* VDD_GPU IVA DSPEVE */
588 regulator-name = "smps3";
589 regulator-min-microvolt = <850000>;
590 regulator-max-microvolt = <1250000>;
591 regulator-boot-on;
592 regulator-always-on;
593 };
595 smps4_reg: smps4 {
596 /* VDDS1V8 */
597 regulator-name = "smps4";
598 regulator-min-microvolt = <1800000>;
599 regulator-max-microvolt = <1800000>;
600 regulator-always-on;
601 regulator-boot-on;
602 };
604 smps5_reg: smps5 {
605 /* VDD_DDR */
606 regulator-name = "smps5";
607 regulator-min-microvolt = <1350000>;
608 regulator-max-microvolt = <1350000>;
609 regulator-boot-on;
610 regulator-always-on;
611 };
613 ldo1_reg: ldo1 {
614 /* LDO1_OUT --> SDIO */
615 regulator-name = "ldo1";
616 regulator-min-microvolt = <1800000>;
617 regulator-max-microvolt = <3300000>;
618 regulator-boot-on;
619 };
621 ldo2_reg: ldo2 {
622 /* LDO2_OUT --> TP1017 (UNUSED) */
623 regulator-name = "ldo2";
624 regulator-min-microvolt = <1800000>;
625 regulator-max-microvolt = <3300000>;
626 };
628 ldo3_reg: ldo3 {
629 /* VDDA_1V8_PHY */
630 regulator-name = "ldo3";
631 regulator-min-microvolt = <1800000>;
632 regulator-max-microvolt = <1800000>;
633 regulator-boot-on;
634 regulator-always-on;
635 };
637 ldo5_reg: ldo5 {
638 /* VDDA_1V8_PLL */
639 regulator-name = "ldo5";
640 regulator-min-microvolt = <1800000>;
641 regulator-max-microvolt = <1800000>;
642 regulator-always-on;
643 regulator-boot-on;
644 };
646 ldo4_reg: ldo4 {
647 /* VDDA_3V_USB: VDDA_USBHS33 */
648 regulator-name = "ldo4";
649 regulator-min-microvolt = <3300000>;
650 regulator-max-microvolt = <3300000>;
651 regulator-boot-on;
652 };
653 };
654 };
656 tps65917_power_button {
657 compatible = "ti,palmas-pwrbutton";
658 interrupt-parent = <&tps65917>;
659 interrupts = <1 IRQ_TYPE_NONE>;
660 wakeup-source;
661 ti,palmas-long-press-seconds = <6>;
662 };
663 };
665 pcf_lcd: gpio@20 {
666 compatible = "nxp,pcf8575";
667 reg = <0x20>;
668 gpio-controller;
669 #gpio-cells = <2>;
670 };
672 pcf_gpio_21: gpio@21 {
673 compatible = "nxp,pcf8575";
674 reg = <0x21>;
675 lines-initial-states = <0x1408>;
676 gpio-controller;
677 #gpio-cells = <2>;
678 interrupt-parent = <&gpio6>;
679 interrupts = <11 2>;
680 interrupt-controller;
681 #interrupt-cells = <2>;
683 cpsw_sel_s0 {
684 gpio-hog;
685 gpios = <4 GPIO_ACTIVE_HIGH>;
686 output-low;
687 };
688 };
690 tlv320aic3106: tlv320aic3106@19 {
691 compatible = "ti,tlv320aic3106";
692 reg = <0x19>;
693 adc-settle-ms = <40>;
694 ai3x-micbias-vg = <1>; /* 2.0V */
695 status = "okay";
697 /* Regulators */
698 AVDD-supply = <&evm_3v3_sw>;
699 IOVDD-supply = <&evm_3v3_sw>;
700 DRVDD-supply = <&evm_3v3_sw>;
701 DVDD-supply = <&aic_dvdd>;
702 };
703 };
705 &dra7_pmx_core {
706 i2c5_pins: pinmux_i2c5_pins {
707 pinctrl-single,pins = <
708 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
709 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
710 >;
711 };
712 };
714 i2c_p3_exp: &i2c5 {
715 status = "okay";
716 pinctrl-names = "default";
717 pinctrl-0 = <&i2c5_pins>;
718 clock-frequency = <400000>;
720 pcf_hdmi: pcf8575@26 {
721 compatible = "nxp,pcf8575";
722 reg = <0x26>;
723 gpio-controller;
724 #gpio-cells = <2>;
725 /*
726 * initial state is used here to keep the mdio interface
727 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
728 * VIN2_S0 driven high otherwise Ethernet stops working
729 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
730 */
731 lines-initial-states = <0x0f2b>;
732 };
734 ov10633@37 {
735 compatible = "ovti,ov10633";
736 reg = <0x37>;
738 mux-gpios = <&pcf_hdmi 2 GPIO_ACTIVE_HIGH>, /* VIN2_S0 */
739 <&pcf_hdmi 6 GPIO_ACTIVE_LOW>; /* VIN2_S2 */
740 port {
741 onboardLI: endpoint {
742 remote-endpoint = <&vin2a>;
743 hsync-active = <1>;
744 vsync-active = <1>;
745 pclk-sample = <1>;
746 };
747 };
748 };
749 };
751 &uart1 {
752 pinctrl-names = "default";
753 pinctrl-0 = <&uart1_pins>;
755 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH
756 &dra7_pmx_core 0x3e0>;
757 status = "okay";
758 };
760 &uart3 {
761 status = "okay";
762 gpios = <&pcf_gpio_21 14 GPIO_ACTIVE_LOW>;
763 };
765 &mmc1 {
766 /* Using default configured pins */
767 status = "okay";
768 pbias-supply = <&pbias_mmc_reg>;
769 vmmc-supply = <&evm_3v3_sd>;
770 vmmc_aux-supply = <&ldo1_reg>;
771 bus-width = <4>;
772 /*
773 * SDCD signal is not being used here - using the fact that GPIO mode
774 * is always hardwired.
775 */
776 cd-gpios = <&gpio6 27 0>;
777 sd-uhs-sdr104;
778 sd-uhs-sdr50;
779 sd-uhs-ddr50;
780 sd-uhs-sdr25;
781 sd-uhs-sdr12;
782 max-frequency = <192000000>;
783 };
785 &mmc2 {
786 /* Using default configured pins */
787 status = "okay";
788 vmmc-supply = <&evm_3v3_sw>;
789 bus-width = <8>;
790 ti,non-removable;
791 mmc-hs200-1_8v;
792 max-frequency = <192000000>;
793 };
795 &mmc4 {
796 status = "okay";
797 vmmc-supply = <&vmmcwl_fixed>;
798 bus-width = <4>;
799 pinctrl-names = "default";
800 pinctrl-0 = <&wlan_pins &wlirq_pins>;
801 cap-power-off-card;
802 keep-power-in-suspend;
803 ti,non-removable;
805 #address-cells = <1>;
806 #size-cells = <0>;
807 wlcore: wlcore@0 {
808 compatible = "ti,wlcore";
809 reg = <2>;
810 interrupt-parent = <&gpio5>;
811 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
812 };
813 };
815 &mac {
816 status = "okay";
817 pinctrl-names = "default", "sleep";
818 pinctrl-0 = <&cpsw_default>;
819 pinctrl-1 = <&cpsw_sleep>;
820 slaves = <1>;
821 };
823 &cpsw_emac0 {
824 phy_id = <&davinci_mdio>, <3>;
825 phy-mode = "rgmii";
826 };
828 &davinci_mdio {
829 pinctrl-names = "default", "sleep";
830 pinctrl-0 = <&davinci_mdio_default>;
831 pinctrl-1 = <&davinci_mdio_sleep>;
832 };
834 &cpu0 {
835 cpu0-voltdm = <&voltdm_mpu>;
836 voltage-tolerance = <1>;
837 };
839 &voltdm_mpu {
840 vdd-supply = <&smps1_reg>;
841 };
843 &voltdm_core {
844 vdd-supply = <&smps2_reg>;
845 };
847 &voltdm_dspeve {
848 vdd-supply = <&smps3_reg>;
849 };
851 &voltdm_gpu {
852 vdd-supply = <&smps3_reg>;
853 };
855 &voltdm_ivahd {
856 vdd-supply = <&smps3_reg>;
857 };
859 &elm {
860 status = "okay";
861 };
863 &gpmc {
864 status = "okay";
865 pinctrl-names = "default";
866 pinctrl-0 = <&nand_default>;
867 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
868 nand@0,0 {
869 /* To use NAND, DIP switch SW5 must be set like so:
870 * SW5.1 (NAND_SELn) = ON (LOW)
871 * SW5.9 (GPMC_WPN) = OFF (HIGH)
872 */
873 reg = <0 0 4>; /* device IO registers */
874 ti,nand-ecc-opt = "bch8";
875 ti,elm-id = <&elm>;
876 nand-bus-width = <16>;
877 gpmc,device-width = <2>;
878 gpmc,sync-clk-ps = <0>;
879 gpmc,cs-on-ns = <0>;
880 gpmc,cs-rd-off-ns = <80>;
881 gpmc,cs-wr-off-ns = <80>;
882 gpmc,adv-on-ns = <0>;
883 gpmc,adv-rd-off-ns = <60>;
884 gpmc,adv-wr-off-ns = <60>;
885 gpmc,we-on-ns = <10>;
886 gpmc,we-off-ns = <50>;
887 gpmc,oe-on-ns = <4>;
888 gpmc,oe-off-ns = <40>;
889 gpmc,access-ns = <40>;
890 gpmc,wr-access-ns = <80>;
891 gpmc,rd-cycle-ns = <80>;
892 gpmc,wr-cycle-ns = <80>;
893 gpmc,bus-turnaround-ns = <0>;
894 gpmc,cycle2cycle-delay-ns = <0>;
895 gpmc,clk-activation-ns = <0>;
896 gpmc,wait-monitoring-ns = <0>;
897 gpmc,wr-data-mux-bus-ns = <0>;
898 /* MTD partition table */
899 /* All SPL-* partitions are sized to minimal length
900 * which can be independently programmable. For
901 * NAND flash this is equal to size of erase-block */
902 #address-cells = <1>;
903 #size-cells = <1>;
904 partition@0 {
905 label = "NAND.SPL";
906 reg = <0x00000000 0x000020000>;
907 };
908 partition@1 {
909 label = "NAND.SPL.backup1";
910 reg = <0x00020000 0x00020000>;
911 };
912 partition@2 {
913 label = "NAND.SPL.backup2";
914 reg = <0x00040000 0x00020000>;
915 };
916 partition@3 {
917 label = "NAND.SPL.backup3";
918 reg = <0x00060000 0x00020000>;
919 };
920 partition@4 {
921 label = "NAND.u-boot-spl-os";
922 reg = <0x00080000 0x00040000>;
923 };
924 partition@5 {
925 label = "NAND.u-boot";
926 reg = <0x000c0000 0x00100000>;
927 };
928 partition@6 {
929 label = "NAND.u-boot-env";
930 reg = <0x001c0000 0x00020000>;
931 };
932 partition@7 {
933 label = "NAND.u-boot-env.backup1";
934 reg = <0x001e0000 0x00020000>;
935 };
936 partition@8 {
937 label = "NAND.kernel";
938 reg = <0x00200000 0x00800000>;
939 };
940 partition@9 {
941 label = "NAND.file-system";
942 reg = <0x00a00000 0x0f600000>;
943 };
944 };
945 };
947 &dss {
948 status = "ok";
950 vdda_video-supply = <&ldo5_reg>;
951 };
953 &hdmi {
954 status = "ok";
955 vdda-supply = <&ldo3_reg>;
956 pinctrl-names = "default";
957 pinctrl-0 = <&i2c2_pins>;
959 port {
960 hdmi_out: endpoint {
961 remote-endpoint = <&tpd12s015_in>;
962 };
963 };
964 };
966 &mailbox5 {
967 status = "okay";
968 mbox_ipu1_legacy: mbox_ipu1_legacy {
969 status = "okay";
970 };
971 mbox_dsp1_legacy: mbox_dsp1_legacy {
972 status = "okay";
973 };
974 };
976 &mailbox6 {
977 status = "okay";
978 mbox_ipu2_legacy: mbox_ipu2_legacy {
979 status = "okay";
980 };
981 };
983 &mmu0_dsp1 {
984 status = "okay";
985 };
987 &mmu1_dsp1 {
988 status = "okay";
989 };
991 &mmu_ipu1 {
992 status = "okay";
993 };
995 &mmu_ipu2 {
996 status = "okay";
997 };
999 &ipu2 {
1000 status = "okay";
1001 memory-region = <&ipu2_cma_pool>;
1002 mboxes = <&mailbox6 &mbox_ipu2_legacy>;
1003 timers = <&timer3>;
1004 watchdog-timers = <&timer4>, <&timer9>;
1005 };
1007 &ipu1 {
1008 status = "okay";
1009 memory-region = <&ipu1_cma_pool>;
1010 mboxes = <&mailbox5 &mbox_ipu1_legacy>;
1011 timers = <&timer11>;
1012 watchdog-timers = <&timer7>, <&timer8>;
1013 };
1015 &dsp1 {
1016 status = "okay";
1017 memory-region = <&dsp1_cma_pool>;
1018 mboxes = <&mailbox5 &mbox_dsp1_legacy>;
1019 timers = <&timer5>;
1020 watchdog-timers = <&timer10>;
1021 };
1023 &atl {
1024 pinctrl-names = "default";
1025 pinctrl-0 = <&atl_pins>;
1027 status = "okay";
1029 atl2 {
1030 bws = <DRA7_ATL_WS_MCASP2_FSX>;
1031 aws = <DRA7_ATL_WS_MCASP3_FSX>;
1032 };
1033 };
1035 &mcasp3 {
1036 pinctrl-names = "default", "sleep";
1037 pinctrl-0 = <&mcasp3_pins>;
1038 pinctrl-1 = <&mcasp3_sleep_pins>;
1040 fck_parent = "atl_clkin2_ck";
1042 status = "okay";
1044 op-mode = <0>; /* MCASP_IIS_MODE */
1045 tdm-slots = <2>;
1046 /* 4 serializer */
1047 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1048 1 2 0 0
1049 >;
1050 };
1052 &mcasp7 {
1053 #sound-dai-cells = <0>;
1054 pinctrl-names = "default", "sleep";
1055 pinctrl-0 = <&mcasp7_pins>;
1056 pinctrl-1 = <&mcasp7_sleep_pins>;
1058 status = "okay";
1060 op-mode = <0>; /* MCASP_IIS_MODE */
1061 tdm-slots = <4>;
1062 /* 4 serializer */
1063 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1064 2 1 0 0
1065 >;
1066 tx-num-evt = <8>;
1067 rx-num-evt = <8>;
1068 };
1070 &omap_dwc3_1 {
1071 extcon = <&extcon_usb1>;
1072 };
1074 &omap_dwc3_2 {
1075 extcon = <&extcon_usb2>;
1076 };
1078 &usb2_phy1 {
1079 phy-supply = <&ldo4_reg>;
1080 };
1082 &usb2_phy2 {
1083 phy-supply = <&ldo4_reg>;
1084 };
1086 &usb1 {
1087 dr_mode = "otg";
1088 pinctrl-names = "default";
1089 pinctrl-0 = <&usb1_pins>;
1090 };
1092 &usb2 {
1093 dr_mode = "host";
1094 pinctrl-names = "default";
1095 pinctrl-0 = <&usb2_pins>;
1096 };
1098 &qspi {
1099 status = "okay";
1100 pinctrl-names = "default";
1101 pinctrl-0 = <&qspi1_pins>;
1103 spi-max-frequency = <48000000>;
1104 m25p80@0 {
1105 compatible = "s25fl256s1";
1106 spi-max-frequency = <48000000>;
1107 reg = <0>;
1108 spi-tx-bus-width = <1>;
1109 spi-rx-bus-width = <4>;
1110 spi-cpol;
1111 spi-cpha;
1112 #address-cells = <1>;
1113 #size-cells = <1>;
1115 /* MTD partition table.
1116 * The ROM checks the first four physical blocks
1117 * for a valid file to boot and the flash here is
1118 * 64KiB block size.
1119 */
1120 partition@0 {
1121 label = "QSPI.SPL";
1122 reg = <0x00000000 0x000010000>;
1123 };
1124 partition@1 {
1125 label = "QSPI.SPL.backup1";
1126 reg = <0x00010000 0x00010000>;
1127 };
1128 partition@2 {
1129 label = "QSPI.SPL.backup2";
1130 reg = <0x00020000 0x00010000>;
1131 };
1132 partition@3 {
1133 label = "QSPI.SPL.backup3";
1134 reg = <0x00030000 0x00010000>;
1135 };
1136 partition@4 {
1137 label = "QSPI.u-boot";
1138 reg = <0x00040000 0x00100000>;
1139 };
1140 partition@5 {
1141 label = "QSPI.u-boot-spl-os";
1142 reg = <0x00140000 0x00080000>;
1143 };
1144 partition@6 {
1145 label = "QSPI.u-boot-env";
1146 reg = <0x001c0000 0x00010000>;
1147 };
1148 partition@7 {
1149 label = "QSPI.u-boot-env.backup1";
1150 reg = <0x001d0000 0x0010000>;
1151 };
1152 partition@8 {
1153 label = "QSPI.kernel";
1154 reg = <0x001e0000 0x0800000>;
1155 };
1156 partition@9 {
1157 label = "QSPI.file-system";
1158 reg = <0x009e0000 0x01620000>;
1159 };
1160 };
1161 };
1163 &dcan1 {
1164 status = "ok";
1165 pinctrl-names = "default", "sleep";
1166 pinctrl-0 = <&dcan1_pins_default>;
1167 pinctrl-1 = <&dcan1_pins_sleep>;
1168 };
1170 &vip1 {
1171 pinctrl-names = "default";
1172 pinctrl-0 = <&vin2a_pins>;
1173 status = "okay";
1174 };
1176 &vin2a {
1177 endpoint@0 {
1178 slave-mode;
1179 remote-endpoint = <&onboardLI>;
1180 };
1181 };
1183 #include "dra7xx-jamr3.dtsi"