1 /*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
10 #include "dra7.dtsi"
12 / {
13 compatible = "ti,dra722", "ti,dra72", "ti,dra7";
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu0: cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a15";
22 reg = <0>;
24 operating-points = <
25 /* kHz uV */
26 1000000 1100000
27 >;
29 clocks = <&dpll_mpu_ck>;
30 clock-names = "cpu";
32 clock-latency = <300000>; /* From omap-cpufreq driver */
34 /* cooling options */
35 cooling-min-level = <0>;
36 cooling-max-level = <2>;
37 #cooling-cells = <2>; /* min followed by max */
38 };
39 };
41 iva_coproc {
42 compatible = "ti,coproc";
43 clocks = <&dpll_iva_m2_ck>, <&dpll_iva_ck>;
44 clock-names = "fclk", "dpll";
45 clock-target-frequency = <532000000>;
46 operating-points = <
47 388200 1060000
48 430000 1150000
49 532000 1250000
50 >;
51 coproc-voltdm = <&voltdm_ivahd>;
52 voltage-tolerance = <1>;
53 };
55 dsp_coproc {
56 compatible = "ti,coproc";
57 clocks = <&dpll_dsp_m2_ck>, <&dpll_dsp_ck>;
58 clock-names = "fclk", "dpll";
59 clock-target-frequency = <700000000>;
60 operating-points = <
61 600000 1060000
62 700000 1150000
63 >;
64 coproc-voltdm = <&voltdm_dspeve>;
65 voltage-tolerance = <1>;
66 };
68 dra72_vip_mux: pinmux@4a002e8c {
69 compatible = "pinctrl-single";
70 reg = <0x4a002e8c 0x4>;
71 #address-cells = <1>;
72 #size-cells = <0>;
73 pinctrl-single,register-width = <32>;
74 pinctrl-single,function-mask = <0x7f>;
75 };
77 thermal_zones: thermal-zones {
78 #include "omap5-cpu-thermal.dtsi"
79 };
81 aliases {
82 rproc0 = &ipu1;
83 rproc1 = &ipu2;
84 rproc2 = &dsp1;
85 };
87 pmu {
88 compatible = "arm,cortex-a15-pmu";
89 interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
90 };
91 };
93 &mailbox1 {
94 mbox_ipu2: mbox_ipu2 {
95 ti,mbox-tx = <0 0 0>;
96 ti,mbox-rx = <1 0 0>;
97 status = "disabled";
98 };
99 mbox_dsp1: mbox_dsp1 {
100 ti,mbox-tx = <3 0 0>;
101 ti,mbox-rx = <2 0 0>;
102 status = "disabled";
103 };
104 };
106 &mailbox2 {
107 mbox_ipu1: mbox_ipu1 {
108 ti,mbox-tx = <0 0 0>;
109 ti,mbox-rx = <1 0 0>;
110 status = "disabled";
111 };
112 };
114 &mailbox5 {
115 mbox_ipu1_legacy: mbox_ipu1_legacy {
116 ti,mbox-tx = <6 2 2>;
117 ti,mbox-rx = <4 2 2>;
118 status = "disabled";
119 };
120 mbox_dsp1_legacy: mbox_dsp1_legacy {
121 ti,mbox-tx = <5 2 2>;
122 ti,mbox-rx = <1 2 2>;
123 status = "disabled";
124 };
125 };
127 &mailbox6 {
128 mbox_ipu2_legacy: mbox_ipu2_legacy {
129 ti,mbox-tx = <6 2 2>;
130 ti,mbox-rx = <4 2 2>;
131 status = "disabled";
132 };
133 };