1 /*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
13 #include "skeleton.dtsi"
15 / {
16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&gic>;
19 aliases {
20 i2c0 = &i2c1;
21 i2c1 = &i2c2;
22 i2c2 = &i2c3;
23 i2c3 = &i2c4;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 rproc0 = &dsp;
29 rproc1 = &ipu;
30 };
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
36 cpu@0 {
37 compatible = "arm,cortex-a9";
38 device_type = "cpu";
39 next-level-cache = <&L2>;
40 reg = <0x0>;
42 clocks = <&dpll_mpu_ck>;
43 clock-names = "cpu";
45 clock-latency = <300000>; /* From omap-cpufreq driver */
46 };
47 cpu@1 {
48 compatible = "arm,cortex-a9";
49 device_type = "cpu";
50 next-level-cache = <&L2>;
51 reg = <0x1>;
52 };
53 };
55 gic: interrupt-controller@48241000 {
56 compatible = "arm,cortex-a9-gic";
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 reg = <0x48241000 0x1000>,
60 <0x48240100 0x0100>;
61 };
63 L2: l2-cache-controller@48242000 {
64 compatible = "arm,pl310-cache";
65 reg = <0x48242000 0x1000>;
66 cache-unified;
67 cache-level = <2>;
68 };
70 local-timer@48240600 {
71 compatible = "arm,cortex-a9-twd-timer";
72 reg = <0x48240600 0x20>;
73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
74 };
76 /*
77 * The soc node represents the soc top level view. It is uses for IPs
78 * that are not memory mapped in the MPU view or for the MPU itself.
79 */
80 soc {
81 compatible = "ti,omap-infra";
82 mpu {
83 compatible = "ti,omap4-mpu";
84 ti,hwmods = "mpu";
85 };
87 iva {
88 compatible = "ti,ivahd";
89 ti,hwmods = "iva";
90 };
91 };
93 /*
94 * XXX: Use a flat representation of the OMAP4 interconnect.
95 * The real OMAP interconnect network is quite complex.
96 * Since that will not bring real advantage to represent that in DT for
97 * the moment, just use a fake OCP bus entry to represent the whole bus
98 * hierarchy.
99 */
100 ocp {
101 compatible = "ti,omap4-l3-noc", "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges;
105 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
106 reg = <0x44000000 0x1000>,
107 <0x44800000 0x2000>,
108 <0x45000000 0x1000>;
109 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
112 cm1: cm1@4a004000 {
113 compatible = "ti,omap4-cm1";
114 reg = <0x4a004000 0x2000>;
116 cm1_clocks: clocks {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 };
121 cm1_clockdomains: clockdomains {
122 };
123 };
125 prm: prm@4a306000 {
126 compatible = "ti,omap4-prm";
127 reg = <0x4a306000 0x3000>;
129 prm_clocks: clocks {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 };
134 prm_clockdomains: clockdomains {
135 };
136 };
138 cm2: cm2@4a008000 {
139 compatible = "ti,omap4-cm2";
140 reg = <0x4a008000 0x3000>;
142 cm2_clocks: clocks {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 };
147 cm2_clockdomains: clockdomains {
148 };
149 };
151 scrm: scrm@4a30a000 {
152 compatible = "ti,omap4-scrm";
153 reg = <0x4a30a000 0x2000>;
155 scrm_clocks: clocks {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 };
160 scrm_clockdomains: clockdomains {
161 };
162 };
164 counter32k: counter@4a304000 {
165 compatible = "ti,omap-counter32k";
166 reg = <0x4a304000 0x20>;
167 ti,hwmods = "counter_32k";
168 };
170 omap4_pmx_core: pinmux@4a100040 {
171 compatible = "ti,omap4-padconf", "pinctrl-single";
172 reg = <0x4a100040 0x0196>;
173 #address-cells = <1>;
174 #size-cells = <0>;
175 #interrupt-cells = <1>;
176 interrupt-controller;
177 pinctrl-single,register-width = <16>;
178 pinctrl-single,function-mask = <0x7fff>;
179 };
180 omap4_pmx_wkup: pinmux@4a31e040 {
181 compatible = "ti,omap4-padconf", "pinctrl-single";
182 reg = <0x4a31e040 0x0038>;
183 #address-cells = <1>;
184 #size-cells = <0>;
185 #interrupt-cells = <1>;
186 interrupt-controller;
187 pinctrl-single,register-width = <16>;
188 pinctrl-single,function-mask = <0x7fff>;
189 };
191 omap4_padconf_global: tisyscon@4a1005a0 {
192 compatible = "syscon";
193 reg = <0x4a1005a0 0x170>;
194 };
196 pbias_regulator: pbias_regulator {
197 compatible = "ti,pbias-omap";
198 reg = <0x60 0x4>;
199 syscon = <&omap4_padconf_global>;
200 pbias_mmc_reg: pbias_mmc_omap4 {
201 regulator-name = "pbias_mmc_omap4";
202 regulator-min-microvolt = <1800000>;
203 regulator-max-microvolt = <3000000>;
204 };
205 };
207 sdma: dma-controller@4a056000 {
208 compatible = "ti,omap4430-sdma";
209 reg = <0x4a056000 0x1000>;
210 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
214 #dma-cells = <1>;
215 #dma-channels = <32>;
216 #dma-requests = <127>;
217 };
219 gpio1: gpio@4a310000 {
220 compatible = "ti,omap4-gpio";
221 reg = <0x4a310000 0x200>;
222 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
223 ti,hwmods = "gpio1";
224 ti,gpio-always-on;
225 gpio-controller;
226 #gpio-cells = <2>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
229 };
231 gpio2: gpio@48055000 {
232 compatible = "ti,omap4-gpio";
233 reg = <0x48055000 0x200>;
234 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
235 ti,hwmods = "gpio2";
236 gpio-controller;
237 #gpio-cells = <2>;
238 interrupt-controller;
239 #interrupt-cells = <2>;
240 };
242 gpio3: gpio@48057000 {
243 compatible = "ti,omap4-gpio";
244 reg = <0x48057000 0x200>;
245 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
246 ti,hwmods = "gpio3";
247 gpio-controller;
248 #gpio-cells = <2>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
253 gpio4: gpio@48059000 {
254 compatible = "ti,omap4-gpio";
255 reg = <0x48059000 0x200>;
256 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
257 ti,hwmods = "gpio4";
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-controller;
261 #interrupt-cells = <2>;
262 };
264 gpio5: gpio@4805b000 {
265 compatible = "ti,omap4-gpio";
266 reg = <0x4805b000 0x200>;
267 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
268 ti,hwmods = "gpio5";
269 gpio-controller;
270 #gpio-cells = <2>;
271 interrupt-controller;
272 #interrupt-cells = <2>;
273 };
275 gpio6: gpio@4805d000 {
276 compatible = "ti,omap4-gpio";
277 reg = <0x4805d000 0x200>;
278 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
279 ti,hwmods = "gpio6";
280 gpio-controller;
281 #gpio-cells = <2>;
282 interrupt-controller;
283 #interrupt-cells = <2>;
284 };
286 gpmc: gpmc@50000000 {
287 compatible = "ti,omap4430-gpmc";
288 reg = <0x50000000 0x1000>;
289 #address-cells = <2>;
290 #size-cells = <1>;
291 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
292 gpmc,num-cs = <8>;
293 gpmc,num-waitpins = <4>;
294 ti,hwmods = "gpmc";
295 ti,no-idle-on-init;
296 clocks = <&l3_div_ck>;
297 clock-names = "fck";
298 };
300 uart1: serial@4806a000 {
301 compatible = "ti,omap4-uart";
302 reg = <0x4806a000 0x100>;
303 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
304 ti,hwmods = "uart1";
305 clock-frequency = <48000000>;
306 };
308 uart2: serial@4806c000 {
309 compatible = "ti,omap4-uart";
310 reg = <0x4806c000 0x100>;
311 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
312 ti,hwmods = "uart2";
313 clock-frequency = <48000000>;
314 };
316 uart3: serial@48020000 {
317 compatible = "ti,omap4-uart";
318 reg = <0x48020000 0x100>;
319 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
320 ti,hwmods = "uart3";
321 clock-frequency = <48000000>;
322 };
324 uart4: serial@4806e000 {
325 compatible = "ti,omap4-uart";
326 reg = <0x4806e000 0x100>;
327 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
328 ti,hwmods = "uart4";
329 clock-frequency = <48000000>;
330 };
332 hwspinlock: spinlock@4a0f6000 {
333 compatible = "ti,omap4-hwspinlock";
334 reg = <0x4a0f6000 0x1000>;
335 ti,hwmods = "spinlock";
336 #hwlock-cells = <1>;
337 };
339 i2c1: i2c@48070000 {
340 compatible = "ti,omap4-i2c";
341 reg = <0x48070000 0x100>;
342 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
343 #address-cells = <1>;
344 #size-cells = <0>;
345 ti,hwmods = "i2c1";
346 };
348 i2c2: i2c@48072000 {
349 compatible = "ti,omap4-i2c";
350 reg = <0x48072000 0x100>;
351 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
352 #address-cells = <1>;
353 #size-cells = <0>;
354 ti,hwmods = "i2c2";
355 };
357 i2c3: i2c@48060000 {
358 compatible = "ti,omap4-i2c";
359 reg = <0x48060000 0x100>;
360 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363 ti,hwmods = "i2c3";
364 };
366 i2c4: i2c@48350000 {
367 compatible = "ti,omap4-i2c";
368 reg = <0x48350000 0x100>;
369 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 ti,hwmods = "i2c4";
373 };
375 mcspi1: spi@48098000 {
376 compatible = "ti,omap4-mcspi";
377 reg = <0x48098000 0x200>;
378 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
379 #address-cells = <1>;
380 #size-cells = <0>;
381 ti,hwmods = "mcspi1";
382 ti,spi-num-cs = <4>;
383 dmas = <&sdma 35>,
384 <&sdma 36>,
385 <&sdma 37>,
386 <&sdma 38>,
387 <&sdma 39>,
388 <&sdma 40>,
389 <&sdma 41>,
390 <&sdma 42>;
391 dma-names = "tx0", "rx0", "tx1", "rx1",
392 "tx2", "rx2", "tx3", "rx3";
393 };
395 mcspi2: spi@4809a000 {
396 compatible = "ti,omap4-mcspi";
397 reg = <0x4809a000 0x200>;
398 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
399 #address-cells = <1>;
400 #size-cells = <0>;
401 ti,hwmods = "mcspi2";
402 ti,spi-num-cs = <2>;
403 dmas = <&sdma 43>,
404 <&sdma 44>,
405 <&sdma 45>,
406 <&sdma 46>;
407 dma-names = "tx0", "rx0", "tx1", "rx1";
408 };
410 mcspi3: spi@480b8000 {
411 compatible = "ti,omap4-mcspi";
412 reg = <0x480b8000 0x200>;
413 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
414 #address-cells = <1>;
415 #size-cells = <0>;
416 ti,hwmods = "mcspi3";
417 ti,spi-num-cs = <2>;
418 dmas = <&sdma 15>, <&sdma 16>;
419 dma-names = "tx0", "rx0";
420 };
422 mcspi4: spi@480ba000 {
423 compatible = "ti,omap4-mcspi";
424 reg = <0x480ba000 0x200>;
425 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
426 #address-cells = <1>;
427 #size-cells = <0>;
428 ti,hwmods = "mcspi4";
429 ti,spi-num-cs = <1>;
430 dmas = <&sdma 70>, <&sdma 71>;
431 dma-names = "tx0", "rx0";
432 };
434 mmc1: mmc@4809c000 {
435 compatible = "ti,omap4-hsmmc";
436 reg = <0x4809c000 0x400>;
437 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
438 ti,hwmods = "mmc1";
439 ti,dual-volt;
440 ti,needs-special-reset;
441 dmas = <&sdma 61>, <&sdma 62>;
442 dma-names = "tx", "rx";
443 pbias-supply = <&pbias_mmc_reg>;
444 };
446 mmc2: mmc@480b4000 {
447 compatible = "ti,omap4-hsmmc";
448 reg = <0x480b4000 0x400>;
449 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
450 ti,hwmods = "mmc2";
451 ti,needs-special-reset;
452 dmas = <&sdma 47>, <&sdma 48>;
453 dma-names = "tx", "rx";
454 };
456 mmc3: mmc@480ad000 {
457 compatible = "ti,omap4-hsmmc";
458 reg = <0x480ad000 0x400>;
459 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
460 ti,hwmods = "mmc3";
461 ti,needs-special-reset;
462 dmas = <&sdma 77>, <&sdma 78>;
463 dma-names = "tx", "rx";
464 };
466 mmc4: mmc@480d1000 {
467 compatible = "ti,omap4-hsmmc";
468 reg = <0x480d1000 0x400>;
469 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
470 ti,hwmods = "mmc4";
471 ti,needs-special-reset;
472 dmas = <&sdma 57>, <&sdma 58>;
473 dma-names = "tx", "rx";
474 };
476 mmc5: mmc@480d5000 {
477 compatible = "ti,omap4-hsmmc";
478 reg = <0x480d5000 0x400>;
479 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
480 ti,hwmods = "mmc5";
481 ti,needs-special-reset;
482 dmas = <&sdma 59>, <&sdma 60>;
483 dma-names = "tx", "rx";
484 };
486 mmu_dsp: mmu@4a066000 {
487 compatible = "ti,omap4-iommu";
488 reg = <0x4a066000 0x100>;
489 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
490 ti,hwmods = "mmu_dsp";
491 };
493 mmu_ipu: mmu@55082000 {
494 compatible = "ti,omap4-iommu";
495 reg = <0x55082000 0x100>;
496 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
497 ti,hwmods = "mmu_ipu";
498 ti,iommu-bus-err-back;
499 };
501 wdt2: wdt@4a314000 {
502 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
503 reg = <0x4a314000 0x80>;
504 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
505 ti,hwmods = "wd_timer2";
506 };
508 mcpdm: mcpdm@40132000 {
509 compatible = "ti,omap4-mcpdm";
510 reg = <0x40132000 0x7f>, /* MPU private access */
511 <0x49032000 0x7f>; /* L3 Interconnect */
512 reg-names = "mpu", "dma";
513 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
514 ti,hwmods = "mcpdm";
515 dmas = <&sdma 65>,
516 <&sdma 66>;
517 dma-names = "up_link", "dn_link";
518 status = "disabled";
519 };
521 dmic: dmic@4012e000 {
522 compatible = "ti,omap4-dmic";
523 reg = <0x4012e000 0x7f>, /* MPU private access */
524 <0x4902e000 0x7f>; /* L3 Interconnect */
525 reg-names = "mpu", "dma";
526 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
527 ti,hwmods = "dmic";
528 dmas = <&sdma 67>;
529 dma-names = "up_link";
530 status = "disabled";
531 };
533 mcbsp1: mcbsp@40122000 {
534 compatible = "ti,omap4-mcbsp";
535 reg = <0x40122000 0xff>, /* MPU private access */
536 <0x49022000 0xff>; /* L3 Interconnect */
537 reg-names = "mpu", "dma";
538 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
539 interrupt-names = "common";
540 ti,buffer-size = <128>;
541 ti,hwmods = "mcbsp1";
542 dmas = <&sdma 33>,
543 <&sdma 34>;
544 dma-names = "tx", "rx";
545 status = "disabled";
546 };
548 mcbsp2: mcbsp@40124000 {
549 compatible = "ti,omap4-mcbsp";
550 reg = <0x40124000 0xff>, /* MPU private access */
551 <0x49024000 0xff>; /* L3 Interconnect */
552 reg-names = "mpu", "dma";
553 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
554 interrupt-names = "common";
555 ti,buffer-size = <128>;
556 ti,hwmods = "mcbsp2";
557 dmas = <&sdma 17>,
558 <&sdma 18>;
559 dma-names = "tx", "rx";
560 status = "disabled";
561 };
563 mcbsp3: mcbsp@40126000 {
564 compatible = "ti,omap4-mcbsp";
565 reg = <0x40126000 0xff>, /* MPU private access */
566 <0x49026000 0xff>; /* L3 Interconnect */
567 reg-names = "mpu", "dma";
568 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
569 interrupt-names = "common";
570 ti,buffer-size = <128>;
571 ti,hwmods = "mcbsp3";
572 dmas = <&sdma 19>,
573 <&sdma 20>;
574 dma-names = "tx", "rx";
575 status = "disabled";
576 };
578 mcbsp4: mcbsp@48096000 {
579 compatible = "ti,omap4-mcbsp";
580 reg = <0x48096000 0xff>; /* L4 Interconnect */
581 reg-names = "mpu";
582 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
583 interrupt-names = "common";
584 ti,buffer-size = <128>;
585 ti,hwmods = "mcbsp4";
586 dmas = <&sdma 31>,
587 <&sdma 32>;
588 dma-names = "tx", "rx";
589 status = "disabled";
590 };
592 keypad: keypad@4a31c000 {
593 compatible = "ti,omap4-keypad";
594 reg = <0x4a31c000 0x80>;
595 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
596 reg-names = "mpu";
597 ti,hwmods = "kbd";
598 };
600 dmm@4e000000 {
601 compatible = "ti,omap4-dmm";
602 reg = <0x4e000000 0x800>;
603 interrupts = <0 113 0x4>;
604 ti,hwmods = "dmm";
605 };
607 emif1: emif@4c000000 {
608 compatible = "ti,emif-4d";
609 reg = <0x4c000000 0x100>;
610 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
611 ti,hwmods = "emif1";
612 ti,no-idle-on-init;
613 phy-type = <1>;
614 hw-caps-read-idle-ctrl;
615 hw-caps-ll-interface;
616 hw-caps-temp-alert;
617 };
619 emif2: emif@4d000000 {
620 compatible = "ti,emif-4d";
621 reg = <0x4d000000 0x100>;
622 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
623 ti,hwmods = "emif2";
624 ti,no-idle-on-init;
625 phy-type = <1>;
626 hw-caps-read-idle-ctrl;
627 hw-caps-ll-interface;
628 hw-caps-temp-alert;
629 };
631 ocp2scp@4a0ad000 {
632 compatible = "ti,omap-ocp2scp";
633 reg = <0x4a0ad000 0x1f>;
634 #address-cells = <1>;
635 #size-cells = <1>;
636 ranges;
637 ti,hwmods = "ocp2scp_usb_phy";
638 usb2_phy: usb2phy@4a0ad080 {
639 compatible = "ti,omap-usb2";
640 reg = <0x4a0ad080 0x58>;
641 ctrl-module = <&omap_control_usb2phy>;
642 clocks = <&usb_phy_cm_clk32k>;
643 clock-names = "wkupclk";
644 #phy-cells = <0>;
645 };
646 };
648 mailbox: mailbox@4a0f4000 {
649 compatible = "ti,omap4-mailbox";
650 reg = <0x4a0f4000 0x200>;
651 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
652 ti,hwmods = "mailbox";
653 #mbox-cells = <1>;
654 ti,mbox-num-users = <3>;
655 ti,mbox-num-fifos = <8>;
656 mbox_ipu: mbox_ipu {
657 ti,mbox-tx = <0 0 0>;
658 ti,mbox-rx = <1 0 0>;
659 };
660 mbox_dsp: mbox_dsp {
661 ti,mbox-tx = <3 0 0>;
662 ti,mbox-rx = <2 0 0>;
663 };
664 };
666 timer1: timer@4a318000 {
667 compatible = "ti,omap3430-timer";
668 reg = <0x4a318000 0x80>;
669 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
670 ti,hwmods = "timer1";
671 ti,timer-alwon;
672 };
674 timer2: timer@48032000 {
675 compatible = "ti,omap3430-timer";
676 reg = <0x48032000 0x80>;
677 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
678 ti,hwmods = "timer2";
679 };
681 timer3: timer@48034000 {
682 compatible = "ti,omap4430-timer";
683 reg = <0x48034000 0x80>;
684 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
685 ti,hwmods = "timer3";
686 };
688 timer4: timer@48036000 {
689 compatible = "ti,omap4430-timer";
690 reg = <0x48036000 0x80>;
691 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
692 ti,hwmods = "timer4";
693 };
695 timer5: timer@40138000 {
696 compatible = "ti,omap4430-timer";
697 reg = <0x40138000 0x80>,
698 <0x49038000 0x80>;
699 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
700 ti,hwmods = "timer5";
701 ti,timer-dsp;
702 };
704 timer6: timer@4013a000 {
705 compatible = "ti,omap4430-timer";
706 reg = <0x4013a000 0x80>,
707 <0x4903a000 0x80>;
708 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
709 ti,hwmods = "timer6";
710 ti,timer-dsp;
711 };
713 timer7: timer@4013c000 {
714 compatible = "ti,omap4430-timer";
715 reg = <0x4013c000 0x80>,
716 <0x4903c000 0x80>;
717 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
718 ti,hwmods = "timer7";
719 ti,timer-dsp;
720 };
722 timer8: timer@4013e000 {
723 compatible = "ti,omap4430-timer";
724 reg = <0x4013e000 0x80>,
725 <0x4903e000 0x80>;
726 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
727 ti,hwmods = "timer8";
728 ti,timer-pwm;
729 ti,timer-dsp;
730 };
732 timer9: timer@4803e000 {
733 compatible = "ti,omap4430-timer";
734 reg = <0x4803e000 0x80>;
735 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
736 ti,hwmods = "timer9";
737 ti,timer-pwm;
738 };
740 timer10: timer@48086000 {
741 compatible = "ti,omap3430-timer";
742 reg = <0x48086000 0x80>;
743 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
744 ti,hwmods = "timer10";
745 ti,timer-pwm;
746 };
748 timer11: timer@48088000 {
749 compatible = "ti,omap4430-timer";
750 reg = <0x48088000 0x80>;
751 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
752 ti,hwmods = "timer11";
753 ti,timer-pwm;
754 };
756 dsp: dsp {
757 compatible = "ti,omap4-rproc-dsp";
758 ti,hwmods = "dsp";
759 iommus = <&mmu_dsp>;
760 mboxes = <&mailbox &mbox_dsp>;
761 ti,rproc-standby-info = <0x4a004420>;
762 status = "disabled";
763 };
765 ipu: ipu {
766 compatible = "ti,omap4-rproc-ipu";
767 ti,hwmods = "ipu";
768 iommus = <&mmu_ipu>;
769 mboxes = <&mailbox &mbox_ipu>;
770 ti,rproc-standby-info = <0x4a008920>;
771 status = "disabled";
772 };
774 usbhstll: usbhstll@4a062000 {
775 compatible = "ti,usbhs-tll";
776 reg = <0x4a062000 0x1000>;
777 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
778 ti,hwmods = "usb_tll_hs";
779 };
781 usbhshost: usbhshost@4a064000 {
782 compatible = "ti,usbhs-host";
783 reg = <0x4a064000 0x800>;
784 ti,hwmods = "usb_host_hs";
785 #address-cells = <1>;
786 #size-cells = <1>;
787 ranges;
788 clocks = <&init_60m_fclk>,
789 <&xclk60mhsp1_ck>,
790 <&xclk60mhsp2_ck>;
791 clock-names = "refclk_60m_int",
792 "refclk_60m_ext_p1",
793 "refclk_60m_ext_p2";
795 usbhsohci: ohci@4a064800 {
796 compatible = "ti,ohci-omap3";
797 reg = <0x4a064800 0x400>;
798 interrupt-parent = <&gic>;
799 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
800 };
802 usbhsehci: ehci@4a064c00 {
803 compatible = "ti,ehci-omap";
804 reg = <0x4a064c00 0x400>;
805 interrupt-parent = <&gic>;
806 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
807 };
808 };
810 omap_control_usb2phy: control-phy@4a002300 {
811 compatible = "ti,control-phy-usb2";
812 reg = <0x4a002300 0x4>;
813 reg-names = "power";
814 };
816 omap_control_usbotg: control-phy@4a00233c {
817 compatible = "ti,control-phy-otghs";
818 reg = <0x4a00233c 0x4>;
819 reg-names = "otghs_control";
820 };
822 usb_otg_hs: usb_otg_hs@4a0ab000 {
823 compatible = "ti,omap4-musb";
824 reg = <0x4a0ab000 0x7ff>;
825 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
826 interrupt-names = "mc", "dma";
827 ti,hwmods = "usb_otg_hs";
828 usb-phy = <&usb2_phy>;
829 phys = <&usb2_phy>;
830 phy-names = "usb2-phy";
831 multipoint = <1>;
832 num-eps = <16>;
833 ram-bits = <12>;
834 ctrl-module = <&omap_control_usbotg>;
835 };
837 aes: aes@4b501000 {
838 compatible = "ti,omap4-aes";
839 ti,hwmods = "aes";
840 reg = <0x4b501000 0xa0>;
841 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
842 dmas = <&sdma 111>, <&sdma 110>;
843 dma-names = "tx", "rx";
844 };
846 des: des@480a5000 {
847 compatible = "ti,omap4-des";
848 ti,hwmods = "des";
849 reg = <0x480a5000 0xa0>;
850 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
851 dmas = <&sdma 117>, <&sdma 116>;
852 dma-names = "tx", "rx";
853 };
855 abb_mpu: regulator-abb-mpu {
856 compatible = "ti,abb-v2";
857 regulator-name = "abb_mpu";
858 #address-cells = <0>;
859 #size-cells = <0>;
860 ti,tranxdone-status-mask = <0x80>;
861 clocks = <&sys_clkin_ck>;
862 ti,settling-time = <50>;
863 ti,clock-cycles = <16>;
865 status = "disabled";
866 };
868 abb_iva: regulator-abb-iva {
869 compatible = "ti,abb-v2";
870 regulator-name = "abb_iva";
871 #address-cells = <0>;
872 #size-cells = <0>;
873 ti,tranxdone-status-mask = <0x80000000>;
874 clocks = <&sys_clkin_ck>;
875 ti,settling-time = <50>;
876 ti,clock-cycles = <16>;
878 status = "disabled";
879 };
881 dss: dss@58000000 {
882 compatible = "ti,omap4-dss";
883 reg = <0x58000000 0x80>;
884 status = "disabled";
885 ti,hwmods = "dss_core";
886 clocks = <&dss_dss_clk>;
887 clock-names = "fck";
888 #address-cells = <1>;
889 #size-cells = <1>;
890 ranges;
892 dispc@58001000 {
893 compatible = "ti,omap4-dispc";
894 reg = <0x58001000 0x1000>;
895 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
896 ti,hwmods = "dss_dispc";
897 clocks = <&dss_dss_clk>;
898 clock-names = "fck";
899 };
901 rfbi: encoder@58002000 {
902 compatible = "ti,omap4-rfbi";
903 reg = <0x58002000 0x1000>;
904 status = "disabled";
905 ti,hwmods = "dss_rfbi";
906 clocks = <&dss_dss_clk>, <&l3_div_ck>;
907 clock-names = "fck", "ick";
908 };
910 venc: encoder@58003000 {
911 compatible = "ti,omap4-venc";
912 reg = <0x58003000 0x1000>;
913 status = "disabled";
914 ti,hwmods = "dss_venc";
915 clocks = <&dss_tv_clk>;
916 clock-names = "fck";
917 };
919 dsi1: encoder@58004000 {
920 compatible = "ti,omap4-dsi";
921 reg = <0x58004000 0x200>,
922 <0x58004200 0x40>,
923 <0x58004300 0x20>;
924 reg-names = "proto", "phy", "pll";
925 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
926 status = "disabled";
927 ti,hwmods = "dss_dsi1";
928 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
929 clock-names = "fck", "sys_clk";
930 };
932 dsi2: encoder@58005000 {
933 compatible = "ti,omap4-dsi";
934 reg = <0x58005000 0x200>,
935 <0x58005200 0x40>,
936 <0x58005300 0x20>;
937 reg-names = "proto", "phy", "pll";
938 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
939 status = "disabled";
940 ti,hwmods = "dss_dsi2";
941 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
942 clock-names = "fck", "sys_clk";
943 };
945 hdmi: encoder@58006000 {
946 compatible = "ti,omap4-hdmi";
947 reg = <0x58006000 0x200>,
948 <0x58006200 0x100>,
949 <0x58006300 0x100>,
950 <0x58006400 0x1000>;
951 reg-names = "wp", "pll", "phy", "core";
952 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
953 status = "disabled";
954 ti,hwmods = "dss_hdmi";
955 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
956 clock-names = "fck", "sys_clk";
957 dmas = <&sdma 76>;
958 dma-names = "audio_tx";
959 };
960 };
961 };
962 };
964 /include/ "omap44xx-clocks.dtsi"