1 /*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
10 /*
11 * Carveout for multimedia usecases
12 * It should be the last 48MB of the first 512MB memory part
13 * In theory, it should not even exist. That zone should be reserved
14 * dynamically during the .reserve callback.
15 */
16 /memreserve/ 0x9d000000 0x03000000;
18 /include/ "skeleton.dtsi"
20 / {
21 #address-cells = <1>;
22 #size-cells = <1>;
24 compatible = "ti,omap5";
25 interrupt-parent = <&gic>;
27 aliases {
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
36 cpus {
37 cpu@0 {
38 compatible = "arm,cortex-a15";
39 operating-points = <
40 /* kHz uV */
41 /* Only for Nominal Samples */
42 500000 880000
43 1000000 1060000
44 1500000 1250000
45 >;
46 clocks = <&dpll_mpu>;
47 clock-names = "cpu";
48 clock-latency = <300000>; /* From omap-cpufreq driver */
49 };
50 cpu@1 {
51 compatible = "arm,cortex-a15";
52 };
53 };
55 timer {
56 compatible = "arm,armv7-timer";
57 /* PPI secure/nonsecure IRQ, active low level-sensitive */
58 interrupts = <1 13 0x308>,
59 <1 14 0x308>,
60 <1 11 0x308>,
61 <1 10 0x308>;
62 clock-frequency = <6144000>;
63 };
65 gic: interrupt-controller@48211000 {
66 compatible = "arm,cortex-a15-gic";
67 interrupt-controller;
68 #interrupt-cells = <3>;
69 reg = <0x48211000 0x1000>,
70 <0x48212000 0x1000>,
71 <0x48214000 0x2000>,
72 <0x48216000 0x2000>;
73 };
75 /*
76 * The soc node represents the soc top level view. It is uses for IPs
77 * that are not memory mapped in the MPU view or for the MPU itself.
78 */
79 soc {
80 compatible = "ti,omap-infra";
81 mpu {
82 compatible = "ti,omap5-mpu";
83 ti,hwmods = "mpu";
84 };
85 };
87 /*
88 * XXX: Use a flat representation of the OMAP3 interconnect.
89 * The real OMAP interconnect network is quite complex.
90 * Since that will not bring real advantage to represent that in DT for
91 * the moment, just use a fake OCP bus entry to represent the whole bus
92 * hierarchy.
93 */
94 ocp {
95 compatible = "ti,omap4-l3-noc", "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <1>;
98 ranges;
99 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
101 counter32k: counter@4ae04000 {
102 compatible = "ti,omap-counter32k";
103 reg = <0x4ae04000 0x40>;
104 ti,hwmods = "counter_32k";
105 };
107 dpll_mpu: dpll_mpu {
108 #clock-cells = <0>;
109 compatible = "ti,omap-clock";
110 };
112 omap5_pmx_core: pinmux@4a002840 {
113 compatible = "ti,omap4-padconf", "pinctrl-single";
114 reg = <0x4a002840 0x01b6>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117 pinctrl-single,register-width = <16>;
118 pinctrl-single,function-mask = <0x7fff>;
119 };
120 omap5_pmx_wkup: pinmux@4ae0c840 {
121 compatible = "ti,omap4-padconf", "pinctrl-single";
122 reg = <0x4ae0c840 0x0038>;
123 #address-cells = <1>;
124 #size-cells = <0>;
125 pinctrl-single,register-width = <16>;
126 pinctrl-single,function-mask = <0x7fff>;
127 };
129 sdma: dma-controller@4a056000 {
130 compatible = "ti,omap4430-sdma";
131 reg = <0x4a056000 0x1000>;
132 interrupts = <0 12 0x4>,
133 <0 13 0x4>,
134 <0 14 0x4>,
135 <0 15 0x4>;
136 #dma-cells = <1>;
137 #dma-channels = <32>;
138 #dma-requests = <127>;
139 };
141 gpio1: gpio@4ae10000 {
142 compatible = "ti,omap4-gpio";
143 reg = <0x4ae10000 0x200>;
144 interrupts = <0 29 0x4>;
145 ti,hwmods = "gpio1";
146 ti,gpio-always-on;
147 gpio-controller;
148 #gpio-cells = <2>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
151 };
153 gpio2: gpio@48055000 {
154 compatible = "ti,omap4-gpio";
155 reg = <0x48055000 0x200>;
156 interrupts = <0 30 0x4>;
157 ti,hwmods = "gpio2";
158 gpio-controller;
159 #gpio-cells = <2>;
160 interrupt-controller;
161 #interrupt-cells = <2>;
162 };
164 gpio3: gpio@48057000 {
165 compatible = "ti,omap4-gpio";
166 reg = <0x48057000 0x200>;
167 interrupts = <0 31 0x4>;
168 ti,hwmods = "gpio3";
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 };
175 gpio4: gpio@48059000 {
176 compatible = "ti,omap4-gpio";
177 reg = <0x48059000 0x200>;
178 interrupts = <0 32 0x4>;
179 ti,hwmods = "gpio4";
180 gpio-controller;
181 #gpio-cells = <2>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 };
186 gpio5: gpio@4805b000 {
187 compatible = "ti,omap4-gpio";
188 reg = <0x4805b000 0x200>;
189 interrupts = <0 33 0x4>;
190 ti,hwmods = "gpio5";
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 };
197 gpio6: gpio@4805d000 {
198 compatible = "ti,omap4-gpio";
199 reg = <0x4805d000 0x200>;
200 interrupts = <0 34 0x4>;
201 ti,hwmods = "gpio6";
202 gpio-controller;
203 #gpio-cells = <2>;
204 interrupt-controller;
205 #interrupt-cells = <2>;
206 };
208 gpio7: gpio@48051000 {
209 compatible = "ti,omap4-gpio";
210 reg = <0x48051000 0x200>;
211 interrupts = <0 35 0x4>;
212 ti,hwmods = "gpio7";
213 gpio-controller;
214 #gpio-cells = <2>;
215 interrupt-controller;
216 #interrupt-cells = <2>;
217 };
219 gpio8: gpio@48053000 {
220 compatible = "ti,omap4-gpio";
221 reg = <0x48053000 0x200>;
222 interrupts = <0 121 0x4>;
223 ti,hwmods = "gpio8";
224 gpio-controller;
225 #gpio-cells = <2>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
228 };
230 gpmc: gpmc@50000000 {
231 compatible = "ti,omap4430-gpmc";
232 reg = <0x50000000 0x1000>;
233 #address-cells = <2>;
234 #size-cells = <1>;
235 interrupts = <0 20 0x4>;
236 gpmc,num-cs = <8>;
237 gpmc,num-waitpins = <4>;
238 ti,hwmods = "gpmc";
239 };
241 i2c1: i2c@48070000 {
242 compatible = "ti,omap4-i2c";
243 reg = <0x48070000 0x100>;
244 interrupts = <0 56 0x4>;
245 #address-cells = <1>;
246 #size-cells = <0>;
247 ti,hwmods = "i2c1";
248 };
250 i2c2: i2c@48072000 {
251 compatible = "ti,omap4-i2c";
252 reg = <0x48072000 0x100>;
253 interrupts = <0 57 0x4>;
254 #address-cells = <1>;
255 #size-cells = <0>;
256 ti,hwmods = "i2c2";
257 };
259 i2c3: i2c@48060000 {
260 compatible = "ti,omap4-i2c";
261 reg = <0x48060000 0x100>;
262 interrupts = <0 61 0x4>;
263 #address-cells = <1>;
264 #size-cells = <0>;
265 ti,hwmods = "i2c3";
266 };
268 i2c4: i2c@4807a000 {
269 compatible = "ti,omap4-i2c";
270 reg = <0x4807a000 0x100>;
271 interrupts = <0 62 0x4>;
272 #address-cells = <1>;
273 #size-cells = <0>;
274 ti,hwmods = "i2c4";
275 };
277 i2c5: i2c@4807c000 {
278 compatible = "ti,omap4-i2c";
279 reg = <0x4807c000 0x100>;
280 interrupts = <0 60 0x4>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 ti,hwmods = "i2c5";
284 };
286 mcspi1: spi@48098000 {
287 compatible = "ti,omap4-mcspi";
288 reg = <0x48098000 0x200>;
289 interrupts = <0 65 0x4>;
290 #address-cells = <1>;
291 #size-cells = <0>;
292 ti,hwmods = "mcspi1";
293 ti,spi-num-cs = <4>;
294 dmas = <&sdma 35>,
295 <&sdma 36>,
296 <&sdma 37>,
297 <&sdma 38>,
298 <&sdma 39>,
299 <&sdma 40>,
300 <&sdma 41>,
301 <&sdma 42>;
302 dma-names = "tx0", "rx0", "tx1", "rx1",
303 "tx2", "rx2", "tx3", "rx3";
304 };
306 mcspi2: spi@4809a000 {
307 compatible = "ti,omap4-mcspi";
308 reg = <0x4809a000 0x200>;
309 interrupts = <0 66 0x4>;
310 #address-cells = <1>;
311 #size-cells = <0>;
312 ti,hwmods = "mcspi2";
313 ti,spi-num-cs = <2>;
314 dmas = <&sdma 43>,
315 <&sdma 44>,
316 <&sdma 45>,
317 <&sdma 46>;
318 dma-names = "tx0", "rx0", "tx1", "rx1";
319 };
321 mcspi3: spi@480b8000 {
322 compatible = "ti,omap4-mcspi";
323 reg = <0x480b8000 0x200>;
324 interrupts = <0 91 0x4>;
325 #address-cells = <1>;
326 #size-cells = <0>;
327 ti,hwmods = "mcspi3";
328 ti,spi-num-cs = <2>;
329 dmas = <&sdma 15>, <&sdma 16>;
330 dma-names = "tx0", "rx0";
331 };
333 mcspi4: spi@480ba000 {
334 compatible = "ti,omap4-mcspi";
335 reg = <0x480ba000 0x200>;
336 interrupts = <0 48 0x4>;
337 #address-cells = <1>;
338 #size-cells = <0>;
339 ti,hwmods = "mcspi4";
340 ti,spi-num-cs = <1>;
341 dmas = <&sdma 70>, <&sdma 71>;
342 dma-names = "tx0", "rx0";
343 };
345 uart1: serial@4806a000 {
346 compatible = "ti,omap4-uart";
347 reg = <0x4806a000 0x100>;
348 interrupts = <0 72 0x4>;
349 ti,hwmods = "uart1";
350 clock-frequency = <48000000>;
351 };
353 uart2: serial@4806c000 {
354 compatible = "ti,omap4-uart";
355 reg = <0x4806c000 0x100>;
356 interrupts = <0 73 0x4>;
357 ti,hwmods = "uart2";
358 clock-frequency = <48000000>;
359 };
361 uart3: serial@48020000 {
362 compatible = "ti,omap4-uart";
363 reg = <0x48020000 0x100>;
364 interrupts = <0 74 0x4>;
365 ti,hwmods = "uart3";
366 clock-frequency = <48000000>;
367 };
369 uart4: serial@4806e000 {
370 compatible = "ti,omap4-uart";
371 reg = <0x4806e000 0x100>;
372 interrupts = <0 70 0x4>;
373 ti,hwmods = "uart4";
374 clock-frequency = <48000000>;
375 };
377 uart5: serial@48066000 {
378 compatible = "ti,omap4-uart";
379 reg = <0x48066000 0x100>;
380 interrupts = <0 105 0x4>;
381 ti,hwmods = "uart5";
382 clock-frequency = <48000000>;
383 };
385 uart6: serial@48068000 {
386 compatible = "ti,omap4-uart";
387 reg = <0x48068000 0x100>;
388 interrupts = <0 106 0x4>;
389 ti,hwmods = "uart6";
390 clock-frequency = <48000000>;
391 };
393 mmc1: mmc@4809c000 {
394 compatible = "ti,omap4-hsmmc";
395 reg = <0x4809c000 0x400>;
396 interrupts = <0 83 0x4>;
397 ti,hwmods = "mmc1";
398 ti,dual-volt;
399 ti,needs-special-reset;
400 dmas = <&sdma 61>, <&sdma 62>;
401 dma-names = "tx", "rx";
402 };
404 mmc2: mmc@480b4000 {
405 compatible = "ti,omap4-hsmmc";
406 reg = <0x480b4000 0x400>;
407 interrupts = <0 86 0x4>;
408 ti,hwmods = "mmc2";
409 ti,needs-special-reset;
410 dmas = <&sdma 47>, <&sdma 48>;
411 dma-names = "tx", "rx";
412 };
414 mmc3: mmc@480ad000 {
415 compatible = "ti,omap4-hsmmc";
416 reg = <0x480ad000 0x400>;
417 interrupts = <0 94 0x4>;
418 ti,hwmods = "mmc3";
419 ti,needs-special-reset;
420 dmas = <&sdma 77>, <&sdma 78>;
421 dma-names = "tx", "rx";
422 };
424 mmc4: mmc@480d1000 {
425 compatible = "ti,omap4-hsmmc";
426 reg = <0x480d1000 0x400>;
427 interrupts = <0 96 0x4>;
428 ti,hwmods = "mmc4";
429 ti,needs-special-reset;
430 dmas = <&sdma 57>, <&sdma 58>;
431 dma-names = "tx", "rx";
432 };
434 mmc5: mmc@480d5000 {
435 compatible = "ti,omap4-hsmmc";
436 reg = <0x480d5000 0x400>;
437 interrupts = <0 59 0x4>;
438 ti,hwmods = "mmc5";
439 ti,needs-special-reset;
440 dmas = <&sdma 59>, <&sdma 60>;
441 dma-names = "tx", "rx";
442 };
444 keypad: keypad@4ae1c000 {
445 compatible = "ti,omap4-keypad";
446 reg = <0x4ae1c000 0x400>;
447 ti,hwmods = "kbd";
448 };
450 mcpdm: mcpdm@40132000 {
451 compatible = "ti,omap4-mcpdm";
452 reg = <0x40132000 0x7f>, /* MPU private access */
453 <0x49032000 0x7f>; /* L3 Interconnect */
454 reg-names = "mpu", "dma";
455 interrupts = <0 112 0x4>;
456 ti,hwmods = "mcpdm";
457 };
459 dmic: dmic@4012e000 {
460 compatible = "ti,omap4-dmic";
461 reg = <0x4012e000 0x7f>, /* MPU private access */
462 <0x4902e000 0x7f>; /* L3 Interconnect */
463 reg-names = "mpu", "dma";
464 interrupts = <0 114 0x4>;
465 ti,hwmods = "dmic";
466 };
468 mcbsp1: mcbsp@40122000 {
469 compatible = "ti,omap4-mcbsp";
470 reg = <0x40122000 0xff>, /* MPU private access */
471 <0x49022000 0xff>; /* L3 Interconnect */
472 reg-names = "mpu", "dma";
473 interrupts = <0 17 0x4>;
474 interrupt-names = "common";
475 ti,buffer-size = <128>;
476 ti,hwmods = "mcbsp1";
477 };
479 mcbsp2: mcbsp@40124000 {
480 compatible = "ti,omap4-mcbsp";
481 reg = <0x40124000 0xff>, /* MPU private access */
482 <0x49024000 0xff>; /* L3 Interconnect */
483 reg-names = "mpu", "dma";
484 interrupts = <0 22 0x4>;
485 interrupt-names = "common";
486 ti,buffer-size = <128>;
487 ti,hwmods = "mcbsp2";
488 };
490 mcbsp3: mcbsp@40126000 {
491 compatible = "ti,omap4-mcbsp";
492 reg = <0x40126000 0xff>, /* MPU private access */
493 <0x49026000 0xff>; /* L3 Interconnect */
494 reg-names = "mpu", "dma";
495 interrupts = <0 23 0x4>;
496 interrupt-names = "common";
497 ti,buffer-size = <128>;
498 ti,hwmods = "mcbsp3";
499 };
501 timer1: timer@4ae18000 {
502 compatible = "ti,omap2-timer";
503 reg = <0x4ae18000 0x80>;
504 interrupts = <0 37 0x4>;
505 ti,hwmods = "timer1";
506 ti,timer-alwon;
507 };
509 timer2: timer@48032000 {
510 compatible = "ti,omap2-timer";
511 reg = <0x48032000 0x80>;
512 interrupts = <0 38 0x4>;
513 ti,hwmods = "timer2";
514 };
516 timer3: timer@48034000 {
517 compatible = "ti,omap2-timer";
518 reg = <0x48034000 0x80>;
519 interrupts = <0 39 0x4>;
520 ti,hwmods = "timer3";
521 };
523 timer4: timer@48036000 {
524 compatible = "ti,omap2-timer";
525 reg = <0x48036000 0x80>;
526 interrupts = <0 40 0x4>;
527 ti,hwmods = "timer4";
528 };
530 timer5: timer@40138000 {
531 compatible = "ti,omap2-timer";
532 reg = <0x40138000 0x80>,
533 <0x49038000 0x80>;
534 interrupts = <0 41 0x4>;
535 ti,hwmods = "timer5";
536 ti,timer-dsp;
537 };
539 timer6: timer@4013a000 {
540 compatible = "ti,omap2-timer";
541 reg = <0x4013a000 0x80>,
542 <0x4903a000 0x80>;
543 interrupts = <0 42 0x4>;
544 ti,hwmods = "timer6";
545 ti,timer-dsp;
546 ti,timer-pwm;
547 };
549 timer7: timer@4013c000 {
550 compatible = "ti,omap2-timer";
551 reg = <0x4013c000 0x80>,
552 <0x4903c000 0x80>;
553 interrupts = <0 43 0x4>;
554 ti,hwmods = "timer7";
555 ti,timer-dsp;
556 };
558 timer8: timer@4013e000 {
559 compatible = "ti,omap2-timer";
560 reg = <0x4013e000 0x80>,
561 <0x4903e000 0x80>;
562 interrupts = <0 44 0x4>;
563 ti,hwmods = "timer8";
564 ti,timer-dsp;
565 ti,timer-pwm;
566 };
568 timer9: timer@4803e000 {
569 compatible = "ti,omap2-timer";
570 reg = <0x4803e000 0x80>;
571 interrupts = <0 45 0x4>;
572 ti,hwmods = "timer9";
573 };
575 timer10: timer@48086000 {
576 compatible = "ti,omap2-timer";
577 reg = <0x48086000 0x80>;
578 interrupts = <0 46 0x4>;
579 ti,hwmods = "timer10";
580 };
582 timer11: timer@48088000 {
583 compatible = "ti,omap2-timer";
584 reg = <0x48088000 0x80>;
585 interrupts = <0 47 0x4>;
586 ti,hwmods = "timer11";
587 ti,timer-pwm;
588 };
590 emif1: emif@0x4c000000 {
591 compatible = "ti,emif-4d5";
592 ti,hwmods = "emif1";
593 phy-type = <2>; /* DDR PHY type: Intelli PHY */
594 reg = <0x4c000000 0x400>;
595 interrupts = <0 110 0x4>;
596 hw-caps-read-idle-ctrl;
597 hw-caps-ll-interface;
598 hw-caps-temp-alert;
599 };
601 emif2: emif@0x4d000000 {
602 compatible = "ti,emif-4d5";
603 ti,hwmods = "emif2";
604 phy-type = <2>; /* DDR PHY type: Intelli PHY */
605 reg = <0x4d000000 0x400>;
606 interrupts = <0 111 0x4>;
607 hw-caps-read-idle-ctrl;
608 hw-caps-ll-interface;
609 hw-caps-temp-alert;
610 };
612 wdt2: wdt@4ae14000 {
613 compatible = "ti,omap5-wdt", "ti,omap4-wdt";
614 reg = <0x4ae14000 0x80>;
615 interrupts = <0 80 0x4>;
616 ti,hwmods = "wd_timer2";
617 };
618 bandgap {
619 reg = <0x4a0021e0 0xc
620 0x4a00232c 0xc
621 0x4a002380 0x2c
622 0x4a0023C0 0x3c>;
623 interrupts = <0 126 4>; /* talert */
624 compatible = "ti,omap5430-bandgap";
625 };
626 };
627 };