1 /*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/pinctrl/omap.h>
14 #include "skeleton.dtsi"
16 / {
17 #address-cells = <1>;
18 #size-cells = <1>;
20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
23 aliases {
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 rproc0 = &dsp;
36 rproc1 = &ipu;
37 };
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
43 cpu0: cpu@0 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a15";
46 reg = <0x0>;
48 operating-points = <
49 /* kHz uV */
50 1000000 1060000
51 1500000 1250000
52 >;
54 clocks = <&dpll_mpu_ck>;
55 clock-names = "cpu";
57 clock-latency = <300000>; /* From omap-cpufreq driver */
59 /* cooling options */
60 cooling-min-level = <0>;
61 cooling-max-level = <2>;
62 #cooling-cells = <2>; /* min followed by max */
63 };
64 cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <0x1>;
68 };
69 };
71 thermal-zones {
72 #include "omap5-cpu-thermal.dtsi"
73 #include "omap5-gpu-thermal.dtsi"
74 #include "omap5-core-thermal.dtsi"
75 };
77 timer {
78 compatible = "arm,armv7-timer";
79 /* PPI secure/nonsecure IRQ */
80 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
84 };
86 pmu {
87 compatible = "arm,cortex-a15-pmu";
88 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
90 };
92 gic: interrupt-controller@48211000 {
93 compatible = "arm,cortex-a15-gic";
94 interrupt-controller;
95 #interrupt-cells = <3>;
96 reg = <0x48211000 0x1000>,
97 <0x48212000 0x1000>,
98 <0x48214000 0x2000>,
99 <0x48216000 0x2000>;
100 };
102 /*
103 * The soc node represents the soc top level view. It is uses for IPs
104 * that are not memory mapped in the MPU view or for the MPU itself.
105 */
106 soc {
107 compatible = "ti,omap-infra";
108 mpu {
109 compatible = "ti,omap5-mpu";
110 ti,hwmods = "mpu";
111 };
112 };
114 /*
115 * XXX: Use a flat representation of the OMAP3 interconnect.
116 * The real OMAP interconnect network is quite complex.
117 * Since that will not bring real advantage to represent that in DT for
118 * the moment, just use a fake OCP bus entry to represent the whole bus
119 * hierarchy.
120 */
121 ocp {
122 compatible = "ti,omap5-l3-noc", "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges;
126 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
127 reg = <0x44000000 0x2000>,
128 <0x44800000 0x3000>,
129 <0x45000000 0x4000>;
130 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
133 prm: prm@4ae06000 {
134 compatible = "ti,omap5-prm";
135 reg = <0x4ae06000 0x3000>;
136 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
138 prm_clocks: clocks {
139 #address-cells = <1>;
140 #size-cells = <0>;
141 };
143 prm_clockdomains: clockdomains {
144 };
145 };
147 cm_core_aon: cm_core_aon@4a004000 {
148 compatible = "ti,omap5-cm-core-aon";
149 reg = <0x4a004000 0x2000>;
151 cm_core_aon_clocks: clocks {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 };
156 cm_core_aon_clockdomains: clockdomains {
157 };
158 };
160 scrm: scrm@4ae0a000 {
161 compatible = "ti,omap5-scrm";
162 reg = <0x4ae0a000 0x2000>;
164 scrm_clocks: clocks {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 };
169 scrm_clockdomains: clockdomains {
170 };
171 };
173 cm_core: cm_core@4a008000 {
174 compatible = "ti,omap5-cm-core";
175 reg = <0x4a008000 0x3000>;
177 cm_core_clocks: clocks {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 };
182 cm_core_clockdomains: clockdomains {
183 };
184 };
186 counter32k: counter@4ae04000 {
187 compatible = "ti,omap-counter32k";
188 reg = <0x4ae04000 0x40>;
189 ti,hwmods = "counter_32k";
190 };
192 omap5_pmx_core: pinmux@4a002840 {
193 compatible = "ti,omap5-padconf", "pinctrl-single";
194 reg = <0x4a002840 0x01b6>;
195 #address-cells = <1>;
196 #size-cells = <0>;
197 #interrupt-cells = <1>;
198 interrupt-controller;
199 pinctrl-single,register-width = <16>;
200 pinctrl-single,function-mask = <0x7fff>;
201 };
202 omap5_pmx_wkup: pinmux@4ae0c840 {
203 compatible = "ti,omap5-padconf", "pinctrl-single";
204 reg = <0x4ae0c840 0x0038>;
205 #address-cells = <1>;
206 #size-cells = <0>;
207 #interrupt-cells = <1>;
208 interrupt-controller;
209 pinctrl-single,register-width = <16>;
210 pinctrl-single,function-mask = <0x7fff>;
211 };
213 omap5_padconf_global: tisyscon@4a002da0 {
214 compatible = "syscon";
215 reg = <0x4A002da0 0xec>;
216 };
218 pbias_regulator: pbias_regulator {
219 compatible = "ti,pbias-omap";
220 reg = <0x60 0x4>;
221 syscon = <&omap5_padconf_global>;
222 pbias_mmc_reg: pbias_mmc_omap5 {
223 regulator-name = "pbias_mmc_omap5";
224 regulator-min-microvolt = <1800000>;
225 regulator-max-microvolt = <3000000>;
226 };
227 };
229 sdma: dma-controller@4a056000 {
230 compatible = "ti,omap4430-sdma";
231 reg = <0x4a056000 0x1000>;
232 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
236 #dma-cells = <1>;
237 #dma-channels = <32>;
238 #dma-requests = <127>;
239 };
241 gpio1: gpio@4ae10000 {
242 compatible = "ti,omap4-gpio";
243 reg = <0x4ae10000 0x200>;
244 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
245 ti,hwmods = "gpio1";
246 ti,gpio-always-on;
247 gpio-controller;
248 #gpio-cells = <2>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
253 gpio2: gpio@48055000 {
254 compatible = "ti,omap4-gpio";
255 reg = <0x48055000 0x200>;
256 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
257 ti,hwmods = "gpio2";
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-controller;
261 #interrupt-cells = <2>;
262 };
264 gpio3: gpio@48057000 {
265 compatible = "ti,omap4-gpio";
266 reg = <0x48057000 0x200>;
267 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
268 ti,hwmods = "gpio3";
269 gpio-controller;
270 #gpio-cells = <2>;
271 interrupt-controller;
272 #interrupt-cells = <2>;
273 };
275 gpio4: gpio@48059000 {
276 compatible = "ti,omap4-gpio";
277 reg = <0x48059000 0x200>;
278 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
279 ti,hwmods = "gpio4";
280 gpio-controller;
281 #gpio-cells = <2>;
282 interrupt-controller;
283 #interrupt-cells = <2>;
284 };
286 gpio5: gpio@4805b000 {
287 compatible = "ti,omap4-gpio";
288 reg = <0x4805b000 0x200>;
289 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
290 ti,hwmods = "gpio5";
291 gpio-controller;
292 #gpio-cells = <2>;
293 interrupt-controller;
294 #interrupt-cells = <2>;
295 };
297 gpio6: gpio@4805d000 {
298 compatible = "ti,omap4-gpio";
299 reg = <0x4805d000 0x200>;
300 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
301 ti,hwmods = "gpio6";
302 gpio-controller;
303 #gpio-cells = <2>;
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 };
308 gpio7: gpio@48051000 {
309 compatible = "ti,omap4-gpio";
310 reg = <0x48051000 0x200>;
311 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
312 ti,hwmods = "gpio7";
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 };
319 gpio8: gpio@48053000 {
320 compatible = "ti,omap4-gpio";
321 reg = <0x48053000 0x200>;
322 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
323 ti,hwmods = "gpio8";
324 gpio-controller;
325 #gpio-cells = <2>;
326 interrupt-controller;
327 #interrupt-cells = <2>;
328 };
330 gpmc: gpmc@50000000 {
331 compatible = "ti,omap4430-gpmc";
332 reg = <0x50000000 0x1000>;
333 #address-cells = <2>;
334 #size-cells = <1>;
335 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
336 gpmc,num-cs = <8>;
337 gpmc,num-waitpins = <4>;
338 ti,hwmods = "gpmc";
339 clocks = <&l3_iclk_div>;
340 clock-names = "fck";
341 };
343 i2c1: i2c@48070000 {
344 compatible = "ti,omap4-i2c";
345 reg = <0x48070000 0x100>;
346 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
347 #address-cells = <1>;
348 #size-cells = <0>;
349 ti,hwmods = "i2c1";
350 };
352 i2c2: i2c@48072000 {
353 compatible = "ti,omap4-i2c";
354 reg = <0x48072000 0x100>;
355 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
356 #address-cells = <1>;
357 #size-cells = <0>;
358 ti,hwmods = "i2c2";
359 };
361 i2c3: i2c@48060000 {
362 compatible = "ti,omap4-i2c";
363 reg = <0x48060000 0x100>;
364 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
365 #address-cells = <1>;
366 #size-cells = <0>;
367 ti,hwmods = "i2c3";
368 };
370 i2c4: i2c@4807a000 {
371 compatible = "ti,omap4-i2c";
372 reg = <0x4807a000 0x100>;
373 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
374 #address-cells = <1>;
375 #size-cells = <0>;
376 ti,hwmods = "i2c4";
377 };
379 i2c5: i2c@4807c000 {
380 compatible = "ti,omap4-i2c";
381 reg = <0x4807c000 0x100>;
382 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
383 #address-cells = <1>;
384 #size-cells = <0>;
385 ti,hwmods = "i2c5";
386 };
388 hwspinlock: spinlock@4a0f6000 {
389 compatible = "ti,omap4-hwspinlock";
390 reg = <0x4a0f6000 0x1000>;
391 ti,hwmods = "spinlock";
392 #hwlock-cells = <1>;
393 };
395 mcspi1: spi@48098000 {
396 compatible = "ti,omap4-mcspi";
397 reg = <0x48098000 0x200>;
398 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
399 #address-cells = <1>;
400 #size-cells = <0>;
401 ti,hwmods = "mcspi1";
402 ti,spi-num-cs = <4>;
403 dmas = <&sdma 35>,
404 <&sdma 36>,
405 <&sdma 37>,
406 <&sdma 38>,
407 <&sdma 39>,
408 <&sdma 40>,
409 <&sdma 41>,
410 <&sdma 42>;
411 dma-names = "tx0", "rx0", "tx1", "rx1",
412 "tx2", "rx2", "tx3", "rx3";
413 };
415 mcspi2: spi@4809a000 {
416 compatible = "ti,omap4-mcspi";
417 reg = <0x4809a000 0x200>;
418 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
419 #address-cells = <1>;
420 #size-cells = <0>;
421 ti,hwmods = "mcspi2";
422 ti,spi-num-cs = <2>;
423 dmas = <&sdma 43>,
424 <&sdma 44>,
425 <&sdma 45>,
426 <&sdma 46>;
427 dma-names = "tx0", "rx0", "tx1", "rx1";
428 };
430 mcspi3: spi@480b8000 {
431 compatible = "ti,omap4-mcspi";
432 reg = <0x480b8000 0x200>;
433 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
434 #address-cells = <1>;
435 #size-cells = <0>;
436 ti,hwmods = "mcspi3";
437 ti,spi-num-cs = <2>;
438 dmas = <&sdma 15>, <&sdma 16>;
439 dma-names = "tx0", "rx0";
440 };
442 mcspi4: spi@480ba000 {
443 compatible = "ti,omap4-mcspi";
444 reg = <0x480ba000 0x200>;
445 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
446 #address-cells = <1>;
447 #size-cells = <0>;
448 ti,hwmods = "mcspi4";
449 ti,spi-num-cs = <1>;
450 dmas = <&sdma 70>, <&sdma 71>;
451 dma-names = "tx0", "rx0";
452 };
454 uart1: serial@4806a000 {
455 compatible = "ti,omap4-uart";
456 reg = <0x4806a000 0x100>;
457 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
458 ti,hwmods = "uart1";
459 clock-frequency = <48000000>;
460 };
462 uart2: serial@4806c000 {
463 compatible = "ti,omap4-uart";
464 reg = <0x4806c000 0x100>;
465 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
466 ti,hwmods = "uart2";
467 clock-frequency = <48000000>;
468 };
470 uart3: serial@48020000 {
471 compatible = "ti,omap4-uart";
472 reg = <0x48020000 0x100>;
473 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
474 ti,hwmods = "uart3";
475 clock-frequency = <48000000>;
476 };
478 uart4: serial@4806e000 {
479 compatible = "ti,omap4-uart";
480 reg = <0x4806e000 0x100>;
481 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
482 ti,hwmods = "uart4";
483 clock-frequency = <48000000>;
484 };
486 uart5: serial@48066000 {
487 compatible = "ti,omap4-uart";
488 reg = <0x48066000 0x100>;
489 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
490 ti,hwmods = "uart5";
491 clock-frequency = <48000000>;
492 };
494 uart6: serial@48068000 {
495 compatible = "ti,omap4-uart";
496 reg = <0x48068000 0x100>;
497 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
498 ti,hwmods = "uart6";
499 clock-frequency = <48000000>;
500 };
502 mmc1: mmc@4809c000 {
503 compatible = "ti,omap4-hsmmc";
504 reg = <0x4809c000 0x400>;
505 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
506 ti,hwmods = "mmc1";
507 ti,dual-volt;
508 ti,needs-special-reset;
509 dmas = <&sdma 61>, <&sdma 62>;
510 dma-names = "tx", "rx";
511 pbias-supply = <&pbias_mmc_reg>;
512 };
514 mmc2: mmc@480b4000 {
515 compatible = "ti,omap4-hsmmc";
516 reg = <0x480b4000 0x400>;
517 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
518 ti,hwmods = "mmc2";
519 ti,needs-special-reset;
520 dmas = <&sdma 47>, <&sdma 48>;
521 dma-names = "tx", "rx";
522 };
524 mmc3: mmc@480ad000 {
525 compatible = "ti,omap4-hsmmc";
526 reg = <0x480ad000 0x400>;
527 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
528 ti,hwmods = "mmc3";
529 ti,needs-special-reset;
530 dmas = <&sdma 77>, <&sdma 78>;
531 dma-names = "tx", "rx";
532 };
534 mmc4: mmc@480d1000 {
535 compatible = "ti,omap4-hsmmc";
536 reg = <0x480d1000 0x400>;
537 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
538 ti,hwmods = "mmc4";
539 ti,needs-special-reset;
540 dmas = <&sdma 57>, <&sdma 58>;
541 dma-names = "tx", "rx";
542 };
544 mmc5: mmc@480d5000 {
545 compatible = "ti,omap4-hsmmc";
546 reg = <0x480d5000 0x400>;
547 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
548 ti,hwmods = "mmc5";
549 ti,needs-special-reset;
550 dmas = <&sdma 59>, <&sdma 60>;
551 dma-names = "tx", "rx";
552 };
554 mmu_dsp: mmu@4a066000 {
555 compatible = "ti,omap4-iommu";
556 reg = <0x4a066000 0x100>;
557 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
558 ti,hwmods = "mmu_dsp";
559 };
561 mmu_ipu: mmu@55082000 {
562 compatible = "ti,omap4-iommu";
563 reg = <0x55082000 0x100>;
564 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
565 ti,hwmods = "mmu_ipu";
566 ti,iommu-bus-err-back;
567 };
569 keypad: keypad@4ae1c000 {
570 compatible = "ti,omap4-keypad";
571 reg = <0x4ae1c000 0x400>;
572 ti,hwmods = "kbd";
573 };
575 mcpdm: mcpdm@40132000 {
576 compatible = "ti,omap4-mcpdm";
577 reg = <0x40132000 0x7f>, /* MPU private access */
578 <0x49032000 0x7f>; /* L3 Interconnect */
579 reg-names = "mpu", "dma";
580 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
581 ti,hwmods = "mcpdm";
582 dmas = <&sdma 65>,
583 <&sdma 66>;
584 dma-names = "up_link", "dn_link";
585 status = "disabled";
586 };
588 dmic: dmic@4012e000 {
589 compatible = "ti,omap4-dmic";
590 reg = <0x4012e000 0x7f>, /* MPU private access */
591 <0x4902e000 0x7f>; /* L3 Interconnect */
592 reg-names = "mpu", "dma";
593 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
594 ti,hwmods = "dmic";
595 dmas = <&sdma 67>;
596 dma-names = "up_link";
597 status = "disabled";
598 };
600 mcbsp1: mcbsp@40122000 {
601 compatible = "ti,omap4-mcbsp";
602 reg = <0x40122000 0xff>, /* MPU private access */
603 <0x49022000 0xff>; /* L3 Interconnect */
604 reg-names = "mpu", "dma";
605 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
606 interrupt-names = "common";
607 ti,buffer-size = <128>;
608 ti,hwmods = "mcbsp1";
609 dmas = <&sdma 33>,
610 <&sdma 34>;
611 dma-names = "tx", "rx";
612 status = "disabled";
613 };
615 mcbsp2: mcbsp@40124000 {
616 compatible = "ti,omap4-mcbsp";
617 reg = <0x40124000 0xff>, /* MPU private access */
618 <0x49024000 0xff>; /* L3 Interconnect */
619 reg-names = "mpu", "dma";
620 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
621 interrupt-names = "common";
622 ti,buffer-size = <128>;
623 ti,hwmods = "mcbsp2";
624 dmas = <&sdma 17>,
625 <&sdma 18>;
626 dma-names = "tx", "rx";
627 status = "disabled";
628 };
630 mcbsp3: mcbsp@40126000 {
631 compatible = "ti,omap4-mcbsp";
632 reg = <0x40126000 0xff>, /* MPU private access */
633 <0x49026000 0xff>; /* L3 Interconnect */
634 reg-names = "mpu", "dma";
635 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
636 interrupt-names = "common";
637 ti,buffer-size = <128>;
638 ti,hwmods = "mcbsp3";
639 dmas = <&sdma 19>,
640 <&sdma 20>;
641 dma-names = "tx", "rx";
642 status = "disabled";
643 };
645 mailbox: mailbox@4a0f4000 {
646 compatible = "ti,omap4-mailbox";
647 reg = <0x4a0f4000 0x200>;
648 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
649 ti,hwmods = "mailbox";
650 #mbox-cells = <1>;
651 ti,mbox-num-users = <3>;
652 ti,mbox-num-fifos = <8>;
653 mbox_ipu: mbox_ipu {
654 ti,mbox-tx = <0 0 0>;
655 ti,mbox-rx = <1 0 0>;
656 };
657 mbox_dsp: mbox_dsp {
658 ti,mbox-tx = <3 0 0>;
659 ti,mbox-rx = <2 0 0>;
660 };
661 };
663 timer1: timer@4ae18000 {
664 compatible = "ti,omap5430-timer";
665 reg = <0x4ae18000 0x80>;
666 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
667 ti,hwmods = "timer1";
668 ti,timer-alwon;
669 };
671 timer2: timer@48032000 {
672 compatible = "ti,omap5430-timer";
673 reg = <0x48032000 0x80>;
674 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
675 ti,hwmods = "timer2";
676 };
678 timer3: timer@48034000 {
679 compatible = "ti,omap5430-timer";
680 reg = <0x48034000 0x80>;
681 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
682 ti,hwmods = "timer3";
683 };
685 timer4: timer@48036000 {
686 compatible = "ti,omap5430-timer";
687 reg = <0x48036000 0x80>;
688 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
689 ti,hwmods = "timer4";
690 };
692 timer5: timer@40138000 {
693 compatible = "ti,omap5430-timer";
694 reg = <0x40138000 0x80>,
695 <0x49038000 0x80>;
696 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
697 ti,hwmods = "timer5";
698 ti,timer-dsp;
699 ti,timer-pwm;
700 };
702 timer6: timer@4013a000 {
703 compatible = "ti,omap5430-timer";
704 reg = <0x4013a000 0x80>,
705 <0x4903a000 0x80>;
706 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
707 ti,hwmods = "timer6";
708 ti,timer-dsp;
709 ti,timer-pwm;
710 };
712 timer7: timer@4013c000 {
713 compatible = "ti,omap5430-timer";
714 reg = <0x4013c000 0x80>,
715 <0x4903c000 0x80>;
716 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
717 ti,hwmods = "timer7";
718 ti,timer-dsp;
719 };
721 timer8: timer@4013e000 {
722 compatible = "ti,omap5430-timer";
723 reg = <0x4013e000 0x80>,
724 <0x4903e000 0x80>;
725 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
726 ti,hwmods = "timer8";
727 ti,timer-dsp;
728 ti,timer-pwm;
729 };
731 timer9: timer@4803e000 {
732 compatible = "ti,omap5430-timer";
733 reg = <0x4803e000 0x80>;
734 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
735 ti,hwmods = "timer9";
736 ti,timer-pwm;
737 };
739 timer10: timer@48086000 {
740 compatible = "ti,omap5430-timer";
741 reg = <0x48086000 0x80>;
742 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
743 ti,hwmods = "timer10";
744 ti,timer-pwm;
745 };
747 timer11: timer@48088000 {
748 compatible = "ti,omap5430-timer";
749 reg = <0x48088000 0x80>;
750 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
751 ti,hwmods = "timer11";
752 ti,timer-pwm;
753 };
755 wdt2: wdt@4ae14000 {
756 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
757 reg = <0x4ae14000 0x80>;
758 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
759 ti,hwmods = "wd_timer2";
760 };
762 dsp: dsp {
763 compatible = "ti,omap5-rproc-dsp";
764 ti,hwmods = "dsp";
765 iommus = <&mmu_dsp>;
766 mboxes = <&mailbox &mbox_dsp>;
767 ti,rproc-standby-info = <0x4a004420>;
768 status = "disabled";
769 };
771 ipu: ipu {
772 compatible = "ti,omap5-rproc-ipu";
773 ti,hwmods = "ipu";
774 iommus = <&mmu_ipu>;
775 mboxes = <&mailbox &mbox_ipu>;
776 ti,rproc-standby-info = <0x4a008920>;
777 status = "disabled";
778 };
780 dmm@4e000000 {
781 compatible = "ti,omap5-dmm";
782 reg = <0x4e000000 0x800>;
783 interrupts = <0 113 0x4>;
784 ti,hwmods = "dmm";
785 };
787 emif1: emif@4c000000 {
788 compatible = "ti,emif-4d5";
789 ti,hwmods = "emif1";
790 ti,no-idle-on-init;
791 phy-type = <2>; /* DDR PHY type: Intelli PHY */
792 reg = <0x4c000000 0x400>;
793 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
794 hw-caps-read-idle-ctrl;
795 hw-caps-ll-interface;
796 hw-caps-temp-alert;
797 };
799 emif2: emif@4d000000 {
800 compatible = "ti,emif-4d5";
801 ti,hwmods = "emif2";
802 ti,no-idle-on-init;
803 phy-type = <2>; /* DDR PHY type: Intelli PHY */
804 reg = <0x4d000000 0x400>;
805 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
806 hw-caps-read-idle-ctrl;
807 hw-caps-ll-interface;
808 hw-caps-temp-alert;
809 };
811 omap_control_usb2phy: control-phy@4a002300 {
812 compatible = "ti,control-phy-usb2";
813 reg = <0x4a002300 0x4>;
814 reg-names = "power";
815 };
817 omap_control_usb3phy: control-phy@4a002370 {
818 compatible = "ti,control-phy-pipe3";
819 reg = <0x4a002370 0x4>;
820 reg-names = "power";
821 };
823 usb3: omap_dwc3@4a020000 {
824 compatible = "ti,dwc3";
825 ti,hwmods = "usb_otg_ss";
826 reg = <0x4a020000 0x10000>;
827 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
828 #address-cells = <1>;
829 #size-cells = <1>;
830 utmi-mode = <2>;
831 ranges;
832 dwc3@4a030000 {
833 compatible = "snps,dwc3";
834 reg = <0x4a030000 0x10000>;
835 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
837 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
838 interrupt-names = "peripheral",
839 "host",
840 "otg";
841 phys = <&usb2_phy>, <&usb3_phy>;
842 phy-names = "usb2-phy", "usb3-phy";
843 dr_mode = "peripheral";
844 tx-fifo-resize;
845 };
846 };
848 ocp2scp@4a080000 {
849 compatible = "ti,omap-ocp2scp";
850 #address-cells = <1>;
851 #size-cells = <1>;
852 reg = <0x4a080000 0x20>;
853 ranges;
854 ti,hwmods = "ocp2scp1";
855 usb2_phy: usb2phy@4a084000 {
856 compatible = "ti,omap-usb2";
857 reg = <0x4a084000 0x7c>;
858 ctrl-module = <&omap_control_usb2phy>;
859 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
860 clock-names = "wkupclk", "refclk";
861 #phy-cells = <0>;
862 };
864 usb3_phy: usb3phy@4a084400 {
865 compatible = "ti,omap-usb3";
866 reg = <0x4a084400 0x80>,
867 <0x4a084800 0x64>,
868 <0x4a084c00 0x40>;
869 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
870 ctrl-module = <&omap_control_usb3phy>;
871 clocks = <&usb_phy_cm_clk32k>,
872 <&sys_clkin>,
873 <&usb_otg_ss_refclk960m>;
874 clock-names = "wkupclk",
875 "sysclk",
876 "refclk";
877 #phy-cells = <0>;
878 };
879 };
881 usbhstll: usbhstll@4a062000 {
882 compatible = "ti,usbhs-tll";
883 reg = <0x4a062000 0x1000>;
884 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
885 ti,hwmods = "usb_tll_hs";
886 };
888 usbhshost: usbhshost@4a064000 {
889 compatible = "ti,usbhs-host";
890 reg = <0x4a064000 0x800>;
891 ti,hwmods = "usb_host_hs";
892 #address-cells = <1>;
893 #size-cells = <1>;
894 ranges;
895 clocks = <&l3init_60m_fclk>,
896 <&xclk60mhsp1_ck>,
897 <&xclk60mhsp2_ck>;
898 clock-names = "refclk_60m_int",
899 "refclk_60m_ext_p1",
900 "refclk_60m_ext_p2";
902 usbhsohci: ohci@4a064800 {
903 compatible = "ti,ohci-omap3";
904 reg = <0x4a064800 0x400>;
905 interrupt-parent = <&gic>;
906 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
907 };
909 usbhsehci: ehci@4a064c00 {
910 compatible = "ti,ehci-omap";
911 reg = <0x4a064c00 0x400>;
912 interrupt-parent = <&gic>;
913 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
914 };
915 };
917 bandgap: bandgap@4a0021e0 {
918 reg = <0x4a0021e0 0xc
919 0x4a00232c 0xc
920 0x4a002380 0x2c
921 0x4a0023C0 0x3c>;
922 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
923 compatible = "ti,omap5430-bandgap";
925 #thermal-sensor-cells = <1>;
926 };
928 omap_control_sata: control-phy@4a002374 {
929 compatible = "ti,control-phy-pipe3";
930 reg = <0x4a002374 0x4>;
931 reg-names = "power";
932 clocks = <&sys_clkin>;
933 clock-names = "sysclk";
934 };
936 /* OCP2SCP3 */
937 ocp2scp@4a090000 {
938 compatible = "ti,omap-ocp2scp";
939 #address-cells = <1>;
940 #size-cells = <1>;
941 reg = <0x4a090000 0x20>;
942 ranges;
943 ti,hwmods = "ocp2scp3";
944 sata_phy: phy@4a096000 {
945 compatible = "ti,phy-pipe3-sata";
946 reg = <0x4A096000 0x80>, /* phy_rx */
947 <0x4A096400 0x64>, /* phy_tx */
948 <0x4A096800 0x40>; /* pll_ctrl */
949 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
950 ctrl-module = <&omap_control_sata>;
951 clocks = <&sys_clkin>, <&sata_ref_clk>;
952 clock-names = "sysclk", "refclk";
953 #phy-cells = <0>;
954 };
955 };
957 sata: sata@4a141100 {
958 compatible = "snps,dwc-ahci";
959 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
960 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
961 phys = <&sata_phy>;
962 phy-names = "sata-phy";
963 clocks = <&sata_ref_clk>;
964 ti,hwmods = "sata";
965 };
967 dss: dss@58000000 {
968 compatible = "ti,omap5-dss";
969 reg = <0x58000000 0x80>;
970 status = "disabled";
971 ti,hwmods = "dss_core";
972 clocks = <&dss_dss_clk>;
973 clock-names = "fck";
974 #address-cells = <1>;
975 #size-cells = <1>;
976 ranges;
978 dispc@58001000 {
979 compatible = "ti,omap5-dispc";
980 reg = <0x58001000 0x1000>;
981 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
982 ti,hwmods = "dss_dispc";
983 clocks = <&dss_dss_clk>;
984 clock-names = "fck";
985 };
987 dsi1: encoder@58004000 {
988 compatible = "ti,omap5-dsi";
989 reg = <0x58004000 0x200>,
990 <0x58004200 0x40>,
991 <0x58004300 0x40>;
992 reg-names = "proto", "phy", "pll";
993 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
994 status = "disabled";
995 ti,hwmods = "dss_dsi1";
996 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
997 clock-names = "fck", "sys_clk";
998 };
1000 dsi2: encoder@58005000 {
1001 compatible = "ti,omap5-dsi";
1002 reg = <0x58009000 0x200>,
1003 <0x58009200 0x40>,
1004 <0x58009300 0x40>;
1005 reg-names = "proto", "phy", "pll";
1006 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1007 status = "disabled";
1008 ti,hwmods = "dss_dsi2";
1009 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1010 clock-names = "fck", "sys_clk";
1011 };
1013 hdmi: encoder@58060000 {
1014 compatible = "ti,omap5-hdmi";
1015 reg = <0x58040000 0x200>,
1016 <0x58040200 0x80>,
1017 <0x58040300 0x80>,
1018 <0x58060000 0x19000>;
1019 reg-names = "wp", "pll", "phy", "core";
1020 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1021 status = "disabled";
1022 ti,hwmods = "dss_hdmi";
1023 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1024 clock-names = "fck", "sys_clk";
1025 dmas = <&sdma 76>;
1026 dma-names = "audio_tx";
1027 };
1028 };
1030 abb_mpu: regulator-abb-mpu {
1031 compatible = "ti,abb-v2";
1032 regulator-name = "abb_mpu";
1033 #address-cells = <0>;
1034 #size-cells = <0>;
1035 clocks = <&sys_clkin>;
1036 ti,settling-time = <50>;
1037 ti,clock-cycles = <16>;
1039 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1040 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1041 reg-names = "base-address", "int-address",
1042 "efuse-address", "ldo-address";
1043 ti,tranxdone-status-mask = <0x80>;
1044 /* LDOVBBMPU_MUX_CTRL */
1045 ti,ldovbb-override-mask = <0x400>;
1046 /* LDOVBBMPU_VSET_OUT */
1047 ti,ldovbb-vset-mask = <0x1F>;
1049 /*
1050 * NOTE: only FBB mode used but actual vset will
1051 * determine final biasing
1052 */
1053 ti,abb_info = <
1054 /*uV ABB efuse rbb_m fbb_m vset_m*/
1055 1060000 0 0x0 0 0x02000000 0x01F00000
1056 1250000 0 0x4 0 0x02000000 0x01F00000
1057 >;
1058 };
1060 abb_mm: regulator-abb-mm {
1061 compatible = "ti,abb-v2";
1062 regulator-name = "abb_mm";
1063 #address-cells = <0>;
1064 #size-cells = <0>;
1065 clocks = <&sys_clkin>;
1066 ti,settling-time = <50>;
1067 ti,clock-cycles = <16>;
1069 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1070 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1071 reg-names = "base-address", "int-address",
1072 "efuse-address", "ldo-address";
1073 ti,tranxdone-status-mask = <0x80000000>;
1074 /* LDOVBBMM_MUX_CTRL */
1075 ti,ldovbb-override-mask = <0x400>;
1076 /* LDOVBBMM_VSET_OUT */
1077 ti,ldovbb-vset-mask = <0x1F>;
1079 /*
1080 * NOTE: only FBB mode used but actual vset will
1081 * determine final biasing
1082 */
1083 ti,abb_info = <
1084 /*uV ABB efuse rbb_m fbb_m vset_m*/
1085 1025000 0 0x0 0 0x02000000 0x01F00000
1086 1120000 0 0x4 0 0x02000000 0x01F00000
1087 >;
1088 };
1090 voltdm_mpu: voltdm@4a0021c4 {
1091 compatible = "ti,omap5-voltdm";
1092 #voltdm-cells = <0>;
1093 vbb-supply = <&abb_mpu>;
1094 reg = <0x4a0021c4 0x8>;
1095 ti,efuse-settings = <
1096 /* uV offset */
1097 1060000 0x0
1098 1250000 0x4
1099 >;
1100 };
1102 voltdm_mm: voltdm@4a0021a4 {
1103 compatible = "ti,omap5-voltdm";
1104 #voltdm-cells = <0>;
1105 vbb-supply = <&abb_mm>;
1106 reg = <0x4a0021a4 0x8>;
1107 ti,efuse-settings = <
1108 /* uV offset */
1109 1025000 0x0
1110 1120000 0x4
1111 >;
1112 };
1114 voltdm_core: voltdm@4a0021d8 {
1115 compatible = "ti,omap5-core-voltdm";
1116 #voltdm-cells = <0>;
1117 reg = <0x4a0021d8 0x4>;
1118 ti,efuse-settings = <
1119 /* uV offset */
1120 1050000 0x0
1121 >;
1122 };
1123 };
1124 };
1126 /include/ "omap54xx-clocks.dtsi"