1 /*
2 * OMAP54xx Clock data
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 * Mike Turquette (mturquette@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * XXX Some of the ES1 clocks have been removed/changed; once support
22 * is added for discriminating clocks by ES level, these should be added back
23 * in.
24 */
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/clk-private.h>
29 #include <linux/clkdev.h>
30 #include <linux/io.h>
32 #include "soc.h"
33 #include "iomap.h"
34 #include "clock.h"
35 #include "clock54xx.h"
36 #include "cm1_54xx.h"
37 #include "cm2_54xx.h"
38 #include "cm-regbits-54xx.h"
39 #include "prm54xx.h"
40 #include "prm-regbits-54xx.h"
41 #include "control.h"
42 #include "scrm54xx.h"
44 /* OMAP4 modulemode control */
45 #define OMAP54XX_MODULEMODE_HWCTRL 0
46 #define OMAP54XX_MODULEMODE_SWCTRL 1
48 /*
49 * OMAP5 ABE DPLL default frequency. In OMAP5430 ES2.0 TRM version R, section
50 * "3.6.3.2.3 CKGEN_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
51 * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
52 * half of this value.
53 */
54 #define OMAP5_DPLL_ABE_DEFFREQ 98304000
56 /*
57 * OMAP543x TRM, section "3.6.3.9.5 DPLL_USB Preferred Settings"
58 * states it must be at 960MHz
59 */
60 #define OMAP5_DPLL_USB_DEFFREQ 960000000
62 /* Root clocks */
64 DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
66 DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
67 OMAP54XX_CM_CLKSEL_ABE, OMAP54XX_PAD_CLKS_GATE_SHIFT, 0x0,
68 NULL);
70 DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
72 DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
74 DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
75 OMAP54XX_CM_CLKSEL_ABE, OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT, 0x0,
76 NULL);
78 DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
80 DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
82 DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
84 DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
86 DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
88 DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
90 DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
92 DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
95 static const char *sys_clkin_parents[] = {
96 "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
97 "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
98 "virt_38400000_ck",
99 };
101 DEFINE_CLK_MUX(sys_clkin, sys_clkin_parents, NULL, 0x0, OMAP54XX_CM_CLKSEL_SYS,
102 OMAP54XX_SYS_CLKSEL_SHIFT, OMAP54XX_SYS_CLKSEL_WIDTH,
103 CLK_MUX_INDEX_ONE, NULL);
105 DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
107 DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
109 /* Module clocks and DPLL outputs */
111 static const char *abe_dpll_bypass_clk_mux_parents[] = {
112 "sys_clkin", "sys_32k_ck",
113 };
115 DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux, abe_dpll_bypass_clk_mux_parents, NULL,
116 0x0, OMAP54XX_CM_CLKSEL_WKUPAON, OMAP54XX_CLKSEL_0_0_SHIFT,
117 OMAP54XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
119 DEFINE_CLK_MUX(abe_dpll_clk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
120 OMAP54XX_CM_CLKSEL_ABE_PLL_REF, OMAP54XX_CLKSEL_0_0_SHIFT,
121 OMAP54XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
123 /* DPLL_ABE */
124 static struct dpll_data dpll_abe_dd = {
125 .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_ABE,
126 .clk_bypass = &abe_dpll_bypass_clk_mux,
127 .clk_ref = &abe_dpll_clk_mux,
128 .control_reg = OMAP54XX_CM_CLKMODE_DPLL_ABE,
129 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
130 .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_ABE,
131 .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_ABE,
132 .mult_mask = OMAP54XX_DPLL_MULT_MASK,
133 .div1_mask = OMAP54XX_DPLL_DIV_MASK,
134 .enable_mask = OMAP54XX_DPLL_EN_MASK,
135 .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
136 .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
137 .m4xen_mask = OMAP54XX_DPLL_REGM4XEN_MASK,
138 .lpmode_mask = OMAP54XX_DPLL_LPMODE_EN_MASK,
139 .max_multiplier = 2047,
140 .max_divider = 128,
141 .min_divider = 1,
142 };
144 static const char *dpll_abe_ck_parents[] = {
145 "abe_dpll_clk_mux", "abe_dpll_bypass_clk_mux"
146 };
148 static struct clk dpll_abe_ck;
150 static const struct clk_ops dpll_abe_ck_ops = {
151 .enable = &omap3_noncore_dpll_enable,
152 .disable = &omap3_noncore_dpll_disable,
153 .recalc_rate = &omap4_dpll_regm4xen_recalc,
154 .round_rate = &omap4_dpll_regm4xen_round_rate,
155 .set_rate = &omap3_noncore_dpll_set_rate,
156 .get_parent = &omap2_init_dpll_parent,
157 };
159 static struct clk_hw_omap dpll_abe_ck_hw = {
160 .hw = {
161 .clk = &dpll_abe_ck,
162 },
163 .dpll_data = &dpll_abe_dd,
164 .ops = &clkhwops_omap3_dpll,
165 };
167 DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
169 static const char *dpll_abe_x2_ck_parents[] = {
170 "dpll_abe_ck",
171 };
173 static struct clk dpll_abe_x2_ck;
175 static const struct clk_ops dpll_abe_x2_ck_ops = {
176 .recalc_rate = &omap3_clkoutx2_recalc,
177 };
179 static struct clk_hw_omap dpll_abe_x2_ck_hw = {
180 .hw = {
181 .clk = &dpll_abe_x2_ck,
182 },
183 };
185 DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
187 static const struct clk_ops omap_hsdivider_ops = {
188 .set_rate = &omap2_clksel_set_rate,
189 .recalc_rate = &omap2_clksel_recalc,
190 .round_rate = &omap2_clksel_round_rate,
191 };
193 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
194 0x0, OMAP54XX_CM_DIV_M2_DPLL_ABE,
195 OMAP54XX_DIVHS_0_4_MASK);
197 DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
198 0x0, 1, 8);
200 DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
201 OMAP54XX_CM_CLKSEL_ABE, OMAP54XX_CLKSEL_OPP_SHIFT,
202 OMAP54XX_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
204 DEFINE_CLK_FIXED_FACTOR(abe_iclk, "abe_clk", &abe_clk, 0x0, 1, 2);
206 DEFINE_CLK_FIXED_FACTOR(abe_lp_clk_div, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
207 0x0, 1, 16);
209 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
210 0x0, OMAP54XX_CM_DIV_M3_DPLL_ABE,
211 OMAP54XX_DIVHS_0_4_MASK);
213 /* DPLL_CORE */
214 static struct dpll_data dpll_core_dd = {
215 .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_CORE,
216 .clk_bypass = &dpll_abe_m3x2_ck,
217 .clk_ref = &sys_clkin,
218 .control_reg = OMAP54XX_CM_CLKMODE_DPLL_CORE,
219 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
220 .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_CORE,
221 .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_CORE,
222 .mult_mask = OMAP54XX_DPLL_MULT_MASK,
223 .div1_mask = OMAP54XX_DPLL_DIV_MASK,
224 .enable_mask = OMAP54XX_DPLL_EN_MASK,
225 .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
226 .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
227 .max_multiplier = 2047,
228 .max_divider = 128,
229 .min_divider = 1,
230 };
232 static const char *dpll_core_ck_parents[] = {
233 "sys_clkin", "dpll_abe_m3x2_ck"
234 };
236 static struct clk dpll_core_ck;
238 static const struct clk_ops dpll_core_ck_ops = {
239 .recalc_rate = &omap3_dpll_recalc,
240 .get_parent = &omap2_init_dpll_parent,
241 };
243 static struct clk_hw_omap dpll_core_ck_hw = {
244 .hw = {
245 .clk = &dpll_core_ck,
246 },
247 .dpll_data = &dpll_core_dd,
248 .ops = &clkhwops_omap3_dpll,
249 };
251 DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
253 static const char *dpll_core_x2_ck_parents[] = {
254 "dpll_core_ck",
255 };
257 static struct clk dpll_core_x2_ck;
259 static struct clk_hw_omap dpll_core_x2_ck_hw = {
260 .hw = {
261 .clk = &dpll_core_x2_ck,
262 },
263 };
265 DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
267 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h21x2_ck, "dpll_core_x2_ck",
268 &dpll_core_x2_ck, 0x0,
269 OMAP54XX_CM_DIV_H21_DPLL_CORE, OMAP54XX_DIVHS_MASK);
271 static const char *c2c_fclk_parents[] = {
272 "dpll_core_h21x2_ck",
273 };
275 static struct clk c2c_fclk;
277 static const struct clk_ops c2c_fclk_ops = {
278 };
280 static struct clk_hw_omap c2c_fclk_hw = {
281 .hw = {
282 .clk = &c2c_fclk,
283 },
284 };
286 DEFINE_STRUCT_CLK(c2c_fclk, c2c_fclk_parents, c2c_fclk_ops);
288 DEFINE_CLK_FIXED_FACTOR(c2c_iclk, "c2c_fclk", &c2c_fclk, 0x0, 1, 2);
290 DEFINE_CLK_FIXED_FACTOR(custefuse_sys_gfclk_div, "sys_clkin", &sys_clkin, 0x0,
291 1, 2);
293 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h11x2_ck, "dpll_core_x2_ck",
294 &dpll_core_x2_ck, 0x0,
295 OMAP54XX_CM_DIV_H11_DPLL_CORE, OMAP54XX_DIVHS_MASK);
297 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h12x2_ck, "dpll_core_x2_ck",
298 &dpll_core_x2_ck, 0x0,
299 OMAP54XX_CM_DIV_H12_DPLL_CORE, OMAP54XX_DIVHS_MASK);
301 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h13x2_ck, "dpll_core_x2_ck",
302 &dpll_core_x2_ck, 0x0,
303 OMAP54XX_CM_DIV_H13_DPLL_CORE, OMAP54XX_DIVHS_MASK);
305 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h14x2_ck, "dpll_core_x2_ck",
306 &dpll_core_x2_ck, 0x0,
307 OMAP54XX_CM_DIV_H14_DPLL_CORE, OMAP54XX_DIVHS_MASK);
309 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h22x2_ck, "dpll_core_x2_ck",
310 &dpll_core_x2_ck, 0x0,
311 OMAP54XX_CM_DIV_H22_DPLL_CORE, OMAP54XX_DIVHS_MASK);
313 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h23x2_ck, "dpll_core_x2_ck",
314 &dpll_core_x2_ck, 0x0,
315 OMAP54XX_CM_DIV_H23_DPLL_CORE, OMAP54XX_DIVHS_MASK);
317 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h24x2_ck, "dpll_core_x2_ck",
318 &dpll_core_x2_ck, 0x0,
319 OMAP54XX_CM_DIV_H24_DPLL_CORE, OMAP54XX_DIVHS_MASK);
321 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
322 OMAP54XX_CM_DIV_M2_DPLL_CORE,
323 OMAP54XX_DIVHS_0_4_MASK);
325 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_m3x2_ck, "dpll_core_x2_ck",
326 &dpll_core_x2_ck, 0x0, OMAP54XX_CM_DIV_M3_DPLL_CORE,
327 OMAP54XX_DIVHS_0_4_MASK);
329 static const char *iva_dpll_hs_clk_div_parents[] = {
330 "dpll_core_h12x2_ck",
331 };
333 static struct clk iva_dpll_hs_clk_div;
335 static struct clk_hw_omap iva_dpll_hs_clk_div_hw = {
336 .hw = {
337 .clk = &iva_dpll_hs_clk_div,
338 },
339 };
341 DEFINE_STRUCT_CLK(iva_dpll_hs_clk_div, iva_dpll_hs_clk_div_parents,
342 c2c_fclk_ops);
344 /* DPLL_IVA */
345 static struct dpll_data dpll_iva_dd = {
346 .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_IVA,
347 .clk_bypass = &iva_dpll_hs_clk_div,
348 .clk_ref = &sys_clkin,
349 .control_reg = OMAP54XX_CM_CLKMODE_DPLL_IVA,
350 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
351 .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_IVA,
352 .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_IVA,
353 .mult_mask = OMAP54XX_DPLL_MULT_MASK,
354 .div1_mask = OMAP54XX_DPLL_DIV_MASK,
355 .enable_mask = OMAP54XX_DPLL_EN_MASK,
356 .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
357 .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
358 .max_multiplier = 2047,
359 .max_divider = 128,
360 .min_divider = 1,
361 };
363 static const char *dpll_iva_ck_parents[] = {
364 "sys_clkin", "iva_dpll_hs_clk_div"
365 };
367 static struct clk dpll_iva_ck;
369 static const struct clk_ops dpll_iva_ck_ops = {
370 .enable = &omap3_noncore_dpll_enable,
371 .disable = &omap3_noncore_dpll_disable,
372 .recalc_rate = &omap3_dpll_recalc,
373 .round_rate = &omap2_dpll_round_rate,
374 .set_rate = &omap3_noncore_dpll_set_rate,
375 .get_parent = &omap2_init_dpll_parent,
376 };
378 static struct clk_hw_omap dpll_iva_ck_hw = {
379 .hw = {
380 .clk = &dpll_iva_ck,
381 },
382 .dpll_data = &dpll_iva_dd,
383 .ops = &clkhwops_omap3_dpll,
384 };
386 DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_iva_ck_ops);
388 static const char *dpll_iva_x2_ck_parents[] = {
389 "dpll_iva_ck",
390 };
392 static struct clk dpll_iva_x2_ck;
394 static struct clk_hw_omap dpll_iva_x2_ck_hw = {
395 .hw = {
396 .clk = &dpll_iva_x2_ck,
397 },
398 };
400 DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
402 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_iva_h11x2_ck, "dpll_iva_x2_ck",
403 &dpll_iva_x2_ck, 0x0, OMAP54XX_CM_DIV_H11_DPLL_IVA,
404 OMAP54XX_DIVHS_MASK);
406 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_iva_h12x2_ck, "dpll_iva_x2_ck",
407 &dpll_iva_x2_ck, 0x0, OMAP54XX_CM_DIV_H12_DPLL_IVA,
408 OMAP54XX_DIVHS_MASK);
410 static struct clk mpu_dpll_hs_clk_div;
412 static struct clk_hw_omap mpu_dpll_hs_clk_div_hw = {
413 .hw = {
414 .clk = &mpu_dpll_hs_clk_div,
415 },
416 };
418 DEFINE_STRUCT_CLK(mpu_dpll_hs_clk_div, iva_dpll_hs_clk_div_parents,
419 c2c_fclk_ops);
421 /* DPLL_MPU */
422 static struct dpll_data dpll_mpu_dd = {
423 .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_MPU,
424 .clk_bypass = &mpu_dpll_hs_clk_div,
425 .clk_ref = &sys_clkin,
426 .control_reg = OMAP54XX_CM_CLKMODE_DPLL_MPU,
427 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
428 .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_MPU,
429 .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_MPU,
430 .dcc_mask = OMAP54XX_DCC_EN_MASK,
431 /* rate bigger than 1.4 GHz will use DCC */
432 .dcc_rate = 1400000000,
433 .mult_mask = OMAP54XX_DPLL_MULT_MASK,
434 .div1_mask = OMAP54XX_DPLL_DIV_MASK,
435 .enable_mask = OMAP54XX_DPLL_EN_MASK,
436 .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
437 .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
438 .max_multiplier = 2047,
439 .max_divider = 128,
440 .min_divider = 1,
441 };
443 static const char *dpll_mpu_ck_parents[] = {
444 "sys_clkin", "mpu_dpll_hs_clk_div"
445 };
447 static struct clk dpll_mpu_ck;
449 static const struct clk_ops dpll_mpu_ck_ops = {
450 .enable = &omap3_noncore_dpll_enable,
451 .disable = &omap3_noncore_dpll_disable,
452 .recalc_rate = &omap3_dpll_recalc,
453 .round_rate = &omap2_dpll_round_rate,
454 .set_rate = &omap5_mpu_dpll_set_rate,
455 .get_parent = &omap2_init_dpll_parent,
456 };
458 static struct clk_hw_omap dpll_mpu_ck_hw = {
459 .hw = {
460 .clk = &dpll_mpu_ck,
461 },
462 .dpll_data = &dpll_mpu_dd,
463 .ops = &clkhwops_omap3_dpll,
464 };
466 DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_mpu_ck_ops);
468 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
469 OMAP54XX_CM_DIV_M2_DPLL_MPU,
470 OMAP54XX_DIVHS_0_4_MASK);
472 DEFINE_CLK_FIXED_FACTOR(per_dpll_hs_clk_div, "dpll_abe_m3x2_ck",
473 &dpll_abe_m3x2_ck, 0x0, 1, 2);
475 /* DPLL_PER */
476 static struct dpll_data dpll_per_dd = {
477 .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_PER,
478 .clk_bypass = &per_dpll_hs_clk_div,
479 .clk_ref = &sys_clkin,
480 .control_reg = OMAP54XX_CM_CLKMODE_DPLL_PER,
481 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
482 .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_PER,
483 .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_PER,
484 .mult_mask = OMAP54XX_DPLL_MULT_MASK,
485 .div1_mask = OMAP54XX_DPLL_DIV_MASK,
486 .enable_mask = OMAP54XX_DPLL_EN_MASK,
487 .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
488 .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
489 .max_multiplier = 2047,
490 .max_divider = 128,
491 .min_divider = 1,
492 };
494 static const char *dpll_per_ck_parents[] = {
495 "sys_clkin", "per_dpll_hs_clk_div"
496 };
498 static struct clk dpll_per_ck;
500 static struct clk_hw_omap dpll_per_ck_hw = {
501 .hw = {
502 .clk = &dpll_per_ck,
503 },
504 .dpll_data = &dpll_per_dd,
505 .ops = &clkhwops_omap3_dpll,
506 };
508 DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_iva_ck_ops);
510 static const char *dpll_per_x2_ck_parents[] = {
511 "dpll_per_ck",
512 };
514 static struct clk dpll_per_x2_ck;
516 static struct clk_hw_omap dpll_per_x2_ck_hw = {
517 .hw = {
518 .clk = &dpll_per_x2_ck,
519 },
520 };
522 DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
524 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h11x2_ck, "dpll_per_x2_ck",
525 &dpll_per_x2_ck, 0x0, OMAP54XX_CM_DIV_H11_DPLL_PER,
526 OMAP54XX_DIVHS_MASK);
528 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h12x2_ck, "dpll_per_x2_ck",
529 &dpll_per_x2_ck, 0x0, OMAP54XX_CM_DIV_H12_DPLL_PER,
530 OMAP54XX_DIVHS_MASK);
532 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h14x2_ck, "dpll_per_x2_ck",
533 &dpll_per_x2_ck, 0x0, OMAP54XX_CM_DIV_H14_DPLL_PER,
534 OMAP54XX_DIVHS_MASK);
536 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
537 OMAP54XX_CM_DIV_M2_DPLL_PER,
538 OMAP54XX_DIVHS_0_4_MASK);
540 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
541 0x0, OMAP54XX_CM_DIV_M2_DPLL_PER,
542 OMAP54XX_DIVHS_0_4_MASK);
544 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m3x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
545 0x0, OMAP54XX_CM_DIV_M3_DPLL_PER,
546 OMAP54XX_DIVHS_0_4_MASK);
548 /* DPLL_UNIPRO1 */
549 static struct dpll_data dpll_unipro1_dd = {
550 .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1,
551 .clk_bypass = &sys_clkin,
552 .clk_ref = &sys_clkin,
553 .control_reg = OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1,
554 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
555 .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1,
556 .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_UNIPRO1,
557 .mult_mask = OMAP54XX_DPLL_MULT_MASK,
558 .div1_mask = OMAP54XX_DPLL_DIV_MASK,
559 .enable_mask = OMAP54XX_DPLL_EN_MASK,
560 .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
561 .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
562 .max_multiplier = 4095,
563 .max_divider = 256,
564 .min_divider = 1,
565 };
567 static const char *dpll_unipro1_ck_parents[] = {
568 "sys_clkin",
569 };
571 static struct clk dpll_unipro1_ck;
573 static struct clk_hw_omap dpll_unipro1_ck_hw = {
574 .hw = {
575 .clk = &dpll_unipro1_ck,
576 },
577 .dpll_data = &dpll_unipro1_dd,
578 .ops = &clkhwops_omap3_dpll,
579 };
581 DEFINE_STRUCT_CLK(dpll_unipro1_ck, dpll_unipro1_ck_parents, dpll_iva_ck_ops);
583 static const char *dpll_unipro1_clkdcoldo_parents[] = {
584 "dpll_unipro1_ck",
585 };
587 static struct clk dpll_unipro1_clkdcoldo;
589 static struct clk_hw_omap dpll_unipro1_clkdcoldo_hw = {
590 .hw = {
591 .clk = &dpll_unipro1_clkdcoldo,
592 },
593 .clksel_reg = OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1,
594 };
596 DEFINE_STRUCT_CLK(dpll_unipro1_clkdcoldo, dpll_unipro1_clkdcoldo_parents,
597 c2c_fclk_ops);
599 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_unipro1_m2_ck, "dpll_unipro1_ck",
600 &dpll_unipro1_ck, 0x0,
601 OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1,
602 OMAP54XX_DIVHS_0_6_MASK);
604 /* DPLL_UNIPRO2 */
605 static struct dpll_data dpll_unipro2_dd = {
606 .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2,
607 .clk_bypass = &sys_clkin,
608 .clk_ref = &sys_clkin,
609 .control_reg = OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2,
610 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
611 .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2,
612 .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_UNIPRO2,
613 .mult_mask = OMAP54XX_DPLL_MULT_MASK,
614 .div1_mask = OMAP54XX_DPLL_DIV_MASK,
615 .enable_mask = OMAP54XX_DPLL_EN_MASK,
616 .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
617 .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
618 .max_multiplier = 4095,
619 .max_divider = 256,
620 .min_divider = 1,
621 };
623 static struct clk dpll_unipro2_ck;
625 static struct clk_hw_omap dpll_unipro2_ck_hw = {
626 .hw = {
627 .clk = &dpll_unipro2_ck,
628 },
629 .dpll_data = &dpll_unipro2_dd,
630 .ops = &clkhwops_omap3_dpll,
631 };
633 DEFINE_STRUCT_CLK(dpll_unipro2_ck, dpll_unipro1_ck_parents, dpll_iva_ck_ops);
635 static const char *dpll_unipro2_clkdcoldo_parents[] = {
636 "dpll_unipro2_ck",
637 };
639 static struct clk dpll_unipro2_clkdcoldo;
641 static struct clk_hw_omap dpll_unipro2_clkdcoldo_hw = {
642 .hw = {
643 .clk = &dpll_unipro2_clkdcoldo,
644 },
645 .clksel_reg = OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2,
646 };
648 DEFINE_STRUCT_CLK(dpll_unipro2_clkdcoldo, dpll_unipro2_clkdcoldo_parents,
649 c2c_fclk_ops);
651 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_unipro2_m2_ck, "dpll_unipro2_ck",
652 &dpll_unipro2_ck, 0x0,
653 OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2,
654 OMAP54XX_DIVHS_0_6_MASK);
656 DEFINE_CLK_FIXED_FACTOR(usb_dpll_hs_clk_div, "dpll_abe_m3x2_ck",
657 &dpll_abe_m3x2_ck, 0x0, 1, 3);
659 /* DPLL_USB */
660 static struct dpll_data dpll_usb_dd = {
661 .mult_div1_reg = OMAP54XX_CM_CLKSEL_DPLL_USB,
662 .clk_bypass = &usb_dpll_hs_clk_div,
663 .flags = DPLL_J_TYPE,
664 .clk_ref = &sys_clkin,
665 .control_reg = OMAP54XX_CM_CLKMODE_DPLL_USB,
666 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
667 .autoidle_reg = OMAP54XX_CM_AUTOIDLE_DPLL_USB,
668 .idlest_reg = OMAP54XX_CM_IDLEST_DPLL_USB,
669 .mult_mask = OMAP54XX_DPLL_MULT_MASK,
670 .div1_mask = OMAP54XX_DPLL_DIV_MASK,
671 .enable_mask = OMAP54XX_DPLL_EN_MASK,
672 .autoidle_mask = OMAP54XX_AUTO_DPLL_MODE_MASK,
673 .idlest_mask = OMAP54XX_ST_DPLL_CLK_MASK,
674 .sddiv_mask = OMAP54XX_DPLL_SD_DIV_MASK,
675 .max_multiplier = 4095,
676 .max_divider = 256,
677 .min_divider = 1,
678 };
680 static const char *dpll_usb_ck_parents[] = {
681 "sys_clkin", "usb_dpll_hs_clk_div"
682 };
684 static struct clk dpll_usb_ck;
686 static const struct clk_ops dpll_usb_ck_ops = {
687 .enable = &omap3_noncore_dpll_enable,
688 .disable = &omap3_noncore_dpll_disable,
689 .recalc_rate = &omap3_dpll_recalc,
690 .round_rate = &omap2_dpll_round_rate,
691 .set_rate = &omap3_noncore_dpll_set_rate,
692 .get_parent = &omap2_init_dpll_parent,
693 .init = &omap2_init_clk_clkdm,
694 };
696 static struct clk_hw_omap dpll_usb_ck_hw = {
697 .hw = {
698 .clk = &dpll_usb_ck,
699 },
700 .dpll_data = &dpll_usb_dd,
701 .clkdm_name = "l3init_clkdm",
702 .ops = &clkhwops_omap3_dpll,
703 };
705 DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
707 static const char *dpll_usb_clkdcoldo_parents[] = {
708 "dpll_usb_ck",
709 };
711 static struct clk dpll_usb_clkdcoldo;
713 static struct clk_hw_omap dpll_usb_clkdcoldo_hw = {
714 .hw = {
715 .clk = &dpll_usb_clkdcoldo,
716 },
717 .clksel_reg = OMAP54XX_CM_CLKDCOLDO_DPLL_USB,
718 };
720 DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo, dpll_usb_clkdcoldo_parents, c2c_fclk_ops);
722 DEFINE_CLK_OMAP_HSDIVIDER63(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
723 OMAP54XX_CM_DIV_M2_DPLL_USB,
724 OMAP54XX_DIVHS_0_6_MASK);
726 static const char *dss_syc_gfclk_div_parents[] = {
727 "sys_clkin",
728 };
730 static struct clk dss_syc_gfclk_div;
732 static struct clk_hw_omap dss_syc_gfclk_div_hw = {
733 .hw = {
734 .clk = &dss_syc_gfclk_div,
735 },
736 };
738 DEFINE_STRUCT_CLK(dss_syc_gfclk_div, dss_syc_gfclk_div_parents, c2c_fclk_ops);
740 DEFINE_CLK_FIXED_FACTOR(func_128m_clk, "dpll_per_h11x2_ck", &dpll_per_h11x2_ck,
741 0x0, 1, 2);
743 DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
744 0x0, 1, 16);
746 DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
747 4);
749 DEFINE_CLK_FIXED_FACTOR(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
750 0x0, 1, 4);
752 DEFINE_CLK_FIXED_FACTOR(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
753 0x0, 1, 2);
755 static struct clk l3_iclk_div;
757 static struct clk_hw_omap l3_iclk_div_hw = {
758 .hw = {
759 .clk = &l3_iclk_div,
760 },
761 };
763 DEFINE_STRUCT_CLK(l3_iclk_div, iva_dpll_hs_clk_div_parents, c2c_fclk_ops);
765 static const char *gpu_l3_iclk_parents[] = {
766 "l3_iclk_div",
767 };
769 static struct clk gpu_l3_iclk;
771 static struct clk_hw_omap gpu_l3_iclk_hw = {
772 .hw = {
773 .clk = &gpu_l3_iclk,
774 },
775 };
777 DEFINE_STRUCT_CLK(gpu_l3_iclk, gpu_l3_iclk_parents, c2c_fclk_ops);
779 static const struct clk_div_table l3init_60m_fclk_rates[] = {
780 { .div = 1, .val = 0 },
781 { .div = 8, .val = 1 },
782 { .div = 0 },
783 };
784 DEFINE_CLK_DIVIDER_TABLE(l3init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
785 0x0, OMAP54XX_CM_CLKSEL_USB_60MHZ,
786 OMAP54XX_CLKSEL_0_0_SHIFT, OMAP54XX_CLKSEL_0_0_WIDTH,
787 0x0, l3init_60m_fclk_rates, NULL);
789 static const char *wkupaon_iclk_mux_parents[] = {
790 "sys_clkin", "abe_lp_clk_div",
791 };
793 DEFINE_CLK_MUX(wkupaon_iclk_mux, wkupaon_iclk_mux_parents, NULL, 0x0,
794 OMAP54XX_CM_CLKSEL_WKUPAON, OMAP54XX_CLKSEL_0_0_SHIFT,
795 OMAP54XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
797 static const char *l3instr_ts_gclk_div_parents[] = {
798 "wkupaon_iclk_mux",
799 };
801 static struct clk l3instr_ts_gclk_div;
803 static struct clk_hw_omap l3instr_ts_gclk_div_hw = {
804 .hw = {
805 .clk = &l3instr_ts_gclk_div,
806 },
807 };
809 DEFINE_STRUCT_CLK(l3instr_ts_gclk_div, l3instr_ts_gclk_div_parents,
810 c2c_fclk_ops);
812 static struct clk l4_root_clk_div;
814 static struct clk_hw_omap l4_root_clk_div_hw = {
815 .hw = {
816 .clk = &l4_root_clk_div,
817 },
818 };
820 DEFINE_STRUCT_CLK(l4_root_clk_div, gpu_l3_iclk_parents, c2c_fclk_ops);
822 /* Leaf clocks controlled by modules */
824 DEFINE_CLK_GATE(dss_32khz_clk, "sys_32k_ck", &sys_32k_ck, 0x0,
825 OMAP54XX_CM_DSS_DSS_CLKCTRL, OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT,
826 0x0, NULL);
828 DEFINE_CLK_GATE(dss_48mhz_clk, "func_48m_fclk", &func_48m_fclk, 0x0,
829 OMAP54XX_CM_DSS_DSS_CLKCTRL, OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT,
830 0x0, NULL);
832 DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_h12x2_ck", &dpll_per_h12x2_ck, 0x0,
833 OMAP54XX_CM_DSS_DSS_CLKCTRL, OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT,
834 0x0, NULL);
836 static const struct clk_ops dss_sys_clk_ops = {
837 .enable = &omap2_dflt_clk_enable,
838 .disable = &omap2_dflt_clk_disable,
839 .is_enabled = &omap2_dflt_clk_is_enabled,
840 .init = &omap2_init_clk_clkdm,
841 };
843 static const char *dss_sys_clk_parents[] = {
844 "dss_syc_gfclk_div",
845 };
847 static struct clk dss_sys_clk;
849 static struct clk_hw_omap dss_sys_clk_hw = {
850 .hw = {
851 .clk = &dss_sys_clk,
852 },
853 .clkdm_name = "dss_clkdm",
854 .enable_reg = OMAP54XX_CM_DSS_DSS_CLKCTRL,
855 .enable_bit = OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT,
856 };
858 DEFINE_STRUCT_CLK(dss_sys_clk, dss_sys_clk_parents, dss_sys_clk_ops);
860 DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
861 OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL,
862 OMAP54XX_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
864 DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
865 OMAP54XX_CM_L4PER_GPIO2_CLKCTRL, OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
866 0x0, NULL);
868 DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
869 OMAP54XX_CM_L4PER_GPIO3_CLKCTRL, OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
870 0x0, NULL);
872 DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
873 OMAP54XX_CM_L4PER_GPIO4_CLKCTRL, OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
874 0x0, NULL);
876 DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
877 OMAP54XX_CM_L4PER_GPIO5_CLKCTRL, OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
878 0x0, NULL);
880 DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
881 OMAP54XX_CM_L4PER_GPIO6_CLKCTRL, OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
882 0x0, NULL);
884 DEFINE_CLK_GATE(gpio7_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
885 OMAP54XX_CM_L4PER_GPIO7_CLKCTRL, OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
886 0x0, NULL);
888 DEFINE_CLK_GATE(gpio8_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
889 OMAP54XX_CM_L4PER_GPIO8_CLKCTRL, OMAP54XX_OPTFCLKEN_DBCLK_SHIFT,
890 0x0, NULL);
892 DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
893 OMAP54XX_CM_CAM_ISS_CLKCTRL, OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT,
894 0x0, NULL);
896 DEFINE_CLK_GATE(lli_txphy_clk, "dpll_unipro1_clkdcoldo",
897 &dpll_unipro1_clkdcoldo, 0x0, OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL,
898 OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT, 0x0, NULL);
900 DEFINE_CLK_GATE(lli_txphy_ls_clk, "dpll_unipro1_m2_ck", &dpll_unipro1_m2_ck,
901 0x0, OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL,
902 OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT, 0x0, NULL);
904 DEFINE_CLK_GATE(mmc1_32khz_clk, "sys_32k_ck", &sys_32k_ck, 0x0,
905 OMAP54XX_CM_L3INIT_MMC1_CLKCTRL,
906 OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT, 0x0, NULL);
908 DEFINE_CLK_GATE(sata_ref_clk, "sys_clkin", &sys_clkin, 0x0,
909 OMAP54XX_CM_L3INIT_SATA_CLKCTRL,
910 OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT, 0x0, NULL);
912 DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
913 OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL,
914 OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
916 DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
917 0x0, OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
918 OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
920 DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
921 0x0, OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
922 OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
924 DEFINE_CLK_GATE(usb_host_hs_hsic480m_p3_clk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
925 0x0, OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
926 OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT, 0x0, NULL);
928 DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "l3init_60m_fclk", &l3init_60m_fclk,
929 0x0, OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
930 OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
932 DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "l3init_60m_fclk", &l3init_60m_fclk,
933 0x0, OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
934 OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
936 DEFINE_CLK_GATE(usb_host_hs_hsic60m_p3_clk, "l3init_60m_fclk", &l3init_60m_fclk,
937 0x0, OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
938 OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT, 0x0, NULL);
940 static const char *utmi_p1_gfclk_parents[] = {
941 "l3init_60m_fclk", "xclk60mhsp1",
942 };
944 DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
945 OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
946 OMAP54XX_CLKSEL_UTMI_P1_SHIFT, OMAP54XX_CLKSEL_UTMI_P1_WIDTH,
947 0x0, NULL);
949 DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
950 OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
951 OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
953 static const char *utmi_p2_gfclk_parents[] = {
954 "l3init_60m_fclk", "xclk60mhsp2",
955 };
957 DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
958 OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
959 OMAP54XX_CLKSEL_UTMI_P2_SHIFT, OMAP54XX_CLKSEL_UTMI_P2_WIDTH,
960 0x0, NULL);
962 DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
963 OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
964 OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
966 DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "l3init_60m_fclk", &l3init_60m_fclk,
967 0x0, OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL,
968 OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
970 DEFINE_CLK_GATE(usb_otg_ss_refclk960m, "dpll_usb_clkdcoldo",
971 &dpll_usb_clkdcoldo, 0x0, OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL,
972 OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT, 0x0, NULL);
974 DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
975 OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL,
976 OMAP54XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
978 DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "l3init_60m_fclk", &l3init_60m_fclk,
979 0x0, OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL,
980 OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
982 DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "l3init_60m_fclk", &l3init_60m_fclk,
983 0x0, OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL,
984 OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
986 DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "l3init_60m_fclk", &l3init_60m_fclk,
987 0x0, OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL,
988 OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
990 /* Remaining optional clocks */
991 DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
992 OMAP54XX_CM_ABE_AESS_CLKCTRL,
993 OMAP54XX_CLKSEL_AESS_FCLK_SHIFT,
994 OMAP54XX_CLKSEL_AESS_FCLK_WIDTH, 0x0, NULL);
996 static const char *dmic_sync_mux_ck_parents[] = {
997 "abe_24m_fclk", "dss_syc_gfclk_div", "func_24m_clk",
998 };
1000 DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1001 OMAP54XX_CM_ABE_DMIC_CLKCTRL,
1002 OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT,
1003 OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1005 static const char *dmic_gfclk_parents[] = {
1006 "dmic_sync_mux_ck", "pad_clks", "slimbus_clk",
1007 };
1009 DEFINE_CLK_MUX(dmic_gfclk, dmic_gfclk_parents, NULL, 0x0,
1010 OMAP54XX_CM_ABE_DMIC_CLKCTRL, OMAP54XX_CLKSEL_SOURCE_SHIFT,
1011 OMAP54XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
1013 DEFINE_CLK_DIVIDER(fdif_fclk, "dpll_per_h11x2_ck", &dpll_per_h11x2_ck, 0x0,
1014 OMAP54XX_CM_CAM_FDIF_CLKCTRL, OMAP54XX_CLKSEL_FCLK_SHIFT,
1015 OMAP54XX_CLKSEL_FCLK_WIDTH, 0x0, NULL);
1017 static const char *gpu_core_gclk_mux_parents[] = {
1018 "dpll_core_h14x2_ck", "dpll_per_h14x2_ck",
1019 };
1021 DEFINE_CLK_MUX(gpu_core_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
1022 OMAP54XX_CM_GPU_GPU_CLKCTRL, OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT,
1023 OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH, 0x0, NULL);
1025 DEFINE_CLK_MUX(gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
1026 OMAP54XX_CM_GPU_GPU_CLKCTRL, OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT,
1027 OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH, 0x0, NULL);
1029 DEFINE_CLK_DIVIDER(hsi_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
1030 OMAP54XX_CM_L3INIT_HSI_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
1031 OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
1033 DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1034 OMAP54XX_CM_ABE_MCASP_CLKCTRL,
1035 OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT,
1036 OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1038 static const char *mcasp_gfclk_parents[] = {
1039 "mcasp_sync_mux_ck", "pad_clks", "slimbus_clk",
1040 };
1042 DEFINE_CLK_MUX(mcasp_gfclk, mcasp_gfclk_parents, NULL, 0x0,
1043 OMAP54XX_CM_ABE_MCASP_CLKCTRL, OMAP54XX_CLKSEL_SOURCE_SHIFT,
1044 OMAP54XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
1046 DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1047 OMAP54XX_CM_ABE_MCBSP1_CLKCTRL,
1048 OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT,
1049 OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1051 static const char *mcbsp1_gfclk_parents[] = {
1052 "mcbsp1_sync_mux_ck", "pad_clks", "slimbus_clk",
1053 };
1055 DEFINE_CLK_MUX(mcbsp1_gfclk, mcbsp1_gfclk_parents, NULL, 0x0,
1056 OMAP54XX_CM_ABE_MCBSP1_CLKCTRL, OMAP54XX_CLKSEL_SOURCE_SHIFT,
1057 OMAP54XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
1059 DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1060 OMAP54XX_CM_ABE_MCBSP2_CLKCTRL,
1061 OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT,
1062 OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1064 static const char *mcbsp2_gfclk_parents[] = {
1065 "mcbsp2_sync_mux_ck", "pad_clks", "slimbus_clk",
1066 };
1068 DEFINE_CLK_MUX(mcbsp2_gfclk, mcbsp2_gfclk_parents, NULL, 0x0,
1069 OMAP54XX_CM_ABE_MCBSP2_CLKCTRL, OMAP54XX_CLKSEL_SOURCE_SHIFT,
1070 OMAP54XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
1072 DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1073 OMAP54XX_CM_ABE_MCBSP3_CLKCTRL,
1074 OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT,
1075 OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1077 static const char *mcbsp3_gfclk_parents[] = {
1078 "mcbsp3_sync_mux_ck", "pad_clks", "slimbus_clk",
1079 };
1081 DEFINE_CLK_MUX(mcbsp3_gfclk, mcbsp3_gfclk_parents, NULL, 0x0,
1082 OMAP54XX_CM_ABE_MCBSP3_CLKCTRL, OMAP54XX_CLKSEL_SOURCE_SHIFT,
1083 OMAP54XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
1085 static const char *mmc1_fclk_mux_parents[] = {
1086 "func_128m_clk", "dpll_per_m2x2_ck",
1087 };
1089 DEFINE_CLK_MUX(mmc1_fclk_mux, mmc1_fclk_mux_parents, NULL, 0x0,
1090 OMAP54XX_CM_L3INIT_MMC1_CLKCTRL,
1091 OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT,
1092 OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH, 0x0, NULL);
1094 DEFINE_CLK_DIVIDER(mmc1_fclk, "mmc1_fclk_mux", &mmc1_fclk_mux, 0x0,
1095 OMAP54XX_CM_L3INIT_MMC1_CLKCTRL, OMAP54XX_CLKSEL_DIV_SHIFT,
1096 OMAP54XX_CLKSEL_DIV_WIDTH, 0x0, NULL);
1098 DEFINE_CLK_MUX(mmc2_fclk_mux, mmc1_fclk_mux_parents, NULL, 0x0,
1099 OMAP54XX_CM_L3INIT_MMC2_CLKCTRL,
1100 OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT,
1101 OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH, 0x0, NULL);
1103 DEFINE_CLK_DIVIDER(mmc2_fclk, "mmc2_fclk_mux", &mmc2_fclk_mux, 0x0,
1104 OMAP54XX_CM_L3INIT_MMC2_CLKCTRL, OMAP54XX_CLKSEL_DIV_SHIFT,
1105 OMAP54XX_CLKSEL_DIV_WIDTH, 0x0, NULL);
1107 DEFINE_CLK_MUX(timer10_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
1108 OMAP54XX_CM_L4PER_TIMER10_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
1109 OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
1111 DEFINE_CLK_MUX(timer11_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
1112 OMAP54XX_CM_L4PER_TIMER11_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
1113 OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
1115 DEFINE_CLK_MUX(timer1_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
1116 OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
1117 OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
1119 DEFINE_CLK_MUX(timer2_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
1120 OMAP54XX_CM_L4PER_TIMER2_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
1121 OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
1123 DEFINE_CLK_MUX(timer3_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
1124 OMAP54XX_CM_L4PER_TIMER3_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
1125 OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
1127 DEFINE_CLK_MUX(timer4_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
1128 OMAP54XX_CM_L4PER_TIMER4_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
1129 OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
1131 static const char *timer5_gfclk_mux_parents[] = {
1132 "dss_syc_gfclk_div", "sys_32k_ck",
1133 };
1135 DEFINE_CLK_MUX(timer5_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
1136 OMAP54XX_CM_ABE_TIMER5_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
1137 OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
1139 DEFINE_CLK_MUX(timer6_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
1140 OMAP54XX_CM_ABE_TIMER6_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
1141 OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
1143 DEFINE_CLK_MUX(timer7_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
1144 OMAP54XX_CM_ABE_TIMER7_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
1145 OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
1147 DEFINE_CLK_MUX(timer8_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
1148 OMAP54XX_CM_ABE_TIMER8_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
1149 OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
1151 DEFINE_CLK_MUX(timer9_gfclk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
1152 OMAP54XX_CM_L4PER_TIMER9_CLKCTRL, OMAP54XX_CLKSEL_SHIFT,
1153 OMAP54XX_CLKSEL_WIDTH, 0x0, NULL);
1155 /* SCRM aux clk nodes */
1156 static const char *dpll_core_m3x2_opt_ck_parents[] = {
1157 "dpll_core_m3x2_ck",
1158 };
1160 static struct clk dpll_core_m3x2_opt_ck;
1162 static struct clk_hw_omap dpll_core_m3x2_opt_ck_hw = {
1163 .hw = {
1164 .clk = &dpll_core_m3x2_opt_ck,
1165 },
1166 .clkdm_name = "wkupaon_clkdm",
1167 .enable_reg = OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL,
1168 .enable_bit = OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT,
1169 };
1171 DEFINE_STRUCT_CLK(dpll_core_m3x2_opt_ck, dpll_core_m3x2_opt_ck_parents,
1172 dss_sys_clk_ops);
1174 static const char *dpll_per_m3x2_opt_ck_parents[] = {
1175 "dpll_per_m3x2_ck",
1176 };
1178 static struct clk dpll_per_m3x2_opt_ck;
1180 static struct clk_hw_omap dpll_per_m3x2_opt_ck_hw = {
1181 .hw = {
1182 .clk = &dpll_per_m3x2_opt_ck,
1183 },
1184 .clkdm_name = "wkupaon_clkdm",
1185 .enable_reg = OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL,
1186 .enable_bit = OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT,
1187 };
1189 DEFINE_STRUCT_CLK(dpll_per_m3x2_opt_ck, dpll_per_m3x2_opt_ck_parents,
1190 dss_sys_clk_ops);
1192 static const struct clksel auxclk_src_sel[] = {
1193 { .parent = &sys_clkin, .rates = div_1_0_rates },
1194 { .parent = &dpll_core_m3x2_opt_ck, .rates = div_1_1_rates },
1195 { .parent = &dpll_per_m3x2_opt_ck, .rates = div_1_2_rates },
1196 { .parent = NULL },
1197 };
1199 static const char *auxclk_src_ck_parents[] = {
1200 "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
1201 };
1203 static const struct clk_ops auxclk_src_ck_ops = {
1204 .enable = &omap2_dflt_clk_enable,
1205 .disable = &omap2_dflt_clk_disable,
1206 .is_enabled = &omap2_dflt_clk_is_enabled,
1207 .recalc_rate = &omap2_clksel_recalc,
1208 .get_parent = &omap2_clksel_find_parent_index,
1209 };
1211 DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
1212 OMAP5_SCRM_AUXCLK0, OMAP5_SRCSELECT_MASK,
1213 OMAP5_SCRM_AUXCLK0, OMAP5_ENABLE_SHIFT, NULL,
1214 auxclk_src_ck_parents, auxclk_src_ck_ops);
1216 DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
1217 OMAP5_SCRM_AUXCLK0, OMAP5_CLKDIV_SHIFT, OMAP5_CLKDIV_WIDTH,
1218 0x0, NULL);
1220 DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
1221 OMAP5_SCRM_AUXCLK1, OMAP5_SRCSELECT_MASK,
1222 OMAP5_SCRM_AUXCLK1, OMAP5_ENABLE_SHIFT, NULL,
1223 auxclk_src_ck_parents, auxclk_src_ck_ops);
1225 DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
1226 OMAP5_SCRM_AUXCLK1, OMAP5_CLKDIV_SHIFT, OMAP5_CLKDIV_WIDTH,
1227 0x0, NULL);
1229 DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
1230 OMAP5_SCRM_AUXCLK2, OMAP5_SRCSELECT_MASK,
1231 OMAP5_SCRM_AUXCLK2, OMAP5_ENABLE_SHIFT, NULL,
1232 auxclk_src_ck_parents, auxclk_src_ck_ops);
1234 DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
1235 OMAP5_SCRM_AUXCLK2, OMAP5_CLKDIV_SHIFT, OMAP5_CLKDIV_WIDTH,
1236 0x0, NULL);
1238 DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
1239 OMAP5_SCRM_AUXCLK3, OMAP5_SRCSELECT_MASK,
1240 OMAP5_SCRM_AUXCLK3, OMAP5_ENABLE_SHIFT, NULL,
1241 auxclk_src_ck_parents, auxclk_src_ck_ops);
1243 DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
1244 OMAP5_SCRM_AUXCLK3, OMAP5_CLKDIV_SHIFT, OMAP5_CLKDIV_WIDTH,
1245 0x0, NULL);
1247 static const char *auxclkreq_ck_parents[] = {
1248 "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
1249 "auxclk5_ck",
1250 };
1252 DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
1253 OMAP5_SCRM_AUXCLKREQ0, OMAP5_MAPPING_SHIFT, OMAP5_MAPPING_WIDTH,
1254 0x0, NULL);
1256 DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
1257 OMAP5_SCRM_AUXCLKREQ1, OMAP5_MAPPING_SHIFT, OMAP5_MAPPING_WIDTH,
1258 0x0, NULL);
1260 DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
1261 OMAP5_SCRM_AUXCLKREQ2, OMAP5_MAPPING_SHIFT, OMAP5_MAPPING_WIDTH,
1262 0x0, NULL);
1264 DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
1265 OMAP5_SCRM_AUXCLKREQ3, OMAP5_MAPPING_SHIFT, OMAP5_MAPPING_WIDTH,
1266 0x0, NULL);
1268 /*
1269 * clkdev
1270 */
1272 static struct omap_clk omap54xx_clks[] = {
1273 CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_54XX),
1274 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_54XX),
1275 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_54XX),
1276 CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_54XX),
1277 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_54XX),
1278 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_54XX),
1279 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_54XX),
1280 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_54XX),
1281 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_54XX),
1282 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_54XX),
1283 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_54XX),
1284 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_54XX),
1285 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_54XX),
1286 CLK(NULL, "sys_clkin", &sys_clkin, CK_54XX),
1287 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_54XX),
1288 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_54XX),
1289 CLK(NULL, "abe_dpll_bypass_clk_mux", &abe_dpll_bypass_clk_mux, CK_54XX),
1290 CLK(NULL, "abe_dpll_clk_mux", &abe_dpll_clk_mux, CK_54XX),
1291 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_54XX),
1292 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_54XX),
1293 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_54XX),
1294 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_54XX),
1295 CLK(NULL, "abe_clk", &abe_clk, CK_54XX),
1296 CLK(NULL, "abe_iclk", &abe_iclk, CK_54XX),
1297 CLK(NULL, "abe_lp_clk_div", &abe_lp_clk_div, CK_54XX),
1298 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_54XX),
1299 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_54XX),
1300 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_54XX),
1301 CLK(NULL, "dpll_core_h21x2_ck", &dpll_core_h21x2_ck, CK_54XX),
1302 CLK(NULL, "c2c_fclk", &c2c_fclk, CK_54XX),
1303 CLK(NULL, "c2c_iclk", &c2c_iclk, CK_54XX),
1304 CLK(NULL, "custefuse_sys_gfclk_div", &custefuse_sys_gfclk_div, CK_54XX),
1305 CLK(NULL, "dpll_core_h11x2_ck", &dpll_core_h11x2_ck, CK_54XX),
1306 CLK(NULL, "dpll_core_h12x2_ck", &dpll_core_h12x2_ck, CK_54XX),
1307 CLK(NULL, "dpll_core_h13x2_ck", &dpll_core_h13x2_ck, CK_54XX),
1308 CLK(NULL, "dpll_core_h14x2_ck", &dpll_core_h14x2_ck, CK_54XX),
1309 CLK(NULL, "dpll_core_h22x2_ck", &dpll_core_h22x2_ck, CK_54XX),
1310 CLK(NULL, "dpll_core_h23x2_ck", &dpll_core_h23x2_ck, CK_54XX),
1311 CLK(NULL, "dpll_core_h24x2_ck", &dpll_core_h24x2_ck, CK_54XX),
1312 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_54XX),
1313 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_54XX),
1314 CLK(NULL, "dpll_core_m3x2_opt_ck", &dpll_core_m3x2_opt_ck, CK_54XX),
1315 CLK(NULL, "iva_dpll_hs_clk_div", &iva_dpll_hs_clk_div, CK_54XX),
1316 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_54XX),
1317 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_54XX),
1318 CLK(NULL, "dpll_iva_h11x2_ck", &dpll_iva_h11x2_ck, CK_54XX),
1319 CLK(NULL, "dpll_iva_h12x2_ck", &dpll_iva_h12x2_ck, CK_54XX),
1320 CLK(NULL, "mpu_dpll_hs_clk_div", &mpu_dpll_hs_clk_div, CK_54XX),
1321 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_54XX),
1322 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_54XX),
1323 CLK(NULL, "per_dpll_hs_clk_div", &per_dpll_hs_clk_div, CK_54XX),
1324 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_54XX),
1325 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_54XX),
1326 CLK(NULL, "dpll_per_h11x2_ck", &dpll_per_h11x2_ck, CK_54XX),
1327 CLK(NULL, "dpll_per_h12x2_ck", &dpll_per_h12x2_ck, CK_54XX),
1328 CLK(NULL, "dpll_per_h14x2_ck", &dpll_per_h14x2_ck, CK_54XX),
1329 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_54XX),
1330 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_54XX),
1331 CLK(NULL, "dpll_per_m3x2_opt_ck", &dpll_per_m3x2_opt_ck, CK_54XX),
1332 CLK(NULL, "dpll_unipro1_ck", &dpll_unipro1_ck, CK_54XX),
1333 CLK(NULL, "dpll_unipro1_clkdcoldo", &dpll_unipro1_clkdcoldo, CK_54XX),
1334 CLK(NULL, "dpll_unipro1_m2_ck", &dpll_unipro1_m2_ck, CK_54XX),
1335 CLK(NULL, "dpll_unipro2_ck", &dpll_unipro2_ck, CK_54XX),
1336 CLK(NULL, "dpll_unipro2_clkdcoldo", &dpll_unipro2_clkdcoldo, CK_54XX),
1337 CLK(NULL, "dpll_unipro2_m2_ck", &dpll_unipro2_m2_ck, CK_54XX),
1338 CLK(NULL, "usb_dpll_hs_clk_div", &usb_dpll_hs_clk_div, CK_54XX),
1339 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_54XX),
1340 CLK(NULL, "dpll_usb_clkdcoldo", &dpll_usb_clkdcoldo, CK_54XX),
1341 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_54XX),
1342 CLK(NULL, "dss_syc_gfclk_div", &dss_syc_gfclk_div, CK_54XX),
1343 CLK(NULL, "func_128m_clk", &func_128m_clk, CK_54XX),
1344 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_54XX),
1345 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_54XX),
1346 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_54XX),
1347 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_54XX),
1348 CLK(NULL, "l3_iclk_div", &l3_iclk_div, CK_54XX),
1349 CLK(NULL, "gpu_l3_iclk", &gpu_l3_iclk, CK_54XX),
1350 CLK(NULL, "l3init_60m_fclk", &l3init_60m_fclk, CK_54XX),
1351 CLK(NULL, "init_60m_fclk", &l3init_60m_fclk, CK_54XX),
1352 CLK(NULL, "wkupaon_iclk_mux", &wkupaon_iclk_mux, CK_54XX),
1353 CLK(NULL, "l3instr_ts_gclk_div", &l3instr_ts_gclk_div, CK_54XX),
1354 CLK(NULL, "l4_root_clk_div", &l4_root_clk_div, CK_54XX),
1355 CLK(NULL, "dss_32khz_clk", &dss_32khz_clk, CK_54XX),
1356 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_54XX),
1357 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_54XX),
1358 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_54XX),
1359 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_54XX),
1360 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_54XX),
1361 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_54XX),
1362 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_54XX),
1363 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_54XX),
1364 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_54XX),
1365 CLK(NULL, "gpio7_dbclk", &gpio7_dbclk, CK_54XX),
1366 CLK(NULL, "gpio8_dbclk", &gpio8_dbclk, CK_54XX),
1367 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_54XX),
1368 CLK(NULL, "lli_txphy_clk", &lli_txphy_clk, CK_54XX),
1369 CLK(NULL, "lli_txphy_ls_clk", &lli_txphy_ls_clk, CK_54XX),
1370 CLK(NULL, "mmc1_32khz_clk", &mmc1_32khz_clk, CK_54XX),
1371 CLK(NULL, "sata_ref_clk", &sata_ref_clk, CK_54XX),
1372 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_54XX),
1373 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_54XX),
1374 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_54XX),
1375 CLK(NULL, "usb_host_hs_hsic480m_p3_clk", &usb_host_hs_hsic480m_p3_clk, CK_54XX),
1376 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_54XX),
1377 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_54XX),
1378 CLK(NULL, "usb_host_hs_hsic60m_p3_clk", &usb_host_hs_hsic60m_p3_clk, CK_54XX),
1379 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_54XX),
1380 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_54XX),
1381 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_54XX),
1382 CLK(NULL, "usb_otg_ss_refclk960m", &usb_otg_ss_refclk960m, CK_54XX),
1383 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_54XX),
1384 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_54XX),
1385 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_54XX),
1386 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_54XX),
1387 CLK(NULL, "aess_fclk", &aess_fclk, CK_54XX),
1388 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_54XX),
1389 CLK(NULL, "dmic_gfclk", &dmic_gfclk, CK_54XX),
1390 CLK(NULL, "fdif_fclk", &fdif_fclk, CK_54XX),
1391 CLK(NULL, "gpu_core_gclk_mux", &gpu_core_gclk_mux, CK_54XX),
1392 CLK(NULL, "gpu_hyd_gclk_mux", &gpu_hyd_gclk_mux, CK_54XX),
1393 CLK(NULL, "hsi_fclk", &hsi_fclk, CK_54XX),
1394 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_54XX),
1395 CLK(NULL, "mcasp_gfclk", &mcasp_gfclk, CK_54XX),
1396 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_54XX),
1397 CLK(NULL, "mcbsp1_gfclk", &mcbsp1_gfclk, CK_54XX),
1398 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_54XX),
1399 CLK(NULL, "mcbsp2_gfclk", &mcbsp2_gfclk, CK_54XX),
1400 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_54XX),
1401 CLK(NULL, "mcbsp3_gfclk", &mcbsp3_gfclk, CK_54XX),
1402 CLK(NULL, "mmc1_fclk_mux", &mmc1_fclk_mux, CK_54XX),
1403 CLK(NULL, "mmc1_fclk", &mmc1_fclk, CK_54XX),
1404 CLK(NULL, "mmc2_fclk_mux", &mmc2_fclk_mux, CK_54XX),
1405 CLK(NULL, "mmc2_fclk", &mmc2_fclk, CK_54XX),
1406 CLK(NULL, "timer10_gfclk_mux", &timer10_gfclk_mux, CK_54XX),
1407 CLK(NULL, "timer11_gfclk_mux", &timer11_gfclk_mux, CK_54XX),
1408 CLK(NULL, "timer1_gfclk_mux", &timer1_gfclk_mux, CK_54XX),
1409 CLK(NULL, "timer2_gfclk_mux", &timer2_gfclk_mux, CK_54XX),
1410 CLK(NULL, "timer3_gfclk_mux", &timer3_gfclk_mux, CK_54XX),
1411 CLK(NULL, "timer4_gfclk_mux", &timer4_gfclk_mux, CK_54XX),
1412 CLK(NULL, "timer5_gfclk_mux", &timer5_gfclk_mux, CK_54XX),
1413 CLK(NULL, "timer6_gfclk_mux", &timer6_gfclk_mux, CK_54XX),
1414 CLK(NULL, "timer7_gfclk_mux", &timer7_gfclk_mux, CK_54XX),
1415 CLK(NULL, "timer8_gfclk_mux", &timer8_gfclk_mux, CK_54XX),
1416 CLK(NULL, "timer9_gfclk_mux", &timer9_gfclk_mux, CK_54XX),
1417 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_54XX),
1418 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_54XX),
1419 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_54XX),
1420 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_54XX),
1421 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_54XX),
1422 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_54XX),
1423 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_54XX),
1424 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_54XX),
1425 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_54XX),
1426 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_54XX),
1427 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_54XX),
1428 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_54XX),
1429 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_54XX),
1430 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_54XX),
1431 CLK(NULL, "gpmc_ck", &dummy_ck, CK_54XX),
1432 CLK("omap_i2c.1", "ick", &dummy_ck, CK_54XX),
1433 CLK("omap_i2c.2", "ick", &dummy_ck, CK_54XX),
1434 CLK("omap_i2c.3", "ick", &dummy_ck, CK_54XX),
1435 CLK("omap_i2c.4", "ick", &dummy_ck, CK_54XX),
1436 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_54XX),
1437 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_54XX),
1438 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_54XX),
1439 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_54XX),
1440 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_54XX),
1441 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_54XX),
1442 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_54XX),
1443 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_54XX),
1444 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_54XX),
1445 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_54XX),
1446 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_54XX),
1447 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_54XX),
1448 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_54XX),
1449 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_54XX),
1450 CLK(NULL, "uart1_ick", &dummy_ck, CK_54XX),
1451 CLK(NULL, "uart2_ick", &dummy_ck, CK_54XX),
1452 CLK(NULL, "uart3_ick", &dummy_ck, CK_54XX),
1453 CLK(NULL, "uart4_ick", &dummy_ck, CK_54XX),
1454 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_54XX),
1455 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_54XX),
1456 CLK("omap_wdt", "ick", &dummy_ck, CK_54XX),
1457 CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_54XX),
1458 CLK("4ae18000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
1459 CLK("48032000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
1460 CLK("48034000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
1461 CLK("48036000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
1462 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
1463 CLK("48086000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
1464 CLK("48088000.timer", "timer_sys_ck", &sys_clkin, CK_54XX),
1465 CLK("40138000.timer", "timer_sys_ck", &dss_syc_gfclk_div, CK_54XX),
1466 CLK("4013a000.timer", "timer_sys_ck", &dss_syc_gfclk_div, CK_54XX),
1467 CLK("4013c000.timer", "timer_sys_ck", &dss_syc_gfclk_div, CK_54XX),
1468 CLK("4013e000.timer", "timer_sys_ck", &dss_syc_gfclk_div, CK_54XX),
1469 CLK("cpu0", NULL, &dpll_mpu_ck, CK_54XX),
1470 };
1472 static struct reparent_init_clks reparent_clks[] = {
1473 { .name = "abe_dpll_clk_mux", .parent = "sys_clkin" }
1474 };
1476 static struct rate_init_clks rate_clks[] = {
1477 { .name = "dpll_usb_ck", .rate = OMAP5_DPLL_USB_DEFFREQ },
1478 { .name = "dpll_usb_m2_ck", .rate = OMAP5_DPLL_USB_DEFFREQ/2 },
1479 { .name = "dpll_abe_ck", .rate = OMAP5_DPLL_ABE_DEFFREQ },
1480 { .name = "dpll_abe_m2x2_ck", .rate = OMAP5_DPLL_ABE_DEFFREQ * 2 },
1481 };
1483 int __init omap5xxx_clk_init(void)
1484 {
1485 u32 cpu_clkflg;
1486 struct omap_clk *c;
1488 if (soc_is_omap54xx()) {
1489 cpu_mask = RATE_IN_54XX;
1490 cpu_clkflg = CK_54XX;
1491 }
1493 /*
1494 * Must stay commented until all OMAP SoC drivers are
1495 * converted to runtime PM, or drivers may start crashing
1496 *
1497 * omap2_clk_disable_clkdm_control();
1498 */
1500 for (c = omap54xx_clks; c < omap54xx_clks + ARRAY_SIZE(omap54xx_clks);
1501 c++) {
1502 if (c->cpu & cpu_clkflg) {
1503 clkdev_add(&c->lk);
1504 if (!__clk_init(NULL, c->lk.clk))
1505 omap2_init_clk_hw_omap_clocks(c->lk.clk);
1506 }
1507 }
1509 omap2_clk_disable_autoidle_all();
1510 omap2_clk_reparent_init_clocks(reparent_clks, ARRAY_SIZE(reparent_clks));
1511 omap2_clk_rate_init_clocks(rate_clks, ARRAY_SIZE(rate_clks));
1513 return 0;
1514 }