1 /*
2 * linux/arch/arm/mach-omap2/clock.h
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
19 #include <linux/kernel.h>
20 #include <linux/list.h>
22 #include <linux/clkdev.h>
23 #include <linux/clk-provider.h>
25 struct omap_clk {
26 u16 cpu;
27 struct clk_lookup lk;
28 };
30 #define CLK(dev, con, ck, cp) \
31 { \
32 .cpu = cp, \
33 .lk = { \
34 .dev_id = dev, \
35 .con_id = con, \
36 .clk = ck, \
37 }, \
38 }
40 /* Platform flags for the clkdev-OMAP integration code */
41 #define CK_242X (1 << 0)
42 #define CK_243X (1 << 1) /* 243x, 253x */
43 #define CK_3430ES1 (1 << 2) /* 34xxES1 only */
44 #define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */
45 #define CK_AM35XX (1 << 4) /* Sitara AM35xx */
46 #define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */
47 #define CK_443X (1 << 6)
48 #define CK_TI816X (1 << 7)
49 #define CK_446X (1 << 8)
50 #define CK_AM33XX (1 << 9) /* AM33xx specific clocks */
51 #define CK_54XX (1 << 10) /* OMAP54xx specific clocks */
52 #define CK_7XX (1 << 11)
55 #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
56 #define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
58 struct clockdomain;
59 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
61 #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
62 static struct clk _name = { \
63 .name = #_name, \
64 .hw = &_name##_hw.hw, \
65 .parent_names = _parent_array_name, \
66 .num_parents = ARRAY_SIZE(_parent_array_name), \
67 .ops = &_clkops_name, \
68 };
70 #define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
71 _clkops_name, _flags) \
72 static struct clk _name = { \
73 .name = #_name, \
74 .hw = &_name##_hw.hw, \
75 .parent_names = _parent_array_name, \
76 .num_parents = ARRAY_SIZE(_parent_array_name), \
77 .ops = &_clkops_name, \
78 .flags = _flags, \
79 };
81 #define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
82 static struct clk_hw_omap _name##_hw = { \
83 .hw = { \
84 .clk = &_name, \
85 }, \
86 .clkdm_name = _clkdm_name, \
87 };
89 #define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \
90 _clksel_reg, _clksel_mask, \
91 _parent_names, _ops) \
92 static struct clk _name; \
93 static struct clk_hw_omap _name##_hw = { \
94 .hw = { \
95 .clk = &_name, \
96 }, \
97 .clksel = _clksel, \
98 .clksel_reg = _clksel_reg, \
99 .clksel_mask = _clksel_mask, \
100 .clkdm_name = _clkdm_name, \
101 }; \
102 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
104 #define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \
105 _clksel_reg, _clksel_mask, \
106 _enable_reg, _enable_bit, \
107 _hwops, _parent_names, _ops) \
108 static struct clk _name; \
109 static struct clk_hw_omap _name##_hw = { \
110 .hw = { \
111 .clk = &_name, \
112 }, \
113 .ops = _hwops, \
114 .enable_reg = _enable_reg, \
115 .enable_bit = _enable_bit, \
116 .clksel = _clksel, \
117 .clksel_reg = _clksel_reg, \
118 .clksel_mask = _clksel_mask, \
119 .clkdm_name = _clkdm_name, \
120 }; \
121 DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
124 #define DEFINE_CLK_OMAP_HSDIVIDER63(_name, _parent_name, \
125 _parent_ptr, _flags, \
126 _clksel_reg, _clksel_mask) \
127 \
128 _DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
129 _parent_ptr, _flags, \
130 _clksel_reg, _clksel_mask, 63)
132 #define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
133 _parent_ptr, _flags, \
134 _clksel_reg, _clksel_mask) \
135 \
136 _DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
137 _parent_ptr, _flags, \
138 _clksel_reg, _clksel_mask, 31)
141 #define _DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
142 _parent_ptr, _flags, \
143 _clksel_reg, _clksel_mask, mdiv)\
144 static const struct clksel _name##_div[] = { \
145 { \
146 .parent = _parent_ptr, \
147 .rates = div##mdiv##_1to##mdiv##_rates \
148 }, \
149 { .parent = NULL }, \
150 }; \
151 static struct clk _name; \
152 static const char *_name##_parent_names[] = { \
153 _parent_name, \
154 }; \
155 static struct clk_hw_omap _name##_hw = { \
156 .hw = { \
157 .clk = &_name, \
158 }, \
159 .clksel = _name##_div, \
160 .clksel_reg = _clksel_reg, \
161 .clksel_mask = _clksel_mask, \
162 .ops = &clkhwops_omap4_dpllmx, \
163 }; \
164 DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
166 /* struct clksel_rate.flags possibilities */
167 #define RATE_IN_242X (1 << 0)
168 #define RATE_IN_243X (1 << 1)
169 #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
170 #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
171 #define RATE_IN_36XX (1 << 4)
172 #define RATE_IN_4430 (1 << 5)
173 #define RATE_IN_TI816X (1 << 6)
174 #define RATE_IN_4460 (1 << 7)
175 #define RATE_IN_AM33XX (1 << 8)
176 #define RATE_IN_TI814X (1 << 9)
177 #define RATE_IN_54XX (1 << 10)
178 #define RATE_IN_7XX (1 << 11)
180 #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
181 #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
182 #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
183 #define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
185 /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
186 #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
189 /**
190 * struct clksel_rate - register bitfield values corresponding to clk divisors
191 * @val: register bitfield value (shifted to bit 0)
192 * @div: clock divisor corresponding to @val
193 * @flags: (see "struct clksel_rate.flags possibilities" above)
194 *
195 * @val should match the value of a read from struct clk.clksel_reg
196 * AND'ed with struct clk.clksel_mask, shifted right to bit 0.
197 *
198 * @div is the divisor that should be applied to the parent clock's rate
199 * to produce the current clock's rate.
200 */
201 struct clksel_rate {
202 u32 val;
203 u8 div;
204 u16 flags;
205 };
207 /**
208 * struct clksel - available parent clocks, and a pointer to their divisors
209 * @parent: struct clk * to a possible parent clock
210 * @rates: available divisors for this parent clock
211 *
212 * A struct clksel is always associated with one or more struct clks
213 * and one or more struct clksel_rates.
214 */
215 struct clksel {
216 struct clk *parent;
217 const struct clksel_rate *rates;
218 };
220 /**
221 * struct dpll_data - DPLL registers and integration data
222 * @mult_div1_reg: register containing the DPLL M and N bitfields
223 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
224 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
225 * @clk_bypass: struct clk pointer to the clock's bypass clock input
226 * @clk_ref: struct clk pointer to the clock's reference clock input
227 * @control_reg: register containing the DPLL mode bitfield
228 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
229 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
230 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
231 * @last_rounded_m4xen: cache of the last M4X result of
232 * omap4_dpll_regm4xen_round_rate()
233 * @last_rounded_lpmode: cache of the last lpmode result of
234 * omap4_dpll_lpmode_recalc()
235 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
236 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
237 * @min_divider: minimum valid non-bypass divider value (actual)
238 * @max_divider: maximum valid non-bypass divider value (actual)
239 * @modes: possible values of @enable_mask
240 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
241 * @idlest_reg: register containing the DPLL idle status bitfield
242 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
243 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
244 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
245 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
246 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
247 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
248 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
249 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
250 * @flags: DPLL type/features (see below)
251 *
252 * Possible values for @flags:
253 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
254 *
255 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
256 *
257 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
258 * correct to only have one @clk_bypass pointer.
259 *
260 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
261 * @last_rounded_n) should be separated from the runtime-fixed fields
262 * and placed into a different structure, so that the runtime-fixed data
263 * can be placed into read-only space.
264 */
265 struct dpll_data {
266 void __iomem *mult_div1_reg;
267 u32 mult_mask;
268 u32 div1_mask;
269 struct clk *clk_bypass;
270 struct clk *clk_ref;
271 void __iomem *control_reg;
272 u32 enable_mask;
273 unsigned long last_rounded_rate;
274 u16 last_rounded_m;
275 u8 last_rounded_m4xen;
276 u8 last_rounded_lpmode;
277 u16 max_multiplier;
278 u8 last_rounded_n;
279 u8 min_divider;
280 u16 max_divider;
281 u8 modes;
282 void __iomem *autoidle_reg;
283 void __iomem *idlest_reg;
284 u32 autoidle_mask;
285 u32 freqsel_mask;
286 u32 idlest_mask;
287 u32 dco_mask;
288 u32 dcc_mask;
289 unsigned long dcc_rate;
290 u32 sddiv_mask;
291 u32 lpmode_mask;
292 u32 m4xen_mask;
293 u8 auto_recal_bit;
294 u8 recal_en_bit;
295 u8 recal_st_bit;
296 u8 flags;
297 };
299 /*
300 * struct clk.flags possibilities
301 *
302 * XXX document the rest of the clock flags here
303 *
304 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
305 * bits share the same register. This flag allows the
306 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
307 * should be used. This is a temporary solution - a better approach
308 * would be to associate clock type-specific data with the clock,
309 * similar to the struct dpll_data approach.
310 */
311 #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
312 #define CLOCK_IDLE_CONTROL (1 << 1)
313 #define CLOCK_NO_IDLE_PARENT (1 << 2)
314 #define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
315 #define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
316 #define CLOCK_CLKOUTX2 (1 << 5)
318 /**
319 * struct clk_hw_omap - OMAP struct clk
320 * @node: list_head connecting this clock into the full clock list
321 * @enable_reg: register to write to enable the clock (see @enable_bit)
322 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
323 * @flags: see "struct clk.flags possibilities" above
324 * @clksel_reg: for clksel clks, register va containing src/divisor select
325 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
326 * @clksel: for clksel clks, pointer to struct clksel for this clock
327 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
328 * @clkdm_name: clockdomain name that this clock is contained in
329 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
330 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
331 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
332 *
333 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
334 * clock code converted to use clksel.
335 *
336 */
338 struct clk_hw_omap_ops;
340 struct clk_hw_omap {
341 struct clk_hw hw;
342 struct list_head node;
343 unsigned long fixed_rate;
344 u8 fixed_div;
345 void __iomem *enable_reg;
346 u8 enable_bit;
347 u8 flags;
348 void __iomem *clksel_reg;
349 u32 clksel_mask;
350 const struct clksel *clksel;
351 struct dpll_data *dpll_data;
352 const char *clkdm_name;
353 struct clockdomain *clkdm;
354 const struct clk_hw_omap_ops *ops;
355 };
357 struct clk_hw_omap_ops {
358 void (*find_idlest)(struct clk_hw_omap *oclk,
359 void __iomem **idlest_reg,
360 u8 *idlest_bit, u8 *idlest_val);
361 void (*find_companion)(struct clk_hw_omap *oclk,
362 void __iomem **other_reg,
363 u8 *other_bit);
364 void (*allow_idle)(struct clk_hw_omap *oclk);
365 void (*deny_idle)(struct clk_hw_omap *oclk);
366 };
368 unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
369 unsigned long parent_rate);
371 struct rate_init_clks {
372 const char *name;
373 unsigned long rate;
374 };
376 struct reparent_init_clks {
377 const char *name;
378 const char *parent;
379 };
381 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
382 #define CORE_CLK_SRC_32K 0x0
383 #define CORE_CLK_SRC_DPLL 0x1
384 #define CORE_CLK_SRC_DPLL_X2 0x2
386 /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
387 #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
388 #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
389 #define OMAP2XXX_EN_DPLL_LOCKED 0x3
391 /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
392 #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
393 #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
394 #define OMAP3XXX_EN_DPLL_LOCKED 0x7
396 /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
397 #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
398 #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
399 #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
400 #define OMAP4XXX_EN_DPLL_LOCKED 0x7
402 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
403 #define DPLL_LOW_POWER_STOP 0x1
404 #define DPLL_LOW_POWER_BYPASS 0x5
405 #define DPLL_LOCKED 0x7
407 /* DPLL Type and DCO Selection Flags */
408 #define DPLL_J_TYPE 0x1
410 long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
411 unsigned long *parent_rate);
412 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
413 int omap3_noncore_dpll_enable(struct clk_hw *hw);
414 void omap3_noncore_dpll_disable(struct clk_hw *hw);
415 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
416 unsigned long parent_rate);
417 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
418 void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
419 void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
420 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
421 unsigned long parent_rate);
422 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
423 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
424 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
425 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
426 unsigned long parent_rate);
427 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
428 unsigned long target_rate,
429 unsigned long *parent_rate);
430 int omap5_mpu_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
431 unsigned long parent_rate);
432 void omap2_init_clk_clkdm(struct clk_hw *clk);
433 void __init omap2_clk_disable_clkdm_control(void);
435 /* clkt_clksel.c public functions */
436 u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
437 unsigned long target_rate,
438 u32 *new_div);
439 u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
440 unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
441 long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
442 unsigned long *parent_rate);
443 int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
444 unsigned long parent_rate);
445 int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
447 /* clkt_iclk.c public functions */
448 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
449 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
451 u8 omap2_init_dpll_parent(struct clk_hw *hw);
452 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
454 int omap2_dflt_clk_enable(struct clk_hw *hw);
455 void omap2_dflt_clk_disable(struct clk_hw *hw);
456 int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
457 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
458 void __iomem **other_reg,
459 u8 *other_bit);
460 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
461 void __iomem **idlest_reg,
462 u8 *idlest_bit, u8 *idlest_val);
463 void omap2_init_clk_hw_omap_clocks(struct clk *clk);
464 int omap2_clk_enable_autoidle_all(void);
465 int omap2_clk_disable_autoidle_all(void);
466 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
467 void omap2_clk_rate_init_clocks(struct rate_init_clks *rclks, u8 num);
468 void omap2_clk_reparent_init_clocks(struct reparent_init_clks *rclks, u8 num);
469 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
470 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
471 const char *core_ck_name,
472 const char *mpu_ck_name);
474 extern u16 cpu_mask;
476 extern const struct clkops clkops_omap2_dflt_wait;
477 extern const struct clkops clkops_dummy;
478 extern const struct clkops clkops_omap2_dflt;
480 extern struct clk_functions omap2_clk_functions;
482 extern const struct clksel_rate gpt_32k_rates[];
483 extern const struct clksel_rate gpt_sys_rates[];
484 extern const struct clksel_rate gfx_l3_rates[];
485 extern const struct clksel_rate dsp_ick_rates[];
486 extern struct clk dummy_ck;
488 extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
489 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
490 extern const struct clk_hw_omap_ops clkhwops_wait;
491 extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
492 extern const struct clk_hw_omap_ops clkhwops_iclk;
493 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
494 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
495 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
496 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
497 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
498 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
499 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
500 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
501 extern const struct clk_hw_omap_ops clkhwops_apll54;
502 extern const struct clk_hw_omap_ops clkhwops_apll96;
503 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
504 extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
506 /* clksel_rate blocks shared between OMAP44xx and AM33xx */
507 extern const struct clksel_rate div_1_0_rates[];
508 extern const struct clksel_rate div3_1to4_rates[];
509 extern const struct clksel_rate div_1_1_rates[];
510 extern const struct clksel_rate div_1_2_rates[];
511 extern const struct clksel_rate div_1_3_rates[];
512 extern const struct clksel_rate div_1_4_rates[];
513 extern const struct clksel_rate div31_1to31_rates[];
514 extern const struct clksel_rate div63_1to63_rates[];
516 extern int am33xx_clk_init(void);
518 extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
519 extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
521 #endif