1 /*
2 * DRA7xx Clock domains framework
3 *
4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2011 Nokia Corporation
6 *
7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 * Paul Walmsley (paul@pwsan.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
22 #include <linux/kernel.h>
23 #include <linux/io.h>
25 #include "clockdomain.h"
26 #include "cm1_7xx.h"
27 #include "cm2_7xx.h"
29 #include "cm-regbits-7xx.h"
30 #include "prm7xx.h"
31 #include "prcm44xx.h"
32 #include "prcm_mpu7xx.h"
34 /* Static Dependencies for DRA7xx Clock Domains */
36 static struct clkdm_dep cam_wkup_sleep_deps[] = {
37 { .clkdm_name = "emif_clkdm" },
38 { NULL },
39 };
41 static struct clkdm_dep dma_wkup_sleep_deps[] = {
42 { .clkdm_name = "dss_clkdm" },
43 { .clkdm_name = "emif_clkdm" },
44 { .clkdm_name = "ipu_clkdm" },
45 { .clkdm_name = "ipu1_clkdm" },
46 { .clkdm_name = "ipu2_clkdm" },
47 { .clkdm_name = "iva_clkdm" },
48 { .clkdm_name = "l3init_clkdm" },
49 { .clkdm_name = "l4cfg_clkdm" },
50 { .clkdm_name = "l4per_clkdm" },
51 { .clkdm_name = "l4per2_clkdm" },
52 { .clkdm_name = "l4per3_clkdm" },
53 { .clkdm_name = "l4sec_clkdm" },
54 { .clkdm_name = "pcie_clkdm" },
55 { .clkdm_name = "wkupaon_clkdm" },
56 { NULL },
57 };
59 static struct clkdm_dep dsp1_wkup_sleep_deps[] = {
60 { .clkdm_name = "atl_clkdm" },
61 { .clkdm_name = "cam_clkdm" },
62 { .clkdm_name = "dsp2_clkdm" },
63 { .clkdm_name = "dss_clkdm" },
64 { .clkdm_name = "emif_clkdm" },
65 { .clkdm_name = "eve1_clkdm" },
66 { .clkdm_name = "eve2_clkdm" },
67 { .clkdm_name = "eve3_clkdm" },
68 { .clkdm_name = "eve4_clkdm" },
69 { .clkdm_name = "gmac_clkdm" },
70 { .clkdm_name = "gpu_clkdm" },
71 { .clkdm_name = "ipu_clkdm" },
72 { .clkdm_name = "ipu1_clkdm" },
73 { .clkdm_name = "ipu2_clkdm" },
74 { .clkdm_name = "iva_clkdm" },
75 { .clkdm_name = "l3init_clkdm" },
76 { .clkdm_name = "l4per_clkdm" },
77 { .clkdm_name = "l4per2_clkdm" },
78 { .clkdm_name = "l4per3_clkdm" },
79 { .clkdm_name = "l4sec_clkdm" },
80 { .clkdm_name = "pcie_clkdm" },
81 { .clkdm_name = "vpe_clkdm" },
82 { .clkdm_name = "wkupaon_clkdm" },
83 { NULL },
84 };
86 static struct clkdm_dep dsp2_wkup_sleep_deps[] = {
87 { .clkdm_name = "atl_clkdm" },
88 { .clkdm_name = "cam_clkdm" },
89 { .clkdm_name = "dsp1_clkdm" },
90 { .clkdm_name = "dss_clkdm" },
91 { .clkdm_name = "emif_clkdm" },
92 { .clkdm_name = "eve1_clkdm" },
93 { .clkdm_name = "eve2_clkdm" },
94 { .clkdm_name = "eve3_clkdm" },
95 { .clkdm_name = "eve4_clkdm" },
96 { .clkdm_name = "gmac_clkdm" },
97 { .clkdm_name = "gpu_clkdm" },
98 { .clkdm_name = "ipu_clkdm" },
99 { .clkdm_name = "ipu1_clkdm" },
100 { .clkdm_name = "ipu2_clkdm" },
101 { .clkdm_name = "iva_clkdm" },
102 { .clkdm_name = "l3init_clkdm" },
103 { .clkdm_name = "l4per_clkdm" },
104 { .clkdm_name = "l4per2_clkdm" },
105 { .clkdm_name = "l4per3_clkdm" },
106 { .clkdm_name = "l4sec_clkdm" },
107 { .clkdm_name = "pcie_clkdm" },
108 { .clkdm_name = "vpe_clkdm" },
109 { .clkdm_name = "wkupaon_clkdm" },
110 { NULL },
111 };
113 static struct clkdm_dep dss_wkup_sleep_deps[] = {
114 { .clkdm_name = "emif_clkdm" },
115 { .clkdm_name = "iva_clkdm" },
116 { NULL },
117 };
119 static struct clkdm_dep eve1_wkup_sleep_deps[] = {
120 { .clkdm_name = "emif_clkdm" },
121 { .clkdm_name = "eve2_clkdm" },
122 { .clkdm_name = "eve3_clkdm" },
123 { .clkdm_name = "eve4_clkdm" },
124 { .clkdm_name = "iva_clkdm" },
125 { NULL },
126 };
128 static struct clkdm_dep eve2_wkup_sleep_deps[] = {
129 { .clkdm_name = "emif_clkdm" },
130 { .clkdm_name = "eve1_clkdm" },
131 { .clkdm_name = "eve3_clkdm" },
132 { .clkdm_name = "eve4_clkdm" },
133 { .clkdm_name = "iva_clkdm" },
134 { NULL },
135 };
137 static struct clkdm_dep eve3_wkup_sleep_deps[] = {
138 { .clkdm_name = "emif_clkdm" },
139 { .clkdm_name = "eve1_clkdm" },
140 { .clkdm_name = "eve2_clkdm" },
141 { .clkdm_name = "eve4_clkdm" },
142 { .clkdm_name = "iva_clkdm" },
143 { NULL },
144 };
146 static struct clkdm_dep eve4_wkup_sleep_deps[] = {
147 { .clkdm_name = "emif_clkdm" },
148 { .clkdm_name = "eve1_clkdm" },
149 { .clkdm_name = "eve2_clkdm" },
150 { .clkdm_name = "eve3_clkdm" },
151 { .clkdm_name = "iva_clkdm" },
152 { NULL },
153 };
155 static struct clkdm_dep gmac_wkup_sleep_deps[] = {
156 { .clkdm_name = "emif_clkdm" },
157 { .clkdm_name = "l4per2_clkdm" },
158 { NULL },
159 };
161 static struct clkdm_dep gpu_wkup_sleep_deps[] = {
162 { .clkdm_name = "emif_clkdm" },
163 { .clkdm_name = "iva_clkdm" },
164 { NULL },
165 };
167 static struct clkdm_dep ipu1_wkup_sleep_deps[] = {
168 { .clkdm_name = "atl_clkdm" },
169 { .clkdm_name = "dsp1_clkdm" },
170 { .clkdm_name = "dsp2_clkdm" },
171 { .clkdm_name = "dss_clkdm" },
172 { .clkdm_name = "emif_clkdm" },
173 { .clkdm_name = "eve1_clkdm" },
174 { .clkdm_name = "eve2_clkdm" },
175 { .clkdm_name = "eve3_clkdm" },
176 { .clkdm_name = "eve4_clkdm" },
177 { .clkdm_name = "gmac_clkdm" },
178 { .clkdm_name = "gpu_clkdm" },
179 { .clkdm_name = "ipu_clkdm" },
180 { .clkdm_name = "ipu2_clkdm" },
181 { .clkdm_name = "iva_clkdm" },
182 { .clkdm_name = "l3init_clkdm" },
183 { .clkdm_name = "l3main1_clkdm" },
184 { .clkdm_name = "l4cfg_clkdm" },
185 { .clkdm_name = "l4per_clkdm" },
186 { .clkdm_name = "l4per2_clkdm" },
187 { .clkdm_name = "l4per3_clkdm" },
188 { .clkdm_name = "l4sec_clkdm" },
189 { .clkdm_name = "pcie_clkdm" },
190 { .clkdm_name = "vpe_clkdm" },
191 { .clkdm_name = "wkupaon_clkdm" },
192 { NULL },
193 };
195 static struct clkdm_dep ipu2_wkup_sleep_deps[] = {
196 { .clkdm_name = "atl_clkdm" },
197 { .clkdm_name = "dsp1_clkdm" },
198 { .clkdm_name = "dsp2_clkdm" },
199 { .clkdm_name = "dss_clkdm" },
200 { .clkdm_name = "emif_clkdm" },
201 { .clkdm_name = "eve1_clkdm" },
202 { .clkdm_name = "eve2_clkdm" },
203 { .clkdm_name = "eve3_clkdm" },
204 { .clkdm_name = "eve4_clkdm" },
205 { .clkdm_name = "gmac_clkdm" },
206 { .clkdm_name = "gpu_clkdm" },
207 { .clkdm_name = "ipu_clkdm" },
208 { .clkdm_name = "ipu1_clkdm" },
209 { .clkdm_name = "iva_clkdm" },
210 { .clkdm_name = "l3init_clkdm" },
211 { .clkdm_name = "l3main1_clkdm" },
212 { .clkdm_name = "l4cfg_clkdm" },
213 { .clkdm_name = "l4per_clkdm" },
214 { .clkdm_name = "l4per2_clkdm" },
215 { .clkdm_name = "l4per3_clkdm" },
216 { .clkdm_name = "l4sec_clkdm" },
217 { .clkdm_name = "pcie_clkdm" },
218 { .clkdm_name = "vpe_clkdm" },
219 { .clkdm_name = "wkupaon_clkdm" },
220 { NULL },
221 };
223 static struct clkdm_dep iva_wkup_sleep_deps[] = {
224 { .clkdm_name = "emif_clkdm" },
225 { NULL },
226 };
228 static struct clkdm_dep l3init_wkup_sleep_deps[] = {
229 { .clkdm_name = "emif_clkdm" },
230 { .clkdm_name = "iva_clkdm" },
231 { .clkdm_name = "l4cfg_clkdm" },
232 { .clkdm_name = "l4per_clkdm" },
233 { .clkdm_name = "l4per3_clkdm" },
234 { .clkdm_name = "l4sec_clkdm" },
235 { .clkdm_name = "wkupaon_clkdm" },
236 { NULL },
237 };
239 static struct clkdm_dep l4per2_wkup_sleep_deps[] = {
240 { .clkdm_name = "dsp1_clkdm" },
241 { .clkdm_name = "dsp2_clkdm" },
242 { .clkdm_name = "ipu1_clkdm" },
243 { .clkdm_name = "ipu2_clkdm" },
244 { NULL },
245 };
247 static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
248 { .clkdm_name = "emif_clkdm" },
249 { .clkdm_name = "l4per_clkdm" },
250 { NULL },
251 };
253 static struct clkdm_dep mpu_wkup_sleep_deps[] = {
254 { .clkdm_name = "cam_clkdm" },
255 { .clkdm_name = "dsp1_clkdm" },
256 { .clkdm_name = "dsp2_clkdm" },
257 { .clkdm_name = "dss_clkdm" },
258 { .clkdm_name = "emif_clkdm" },
259 { .clkdm_name = "eve1_clkdm" },
260 { .clkdm_name = "eve2_clkdm" },
261 { .clkdm_name = "eve3_clkdm" },
262 { .clkdm_name = "eve4_clkdm" },
263 { .clkdm_name = "gmac_clkdm" },
264 { .clkdm_name = "gpu_clkdm" },
265 { .clkdm_name = "ipu_clkdm" },
266 { .clkdm_name = "ipu1_clkdm" },
267 { .clkdm_name = "ipu2_clkdm" },
268 { .clkdm_name = "iva_clkdm" },
269 { .clkdm_name = "l3init_clkdm" },
270 { .clkdm_name = "l3main1_clkdm" },
271 { .clkdm_name = "l4cfg_clkdm" },
272 { .clkdm_name = "l4per_clkdm" },
273 { .clkdm_name = "l4per2_clkdm" },
274 { .clkdm_name = "l4per3_clkdm" },
275 { .clkdm_name = "l4sec_clkdm" },
276 { .clkdm_name = "pcie_clkdm" },
277 { .clkdm_name = "vpe_clkdm" },
278 { .clkdm_name = "wkupaon_clkdm" },
279 { NULL },
280 };
282 static struct clkdm_dep pcie_wkup_sleep_deps[] = {
283 { .clkdm_name = "atl_clkdm" },
284 { .clkdm_name = "cam_clkdm" },
285 { .clkdm_name = "dsp1_clkdm" },
286 { .clkdm_name = "dsp2_clkdm" },
287 { .clkdm_name = "dss_clkdm" },
288 { .clkdm_name = "emif_clkdm" },
289 { .clkdm_name = "eve1_clkdm" },
290 { .clkdm_name = "eve2_clkdm" },
291 { .clkdm_name = "eve3_clkdm" },
292 { .clkdm_name = "eve4_clkdm" },
293 { .clkdm_name = "gmac_clkdm" },
294 { .clkdm_name = "gpu_clkdm" },
295 { .clkdm_name = "ipu_clkdm" },
296 { .clkdm_name = "ipu1_clkdm" },
297 { .clkdm_name = "iva_clkdm" },
298 { .clkdm_name = "l3init_clkdm" },
299 { .clkdm_name = "l4cfg_clkdm" },
300 { .clkdm_name = "l4per_clkdm" },
301 { .clkdm_name = "l4per2_clkdm" },
302 { .clkdm_name = "l4per3_clkdm" },
303 { .clkdm_name = "l4sec_clkdm" },
304 { .clkdm_name = "vpe_clkdm" },
305 { NULL },
306 };
308 static struct clkdm_dep vpe_wkup_sleep_deps[] = {
309 { .clkdm_name = "emif_clkdm" },
310 { .clkdm_name = "l4per3_clkdm" },
311 { NULL },
312 };
314 static struct clockdomain l4per3_7xx_clkdm = {
315 .name = "l4per3_clkdm",
316 .pwrdm = { .name = "l4per_pwrdm" },
317 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
318 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
319 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
320 .dep_bit = DRA7XX_L4PER3_STATDEP_SHIFT,
321 .flags = CLKDM_CAN_HWSUP_SWSUP,
322 };
324 static struct clockdomain l4per2_7xx_clkdm = {
325 .name = "l4per2_clkdm",
326 .pwrdm = { .name = "l4per_pwrdm" },
327 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
328 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
329 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
330 .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT,
331 .wkdep_srcs = l4per2_wkup_sleep_deps,
332 .sleepdep_srcs = l4per2_wkup_sleep_deps,
333 .flags = CLKDM_CAN_HWSUP_SWSUP,
334 };
336 static struct clockdomain mpu0_7xx_clkdm = {
337 .name = "mpu0_clkdm",
338 .pwrdm = { .name = "cpu0_pwrdm" },
339 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
340 .cm_inst = DRA7XX_MPU_PRCM_CM_C0_INST,
341 .clkdm_offs = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
342 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
343 };
345 static struct clockdomain iva_7xx_clkdm = {
346 .name = "iva_clkdm",
347 .pwrdm = { .name = "iva_pwrdm" },
348 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
349 .cm_inst = DRA7XX_CM_CORE_IVA_INST,
350 .clkdm_offs = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
351 .dep_bit = DRA7XX_IVA_STATDEP_SHIFT,
352 .wkdep_srcs = iva_wkup_sleep_deps,
353 .sleepdep_srcs = iva_wkup_sleep_deps,
354 .flags = CLKDM_CAN_HWSUP_SWSUP,
355 };
357 static struct clockdomain coreaon_7xx_clkdm = {
358 .name = "coreaon_clkdm",
359 .pwrdm = { .name = "coreaon_pwrdm" },
360 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
361 .cm_inst = DRA7XX_CM_CORE_COREAON_INST,
362 .clkdm_offs = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
363 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
364 };
366 static struct clockdomain ipu1_7xx_clkdm = {
367 .name = "ipu1_clkdm",
368 .pwrdm = { .name = "ipu_pwrdm" },
369 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
370 .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
371 .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
372 .dep_bit = DRA7XX_IPU1_STATDEP_SHIFT,
373 .wkdep_srcs = ipu1_wkup_sleep_deps,
374 .sleepdep_srcs = ipu1_wkup_sleep_deps,
375 .flags = CLKDM_CAN_HWSUP_SWSUP,
376 };
378 static struct clockdomain ipu2_7xx_clkdm = {
379 .name = "ipu2_clkdm",
380 .pwrdm = { .name = "core_pwrdm" },
381 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
382 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
383 .clkdm_offs = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
384 .dep_bit = DRA7XX_IPU2_STATDEP_SHIFT,
385 .wkdep_srcs = ipu2_wkup_sleep_deps,
386 .sleepdep_srcs = ipu2_wkup_sleep_deps,
387 .flags = CLKDM_CAN_HWSUP_SWSUP,
388 };
390 static struct clockdomain l3init_7xx_clkdm = {
391 .name = "l3init_clkdm",
392 .pwrdm = { .name = "l3init_pwrdm" },
393 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
394 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
395 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
396 .dep_bit = DRA7XX_L3INIT_STATDEP_SHIFT,
397 .wkdep_srcs = l3init_wkup_sleep_deps,
398 .sleepdep_srcs = l3init_wkup_sleep_deps,
399 .flags = CLKDM_CAN_HWSUP_SWSUP,
400 };
402 static struct clockdomain l4sec_7xx_clkdm = {
403 .name = "l4sec_clkdm",
404 .pwrdm = { .name = "l4per_pwrdm" },
405 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
406 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
407 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
408 .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT,
409 .wkdep_srcs = l4sec_wkup_sleep_deps,
410 .sleepdep_srcs = l4sec_wkup_sleep_deps,
411 .flags = CLKDM_CAN_HWSUP_SWSUP,
412 };
414 static struct clockdomain l3main1_7xx_clkdm = {
415 .name = "l3main1_clkdm",
416 .pwrdm = { .name = "core_pwrdm" },
417 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
418 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
419 .clkdm_offs = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
420 .dep_bit = DRA7XX_L3MAIN1_STATDEP_SHIFT,
421 .flags = CLKDM_CAN_HWSUP,
422 };
424 static struct clockdomain vpe_7xx_clkdm = {
425 .name = "vpe_clkdm",
426 .pwrdm = { .name = "vpe_pwrdm" },
427 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
428 .cm_inst = DRA7XX_CM_CORE_AON_VPE_INST,
429 .clkdm_offs = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
430 .dep_bit = DRA7XX_VPE_STATDEP_SHIFT,
431 .wkdep_srcs = vpe_wkup_sleep_deps,
432 .sleepdep_srcs = vpe_wkup_sleep_deps,
433 .flags = CLKDM_CAN_HWSUP_SWSUP,
434 };
436 static struct clockdomain mpu_7xx_clkdm = {
437 .name = "mpu_clkdm",
438 .pwrdm = { .name = "mpu_pwrdm" },
439 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
440 .cm_inst = DRA7XX_CM_CORE_AON_MPU_INST,
441 .clkdm_offs = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
442 .wkdep_srcs = mpu_wkup_sleep_deps,
443 .sleepdep_srcs = mpu_wkup_sleep_deps,
444 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
445 };
447 static struct clockdomain custefuse_7xx_clkdm = {
448 .name = "custefuse_clkdm",
449 .pwrdm = { .name = "custefuse_pwrdm" },
450 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
451 .cm_inst = DRA7XX_CM_CORE_CUSTEFUSE_INST,
452 .clkdm_offs = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
453 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
454 };
456 static struct clockdomain ipu_7xx_clkdm = {
457 .name = "ipu_clkdm",
458 .pwrdm = { .name = "ipu_pwrdm" },
459 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
460 .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
461 .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
462 .dep_bit = DRA7XX_IPU_STATDEP_SHIFT,
463 .flags = CLKDM_CAN_HWSUP_SWSUP,
464 };
466 static struct clockdomain mpu1_7xx_clkdm = {
467 .name = "mpu1_clkdm",
468 .pwrdm = { .name = "cpu1_pwrdm" },
469 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
470 .cm_inst = DRA7XX_MPU_PRCM_CM_C1_INST,
471 .clkdm_offs = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
472 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
473 };
475 static struct clockdomain gmac_7xx_clkdm = {
476 .name = "gmac_clkdm",
477 .pwrdm = { .name = "l3init_pwrdm" },
478 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
479 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
480 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
481 .dep_bit = DRA7XX_GMAC_STATDEP_SHIFT,
482 .wkdep_srcs = gmac_wkup_sleep_deps,
483 .sleepdep_srcs = gmac_wkup_sleep_deps,
484 .flags = CLKDM_CAN_HWSUP_SWSUP,
485 };
487 static struct clockdomain l4cfg_7xx_clkdm = {
488 .name = "l4cfg_clkdm",
489 .pwrdm = { .name = "core_pwrdm" },
490 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
491 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
492 .clkdm_offs = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
493 .dep_bit = DRA7XX_L4CFG_STATDEP_SHIFT,
494 .flags = CLKDM_CAN_HWSUP,
495 };
497 static struct clockdomain dma_7xx_clkdm = {
498 .name = "dma_clkdm",
499 .pwrdm = { .name = "core_pwrdm" },
500 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
501 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
502 .clkdm_offs = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
503 .wkdep_srcs = dma_wkup_sleep_deps,
504 .sleepdep_srcs = dma_wkup_sleep_deps,
505 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
506 };
508 static struct clockdomain rtc_7xx_clkdm = {
509 .name = "rtc_clkdm",
510 .pwrdm = { .name = "rtc_pwrdm" },
511 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
512 .cm_inst = DRA7XX_CM_CORE_AON_RTC_INST,
513 .clkdm_offs = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
514 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
515 };
517 static struct clockdomain pcie_7xx_clkdm = {
518 .name = "pcie_clkdm",
519 .pwrdm = { .name = "l3init_pwrdm" },
520 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
521 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
522 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
523 .dep_bit = DRA7XX_PCIE_STATDEP_SHIFT,
524 .wkdep_srcs = pcie_wkup_sleep_deps,
525 .sleepdep_srcs = pcie_wkup_sleep_deps,
526 .flags = CLKDM_CAN_HWSUP_SWSUP,
527 };
529 static struct clockdomain atl_7xx_clkdm = {
530 .name = "atl_clkdm",
531 .pwrdm = { .name = "core_pwrdm" },
532 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
533 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
534 .clkdm_offs = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
535 .dep_bit = DRA7XX_ATL_STATDEP_SHIFT,
536 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
537 };
539 static struct clockdomain l3instr_7xx_clkdm = {
540 .name = "l3instr_clkdm",
541 .pwrdm = { .name = "core_pwrdm" },
542 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
543 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
544 .clkdm_offs = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
545 };
547 static struct clockdomain dss_7xx_clkdm = {
548 .name = "dss_clkdm",
549 .pwrdm = { .name = "dss_pwrdm" },
550 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
551 .cm_inst = DRA7XX_CM_CORE_DSS_INST,
552 .clkdm_offs = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
553 .dep_bit = DRA7XX_DSS_STATDEP_SHIFT,
554 .wkdep_srcs = dss_wkup_sleep_deps,
555 .sleepdep_srcs = dss_wkup_sleep_deps,
556 .flags = CLKDM_CAN_HWSUP_SWSUP,
557 };
559 static struct clockdomain emif_7xx_clkdm = {
560 .name = "emif_clkdm",
561 .pwrdm = { .name = "core_pwrdm" },
562 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
563 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
564 .clkdm_offs = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
565 .dep_bit = DRA7XX_EMIF_STATDEP_SHIFT,
566 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
567 };
569 static struct clockdomain emu_7xx_clkdm = {
570 .name = "emu_clkdm",
571 .pwrdm = { .name = "emu_pwrdm" },
572 .prcm_partition = DRA7XX_PRM_PARTITION,
573 .cm_inst = DRA7XX_PRM_EMU_CM_INST,
574 .clkdm_offs = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
575 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
576 };
578 static struct clockdomain dsp2_7xx_clkdm = {
579 .name = "dsp2_clkdm",
580 .pwrdm = { .name = "dsp2_pwrdm" },
581 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
582 .cm_inst = DRA7XX_CM_CORE_AON_DSP2_INST,
583 .clkdm_offs = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
584 .dep_bit = DRA7XX_DSP2_STATDEP_SHIFT,
585 .wkdep_srcs = dsp2_wkup_sleep_deps,
586 .sleepdep_srcs = dsp2_wkup_sleep_deps,
587 .flags = CLKDM_CAN_HWSUP_SWSUP,
588 };
590 static struct clockdomain dsp1_7xx_clkdm = {
591 .name = "dsp1_clkdm",
592 .pwrdm = { .name = "dsp1_pwrdm" },
593 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
594 .cm_inst = DRA7XX_CM_CORE_AON_DSP1_INST,
595 .clkdm_offs = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
596 .dep_bit = DRA7XX_DSP1_STATDEP_SHIFT,
597 .wkdep_srcs = dsp1_wkup_sleep_deps,
598 .sleepdep_srcs = dsp1_wkup_sleep_deps,
599 .flags = CLKDM_CAN_HWSUP_SWSUP,
600 };
602 static struct clockdomain cam_7xx_clkdm = {
603 .name = "cam_clkdm",
604 .pwrdm = { .name = "cam_pwrdm" },
605 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
606 .cm_inst = DRA7XX_CM_CORE_CAM_INST,
607 .clkdm_offs = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
608 .dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
609 .wkdep_srcs = cam_wkup_sleep_deps,
610 .sleepdep_srcs = cam_wkup_sleep_deps,
611 .flags = CLKDM_CAN_HWSUP_SWSUP,
612 };
614 static struct clockdomain l4per_7xx_clkdm = {
615 .name = "l4per_clkdm",
616 .pwrdm = { .name = "l4per_pwrdm" },
617 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
618 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
619 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
620 .dep_bit = DRA7XX_L4PER_STATDEP_SHIFT,
621 .flags = CLKDM_CAN_HWSUP_SWSUP,
622 };
624 static struct clockdomain gpu_7xx_clkdm = {
625 .name = "gpu_clkdm",
626 .pwrdm = { .name = "gpu_pwrdm" },
627 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
628 .cm_inst = DRA7XX_CM_CORE_GPU_INST,
629 .clkdm_offs = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
630 .dep_bit = DRA7XX_GPU_STATDEP_SHIFT,
631 .wkdep_srcs = gpu_wkup_sleep_deps,
632 .sleepdep_srcs = gpu_wkup_sleep_deps,
633 .flags = CLKDM_CAN_HWSUP_SWSUP,
634 };
636 static struct clockdomain eve4_7xx_clkdm = {
637 .name = "eve4_clkdm",
638 .pwrdm = { .name = "eve4_pwrdm" },
639 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
640 .cm_inst = DRA7XX_CM_CORE_AON_EVE4_INST,
641 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
642 .dep_bit = DRA7XX_EVE4_STATDEP_SHIFT,
643 .wkdep_srcs = eve4_wkup_sleep_deps,
644 .sleepdep_srcs = eve4_wkup_sleep_deps,
645 .flags = CLKDM_CAN_HWSUP_SWSUP,
646 };
648 static struct clockdomain eve2_7xx_clkdm = {
649 .name = "eve2_clkdm",
650 .pwrdm = { .name = "eve2_pwrdm" },
651 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
652 .cm_inst = DRA7XX_CM_CORE_AON_EVE2_INST,
653 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
654 .dep_bit = DRA7XX_EVE2_STATDEP_SHIFT,
655 .wkdep_srcs = eve2_wkup_sleep_deps,
656 .sleepdep_srcs = eve2_wkup_sleep_deps,
657 .flags = CLKDM_CAN_HWSUP_SWSUP,
658 };
660 static struct clockdomain eve3_7xx_clkdm = {
661 .name = "eve3_clkdm",
662 .pwrdm = { .name = "eve3_pwrdm" },
663 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
664 .cm_inst = DRA7XX_CM_CORE_AON_EVE3_INST,
665 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
666 .dep_bit = DRA7XX_EVE3_STATDEP_SHIFT,
667 .wkdep_srcs = eve3_wkup_sleep_deps,
668 .sleepdep_srcs = eve3_wkup_sleep_deps,
669 .flags = CLKDM_CAN_HWSUP_SWSUP,
670 };
672 static struct clockdomain wkupaon_7xx_clkdm = {
673 .name = "wkupaon_clkdm",
674 .pwrdm = { .name = "wkupaon_pwrdm" },
675 .prcm_partition = DRA7XX_PRM_PARTITION,
676 .cm_inst = DRA7XX_PRM_WKUPAON_CM_INST,
677 .clkdm_offs = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
678 .dep_bit = DRA7XX_WKUPAON_STATDEP_SHIFT,
679 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
680 };
682 static struct clockdomain eve1_7xx_clkdm = {
683 .name = "eve1_clkdm",
684 .pwrdm = { .name = "eve1_pwrdm" },
685 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
686 .cm_inst = DRA7XX_CM_CORE_AON_EVE1_INST,
687 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,
688 .dep_bit = DRA7XX_EVE1_STATDEP_SHIFT,
689 .wkdep_srcs = eve1_wkup_sleep_deps,
690 .sleepdep_srcs = eve1_wkup_sleep_deps,
691 .flags = CLKDM_CAN_HWSUP_SWSUP,
692 };
694 /* As clockdomains are added or removed above, this list must also be changed */
695 static struct clockdomain *clockdomains_dra7xx[] __initdata = {
696 &l4per3_7xx_clkdm,
697 &l4per2_7xx_clkdm,
698 &mpu0_7xx_clkdm,
699 &iva_7xx_clkdm,
700 &coreaon_7xx_clkdm,
701 &ipu1_7xx_clkdm,
702 &ipu2_7xx_clkdm,
703 &l3init_7xx_clkdm,
704 &l4sec_7xx_clkdm,
705 &l3main1_7xx_clkdm,
706 &vpe_7xx_clkdm,
707 &mpu_7xx_clkdm,
708 &custefuse_7xx_clkdm,
709 &ipu_7xx_clkdm,
710 &mpu1_7xx_clkdm,
711 &gmac_7xx_clkdm,
712 &l4cfg_7xx_clkdm,
713 &dma_7xx_clkdm,
714 &rtc_7xx_clkdm,
715 &pcie_7xx_clkdm,
716 &atl_7xx_clkdm,
717 &l3instr_7xx_clkdm,
718 &dss_7xx_clkdm,
719 &emif_7xx_clkdm,
720 &emu_7xx_clkdm,
721 &dsp2_7xx_clkdm,
722 &dsp1_7xx_clkdm,
723 &cam_7xx_clkdm,
724 &l4per_7xx_clkdm,
725 &gpu_7xx_clkdm,
726 &eve4_7xx_clkdm,
727 &eve2_7xx_clkdm,
728 &eve3_7xx_clkdm,
729 &wkupaon_7xx_clkdm,
730 &eve1_7xx_clkdm,
731 NULL
732 };
734 void __init dra7xx_clockdomains_init(void)
735 {
736 clkdm_register_platform_funcs(&omap4_clkdm_operations);
737 clkdm_register_clkdms(clockdomains_dra7xx);
738 clkdm_complete_init();
739 }