arch/arm/mach-omap2/id.c

   1 /*
   2  * linux/arch/arm/mach-omap2/id.c
   3  *
   4  * OMAP2 CPU identification code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009-11 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/io.h>
  21 #include <linux/random.h>
  22 #include <linux/slab.h>
  23
  24 #ifdef CONFIG_SOC_BUS
  25 #include <linux/sys_soc.h>
  26 #endif
  27
  28 #include <asm/cputype.h>
  29
  30 #include "common.h"
  31
  32 #include "id.h"
  33
  34 #include "soc.h"
  35 #include "control.h"
  36
  37 #define OMAP4_SILICON_TYPE_STANDARD             0x01
  38 #define OMAP4_SILICON_TYPE_PERFORMANCE          0x02
  39
  40 #define OMAP_SOC_MAX_NAME_LENGTH                16
  41
  42 static unsigned int omap_revision;
  43 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
  44 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
  45 u32 omap_features;
  46
  47 unsigned int omap_rev(void)
  48 {
  49         return omap_revision;
  50 }
  51 EXPORT_SYMBOL(omap_rev);
  52
  53 int omap_type(void)
  54 {
  55         u32 val = 0;
  56
  57         if (cpu_is_omap24xx()) {
  58                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
  59         } else if (soc_is_am33xx() || soc_is_am43xx()) {
  60                 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
  61         } else if (cpu_is_omap34xx()) {
  62                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
  63         } else if (cpu_is_omap44xx()) {
  64                 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
  65         } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
  66                 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
  67                 val &= OMAP5_DEVICETYPE_MASK;
  68                 val >>= 6;
  69                 goto out;
  70         } else {
  71                 pr_err("Cannot detect omap type!\n");
  72                 goto out;
  73         }
  74
  75         val &= OMAP2_DEVICETYPE_MASK;
  76         val >>= 8;
  77
  78 out:
  79         return val;
  80 }
  81 EXPORT_SYMBOL(omap_type);
  82
  83
  84 /*----------------------------------------------------------------------------*/
  85
  86 #define OMAP_TAP_IDCODE         0x0204
  87 #define OMAP_TAP_DIE_ID_0       0x0218
  88 #define OMAP_TAP_DIE_ID_1       0x021C
  89 #define OMAP_TAP_DIE_ID_2       0x0220
  90 #define OMAP_TAP_DIE_ID_3       0x0224
  91
  92 #define OMAP_TAP_DIE_ID_44XX_0  0x0200
  93 #define OMAP_TAP_DIE_ID_44XX_1  0x0208
  94 #define OMAP_TAP_DIE_ID_44XX_2  0x020c
  95 #define OMAP_TAP_DIE_ID_44XX_3  0x0210
  96
  97 #define read_tap_reg(reg)       __raw_readl(tap_base  + (reg))
  98
  99 struct omap_id {
 100         u16     hawkeye;        /* Silicon type (Hawkeye id) */
 101         u8      dev;            /* Device type from production_id reg */
 102         u32     type;           /* Combined type id copied to omap_revision */
 103 };
 104
 105 /* Register values to detect the OMAP version */
 106 static struct omap_id omap_ids[] __initdata = {
 107         { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
 108         { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
 109         { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
 110         { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
 111         { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
 112         { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
 113 };
 114
 115 static void __iomem *tap_base;
 116 static u16 tap_prod_id;
 117
 118 void omap_get_die_id(struct omap_die_id *odi)
 119 {
 120         if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
 121                 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
 122                 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
 123                 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
 124                 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
 125
 126                 return;
 127         }
 128         odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
 129         odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
 130         odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
 131         odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
 132 }
 133
 134 static int __init omap_feed_randpool(void)
 135 {
 136         struct omap_die_id odi;
 137
 138         /* Throw the die ID into the entropy pool at boot */
 139         omap_get_die_id(&odi);
 140         add_device_randomness(&odi, sizeof(odi));
 141         return 0;
 142 }
 143 omap_device_initcall(omap_feed_randpool);
 144
 145 void __init omap2xxx_check_revision(void)
 146 {
 147         int i, j;
 148         u32 idcode, prod_id;
 149         u16 hawkeye;
 150         u8  dev_type, rev;
 151         struct omap_die_id odi;
 152
 153         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 154         prod_id = read_tap_reg(tap_prod_id);
 155         hawkeye = (idcode >> 12) & 0xffff;
 156         rev = (idcode >> 28) & 0x0f;
 157         dev_type = (prod_id >> 16) & 0x0f;
 158         omap_get_die_id(&odi);
 159
 160         pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
 161                  idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
 162         pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
 163         pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
 164                  odi.id_1, (odi.id_1 >> 28) & 0xf);
 165         pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
 166         pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
 167         pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
 168                  prod_id, dev_type);
 169
 170         /* Check hawkeye ids */
 171         for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
 172                 if (hawkeye == omap_ids[i].hawkeye)
 173                         break;
 174         }
 175
 176         if (i == ARRAY_SIZE(omap_ids)) {
 177                 printk(KERN_ERR "Unknown OMAP CPU id\n");
 178                 return;
 179         }
 180
 181         for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
 182                 if (dev_type == omap_ids[j].dev)
 183                         break;
 184         }
 185
 186         if (j == ARRAY_SIZE(omap_ids)) {
 187                 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
 188                        omap_ids[i].type >> 16);
 189                 j = i;
 190         }
 191
 192         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 193         sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
 194
 195         pr_info("%s", soc_name);
 196         if ((omap_rev() >> 8) & 0x0f)
 197                 pr_info("%s", soc_rev);
 198         pr_info("\n");
 199 }
 200
 201 #define OMAP3_SHOW_FEATURE(feat)                \
 202         if (omap3_has_ ##feat())                \
 203                 printk(#feat" ");
 204
 205 static void __init omap3_cpuinfo(void)
 206 {
 207         const char *cpu_name;
 208
 209         /*
 210          * OMAP3430 and OMAP3530 are assumed to be same.
 211          *
 212          * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
 213          * on available features. Upon detection, update the CPU id
 214          * and CPU class bits.
 215          */
 216         if (cpu_is_omap3630()) {
 217                 cpu_name = "OMAP3630";
 218         } else if (soc_is_am35xx()) {
 219                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
 220         } else if (cpu_is_ti816x()) {
 221                 cpu_name = "TI816X";
 222         } else if (soc_is_am335x()) {
 223                 cpu_name =  "AM335X";
 224         } else if (soc_is_am437x()) {
 225                 cpu_name =  "AM437x";
 226         } else if (cpu_is_ti814x()) {
 227                 cpu_name = "TI814X";
 228         } else if (omap3_has_iva() && omap3_has_sgx()) {
 229                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
 230                 cpu_name = "OMAP3430/3530";
 231         } else if (omap3_has_iva()) {
 232                 cpu_name = "OMAP3525";
 233         } else if (omap3_has_sgx()) {
 234                 cpu_name = "OMAP3515";
 235         } else {
 236                 cpu_name = "OMAP3503";
 237         }
 238
 239         sprintf(soc_name, "%s", cpu_name);
 240
 241         /* Print verbose information */
 242         pr_info("%s %s (", soc_name, soc_rev);
 243
 244         OMAP3_SHOW_FEATURE(l2cache);
 245         OMAP3_SHOW_FEATURE(iva);
 246         OMAP3_SHOW_FEATURE(sgx);
 247         OMAP3_SHOW_FEATURE(neon);
 248         OMAP3_SHOW_FEATURE(isp);
 249         OMAP3_SHOW_FEATURE(192mhz_clk);
 250
 251         printk(")\n");
 252 }
 253
 254 #define OMAP3_CHECK_FEATURE(status,feat)                                \
 255         if (((status & OMAP3_ ##feat## _MASK)                           \
 256                 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
 257                 omap_features |= OMAP3_HAS_ ##feat;                     \
 258         }
 259
 260 void __init omap3xxx_check_features(void)
 261 {
 262         u32 status;
 263
 264         omap_features = 0;
 265
 266         status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
 267
 268         OMAP3_CHECK_FEATURE(status, L2CACHE);
 269         OMAP3_CHECK_FEATURE(status, IVA);
 270         OMAP3_CHECK_FEATURE(status, SGX);
 271         OMAP3_CHECK_FEATURE(status, NEON);
 272         OMAP3_CHECK_FEATURE(status, ISP);
 273         if (cpu_is_omap3630())
 274                 omap_features |= OMAP3_HAS_192MHZ_CLK;
 275         if (cpu_is_omap3430() || cpu_is_omap3630())
 276                 omap_features |= OMAP3_HAS_IO_WAKEUP;
 277         if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
 278             omap_rev() == OMAP3430_REV_ES3_1_2)
 279                 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
 280
 281         omap_features |= OMAP3_HAS_SDRC;
 282
 283         /*
 284          * am35x fixups:
 285          * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
 286          *   reserved and therefore return 0 when read.  Unfortunately,
 287          *   OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
 288          *   mean that a feature is present even though it isn't so clear
 289          *   the incorrectly set feature bits.
 290          */
 291         if (soc_is_am35xx())
 292                 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
 293
 294         /*
 295          * TODO: Get additional info (where applicable)
 296          *       e.g. Size of L2 cache.
 297          */
 298
 299         omap3_cpuinfo();
 300 }
 301
 302 void __init omap4xxx_check_features(void)
 303 {
 304         u32 si_type;
 305
 306         si_type =
 307         (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
 308
 309         if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
 310                 omap_features = OMAP4_HAS_PERF_SILICON;
 311 }
 312
 313 void __init ti81xx_check_features(void)
 314 {
 315         omap_features = OMAP3_HAS_NEON;
 316         omap3_cpuinfo();
 317 }
 318
 319 void __init am33xx_check_features(void)
 320 {
 321         u32 status;
 322
 323         omap_features = OMAP3_HAS_NEON;
 324
 325         status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
 326         if (status & AM33XX_SGX_MASK)
 327                 omap_features |= OMAP3_HAS_SGX;
 328
 329         omap3_cpuinfo();
 330 }
 331
 332 void __init omap3xxx_check_revision(void)
 333 {
 334         const char *cpu_rev;
 335         u32 cpuid, idcode;
 336         u16 hawkeye;
 337         u8 rev;
 338
 339         /*
 340          * We cannot access revision registers on ES1.0.
 341          * If the processor type is Cortex-A8 and the revision is 0x0
 342          * it means its Cortex r0p0 which is 3430 ES1.0.
 343          */
 344         cpuid = read_cpuid_id();
 345         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
 346                 omap_revision = OMAP3430_REV_ES1_0;
 347                 cpu_rev = "1.0";
 348                 return;
 349         }
 350
 351         /*
 352          * Detection for 34xx ES2.0 and above can be done with just
 353          * hawkeye and rev. See TRM 1.5.2 Device Identification.
 354          * Note that rev does not map directly to our defined processor
 355          * revision numbers as ES1.0 uses value 0.
 356          */
 357         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 358         hawkeye = (idcode >> 12) & 0xffff;
 359         rev = (idcode >> 28) & 0xff;
 360
 361         switch (hawkeye) {
 362         case 0xb7ae:
 363                 /* Handle 34xx/35xx devices */
 364                 switch (rev) {
 365                 case 0: /* Take care of early samples */
 366                 case 1:
 367                         omap_revision = OMAP3430_REV_ES2_0;
 368                         cpu_rev = "2.0";
 369                         break;
 370                 case 2:
 371                         omap_revision = OMAP3430_REV_ES2_1;
 372                         cpu_rev = "2.1";
 373                         break;
 374                 case 3:
 375                         omap_revision = OMAP3430_REV_ES3_0;
 376                         cpu_rev = "3.0";
 377                         break;
 378                 case 4:
 379                         omap_revision = OMAP3430_REV_ES3_1;
 380                         cpu_rev = "3.1";
 381                         break;
 382                 case 7:
 383                 /* FALLTHROUGH */
 384                 default:
 385                         /* Use the latest known revision as default */
 386                         omap_revision = OMAP3430_REV_ES3_1_2;
 387                         cpu_rev = "3.1.2";
 388                 }
 389                 break;
 390         case 0xb868:
 391                 /*
 392                  * Handle OMAP/AM 3505/3517 devices
 393                  *
 394                  * Set the device to be OMAP3517 here. Actual device
 395                  * is identified later based on the features.
 396                  */
 397                 switch (rev) {
 398                 case 0:
 399                         omap_revision = AM35XX_REV_ES1_0;
 400                         cpu_rev = "1.0";
 401                         break;
 402                 case 1:
 403                 /* FALLTHROUGH */
 404                 default:
 405                         omap_revision = AM35XX_REV_ES1_1;
 406                         cpu_rev = "1.1";
 407                 }
 408                 break;
 409         case 0xb891:
 410                 /* Handle 36xx devices */
 411
 412                 switch(rev) {
 413                 case 0: /* Take care of early samples */
 414                         omap_revision = OMAP3630_REV_ES1_0;
 415                         cpu_rev = "1.0";
 416                         break;
 417                 case 1:
 418                         omap_revision = OMAP3630_REV_ES1_1;
 419                         cpu_rev = "1.1";
 420                         break;
 421                 case 2:
 422                 /* FALLTHROUGH */
 423                 default:
 424                         omap_revision = OMAP3630_REV_ES1_2;
 425                         cpu_rev = "1.2";
 426                 }
 427                 break;
 428         case 0xb81e:
 429                 switch (rev) {
 430                 case 0:
 431                         omap_revision = TI8168_REV_ES1_0;
 432                         cpu_rev = "1.0";
 433                         break;
 434                 case 1:
 435                         omap_revision = TI8168_REV_ES1_1;
 436                         cpu_rev = "1.1";
 437                         break;
 438                 case 2:
 439                         omap_revision = TI8168_REV_ES2_0;
 440                         cpu_rev = "2.0";
 441                         break;
 442                 case 3:
 443                         /* FALLTHROUGH */
 444                 default:
 445                         omap_revision = TI8168_REV_ES2_1;
 446                         cpu_rev = "2.1";
 447                 }
 448                 break;
 449         case 0xb944:
 450                 switch (rev) {
 451                 case 0:
 452                         omap_revision = AM335X_REV_ES1_0;
 453                         cpu_rev = "1.0";
 454                         break;
 455                 case 1:
 456                         omap_revision = AM335X_REV_ES2_0;
 457                         cpu_rev = "2.0";
 458                         break;
 459                 case 2:
 460                 /* FALLTHROUGH */
 461                 default:
 462                         omap_revision = AM335X_REV_ES2_1;
 463                         cpu_rev = "2.1";
 464                         break;
 465                 }
 466                 break;
 467         case 0xb98c:
 468                 switch (rev) {
 469                 case 0:
 470                         omap_revision = AM437X_REV_ES1_0;
 471                         cpu_rev = "1.0";
 472                         break;
 473                 case 1:
 474                         omap_revision = AM437X_REV_ES1_1;
 475                         cpu_rev = "1.1";
 476                         break;
 477                 case 2:
 478                 /* FALLTHROUGH */
 479                 default:
 480                         omap_revision = AM437X_REV_ES1_2;
 481                         cpu_rev = "1.2";
 482                         break;
 483                 }
 484                 break;
 485         case 0xb8f2:
 486                 switch (rev) {
 487                 case 0:
 488                 /* FALLTHROUGH */
 489                 case 1:
 490                         omap_revision = TI8148_REV_ES1_0;
 491                         cpu_rev = "1.0";
 492                         break;
 493                 case 2:
 494                         omap_revision = TI8148_REV_ES2_0;
 495                         cpu_rev = "2.0";
 496                         break;
 497                 case 3:
 498                 /* FALLTHROUGH */
 499                 default:
 500                         omap_revision = TI8148_REV_ES2_1;
 501                         cpu_rev = "2.1";
 502                         break;
 503                 }
 504                 break;
 505         default:
 506                 /* Unknown default to latest silicon rev as default */
 507                 omap_revision = OMAP3630_REV_ES1_2;
 508                 cpu_rev = "1.2";
 509                 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
 510         }
 511         sprintf(soc_rev, "ES%s", cpu_rev);
 512 }
 513
 514 void __init omap4xxx_check_revision(void)
 515 {
 516         u32 idcode;
 517         u16 hawkeye;
 518         u8 rev;
 519
 520         /*
 521          * The IC rev detection is done with hawkeye and rev.
 522          * Note that rev does not map directly to defined processor
 523          * revision numbers as ES1.0 uses value 0.
 524          */
 525         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 526         hawkeye = (idcode >> 12) & 0xffff;
 527         rev = (idcode >> 28) & 0xf;
 528
 529         /*
 530          * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
 531          * Use ARM register to detect the correct ES version
 532          */
 533         if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
 534                 idcode = read_cpuid_id();
 535                 rev = (idcode & 0xf) - 1;
 536         }
 537
 538         switch (hawkeye) {
 539         case 0xb852:
 540                 switch (rev) {
 541                 case 0:
 542                         omap_revision = OMAP4430_REV_ES1_0;
 543                         break;
 544                 case 1:
 545                 default:
 546                         omap_revision = OMAP4430_REV_ES2_0;
 547                 }
 548                 break;
 549         case 0xb95c:
 550                 switch (rev) {
 551                 case 3:
 552                         omap_revision = OMAP4430_REV_ES2_1;
 553                         break;
 554                 case 4:
 555                         omap_revision = OMAP4430_REV_ES2_2;
 556                         break;
 557                 case 6:
 558                 default:
 559                         omap_revision = OMAP4430_REV_ES2_3;
 560                 }
 561                 break;
 562         case 0xb94e:
 563                 switch (rev) {
 564                 case 0:
 565                         omap_revision = OMAP4460_REV_ES1_0;
 566                         break;
 567                 case 2:
 568                 default:
 569                         omap_revision = OMAP4460_REV_ES1_1;
 570                         break;
 571                 }
 572                 break;
 573         case 0xb975:
 574                 switch (rev) {
 575                 case 0:
 576                 default:
 577                         omap_revision = OMAP4470_REV_ES1_0;
 578                         break;
 579                 }
 580                 break;
 581         default:
 582                 /* Unknown default to latest silicon rev as default */
 583                 omap_revision = OMAP4430_REV_ES2_3;
 584         }
 585
 586         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 587         sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
 588                                                 (omap_rev() >> 8) & 0xf);
 589         pr_info("%s %s\n", soc_name, soc_rev);
 590 }
 591
 592 void __init omap5xxx_check_revision(void)
 593 {
 594         u32 idcode;
 595         u16 hawkeye;
 596         u8 rev;
 597
 598         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 599         hawkeye = (idcode >> 12) & 0xffff;
 600         rev = (idcode >> 28) & 0xff;
 601         switch (hawkeye) {
 602         case 0xb942:
 603                 switch (rev) {
 604                 case 0:
 605                         /* No support for ES1.0 Test chip */
 606                         BUG();
 607                 case 1:
 608                 default:
 609                         omap_revision = OMAP5430_REV_ES2_0;
 610                 }
 611                 break;
 612
 613         case 0xb998:
 614                 switch (rev) {
 615                 case 0:
 616                         /* No support for ES1.0 Test chip */
 617                         BUG();
 618                 case 1:
 619                 default:
 620                         omap_revision = OMAP5432_REV_ES2_0;
 621                 }
 622                 break;
 623
 624         default:
 625                 /* Unknown default to latest silicon rev as default*/
 626                 omap_revision = OMAP5430_REV_ES2_0;
 627         }
 628
 629         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 630         sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
 631
 632         pr_info("%s %s\n", soc_name, soc_rev);
 633 }
 634
 635 void __init dra7xxx_check_revision(void)
 636 {
 637         u32 idcode;
 638         u16 hawkeye;
 639         u8 rev;
 640
 641         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 642         hawkeye = (idcode >> 12) & 0xffff;
 643         rev = (idcode >> 28) & 0xff;
 644         switch (hawkeye) {
 645         case 0xb990:
 646                 switch (rev) {
 647                 case 0:
 648                         omap_revision = DRA752_REV_ES1_0;
 649                         break;
 650                 case 1:
 651                 default:
 652                         omap_revision = DRA752_REV_ES1_1;
 653                 }
 654                 break;
 655
 656         case 0xb9bc:
 657                 switch (rev) {
 658                 case 0:
 659                         omap_revision = DRA722_REV_ES1_0;
 660                         break;
 661                 default:
 662                         /* If we have no new revisions */
 663                         omap_revision = DRA722_REV_ES1_0;
 664                         break;
 665                 }
 666                 break;
 667
 668         default:
 669                 /* Unknown default to latest silicon rev as default*/
 670                 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n",
 671                         __func__, idcode, hawkeye, rev);
 672                 omap_revision = DRA752_REV_ES1_1;
 673         }
 674
 675         sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
 676         sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
 677                 (omap_rev() >> 8) & 0xf);
 678
 679         pr_info("%s %s\n", soc_name, soc_rev);
 680 }
 681
 682 /*
 683  * Set up things for map_io and processor detection later on. Gets called
 684  * pretty much first thing from board init. For multi-omap, this gets
 685  * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 686  * detect the exact revision later on in omap2_detect_revision() once map_io
 687  * is done.
 688  */
 689 void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
 690 {
 691         omap_revision = class;
 692         tap_base = tap;
 693
 694         /* XXX What is this intended to do? */
 695         if (cpu_is_omap34xx())
 696                 tap_prod_id = 0x0210;
 697         else
 698                 tap_prod_id = 0x0208;
 699 }
 700
 701 #ifdef CONFIG_SOC_BUS
 702
 703 static const char * const omap_types[] = {
 704         [OMAP2_DEVICE_TYPE_TEST]        = "TST",
 705         [OMAP2_DEVICE_TYPE_EMU]         = "EMU",
 706         [OMAP2_DEVICE_TYPE_SEC]         = "HS",
 707         [OMAP2_DEVICE_TYPE_GP]          = "GP",
 708         [OMAP2_DEVICE_TYPE_BAD]         = "BAD",
 709 };
 710
 711 static const char * __init omap_get_family(void)
 712 {
 713         if (cpu_is_omap24xx())
 714                 return kasprintf(GFP_KERNEL, "OMAP2");
 715         else if (cpu_is_omap34xx())
 716                 return kasprintf(GFP_KERNEL, "OMAP3");
 717         else if (cpu_is_omap44xx())
 718                 return kasprintf(GFP_KERNEL, "OMAP4");
 719         else if (soc_is_omap54xx())
 720                 return kasprintf(GFP_KERNEL, "OMAP5");
 721         else if (soc_is_am43xx())
 722                 return kasprintf(GFP_KERNEL, "AM43xx");
 723         else if (soc_is_dra7xx())
 724                 return kasprintf(GFP_KERNEL, "DRA7");
 725         else
 726                 return kasprintf(GFP_KERNEL, "Unknown");
 727 }
 728
 729 static ssize_t omap_get_type(struct device *dev,
 730                                         struct device_attribute *attr,
 731                                         char *buf)
 732 {
 733         return sprintf(buf, "%s\n", omap_types[omap_type()]);
 734 }
 735
 736 static struct device_attribute omap_soc_attr =
 737         __ATTR(type,  S_IRUGO, omap_get_type,  NULL);
 738
 739 void __init omap_soc_device_init(void)
 740 {
 741         struct device *parent;
 742         struct soc_device *soc_dev;
 743         struct soc_device_attribute *soc_dev_attr;
 744
 745         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 746         if (!soc_dev_attr)
 747                 return;
 748
 749         soc_dev_attr->machine  = soc_name;
 750         soc_dev_attr->family   = omap_get_family();
 751         soc_dev_attr->revision = soc_rev;
 752
 753         soc_dev = soc_device_register(soc_dev_attr);
 754         if (IS_ERR(soc_dev)) {
 755                 kfree(soc_dev_attr);
 756                 return;
 757         }
 758
 759         parent = soc_device_to_device(soc_dev);
 760         device_create_file(parent, &omap_soc_attr);
 761 }
 762 #endif /* CONFIG_SOC_BUS */