1 /*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
12 *
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
25 #include <asm/tlb.h>
26 #include <asm/mach/map.h>
28 #include <linux/omap-dma.h>
30 #include "omap_hwmod.h"
31 #include "soc.h"
32 #include "iomap.h"
33 #include "voltage.h"
34 #include "powerdomain.h"
35 #include "clockdomain.h"
36 #include "common.h"
37 #include "clock.h"
38 #include "clock2xxx.h"
39 #include "clock3xxx.h"
40 #include "clock44xx.h"
41 #include "clock54xx.h"
42 #include "clock7xx.h"
43 #include "omap-pm.h"
44 #include "sdrc.h"
45 #include "control.h"
46 #include "serial.h"
47 #include "sram.h"
48 #include "cm2xxx.h"
49 #include "cm3xxx.h"
50 #include "prm.h"
51 #include "cm.h"
52 #include "prcm_mpu44xx.h"
53 #include "prminst44xx.h"
54 #include "cminst44xx.h"
55 #include "prm2xxx.h"
56 #include "prm3xxx.h"
57 #include "prm44xx.h"
59 /*
60 * omap_clk_init: points to a function that does the SoC-specific
61 * clock initializations
62 */
63 int (*omap_clk_init)(void);
65 /*
66 * The machine specific code may provide the extra mapping besides the
67 * default mapping provided here.
68 */
70 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
71 static struct map_desc omap24xx_io_desc[] __initdata = {
72 {
73 .virtual = L3_24XX_VIRT,
74 .pfn = __phys_to_pfn(L3_24XX_PHYS),
75 .length = L3_24XX_SIZE,
76 .type = MT_DEVICE
77 },
78 {
79 .virtual = L4_24XX_VIRT,
80 .pfn = __phys_to_pfn(L4_24XX_PHYS),
81 .length = L4_24XX_SIZE,
82 .type = MT_DEVICE
83 },
84 };
86 #ifdef CONFIG_SOC_OMAP2420
87 static struct map_desc omap242x_io_desc[] __initdata = {
88 {
89 .virtual = DSP_MEM_2420_VIRT,
90 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
91 .length = DSP_MEM_2420_SIZE,
92 .type = MT_DEVICE
93 },
94 {
95 .virtual = DSP_IPI_2420_VIRT,
96 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
97 .length = DSP_IPI_2420_SIZE,
98 .type = MT_DEVICE
99 },
100 {
101 .virtual = DSP_MMU_2420_VIRT,
102 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
103 .length = DSP_MMU_2420_SIZE,
104 .type = MT_DEVICE
105 },
106 };
108 #endif
110 #ifdef CONFIG_SOC_OMAP2430
111 static struct map_desc omap243x_io_desc[] __initdata = {
112 {
113 .virtual = L4_WK_243X_VIRT,
114 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
115 .length = L4_WK_243X_SIZE,
116 .type = MT_DEVICE
117 },
118 {
119 .virtual = OMAP243X_GPMC_VIRT,
120 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
121 .length = OMAP243X_GPMC_SIZE,
122 .type = MT_DEVICE
123 },
124 {
125 .virtual = OMAP243X_SDRC_VIRT,
126 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
127 .length = OMAP243X_SDRC_SIZE,
128 .type = MT_DEVICE
129 },
130 {
131 .virtual = OMAP243X_SMS_VIRT,
132 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
133 .length = OMAP243X_SMS_SIZE,
134 .type = MT_DEVICE
135 },
136 };
137 #endif
138 #endif
140 #ifdef CONFIG_ARCH_OMAP3
141 static struct map_desc omap34xx_io_desc[] __initdata = {
142 {
143 .virtual = L3_34XX_VIRT,
144 .pfn = __phys_to_pfn(L3_34XX_PHYS),
145 .length = L3_34XX_SIZE,
146 .type = MT_DEVICE
147 },
148 {
149 .virtual = L4_34XX_VIRT,
150 .pfn = __phys_to_pfn(L4_34XX_PHYS),
151 .length = L4_34XX_SIZE,
152 .type = MT_DEVICE
153 },
154 {
155 .virtual = OMAP34XX_GPMC_VIRT,
156 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
157 .length = OMAP34XX_GPMC_SIZE,
158 .type = MT_DEVICE
159 },
160 {
161 .virtual = OMAP343X_SMS_VIRT,
162 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
163 .length = OMAP343X_SMS_SIZE,
164 .type = MT_DEVICE
165 },
166 {
167 .virtual = OMAP343X_SDRC_VIRT,
168 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
169 .length = OMAP343X_SDRC_SIZE,
170 .type = MT_DEVICE
171 },
172 {
173 .virtual = L4_PER_34XX_VIRT,
174 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
175 .length = L4_PER_34XX_SIZE,
176 .type = MT_DEVICE
177 },
178 {
179 .virtual = L4_EMU_34XX_VIRT,
180 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
181 .length = L4_EMU_34XX_SIZE,
182 .type = MT_DEVICE
183 },
184 #if defined(CONFIG_DEBUG_LL) && \
185 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
186 {
187 .virtual = ZOOM_UART_VIRT,
188 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
189 .length = SZ_1M,
190 .type = MT_DEVICE
191 },
192 #endif
193 };
194 #endif
196 #ifdef CONFIG_SOC_TI81XX
197 static struct map_desc omapti81xx_io_desc[] __initdata = {
198 {
199 .virtual = L4_34XX_VIRT,
200 .pfn = __phys_to_pfn(L4_34XX_PHYS),
201 .length = L4_34XX_SIZE,
202 .type = MT_DEVICE
203 }
204 };
205 #endif
207 #ifdef CONFIG_SOC_AM33XX
208 static struct map_desc omapam33xx_io_desc[] __initdata = {
209 {
210 .virtual = L4_34XX_VIRT,
211 .pfn = __phys_to_pfn(L4_34XX_PHYS),
212 .length = L4_34XX_SIZE,
213 .type = MT_DEVICE
214 },
215 {
216 .virtual = L4_WK_AM33XX_VIRT,
217 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
218 .length = L4_WK_AM33XX_SIZE,
219 .type = MT_DEVICE
220 }
221 };
222 #endif
224 #ifdef CONFIG_ARCH_OMAP4
225 static struct map_desc omap44xx_io_desc[] __initdata = {
226 {
227 .virtual = L3_44XX_VIRT,
228 .pfn = __phys_to_pfn(L3_44XX_PHYS),
229 .length = L3_44XX_SIZE,
230 .type = MT_DEVICE,
231 },
232 {
233 .virtual = L4_44XX_VIRT,
234 .pfn = __phys_to_pfn(L4_44XX_PHYS),
235 .length = L4_44XX_SIZE,
236 .type = MT_DEVICE,
237 },
238 {
239 .virtual = L4_PER_44XX_VIRT,
240 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
241 .length = L4_PER_44XX_SIZE,
242 .type = MT_DEVICE,
243 },
244 #ifdef CONFIG_OMAP4_ERRATA_I688
245 {
246 .virtual = OMAP4_ERRATA_I688_SRAM_VA,
247 .pfn = __phys_to_pfn(OMAP4_ERRATA_I688_SRAM_PA),
248 .length = OMAP4_ERRATA_I688_SIZE,
249 .type = MT_MEMORY_SO,
250 },
251 #endif
253 };
254 #endif
256 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
257 static struct map_desc omap54xx_io_desc[] __initdata = {
258 {
259 .virtual = L3_54XX_VIRT,
260 .pfn = __phys_to_pfn(L3_54XX_PHYS),
261 .length = L3_54XX_SIZE,
262 .type = MT_DEVICE,
263 },
264 {
265 .virtual = L4_54XX_VIRT,
266 .pfn = __phys_to_pfn(L4_54XX_PHYS),
267 .length = L4_54XX_SIZE,
268 .type = MT_DEVICE,
269 },
270 {
271 .virtual = L4_WK_54XX_VIRT,
272 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
273 .length = L4_WK_54XX_SIZE,
274 .type = MT_DEVICE,
275 },
276 {
277 .virtual = L4_PER_54XX_VIRT,
278 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
279 .length = L4_PER_54XX_SIZE,
280 .type = MT_DEVICE,
281 },
282 #ifdef CONFIG_OMAP4_ERRATA_I688
283 {
284 .virtual = OMAP5_ERRATA_I688_SRAM_VA,
285 .pfn = __phys_to_pfn(OMAP5_ERRATA_I688_SRAM_PA),
286 .length = OMAP4_ERRATA_I688_SIZE,
287 .type = MT_MEMORY_SO,
288 },
289 #endif
290 };
291 #endif
293 #ifdef CONFIG_SOC_OMAP2420
294 void __init omap242x_map_io(void)
295 {
296 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
297 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
298 }
299 #endif
301 #ifdef CONFIG_SOC_OMAP2430
302 void __init omap243x_map_io(void)
303 {
304 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
305 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
306 }
307 #endif
309 #ifdef CONFIG_ARCH_OMAP3
310 void __init omap3_map_io(void)
311 {
312 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
313 }
314 #endif
316 #ifdef CONFIG_SOC_TI81XX
317 void __init ti81xx_map_io(void)
318 {
319 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
320 }
321 #endif
323 #ifdef CONFIG_SOC_AM33XX
324 void __init am33xx_map_io(void)
325 {
326 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
327 }
328 #endif
330 #ifdef CONFIG_ARCH_OMAP4
331 void __init omap4_map_io(void)
332 {
333 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
334 omap_barriers_init();
335 }
336 #endif
338 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
339 void __init omap5_map_io(void)
340 {
341 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
342 omap_barriers_init();
343 }
344 #endif
345 /*
346 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
347 *
348 * Sets the CORE DPLL3 M2 divider to the same value that it's at
349 * currently. This has the effect of setting the SDRC SDRAM AC timing
350 * registers to the values currently defined by the kernel. Currently
351 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
352 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
353 * or passes along the return value of clk_set_rate().
354 */
355 static int __init _omap2_init_reprogram_sdrc(void)
356 {
357 struct clk *dpll3_m2_ck;
358 int v = -EINVAL;
359 long rate;
361 if (!cpu_is_omap34xx())
362 return 0;
364 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
365 if (IS_ERR(dpll3_m2_ck))
366 return -EINVAL;
368 rate = clk_get_rate(dpll3_m2_ck);
369 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
370 v = clk_set_rate(dpll3_m2_ck, rate);
371 if (v)
372 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
374 clk_put(dpll3_m2_ck);
376 return v;
377 }
379 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
380 {
381 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
382 }
384 static void __init omap_hwmod_init_postsetup(void)
385 {
386 u8 postsetup_state;
388 /* Set the default postsetup state for all hwmods */
389 #ifdef CONFIG_PM_RUNTIME
390 postsetup_state = _HWMOD_STATE_IDLE;
391 #else
392 postsetup_state = _HWMOD_STATE_ENABLED;
393 #endif
394 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
396 omap_pm_if_early_init();
397 }
399 #ifdef CONFIG_SOC_OMAP2420
400 void __init omap2420_init_early(void)
401 {
402 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
403 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
404 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
405 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
406 NULL);
407 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
408 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
409 omap2xxx_check_revision();
410 omap2xxx_prm_init();
411 omap2xxx_cm_init();
412 omap2xxx_voltagedomains_init();
413 omap242x_powerdomains_init();
414 omap242x_clockdomains_init();
415 omap2420_hwmod_init();
416 omap_hwmod_init_postsetup();
417 omap_clk_init = omap2420_clk_init;
418 }
420 void __init omap2420_init_late(void)
421 {
422 omap_mux_late_init();
423 omap2_common_pm_late_init();
424 omap2_pm_init();
425 omap2_clk_enable_autoidle_all();
426 }
427 #endif
429 #ifdef CONFIG_SOC_OMAP2430
430 void __init omap2430_init_early(void)
431 {
432 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
433 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
434 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
435 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
436 NULL);
437 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
438 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
439 omap2xxx_check_revision();
440 omap2xxx_prm_init();
441 omap2xxx_cm_init();
442 omap2xxx_voltagedomains_init();
443 omap243x_powerdomains_init();
444 omap243x_clockdomains_init();
445 omap2430_hwmod_init();
446 omap_hwmod_init_postsetup();
447 omap_clk_init = omap2430_clk_init;
448 }
450 void __init omap2430_init_late(void)
451 {
452 omap_mux_late_init();
453 omap2_common_pm_late_init();
454 omap2_pm_init();
455 omap2_clk_enable_autoidle_all();
456 }
457 #endif
459 /*
460 * Currently only board-omap3beagle.c should call this because of the
461 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
462 */
463 #ifdef CONFIG_ARCH_OMAP3
464 void __init omap3_init_early(void)
465 {
466 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
467 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
468 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
469 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
470 NULL);
471 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
472 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
473 omap3xxx_check_revision();
474 omap3xxx_check_features();
475 omap3xxx_prm_init();
476 omap3xxx_cm_init();
477 omap3xxx_voltagedomains_init();
478 omap3xxx_powerdomains_init();
479 omap3xxx_clockdomains_init();
480 omap3xxx_hwmod_init();
481 omap_hwmod_init_postsetup();
482 omap_clk_init = omap3xxx_clk_init;
483 }
485 void __init omap3430_init_early(void)
486 {
487 omap3_init_early();
488 }
490 void __init omap35xx_init_early(void)
491 {
492 omap3_init_early();
493 }
495 void __init omap3630_init_early(void)
496 {
497 omap3_init_early();
498 }
500 void __init am35xx_init_early(void)
501 {
502 omap3_init_early();
503 }
505 void __init ti81xx_init_early(void)
506 {
507 omap2_set_globals_tap(OMAP343X_CLASS,
508 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
509 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
510 NULL);
511 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
512 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
513 omap3xxx_check_revision();
514 ti81xx_check_features();
515 omap3xxx_voltagedomains_init();
516 omap3xxx_powerdomains_init();
517 omap3xxx_clockdomains_init();
518 omap3xxx_hwmod_init();
519 omap_hwmod_init_postsetup();
520 omap_clk_init = omap3xxx_clk_init;
521 }
523 void __init omap3_init_late(void)
524 {
525 omap_mux_late_init();
526 omap2_common_pm_late_init();
527 omap3_pm_init();
528 omap2_clk_enable_autoidle_all();
529 }
531 void __init omap3430_init_late(void)
532 {
533 omap_mux_late_init();
534 omap2_common_pm_late_init();
535 omap3_pm_init();
536 omap2_clk_enable_autoidle_all();
537 }
539 void __init omap35xx_init_late(void)
540 {
541 omap_mux_late_init();
542 omap2_common_pm_late_init();
543 omap3_pm_init();
544 omap2_clk_enable_autoidle_all();
545 }
547 void __init omap3630_init_late(void)
548 {
549 omap_mux_late_init();
550 omap2_common_pm_late_init();
551 omap3_pm_init();
552 omap2_clk_enable_autoidle_all();
553 }
555 void __init am35xx_init_late(void)
556 {
557 omap_mux_late_init();
558 omap2_common_pm_late_init();
559 omap3_pm_init();
560 omap2_clk_enable_autoidle_all();
561 }
563 void __init ti81xx_init_late(void)
564 {
565 omap_mux_late_init();
566 omap2_common_pm_late_init();
567 omap3_pm_init();
568 omap2_clk_enable_autoidle_all();
569 }
570 #endif
572 #ifdef CONFIG_SOC_AM33XX
573 void __init am33xx_init_early(void)
574 {
575 omap2_set_globals_tap(AM335X_CLASS,
576 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
577 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
578 NULL);
579 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
580 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
581 omap3xxx_check_revision();
582 am33xx_check_features();
583 am33xx_voltagedomains_init();
584 am33xx_powerdomains_init();
585 am33xx_clockdomains_init();
586 am33xx_hwmod_init();
587 omap_hwmod_init_postsetup();
588 omap_clk_init = am33xx_clk_init;
589 }
591 void __init am33xx_init_late(void)
592 {
593 omap_mux_late_init();
594 omap2_common_pm_late_init();
595 am33xx_pm_init();
596 }
597 #endif
599 #ifdef CONFIG_ARCH_OMAP4
600 void __init omap4430_init_early(void)
601 {
602 omap2_set_globals_tap(OMAP443X_CLASS,
603 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
604 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
605 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
606 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
607 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
608 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
609 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
610 omap_prm_base_init();
611 omap_cm_base_init();
612 omap4xxx_check_revision();
613 omap4xxx_check_features();
614 omap44xx_prm_init();
615 omap44xx_voltagedomains_init();
616 omap44xx_powerdomains_init();
617 omap44xx_clockdomains_init();
618 omap44xx_hwmod_init();
619 omap_hwmod_init_postsetup();
620 omap_clk_init = omap4xxx_clk_init;
621 }
623 void __init omap4430_init_late(void)
624 {
625 omap_mux_late_init();
626 omap2_common_pm_late_init();
627 omap4_pm_init();
628 omap2_clk_enable_autoidle_all();
629 }
630 #endif
632 #ifdef CONFIG_SOC_OMAP5
633 void __init omap5_init_early(void)
634 {
635 omap2_set_globals_tap(OMAP54XX_CLASS,
636 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
637 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
638 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
639 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
640 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
641 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
642 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
643 omap_prm_base_init();
644 omap_cm_base_init();
645 omap44xx_prm_init();
646 omap5xxx_check_revision();
647 omap54xx_voltagedomains_init();
648 omap54xx_powerdomains_init();
649 omap54xx_clockdomains_init();
650 omap54xx_hwmod_init();
651 omap_hwmod_init_postsetup();
652 omap5xxx_clk_init();
654 }
656 void __init omap5_init_late(void)
657 {
658 omap_mux_late_init();
659 omap2_common_pm_late_init();
660 omap4_pm_init();
661 omap2_clk_enable_autoidle_all();
662 }
663 #endif
665 #ifdef CONFIG_SOC_DRA7XX
666 void __init dra7xx_init_early(void)
667 {
668 omap2_set_globals_tap(DRA7XX_CLASS,
669 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
670 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
671 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
672 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
673 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
674 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
675 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
676 omap_prm_base_init();
677 omap_cm_base_init();
678 dra7xx_check_revision();
679 omap44xx_prm_init();
680 dra7xx_powerdomains_init();
681 dra7xx_clockdomains_init();
682 dra7xx_hwmod_init();
683 omap_hwmod_init_postsetup();
684 dra7xx_clk_init();
685 }
687 void __init dra7xx_init_late(void)
688 {
689 omap2_common_pm_late_init();
690 omap4_pm_init();
691 omap2_clk_enable_autoidle_all();
692 }
693 #endif
695 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
696 struct omap_sdrc_params *sdrc_cs1)
697 {
698 omap_sram_init();
700 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
701 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
702 _omap2_init_reprogram_sdrc();
703 }
704 }