1 /*
2 * linux/arch/arm/mach-omap2/irq.c
3 *
4 * Interrupt handler for OMAP2 boards.
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
19 #include <asm/exception.h>
20 #include <asm/mach/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
26 #include "soc.h"
27 #include "iomap.h"
28 #include "common.h"
30 /* selected INTC register offsets */
32 #define INTC_REVISION 0x0000
33 #define INTC_SYSCONFIG 0x0010
34 #define INTC_SYSSTATUS 0x0014
35 #define INTC_SIR 0x0040
36 #define INTC_CONTROL 0x0048
37 #define INTC_PROTECTION 0x004C
38 #define INTC_IDLE 0x0050
39 #define INTC_THRESHOLD 0x0068
40 #define INTC_MIR0 0x0084
41 #define INTC_MIR_CLEAR0 0x0088
42 #define INTC_MIR_SET0 0x008c
43 #define INTC_PENDING_IRQ0 0x0098
44 /* Number of IRQ state bits in each MIR register */
45 #define IRQ_BITS_PER_REG 32
47 #define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
48 #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
49 #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
50 #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
51 /*
52 * Max from AM33XX device
53 */
54 #define INTCPS_MAX_NR_REGS_REQ 4
55 #define INTCPS_MAX_NR_IRQS 128
58 /*
59 * OMAP2 has a number of different interrupt controllers, each interrupt
60 * controller is identified as its own "bank". Register definitions are
61 * fairly consistent for each bank, but not all registers are implemented
62 * for each bank.. when in doubt, consult the TRM.
63 */
64 static struct omap_irq_bank {
65 void __iomem *base_reg;
66 unsigned int nr_irqs;
67 unsigned int nr_regs_req;
68 } __attribute__ ((aligned(4))) irq_banks[] = {
69 {
70 /* MPU INTC */
71 .nr_irqs = 96,
72 .nr_regs_req = 3,
73 },
74 };
76 static struct irq_domain *domain;
78 /* Structure to save interrupt controller context */
79 struct omap3_intc_regs {
80 u32 sysconfig;
81 u32 protection;
82 u32 idle;
83 u32 threshold;
84 u32 ilr[INTCPS_MAX_NR_IRQS];
85 u32 mir[INTCPS_MAX_NR_REGS_REQ];
86 };
88 /* INTC bank register get/set */
90 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
91 {
92 __raw_writel(val, bank->base_reg + reg);
93 }
95 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
96 {
97 return __raw_readl(bank->base_reg + reg);
98 }
100 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
101 static void omap_ack_irq(struct irq_data *d)
102 {
103 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
104 }
106 static void omap_mask_ack_irq(struct irq_data *d)
107 {
108 irq_gc_mask_disable_reg(d);
109 omap_ack_irq(d);
110 }
112 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
113 {
114 unsigned long tmp;
116 tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
117 pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
118 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
120 tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
121 tmp |= 1 << 1; /* soft reset */
122 intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
124 while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
125 /* Wait for reset to complete */;
127 /* Enable autoidle */
128 intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
129 }
131 int omap_irq_pending(void)
132 {
133 int i;
135 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
136 struct omap_irq_bank *bank = irq_banks + i;
137 int irq;
139 for (irq = 0; irq < bank->nr_irqs; irq += 32)
140 if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
141 ((irq >> 5) << 5)))
142 return 1;
143 }
144 return 0;
145 }
147 static __init void
148 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
149 {
150 struct irq_chip_generic *gc;
151 struct irq_chip_type *ct;
153 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
154 handle_level_irq);
155 ct = gc->chip_types;
156 ct->chip.irq_ack = omap_mask_ack_irq;
157 ct->chip.irq_mask = irq_gc_mask_disable_reg;
158 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
159 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
161 ct->regs.enable = INTC_MIR_CLEAR0;
162 ct->regs.disable = INTC_MIR_SET0;
163 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
164 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
165 }
167 static void __init omap_init_irq(u32 base, int nr_irqs,
168 struct device_node *node)
169 {
170 void __iomem *omap_irq_base;
171 unsigned long nr_of_irqs = 0;
172 unsigned int nr_banks = 0;
173 int i, j, irq_base;
175 omap_irq_base = ioremap(base, SZ_4K);
176 if (WARN_ON(!omap_irq_base))
177 return;
179 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
180 if (irq_base < 0) {
181 pr_warn("Couldn't allocate IRQ numbers\n");
182 irq_base = 0;
183 }
185 domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
186 &irq_domain_simple_ops, NULL);
188 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
189 struct omap_irq_bank *bank = irq_banks + i;
191 bank->nr_irqs = nr_irqs;
192 bank->nr_regs_req = 0;
194 /* Static mapping, never released */
195 bank->base_reg = ioremap(base, SZ_4K);
196 if (!bank->base_reg) {
197 pr_err("Could not ioremap irq bank%i\n", i);
198 continue;
199 }
201 omap_irq_bank_init_one(bank);
203 for (j = 0; j < bank->nr_irqs; j += 32) {
204 omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
205 bank->nr_regs_req++;
206 }
207 nr_of_irqs += bank->nr_irqs;
208 nr_banks++;
209 }
211 pr_info("Total of %ld interrupts on %d active controller%s\n",
212 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
213 }
215 void __init omap2_init_irq(void)
216 {
217 omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
218 }
220 void __init omap3_init_irq(void)
221 {
222 omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
223 }
225 void __init ti81xx_init_irq(void)
226 {
227 omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
228 }
230 static inline void omap_intc_handle_irq(void __iomem *base_addr,
231 unsigned int no_regs_req, struct pt_regs *regs)
232 {
233 u32 irqnr = 0;
235 do {
236 int i = 0;
238 for (i = 0; i < no_regs_req; i++) {
239 irqnr = readl_relaxed(base_addr + 0x98 + (0x20 * i));
240 if (irqnr)
241 goto out;
242 }
244 out:
245 if (!irqnr)
246 break;
248 irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
249 irqnr &= ACTIVEIRQ_MASK;
251 if (irqnr) {
252 irqnr = irq_find_mapping(domain, irqnr);
253 handle_IRQ(irqnr, regs);
254 }
255 } while (irqnr);
256 }
258 asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
259 {
260 void __iomem *base_addr = OMAP2_IRQ_BASE;
261 omap_intc_handle_irq(base_addr, irq_banks[0].nr_regs_req, regs);
262 }
264 int __init intc_of_init(struct device_node *node,
265 struct device_node *parent)
266 {
267 struct resource res;
268 u32 nr_irq = 96;
270 if (WARN_ON(!node))
271 return -ENODEV;
273 if (of_address_to_resource(node, 0, &res)) {
274 WARN(1, "unable to get intc registers\n");
275 return -EINVAL;
276 }
278 if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
279 pr_warn("unable to get intc-size, default to %d\n", nr_irq);
281 omap_init_irq(res.start, nr_irq, of_node_get(node));
283 return 0;
284 }
286 static struct of_device_id irq_match[] __initdata = {
287 { .compatible = "ti,omap2-intc", .data = intc_of_init, },
288 { }
289 };
291 void __init omap_intc_of_init(void)
292 {
293 of_irq_init(irq_match);
294 }
296 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
297 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
299 void omap_intc_save_context(void)
300 {
301 int ind = 0, i = 0;
302 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
303 struct omap_irq_bank *bank = irq_banks + ind;
304 intc_context[ind].sysconfig =
305 intc_bank_read_reg(bank, INTC_SYSCONFIG);
306 intc_context[ind].protection =
307 intc_bank_read_reg(bank, INTC_PROTECTION);
308 intc_context[ind].idle =
309 intc_bank_read_reg(bank, INTC_IDLE);
310 intc_context[ind].threshold =
311 intc_bank_read_reg(bank, INTC_THRESHOLD);
312 for (i = 0; i < bank->nr_irqs; i++)
313 intc_context[ind].ilr[i] =
314 intc_bank_read_reg(bank, (0x100 + 0x4*i));
315 for (i = 0; i < bank->nr_regs_req; i++)
316 intc_context[ind].mir[i] =
317 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
318 (0x20 * i));
319 }
320 }
322 void omap_intc_restore_context(void)
323 {
324 int ind = 0, i = 0;
326 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
327 struct omap_irq_bank *bank = irq_banks + ind;
328 intc_bank_write_reg(intc_context[ind].sysconfig,
329 bank, INTC_SYSCONFIG);
330 intc_bank_write_reg(intc_context[ind].sysconfig,
331 bank, INTC_SYSCONFIG);
332 intc_bank_write_reg(intc_context[ind].protection,
333 bank, INTC_PROTECTION);
334 intc_bank_write_reg(intc_context[ind].idle,
335 bank, INTC_IDLE);
336 intc_bank_write_reg(intc_context[ind].threshold,
337 bank, INTC_THRESHOLD);
338 for (i = 0; i < bank->nr_irqs; i++)
339 intc_bank_write_reg(intc_context[ind].ilr[i],
340 bank, (0x100 + 0x4*i));
341 for (i = 0; i < bank->nr_regs_req; i++)
342 intc_bank_write_reg(intc_context[ind].mir[i],
343 &irq_banks[0], INTC_MIR0 + (0x20 * i));
344 }
345 /* MIRs are saved and restore with other PRCM registers */
346 }
348 void omap3_intc_suspend(void)
349 {
350 /* A pending interrupt would prevent OMAP from entering suspend */
351 omap_ack_irq(NULL);
352 }
354 void omap3_intc_prepare_idle(void)
355 {
356 /*
357 * Disable autoidle as it can stall interrupt controller,
358 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
359 */
360 intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
361 }
363 void omap3_intc_resume_idle(void)
364 {
365 /* Re-enable autoidle */
366 intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
367 }
369 asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
370 {
371 void __iomem *base_addr = OMAP3_IRQ_BASE;
372 omap_intc_handle_irq(base_addr, irq_banks[0].nr_regs_req, regs);
373 }
374 #endif /* CONFIG_ARCH_OMAP3 */