ARM: OMAP5/DRA7: hwmod: add ADDR_TYPE_RT to bb2d address flags
[android-sdk/kernel-video.git] / arch / arm / mach-omap2 / omap_hwmod_54xx_data.c
1 /*
2  * Hardware modules present on the OMAP54xx chips
3  *
4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5  *
6  * Paul Walmsley
7  * Benoit Cousson
8  *
9  * This file is automatically generated from the OMAP hardware databases.
10  * We respectfully ask that any modifications to this file be coordinated
11  * with the public linux-omap@vger.kernel.org mailing list and the
12  * authors above to ensure that the autogeneration scripts are kept
13  * up-to-date with the file contents.
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License version 2 as
17  * published by the Free Software Foundation.
18  */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/platform_data/omap_ocp2scp.h>
24 #include <linux/i2c-omap.h>
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <linux/platform_data/mailbox-omap.h>
30 #include <plat/dmtimer.h>
32 #include "omap_hwmod.h"
33 #include "omap_hwmod_common_data.h"
34 #include "cm1_54xx.h"
35 #include "cm2_54xx.h"
36 #include "prm54xx.h"
37 #include "prm-regbits-54xx.h"
38 #include "i2c.h"
39 #include "mmc.h"
40 #include "wd_timer.h"
42 /* Base offset for all OMAP5 interrupts external to MPUSS */
43 #define OMAP54XX_IRQ_GIC_START  32
45 /* Base offset for all OMAP5 dma requests */
46 #define OMAP54XX_DMA_REQ_START  1
48 /* Backward references (IPs with Bus Master capability) */
49 static struct omap_hwmod omap54xx_bb2d_hwmod;
52 /*
53  * IP blocks
54  */
56 /*
57  * 'dmm' class
58  * instance(s): dmm
59  */
60 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
61         .name   = "dmm",
62 };
64 /* dmm */
65 static struct omap_hwmod_irq_info omap54xx_dmm_irqs[] = {
66         { .irq = 113 + OMAP54XX_IRQ_GIC_START },
67         { .irq = -1 }
68 };
70 static struct omap_hwmod omap54xx_dmm_hwmod = {
71         .name           = "dmm",
72         .class          = &omap54xx_dmm_hwmod_class,
73         .clkdm_name     = "emif_clkdm",
74         .mpu_irqs       = omap54xx_dmm_irqs,
75         .prcm = {
76                 .omap4 = {
77                         .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
78                         .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
79                 },
80         },
81 };
83 /*
84  * 'emif_ocp_fw' class
85  * instance(s): emif_ocp_fw
86  */
87 static struct omap_hwmod_class omap54xx_emif_ocp_fw_hwmod_class = {
88         .name   = "emif_ocp_fw",
89 };
91 /* emif_ocp_fw */
92 static struct omap_hwmod omap54xx_emif_ocp_fw_hwmod = {
93         .name           = "emif_ocp_fw",
94         .class          = &omap54xx_emif_ocp_fw_hwmod_class,
95         .clkdm_name     = "emif_clkdm",
96         .prcm = {
97                 .omap4 = {
98                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
99                         .context_offs = OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
100                 },
101         },
102 };
104 /*
105  * 'l3' class
106  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
107  */
108 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
109         .name   = "l3",
110 };
112 /* l3_instr */
113 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
114         .name           = "l3_instr",
115         .class          = &omap54xx_l3_hwmod_class,
116         .clkdm_name     = "l3instr_clkdm",
117         .prcm = {
118                 .omap4 = {
119                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
120                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
121                         .modulemode   = MODULEMODE_HWCTRL,
122                 },
123         },
124 };
126 /* l3_main_1 */
127 static struct omap_hwmod_irq_info omap54xx_l3_main_1_irqs[] = {
128         { .name = "dbg_err", .irq = 9 + OMAP54XX_IRQ_GIC_START },
129         { .name = "app_err", .irq = 10 + OMAP54XX_IRQ_GIC_START },
130         { .name = "stat_alarm", .irq = 16 + OMAP54XX_IRQ_GIC_START },
131         { .irq = -1 }
132 };
134 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
135         .name           = "l3_main_1",
136         .class          = &omap54xx_l3_hwmod_class,
137         .clkdm_name     = "l3main1_clkdm",
138         .mpu_irqs       = omap54xx_l3_main_1_irqs,
139         .prcm = {
140                 .omap4 = {
141                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
142                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
143                 },
144         },
145 };
147 /* l3_main_2 */
148 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
149         .name           = "l3_main_2",
150         .class          = &omap54xx_l3_hwmod_class,
151         .clkdm_name     = "l3main2_clkdm",
152         .prcm = {
153                 .omap4 = {
154                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
155                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
156                 },
157         },
158 };
160 /* l3_main_3 */
161 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
162         .name           = "l3_main_3",
163         .class          = &omap54xx_l3_hwmod_class,
164         .clkdm_name     = "l3instr_clkdm",
165         .prcm = {
166                 .omap4 = {
167                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
168                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
169                         .modulemode   = MODULEMODE_HWCTRL,
170                 },
171         },
172 };
174 /*
175  * 'l4' class
176  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
177  */
178 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
179         .name   = "l4",
180 };
182 /* l4_abe */
183 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
184         .name           = "l4_abe",
185         .class          = &omap54xx_l4_hwmod_class,
186         .clkdm_name     = "abe_clkdm",
187         .prcm = {
188                 .omap4 = {
189                         .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
190                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
191                 },
192         },
193 };
195 /* l4_cfg */
196 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
197         .name           = "l4_cfg",
198         .class          = &omap54xx_l4_hwmod_class,
199         .clkdm_name     = "l4cfg_clkdm",
200         .prcm = {
201                 .omap4 = {
202                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
203                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
204                 },
205         },
206 };
208 /* l4_per */
209 static struct omap_hwmod omap54xx_l4_per_hwmod = {
210         .name           = "l4_per",
211         .class          = &omap54xx_l4_hwmod_class,
212         .clkdm_name     = "l4per_clkdm",
213         .prcm = {
214                 .omap4 = {
215                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
216                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
217                 },
218         },
219 };
221 /* l4_wkup */
222 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
223         .name           = "l4_wkup",
224         .class          = &omap54xx_l4_hwmod_class,
225         .clkdm_name     = "wkupaon_clkdm",
226         .prcm = {
227                 .omap4 = {
228                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
229                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
230                 },
231         },
232 };
234 /*
235  * 'mpu_bus' class
236  * instance(s): mpu_private
237  */
238 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
239         .name   = "mpu_bus",
240 };
242 /* mpu_private */
243 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
244         .name           = "mpu_private",
245         .class          = &omap54xx_mpu_bus_hwmod_class,
246         .clkdm_name     = "mpu_clkdm",
247         .prcm = {
248                 .omap4 = {
249                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
250                 },
251         },
252 };
254 /*
255  * 'ocp_wp_noc' class
256  * instance(s): ocp_wp_noc
257  */
258 static struct omap_hwmod_class omap54xx_ocp_wp_noc_hwmod_class = {
259         .name   = "ocp_wp_noc",
260 };
262 /* ocp_wp_noc */
263 static struct omap_hwmod omap54xx_ocp_wp_noc_hwmod = {
264         .name           = "ocp_wp_noc",
265         .class          = &omap54xx_ocp_wp_noc_hwmod_class,
266         .clkdm_name     = "l3instr_clkdm",
267         .prcm = {
268                 .omap4 = {
269                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET,
270                         .context_offs = OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET,
271                         .modulemode   = MODULEMODE_HWCTRL,
272                 },
273         },
274 };
276 /*
277  * 'aess' class
278  * audio engine sub system
279  */
281 static struct omap_hwmod_class_sysconfig omap54xx_aess_sysc = {
282         .rev_offs       = 0x0000,
283         .sysc_offs      = 0x0010,
284         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
285         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
286                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
287                            MSTANDBY_SMART_WKUP),
288         .sysc_fields    = &omap_hwmod_sysc_type2,
289 };
291 static struct omap_hwmod_class omap54xx_aess_hwmod_class = {
292         .name   = "aess",
293         .sysc   = &omap54xx_aess_sysc,
294 };
296 /* aess */
297 static struct omap_hwmod_irq_info omap54xx_aess_irqs[] = {
298         { .irq = 99 + OMAP54XX_IRQ_GIC_START },
299         { .irq = -1 }
300 };
302 static struct omap_hwmod_dma_info omap54xx_aess_sdma_reqs[] = {
303         { .name = "fifo0", .dma_req = 100 + OMAP54XX_DMA_REQ_START },
304         { .name = "fifo1", .dma_req = 101 + OMAP54XX_DMA_REQ_START },
305         { .name = "fifo2", .dma_req = 102 + OMAP54XX_DMA_REQ_START },
306         { .name = "fifo3", .dma_req = 103 + OMAP54XX_DMA_REQ_START },
307         { .name = "fifo4", .dma_req = 104 + OMAP54XX_DMA_REQ_START },
308         { .name = "fifo5", .dma_req = 105 + OMAP54XX_DMA_REQ_START },
309         { .name = "fifo6", .dma_req = 106 + OMAP54XX_DMA_REQ_START },
310         { .name = "fifo7", .dma_req = 107 + OMAP54XX_DMA_REQ_START },
311         { .dma_req = -1 }
312 };
314 static struct omap_hwmod omap54xx_aess_hwmod = {
315         .name           = "aess",
316         .class          = &omap54xx_aess_hwmod_class,
317         .clkdm_name     = "abe_clkdm",
318         .mpu_irqs       = omap54xx_aess_irqs,
319         .sdma_reqs      = omap54xx_aess_sdma_reqs,
320         .main_clk       = "aess_fclk",
321         .prcm = {
322                 .omap4 = {
323                         .clkctrl_offs = OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET,
324                         .context_offs = OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET,
325                         .modulemode   = MODULEMODE_SWCTRL,
326                 },
327         },
328 };
330 /*
331  * 'bb2d' class
332  * bit blit 2d accelerator
333  */
335 static struct omap_hwmod_class omap54xx_bb2d_hwmod_class = {
336         .name   = "bb2d",
337 };
339 /* bb2d */
340 static struct omap_hwmod_irq_info omap54xx_bb2d_irqs[] = {
341         { .irq = 125 + OMAP54XX_IRQ_GIC_START },
342         { .irq = -1 }
343 };
345 static struct omap_hwmod_addr_space omap54xx_bb2d_addrs[] = {
346         {
347                 .pa_start       = 0x59000000,
348                 .pa_end         = 0x590007ff,
349                 .flags      = ADDR_TYPE_RT
350         },
351         { }
352 };
354 /* l3_main_2 -> bb2d */
355 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__bb2d = {
356         .master         = &omap54xx_l3_main_2_hwmod,
357         .slave          = &omap54xx_bb2d_hwmod,
358         .clk            = "l3_iclk_div",
359         .addr           = omap54xx_bb2d_addrs,
360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
361 };
363 static struct omap_hwmod omap54xx_bb2d_hwmod = {
364         .name           = "bb2d",
365         .class          = &omap54xx_bb2d_hwmod_class,
366         .clkdm_name     = "dss_clkdm",
367         .mpu_irqs       = omap54xx_bb2d_irqs,
368         .main_clk       = "dpll_core_h24x2_ck",
369         .prcm = {
370                 .omap4 = {
371                         .clkctrl_offs = OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
372                         .context_offs = OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET,
373                         .modulemode   = MODULEMODE_SWCTRL,
374                 },
375         },
376 };
378 /*
379  * 'c2c' class
380  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
381  * soc
382  */
384 static struct omap_hwmod_class_sysconfig omap54xx_c2c_sysc = {
385         .rev_offs       = 0x0000,
386         .syss_offs      = 0x0008,
387         .sysc_flags     = SYSS_HAS_RESET_STATUS,
388 };
390 static struct omap_hwmod_class omap54xx_c2c_hwmod_class = {
391         .name   = "c2c",
392         .sysc   = &omap54xx_c2c_sysc,
393 };
395 /* c2c */
396 static struct omap_hwmod_irq_info omap54xx_c2c_irqs[] = {
397         { .irq = 88 + OMAP54XX_IRQ_GIC_START },
398         { .irq = -1 }
399 };
401 static struct omap_hwmod_dma_info omap54xx_c2c_sdma_reqs[] = {
402         { .dma_req = 68 + OMAP54XX_DMA_REQ_START },
403         { .dma_req = -1 }
404 };
406 static struct omap_hwmod omap54xx_c2c_hwmod = {
407         .name           = "c2c",
408         .class          = &omap54xx_c2c_hwmod_class,
409         .clkdm_name     = "c2c_clkdm",
410         .mpu_irqs       = omap54xx_c2c_irqs,
411         .sdma_reqs      = omap54xx_c2c_sdma_reqs,
412         .main_clk       = "c2c_fclk",
413         .prcm = {
414                 .omap4 = {
415                         .clkctrl_offs = OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET,
416                         .context_offs = OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET,
417                 },
418         },
419 };
421 /*
422  * 'counter' class
423  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
424  */
426 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
427         .rev_offs       = 0x0000,
428         .sysc_offs      = 0x0010,
429         .sysc_flags     = SYSC_HAS_SIDLEMODE,
430         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
431         .sysc_fields    = &omap_hwmod_sysc_type1,
432 };
434 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
435         .name   = "counter",
436         .sysc   = &omap54xx_counter_sysc,
437 };
439 /* counter_32k */
440 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
441         .name           = "counter_32k",
442         .class          = &omap54xx_counter_hwmod_class,
443         .clkdm_name     = "wkupaon_clkdm",
444         .flags          = HWMOD_SWSUP_SIDLE,
445         .main_clk       = "wkupaon_iclk_mux",
446         .prcm = {
447                 .omap4 = {
448                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
449                         .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
450                 },
451         },
452 };
454 /*
455  * 'ctrl_module' class
456  * omap5430 core control module + omap5430 wkup control module
457  */
459 static struct omap_hwmod_class_sysconfig omap54xx_ctrl_module_sysc = {
460         .rev_offs       = 0x0000,
461 };
463 static struct omap_hwmod_class omap54xx_ctrl_module_hwmod_class = {
464         .name   = "ctrl_module",
465         .sysc   = &omap54xx_ctrl_module_sysc,
466 };
468 /* ctrl_module_core */
469 static struct omap_hwmod_irq_info omap54xx_ctrl_module_core_irqs[] = {
470         { .name = "sec_evts", .irq = 8 + OMAP54XX_IRQ_GIC_START },
471         { .name = "thermal_alert", .irq = 126 + OMAP54XX_IRQ_GIC_START },
472         { .irq = -1 }
473 };
475 static struct omap_hwmod omap54xx_ctrl_module_core_hwmod = {
476         .name           = "ctrl_module_core",
477         .class          = &omap54xx_ctrl_module_hwmod_class,
478         .clkdm_name     = "l4cfg_clkdm",
479         .mpu_irqs       = omap54xx_ctrl_module_core_irqs,
480         .prcm = {
481                 .omap4 = {
482                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
483                 },
484         },
485 };
487 /* ctrl_module_wkup */
488 static struct omap_hwmod omap54xx_ctrl_module_wkup_hwmod = {
489         .name           = "ctrl_module_wkup",
490         .class          = &omap54xx_ctrl_module_hwmod_class,
491         .clkdm_name     = "wkupaon_clkdm",
492         .prcm = {
493                 .omap4 = {
494                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
495                 },
496         },
497 };
499 /*
500  * 'dma' class
501  * dma controller for data exchange between memory to memory (i.e. internal or
502  * external memory) and gp peripherals to memory or memory to gp peripherals
503  */
505 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
506         .rev_offs       = 0x0000,
507         .sysc_offs      = 0x002c,
508         .syss_offs      = 0x0028,
509         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
510                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
511                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
512                            SYSS_HAS_RESET_STATUS),
513         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
514                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
515         .sysc_fields    = &omap_hwmod_sysc_type1,
516 };
518 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
519         .name   = "dma",
520         .sysc   = &omap54xx_dma_sysc,
521 };
523 /* dma dev_attr */
524 static struct omap_dma_dev_attr dma_dev_attr = {
525         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
526                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
527         .lch_count      = 32,
528 };
530 /* dma_system */
531 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
532         { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
533         { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
534         { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
535         { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
536         { .irq = -1 }
537 };
539 static struct omap_hwmod omap54xx_dma_system_hwmod = {
540         .name           = "dma_system",
541         .class          = &omap54xx_dma_hwmod_class,
542         .clkdm_name     = "dma_clkdm",
543         .mpu_irqs       = omap54xx_dma_system_irqs,
544         .main_clk       = "l3_iclk_div",
545         .prcm = {
546                 .omap4 = {
547                         .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
548                         .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
549                 },
550         },
551         .dev_attr       = &dma_dev_attr,
552 };
554 /*
555  * 'dmic' class
556  * digital microphone controller
557  */
559 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
560         .rev_offs       = 0x0000,
561         .sysc_offs      = 0x0010,
562         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
563                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
564         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
565                            SIDLE_SMART_WKUP),
566         .sysc_fields    = &omap_hwmod_sysc_type2,
567 };
569 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
570         .name   = "dmic",
571         .sysc   = &omap54xx_dmic_sysc,
572 };
574 /* dmic */
575 static struct omap_hwmod_irq_info omap54xx_dmic_irqs[] = {
576         { .irq = 114 + OMAP54XX_IRQ_GIC_START },
577         { .irq = -1 }
578 };
580 static struct omap_hwmod_dma_info omap54xx_dmic_sdma_reqs[] = {
581         { .dma_req = 66 + OMAP54XX_DMA_REQ_START },
582         { .dma_req = -1 }
583 };
585 static struct omap_hwmod omap54xx_dmic_hwmod = {
586         .name           = "dmic",
587         .class          = &omap54xx_dmic_hwmod_class,
588         .clkdm_name     = "abe_clkdm",
589         .mpu_irqs       = omap54xx_dmic_irqs,
590         .sdma_reqs      = omap54xx_dmic_sdma_reqs,
591         .main_clk       = "dmic_gfclk",
592         .prcm = {
593                 .omap4 = {
594                         .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
595                         .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
596                         .modulemode   = MODULEMODE_SWCTRL,
597                 },
598         },
599 };
601 /*
602  * 'dsp' class
603  * dsp sub-system
604  */
606 static struct omap_hwmod_class omap54xx_dsp_hwmod_class = {
607         .name   = "dsp",
608 };
610 /* dsp */
611 static struct omap_hwmod_irq_info omap54xx_dsp_irqs[] = {
612         { .irq = 28 + OMAP54XX_IRQ_GIC_START },
613         { .irq = -1 }
614 };
616 static struct omap_hwmod_rst_info omap54xx_dsp_resets[] = {
617         { .name = "dsp", .rst_shift = 0 },
618         { .name = "mmu_cache", .rst_shift = 1 },
619 };
621 static struct omap_hwmod omap54xx_dsp_hwmod = {
622         .name           = "dsp",
623         .class          = &omap54xx_dsp_hwmod_class,
624         .clkdm_name     = "dsp_clkdm",
625         .mpu_irqs       = omap54xx_dsp_irqs,
626         .rst_lines      = omap54xx_dsp_resets,
627         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_dsp_resets),
628         .main_clk       = "dpll_iva_h11x2_ck",
629         .prcm = {
630                 .omap4 = {
631                         .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
632                         .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
633                         .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
634                         .modulemode   = MODULEMODE_HWCTRL,
635                 },
636         },
637 };
639 /*
640  * 'dss' class
641  * display sub-system
642  */
644 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
645         .rev_offs       = 0x0000,
646         .syss_offs      = 0x0014,
647         .sysc_flags     = SYSS_HAS_RESET_STATUS,
648 };
650 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
651         .name   = "dss",
652         .sysc   = &omap54xx_dss_sysc,
653         .reset  = omap_dss_reset,
654 };
656 /* dss */
657 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
658         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
659         { .role = "sys_clk", .clk = "dss_sys_clk" },
660         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
661 };
663 static struct omap_hwmod omap54xx_dss_hwmod = {
664         .name           = "dss_core",
665         .class          = &omap54xx_dss_hwmod_class,
666         .clkdm_name     = "dss_clkdm",
667         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
668         .main_clk       = "dss_dss_clk",
669         .prcm = {
670                 .omap4 = {
671                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
672                         .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
673                         .modulemode   = MODULEMODE_SWCTRL,
674                 },
675         },
676         .opt_clks       = dss_opt_clks,
677         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
678 };
680 /*
681  * 'dispc' class
682  * display controller
683  */
685 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
686         .rev_offs       = 0x0000,
687         .sysc_offs      = 0x0010,
688         .syss_offs      = 0x0014,
689         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
690                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
691                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
692                            SYSS_HAS_RESET_STATUS),
693         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
694                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
695         .sysc_fields    = &omap_hwmod_sysc_type1,
696 };
698 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
699         .name   = "dispc",
700         .sysc   = &omap54xx_dispc_sysc,
701 };
703 /* dss_dispc */
704 static struct omap_hwmod_irq_info omap54xx_dss_dispc_irqs[] = {
705         { .irq = 25 + OMAP54XX_IRQ_GIC_START },
706         { .irq = -1 }
707 };
709 static struct omap_hwmod_dma_info omap54xx_dss_dispc_sdma_reqs[] = {
710         { .dma_req = 5 + OMAP54XX_DMA_REQ_START },
711         { .dma_req = -1 }
712 };
714 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
715         { .role = "sys_clk", .clk = "dss_sys_clk" },
716 };
718 /* dss_dispc dev_attr */
719 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
720         .has_framedonetv_irq    = 1,
721         .manager_count          = 4,
722 };
724 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
725         .name           = "dss_dispc",
726         .class          = &omap54xx_dispc_hwmod_class,
727         .clkdm_name     = "dss_clkdm",
728         .mpu_irqs       = omap54xx_dss_dispc_irqs,
729         .sdma_reqs      = omap54xx_dss_dispc_sdma_reqs,
730         .main_clk       = "dss_dss_clk",
731         .prcm = {
732                 .omap4 = {
733                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
734                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
735                 },
736         },
737         .opt_clks       = dss_dispc_opt_clks,
738         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
739         .dev_attr       = &dss_dispc_dev_attr,
740 };
742 /*
743  * 'dsi1' class
744  * display serial interface controller
745  */
747 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
748         .rev_offs       = 0x0000,
749         .sysc_offs      = 0x0010,
750         .syss_offs      = 0x0014,
751         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
752                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
753                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
754         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
755         .sysc_fields    = &omap_hwmod_sysc_type1,
756 };
758 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
759         .name   = "dsi1",
760         .sysc   = &omap54xx_dsi1_sysc,
761 };
763 /* dss_dsi1_a */
764 static struct omap_hwmod_irq_info omap54xx_dss_dsi1_a_irqs[] = {
765         { .irq = 53 + OMAP54XX_IRQ_GIC_START },
766         { .irq = -1 }
767 };
769 static struct omap_hwmod_dma_info omap54xx_dss_dsi1_a_sdma_reqs[] = {
770         { .dma_req = 74 + OMAP54XX_DMA_REQ_START },
771         { .dma_req = -1 }
772 };
774 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
775         { .role = "sys_clk", .clk = "dss_sys_clk" },
776 };
778 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
779         .name           = "dss_dsi1_a",
780         .class          = &omap54xx_dsi1_hwmod_class,
781         .clkdm_name     = "dss_clkdm",
782         .mpu_irqs       = omap54xx_dss_dsi1_a_irqs,
783         .sdma_reqs      = omap54xx_dss_dsi1_a_sdma_reqs,
784         .main_clk       = "dss_dss_clk",
785         .prcm = {
786                 .omap4 = {
787                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
788                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
789                 },
790         },
791         .opt_clks       = dss_dsi1_a_opt_clks,
792         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_a_opt_clks),
793 };
795 /* dss_dsi1_b */
796 static struct omap_hwmod omap54xx_dss_dsi1_b_hwmod = {
797         .name           = "dss_dsi1_b",
798         .class          = &omap54xx_dsi1_hwmod_class,
799         .clkdm_name     = "dss_clkdm",
800         .main_clk       = "dss_dss_clk",
801         .prcm = {
802                 .omap4 = {
803                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
804                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
805                 },
806         },
807 };
809 /* dss_dsi1_c */
810 static struct omap_hwmod_irq_info omap54xx_dss_dsi1_c_irqs[] = {
811         { .irq = 55 + OMAP54XX_IRQ_GIC_START },
812         { .irq = -1 }
813 };
815 static struct omap_hwmod_dma_info omap54xx_dss_dsi1_c_sdma_reqs[] = {
816         { .dma_req = 83 + OMAP54XX_DMA_REQ_START },
817         { .dma_req = -1 }
818 };
820 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
821         { .role = "sys_clk", .clk = "dss_sys_clk" },
822 };
824 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
825         .name           = "dss_dsi1_c",
826         .class          = &omap54xx_dsi1_hwmod_class,
827         .clkdm_name     = "dss_clkdm",
828         .mpu_irqs       = omap54xx_dss_dsi1_c_irqs,
829         .sdma_reqs      = omap54xx_dss_dsi1_c_sdma_reqs,
830         .main_clk       = "dss_dss_clk",
831         .prcm = {
832                 .omap4 = {
833                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
834                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
835                 },
836         },
837         .opt_clks       = dss_dsi1_c_opt_clks,
838         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_c_opt_clks),
839 };
841 /*
842  * 'hdmi' class
843  * hdmi controller
844  */
846 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
847         .rev_offs       = 0x0000,
848         .sysc_offs      = 0x0010,
849         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
850                            SYSC_HAS_SOFTRESET),
851         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
852                            SIDLE_SMART_WKUP),
853         .sysc_fields    = &omap_hwmod_sysc_type2,
854 };
856 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
857         .name   = "hdmi",
858         .sysc   = &omap54xx_hdmi_sysc,
859 };
861 /* dss_hdmi */
862 static struct omap_hwmod_irq_info omap54xx_dss_hdmi_irqs[] = {
863         { .irq = 101 + OMAP54XX_IRQ_GIC_START },
864         { .irq = -1 }
865 };
867 static struct omap_hwmod_dma_info omap54xx_dss_hdmi_sdma_reqs[] = {
868         { .dma_req = 75 + OMAP54XX_DMA_REQ_START },
869         { .dma_req = -1 }
870 };
872 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
873         { .role = "sys_clk", .clk = "dss_sys_clk" },
874 };
876 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
877         .name           = "dss_hdmi",
878         .class          = &omap54xx_hdmi_hwmod_class,
879         .clkdm_name     = "dss_clkdm",
880         .mpu_irqs       = omap54xx_dss_hdmi_irqs,
881         .sdma_reqs      = omap54xx_dss_hdmi_sdma_reqs,
882         .main_clk       = "dss_48mhz_clk",
883         .prcm = {
884                 .omap4 = {
885                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
886                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
887                 },
888         },
889         .opt_clks       = dss_hdmi_opt_clks,
890         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
891 };
893 /*
894  * 'rfbi' class
895  * remote frame buffer interface
896  */
898 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
899         .rev_offs       = 0x0000,
900         .sysc_offs      = 0x0010,
901         .syss_offs      = 0x0014,
902         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
903                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
904         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
905         .sysc_fields    = &omap_hwmod_sysc_type1,
906 };
908 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
909         .name   = "rfbi",
910         .sysc   = &omap54xx_rfbi_sysc,
911 };
913 /* dss_rfbi */
914 static struct omap_hwmod_dma_info omap54xx_dss_rfbi_sdma_reqs[] = {
915         { .dma_req = 13 + OMAP54XX_DMA_REQ_START },
916         { .dma_req = -1 }
917 };
919 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
920         { .role = "ick", .clk = "l3_iclk_div" },
921 };
923 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
924         .name           = "dss_rfbi",
925         .class          = &omap54xx_rfbi_hwmod_class,
926         .clkdm_name     = "dss_clkdm",
927         .sdma_reqs      = omap54xx_dss_rfbi_sdma_reqs,
928         .prcm = {
929                 .omap4 = {
930                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
931                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
932                 },
933         },
934         .opt_clks       = dss_rfbi_opt_clks,
935         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
936 };
938 /*
939  * 'elm' class
940  * bch error location module
941  */
943 static struct omap_hwmod_class_sysconfig omap54xx_elm_sysc = {
944         .rev_offs       = 0x0000,
945         .sysc_offs      = 0x0010,
946         .syss_offs      = 0x0014,
947         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
948                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
949                            SYSS_HAS_RESET_STATUS),
950         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
951         .sysc_fields    = &omap_hwmod_sysc_type1,
952 };
954 static struct omap_hwmod_class omap54xx_elm_hwmod_class = {
955         .name   = "elm",
956         .sysc   = &omap54xx_elm_sysc,
957 };
959 /* elm */
960 static struct omap_hwmod_irq_info omap54xx_elm_irqs[] = {
961         { .irq = 4 + OMAP54XX_IRQ_GIC_START },
962         { .irq = -1 }
963 };
965 static struct omap_hwmod omap54xx_elm_hwmod = {
966         .name           = "elm",
967         .class          = &omap54xx_elm_hwmod_class,
968         .clkdm_name     = "l4per_clkdm",
969         .mpu_irqs       = omap54xx_elm_irqs,
970         .main_clk       = "l4_root_clk_div",
971         .prcm = {
972                 .omap4 = {
973                         .clkctrl_offs = OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
974                         .context_offs = OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET,
975                 },
976         },
977 };
979 /*
980  * 'emif' class
981  * external memory interface no1 (wrapper)
982  */
984 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
985         .rev_offs       = 0x0000,
986 };
988 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
989         .name   = "emif",
990         .sysc   = &omap54xx_emif_sysc,
991 };
993 /* emif1 */
994 static struct omap_hwmod_irq_info omap54xx_emif1_irqs[] = {
995         { .irq = 110 + OMAP54XX_IRQ_GIC_START },
996         { .irq = -1 }
997 };
999 static struct omap_hwmod omap54xx_emif1_hwmod = {
1000         .name           = "emif1",
1001         .class          = &omap54xx_emif_hwmod_class,
1002         .clkdm_name     = "emif_clkdm",
1003         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1004         .mpu_irqs       = omap54xx_emif1_irqs,
1005         .main_clk       = "dpll_core_h11x2_ck",
1006         .prcm = {
1007                 .omap4 = {
1008                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
1009                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
1010                         .modulemode   = MODULEMODE_HWCTRL,
1011                 },
1012         },
1013 };
1015 /* emif2 */
1016 static struct omap_hwmod_irq_info omap54xx_emif2_irqs[] = {
1017         { .irq = 111 + OMAP54XX_IRQ_GIC_START },
1018         { .irq = -1 }
1019 };
1021 static struct omap_hwmod omap54xx_emif2_hwmod = {
1022         .name           = "emif2",
1023         .class          = &omap54xx_emif_hwmod_class,
1024         .clkdm_name     = "emif_clkdm",
1025         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1026         .mpu_irqs       = omap54xx_emif2_irqs,
1027         .main_clk       = "dpll_core_h11x2_ck",
1028         .prcm = {
1029                 .omap4 = {
1030                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
1031                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
1032                         .modulemode   = MODULEMODE_HWCTRL,
1033                 },
1034         },
1035 };
1037 /*
1038  * 'fdif' class
1039  * face detection hw accelerator module
1040  */
1042 static struct omap_hwmod_class_sysconfig omap54xx_fdif_sysc = {
1043         .rev_offs       = 0x0000,
1044         .sysc_offs      = 0x0010,
1045         /*
1046          * FDIF needs 100 OCP clk cycles delay after a softreset before
1047          * accessing sysconfig again.
1048          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1049          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1050          *
1051          * TODO: Indicate errata when available.
1052          */
1053         .srst_udelay    = 2,
1054         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1055                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1056         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1057                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1058         .sysc_fields    = &omap_hwmod_sysc_type2,
1059 };
1061 static struct omap_hwmod_class omap54xx_fdif_hwmod_class = {
1062         .name   = "fdif",
1063         .sysc   = &omap54xx_fdif_sysc,
1064 };
1066 /* fdif */
1067 static struct omap_hwmod_irq_info omap54xx_fdif_irqs[] = {
1068         { .irq = 69 + OMAP54XX_IRQ_GIC_START },
1069         { .irq = -1 }
1070 };
1072 static struct omap_hwmod omap54xx_fdif_hwmod = {
1073         .name           = "fdif",
1074         .class          = &omap54xx_fdif_hwmod_class,
1075         .clkdm_name     = "cam_clkdm",
1076         .mpu_irqs       = omap54xx_fdif_irqs,
1077         .main_clk       = "fdif_fclk",
1078         .prcm = {
1079                 .omap4 = {
1080                         .clkctrl_offs = OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET,
1081                         .context_offs = OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET,
1082                         .modulemode   = MODULEMODE_SWCTRL,
1083                 },
1084         },
1085 };
1087 /*
1088  * 'gpio' class
1089  * general purpose io module
1090  */
1092 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
1093         .rev_offs       = 0x0000,
1094         .sysc_offs      = 0x0010,
1095         .syss_offs      = 0x0114,
1096         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1097                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1098                            SYSS_HAS_RESET_STATUS),
1099         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1100                            SIDLE_SMART_WKUP),
1101         .sysc_fields    = &omap_hwmod_sysc_type1,
1102 };
1104 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
1105         .name   = "gpio",
1106         .sysc   = &omap54xx_gpio_sysc,
1107         .rev    = 2,
1108 };
1110 /* gpio dev_attr */
1111 static struct omap_gpio_dev_attr gpio_dev_attr = {
1112         .bank_width     = 32,
1113         .dbck_flag      = true,
1114 };
1116 /* gpio1 */
1117 static struct omap_hwmod_irq_info omap54xx_gpio1_irqs[] = {
1118         { .irq = 29 + OMAP54XX_IRQ_GIC_START },
1119         { .irq = -1 }
1120 };
1122 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1123         { .role = "dbclk", .clk = "gpio1_dbclk" },
1124 };
1126 static struct omap_hwmod omap54xx_gpio1_hwmod = {
1127         .name           = "gpio1",
1128         .class          = &omap54xx_gpio_hwmod_class,
1129         .clkdm_name     = "wkupaon_clkdm",
1130         .mpu_irqs       = omap54xx_gpio1_irqs,
1131         .main_clk       = "wkupaon_iclk_mux",
1132         .prcm = {
1133                 .omap4 = {
1134                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
1135                         .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
1136                         .modulemode   = MODULEMODE_HWCTRL,
1137                 },
1138         },
1139         .opt_clks       = gpio1_opt_clks,
1140         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1141         .dev_attr       = &gpio_dev_attr,
1142 };
1144 /* gpio2 */
1145 static struct omap_hwmod_irq_info omap54xx_gpio2_irqs[] = {
1146         { .irq = 30 + OMAP54XX_IRQ_GIC_START },
1147         { .irq = -1 }
1148 };
1150 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1151         { .role = "dbclk", .clk = "gpio2_dbclk" },
1152 };
1154 static struct omap_hwmod omap54xx_gpio2_hwmod = {
1155         .name           = "gpio2",
1156         .class          = &omap54xx_gpio_hwmod_class,
1157         .clkdm_name     = "l4per_clkdm",
1158         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1159         .mpu_irqs       = omap54xx_gpio2_irqs,
1160         .main_clk       = "l4_root_clk_div",
1161         .prcm = {
1162                 .omap4 = {
1163                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1164                         .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1165                         .modulemode   = MODULEMODE_HWCTRL,
1166                 },
1167         },
1168         .opt_clks       = gpio2_opt_clks,
1169         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1170         .dev_attr       = &gpio_dev_attr,
1171 };
1173 /* gpio3 */
1174 static struct omap_hwmod_irq_info omap54xx_gpio3_irqs[] = {
1175         { .irq = 31 + OMAP54XX_IRQ_GIC_START },
1176         { .irq = -1 }
1177 };
1179 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1180         { .role = "dbclk", .clk = "gpio3_dbclk" },
1181 };
1183 static struct omap_hwmod omap54xx_gpio3_hwmod = {
1184         .name           = "gpio3",
1185         .class          = &omap54xx_gpio_hwmod_class,
1186         .clkdm_name     = "l4per_clkdm",
1187         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1188         .mpu_irqs       = omap54xx_gpio3_irqs,
1189         .main_clk       = "l4_root_clk_div",
1190         .prcm = {
1191                 .omap4 = {
1192                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1193                         .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1194                         .modulemode   = MODULEMODE_HWCTRL,
1195                 },
1196         },
1197         .opt_clks       = gpio3_opt_clks,
1198         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1199         .dev_attr       = &gpio_dev_attr,
1200 };
1202 /* gpio4 */
1203 static struct omap_hwmod_irq_info omap54xx_gpio4_irqs[] = {
1204         { .irq = 32 + OMAP54XX_IRQ_GIC_START },
1205         { .irq = -1 }
1206 };
1208 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1209         { .role = "dbclk", .clk = "gpio4_dbclk" },
1210 };
1212 static struct omap_hwmod omap54xx_gpio4_hwmod = {
1213         .name           = "gpio4",
1214         .class          = &omap54xx_gpio_hwmod_class,
1215         .clkdm_name     = "l4per_clkdm",
1216         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1217         .mpu_irqs       = omap54xx_gpio4_irqs,
1218         .main_clk       = "l4_root_clk_div",
1219         .prcm = {
1220                 .omap4 = {
1221                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1222                         .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1223                         .modulemode   = MODULEMODE_HWCTRL,
1224                 },
1225         },
1226         .opt_clks       = gpio4_opt_clks,
1227         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1228         .dev_attr       = &gpio_dev_attr,
1229 };
1231 /* gpio5 */
1232 static struct omap_hwmod_irq_info omap54xx_gpio5_irqs[] = {
1233         { .irq = 33 + OMAP54XX_IRQ_GIC_START },
1234         { .irq = -1 }
1235 };
1237 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1238         { .role = "dbclk", .clk = "gpio5_dbclk" },
1239 };
1241 static struct omap_hwmod omap54xx_gpio5_hwmod = {
1242         .name           = "gpio5",
1243         .class          = &omap54xx_gpio_hwmod_class,
1244         .clkdm_name     = "l4per_clkdm",
1245         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1246         .mpu_irqs       = omap54xx_gpio5_irqs,
1247         .main_clk       = "l4_root_clk_div",
1248         .prcm = {
1249                 .omap4 = {
1250                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1251                         .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1252                         .modulemode   = MODULEMODE_HWCTRL,
1253                 },
1254         },
1255         .opt_clks       = gpio5_opt_clks,
1256         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1257         .dev_attr       = &gpio_dev_attr,
1258 };
1260 /* gpio6 */
1261 static struct omap_hwmod_irq_info omap54xx_gpio6_irqs[] = {
1262         { .irq = 34 + OMAP54XX_IRQ_GIC_START },
1263         { .irq = -1 }
1264 };
1266 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1267         { .role = "dbclk", .clk = "gpio6_dbclk" },
1268 };
1270 static struct omap_hwmod omap54xx_gpio6_hwmod = {
1271         .name           = "gpio6",
1272         .class          = &omap54xx_gpio_hwmod_class,
1273         .clkdm_name     = "l4per_clkdm",
1274         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1275         .mpu_irqs       = omap54xx_gpio6_irqs,
1276         .main_clk       = "l4_root_clk_div",
1277         .prcm = {
1278                 .omap4 = {
1279                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1280                         .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1281                         .modulemode   = MODULEMODE_HWCTRL,
1282                 },
1283         },
1284         .opt_clks       = gpio6_opt_clks,
1285         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1286         .dev_attr       = &gpio_dev_attr,
1287 };
1289 /* gpio7 */
1290 static struct omap_hwmod_irq_info omap54xx_gpio7_irqs[] = {
1291         { .irq = 35 + OMAP54XX_IRQ_GIC_START },
1292         { .irq = -1 }
1293 };
1295 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
1296         { .role = "dbclk", .clk = "gpio7_dbclk" },
1297 };
1299 static struct omap_hwmod omap54xx_gpio7_hwmod = {
1300         .name           = "gpio7",
1301         .class          = &omap54xx_gpio_hwmod_class,
1302         .clkdm_name     = "l4per_clkdm",
1303         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1304         .mpu_irqs       = omap54xx_gpio7_irqs,
1305         .main_clk       = "l4_root_clk_div",
1306         .prcm = {
1307                 .omap4 = {
1308                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
1309                         .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
1310                         .modulemode   = MODULEMODE_HWCTRL,
1311                 },
1312         },
1313         .opt_clks       = gpio7_opt_clks,
1314         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
1315         .dev_attr       = &gpio_dev_attr,
1316 };
1318 /* gpio8 */
1319 static struct omap_hwmod_irq_info omap54xx_gpio8_irqs[] = {
1320         { .irq = 121 + OMAP54XX_IRQ_GIC_START },
1321         { .irq = -1 }
1322 };
1324 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
1325         { .role = "dbclk", .clk = "gpio8_dbclk" },
1326 };
1328 static struct omap_hwmod omap54xx_gpio8_hwmod = {
1329         .name           = "gpio8",
1330         .class          = &omap54xx_gpio_hwmod_class,
1331         .clkdm_name     = "l4per_clkdm",
1332         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1333         .mpu_irqs       = omap54xx_gpio8_irqs,
1334         .main_clk       = "l4_root_clk_div",
1335         .prcm = {
1336                 .omap4 = {
1337                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1338                         .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1339                         .modulemode   = MODULEMODE_HWCTRL,
1340                 },
1341         },
1342         .opt_clks       = gpio8_opt_clks,
1343         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
1344         .dev_attr       = &gpio_dev_attr,
1345 };
1347 /*
1348  * 'gpmc' class
1349  * general purpose memory controller
1350  */
1352 static struct omap_hwmod_class_sysconfig omap54xx_gpmc_sysc = {
1353         .rev_offs       = 0x0000,
1354         .sysc_offs      = 0x0010,
1355         .syss_offs      = 0x0014,
1356         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1357                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1358         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1359         .sysc_fields    = &omap_hwmod_sysc_type1,
1360 };
1362 static struct omap_hwmod_class omap54xx_gpmc_hwmod_class = {
1363         .name   = "gpmc",
1364         .sysc   = &omap54xx_gpmc_sysc,
1365 };
1367 /* gpmc */
1368 static struct omap_hwmod_irq_info omap54xx_gpmc_irqs[] = {
1369         { .irq = 20 + OMAP54XX_IRQ_GIC_START },
1370         { .irq = -1 }
1371 };
1373 static struct omap_hwmod_dma_info omap54xx_gpmc_sdma_reqs[] = {
1374         { .dma_req = 3 + OMAP54XX_DMA_REQ_START },
1375         { .dma_req = -1 }
1376 };
1378 static struct omap_hwmod omap54xx_gpmc_hwmod = {
1379         .name           = "gpmc",
1380         .class          = &omap54xx_gpmc_hwmod_class,
1381         .clkdm_name     = "l3main2_clkdm",
1382         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1383         .mpu_irqs       = omap54xx_gpmc_irqs,
1384         .sdma_reqs      = omap54xx_gpmc_sdma_reqs,
1385         .main_clk       = "l3_iclk_div",
1386         .prcm = {
1387                 .omap4 = {
1388                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET,
1389                         .context_offs = OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET,
1390                         .modulemode   = MODULEMODE_HWCTRL,
1391                 },
1392         },
1393 };
1395 /*
1396  * 'gpu' class
1397  * 2d/3d graphics accelerator
1398  */
1400 static struct omap_hwmod_class_sysconfig omap54xx_gpu_sysc = {
1401         .rev_offs       = 0x0000,
1402         .sysc_offs      = 0x0010,
1403         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1404         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1405                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1406                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1407         .sysc_fields    = &omap_hwmod_sysc_type2,
1408 };
1410 static struct omap_hwmod_class omap54xx_gpu_hwmod_class = {
1411         .name   = "gpu",
1412         .sysc   = &omap54xx_gpu_sysc,
1413 };
1415 /* gpu */
1416 static struct omap_hwmod_irq_info omap54xx_gpu_irqs[] = {
1417         { .irq = 21 + OMAP54XX_IRQ_GIC_START },
1418         { .irq = -1 }
1419 };
1421 static struct omap_hwmod omap54xx_gpu_hwmod = {
1422         .name           = "gpu",
1423         .class          = &omap54xx_gpu_hwmod_class,
1424         .clkdm_name     = "gpu_clkdm",
1425         .mpu_irqs       = omap54xx_gpu_irqs,
1426         .main_clk       = "gpu_core_gclk_mux",
1427         .prcm = {
1428                 .omap4 = {
1429                         .clkctrl_offs = OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET,
1430                         .context_offs = OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET,
1431                         .modulemode   = MODULEMODE_SWCTRL,
1432                 },
1433         },
1434 };
1436 /*
1437  * 'hdq1w' class
1438  * hdq / 1-wire serial interface controller
1439  */
1441 static struct omap_hwmod_class_sysconfig omap54xx_hdq1w_sysc = {
1442         .rev_offs       = 0x0000,
1443         .sysc_offs      = 0x0014,
1444         .syss_offs      = 0x0018,
1445         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1446                            SYSS_HAS_RESET_STATUS),
1447         .sysc_fields    = &omap_hwmod_sysc_type1,
1448 };
1450 static struct omap_hwmod_class omap54xx_hdq1w_hwmod_class = {
1451         .name   = "hdq1w",
1452         .sysc   = &omap54xx_hdq1w_sysc,
1453 };
1455 /* hdq1w */
1456 static struct omap_hwmod_irq_info omap54xx_hdq1w_irqs[] = {
1457         { .irq = 58 + OMAP54XX_IRQ_GIC_START },
1458         { .irq = -1 }
1459 };
1461 static struct omap_hwmod omap54xx_hdq1w_hwmod = {
1462         .name           = "hdq1w",
1463         .class          = &omap54xx_hdq1w_hwmod_class,
1464         .clkdm_name     = "l4per_clkdm",
1465         .flags          = HWMOD_INIT_NO_RESET,
1466         .mpu_irqs       = omap54xx_hdq1w_irqs,
1467         .main_clk       = "func_12m_fclk",
1468         .prcm = {
1469                 .omap4 = {
1470                         .clkctrl_offs = OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1471                         .context_offs = OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1472                         .modulemode   = MODULEMODE_SWCTRL,
1473                 },
1474         },
1475 };
1477 /*
1478  * 'hsi' class
1479  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1480  * serial if)
1481  */
1483 static struct omap_hwmod_class_sysconfig omap54xx_hsi_sysc = {
1484         .rev_offs       = 0x0000,
1485         .sysc_offs      = 0x0010,
1486         .syss_offs      = 0x0014,
1487         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1488                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1489                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1490         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1491                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1492                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1493         .sysc_fields    = &omap_hwmod_sysc_type1,
1494 };
1496 static struct omap_hwmod_class omap54xx_hsi_hwmod_class = {
1497         .name   = "hsi",
1498         .sysc   = &omap54xx_hsi_sysc,
1499 };
1501 /* hsi */
1502 static struct omap_hwmod_irq_info omap54xx_hsi_irqs[] = {
1503         { .name = "mpu_p1", .irq = 67 + OMAP54XX_IRQ_GIC_START },
1504         { .name = "mpu_p2", .irq = 68 + OMAP54XX_IRQ_GIC_START },
1505         { .name = "mpu_dma", .irq = 71 + OMAP54XX_IRQ_GIC_START },
1506         { .irq = -1 }
1507 };
1509 static struct omap_hwmod omap54xx_hsi_hwmod = {
1510         .name           = "hsi",
1511         .class          = &omap54xx_hsi_hwmod_class,
1512         .clkdm_name     = "l3init_clkdm",
1513         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1514         .mpu_irqs       = omap54xx_hsi_irqs,
1515         .main_clk       = "hsi_fclk",
1516         .prcm = {
1517                 .omap4 = {
1518                         .clkctrl_offs = OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1519                         .context_offs = OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET,
1520                         .modulemode   = MODULEMODE_HWCTRL,
1521                 },
1522         },
1523 };
1525 /*
1526  * 'i2c' class
1527  * multimaster high-speed i2c controller
1528  */
1530 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
1531         .sysc_offs      = 0x0010,
1532         .syss_offs      = 0x0090,
1533         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1534                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1535                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1536         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1537                            SIDLE_SMART_WKUP),
1538         .clockact       = CLOCKACT_TEST_ICLK,
1539         .sysc_fields    = &omap_hwmod_sysc_type1,
1540 };
1542 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
1543         .name   = "i2c",
1544         .sysc   = &omap54xx_i2c_sysc,
1545         .reset  = &omap_i2c_reset,
1546         .rev    = OMAP_I2C_IP_VERSION_2,
1547 };
1549 /* i2c dev_attr */
1550 static struct omap_i2c_dev_attr i2c_dev_attr = {
1551         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1552 };
1554 /* i2c1 */
1555 static struct omap_hwmod_irq_info omap54xx_i2c1_irqs[] = {
1556         { .irq = 56 + OMAP54XX_IRQ_GIC_START },
1557         { .irq = -1 }
1558 };
1560 static struct omap_hwmod_dma_info omap54xx_i2c1_sdma_reqs[] = {
1561         { .name = "tx", .dma_req = 26 + OMAP54XX_DMA_REQ_START },
1562         { .name = "rx", .dma_req = 27 + OMAP54XX_DMA_REQ_START },
1563         { .dma_req = -1 }
1564 };
1566 static struct omap_hwmod omap54xx_i2c1_hwmod = {
1567         .name           = "i2c1",
1568         .class          = &omap54xx_i2c_hwmod_class,
1569         .clkdm_name     = "l4per_clkdm",
1570         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1571         .mpu_irqs       = omap54xx_i2c1_irqs,
1572         .sdma_reqs      = omap54xx_i2c1_sdma_reqs,
1573         .main_clk       = "func_96m_fclk",
1574         .prcm = {
1575                 .omap4 = {
1576                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1577                         .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1578                         .modulemode   = MODULEMODE_SWCTRL,
1579                 },
1580         },
1581         .dev_attr       = &i2c_dev_attr,
1582 };
1584 /* i2c2 */
1585 static struct omap_hwmod_irq_info omap54xx_i2c2_irqs[] = {
1586         { .irq = 57 + OMAP54XX_IRQ_GIC_START },
1587         { .irq = -1 }
1588 };
1590 static struct omap_hwmod_dma_info omap54xx_i2c2_sdma_reqs[] = {
1591         { .name = "tx", .dma_req = 28 + OMAP54XX_DMA_REQ_START },
1592         { .name = "rx", .dma_req = 29 + OMAP54XX_DMA_REQ_START },
1593         { .dma_req = -1 }
1594 };
1596 static struct omap_hwmod omap54xx_i2c2_hwmod = {
1597         .name           = "i2c2",
1598         .class          = &omap54xx_i2c_hwmod_class,
1599         .clkdm_name     = "l4per_clkdm",
1600         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1601         .mpu_irqs       = omap54xx_i2c2_irqs,
1602         .sdma_reqs      = omap54xx_i2c2_sdma_reqs,
1603         .main_clk       = "func_96m_fclk",
1604         .prcm = {
1605                 .omap4 = {
1606                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1607                         .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1608                         .modulemode   = MODULEMODE_SWCTRL,
1609                 },
1610         },
1611         .dev_attr       = &i2c_dev_attr,
1612 };
1614 /* i2c3 */
1615 static struct omap_hwmod_irq_info omap54xx_i2c3_irqs[] = {
1616         { .irq = 61 + OMAP54XX_IRQ_GIC_START },
1617         { .irq = -1 }
1618 };
1620 static struct omap_hwmod_dma_info omap54xx_i2c3_sdma_reqs[] = {
1621         { .name = "tx", .dma_req = 24 + OMAP54XX_DMA_REQ_START },
1622         { .name = "rx", .dma_req = 25 + OMAP54XX_DMA_REQ_START },
1623         { .dma_req = -1 }
1624 };
1626 static struct omap_hwmod omap54xx_i2c3_hwmod = {
1627         .name           = "i2c3",
1628         .class          = &omap54xx_i2c_hwmod_class,
1629         .clkdm_name     = "l4per_clkdm",
1630         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1631         .mpu_irqs       = omap54xx_i2c3_irqs,
1632         .sdma_reqs      = omap54xx_i2c3_sdma_reqs,
1633         .main_clk       = "func_96m_fclk",
1634         .prcm = {
1635                 .omap4 = {
1636                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1637                         .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1638                         .modulemode   = MODULEMODE_SWCTRL,
1639                 },
1640         },
1641         .dev_attr       = &i2c_dev_attr,
1642 };
1644 /* i2c4 */
1645 static struct omap_hwmod_irq_info omap54xx_i2c4_irqs[] = {
1646         { .irq = 62 + OMAP54XX_IRQ_GIC_START },
1647         { .irq = -1 }
1648 };
1650 static struct omap_hwmod_dma_info omap54xx_i2c4_sdma_reqs[] = {
1651         { .name = "tx", .dma_req = 123 + OMAP54XX_DMA_REQ_START },
1652         { .name = "rx", .dma_req = 124 + OMAP54XX_DMA_REQ_START },
1653         { .dma_req = -1 }
1654 };
1656 static struct omap_hwmod omap54xx_i2c4_hwmod = {
1657         .name           = "i2c4",
1658         .class          = &omap54xx_i2c_hwmod_class,
1659         .clkdm_name     = "l4per_clkdm",
1660         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1661         .mpu_irqs       = omap54xx_i2c4_irqs,
1662         .sdma_reqs      = omap54xx_i2c4_sdma_reqs,
1663         .main_clk       = "func_96m_fclk",
1664         .prcm = {
1665                 .omap4 = {
1666                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1667                         .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1668                         .modulemode   = MODULEMODE_SWCTRL,
1669                 },
1670         },
1671         .dev_attr       = &i2c_dev_attr,
1672 };
1674 /* i2c5 */
1675 static struct omap_hwmod_irq_info omap54xx_i2c5_irqs[] = {
1676         { .irq = 60 + OMAP54XX_IRQ_GIC_START },
1677         { .irq = -1 }
1678 };
1680 static struct omap_hwmod omap54xx_i2c5_hwmod = {
1681         .name           = "i2c5",
1682         .class          = &omap54xx_i2c_hwmod_class,
1683         .clkdm_name     = "l4per_clkdm",
1684         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1685         .mpu_irqs       = omap54xx_i2c5_irqs,
1686         .main_clk       = "func_96m_fclk",
1687         .prcm = {
1688                 .omap4 = {
1689                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
1690                         .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
1691                         .modulemode   = MODULEMODE_SWCTRL,
1692                 },
1693         },
1694         .dev_attr       = &i2c_dev_attr,
1695 };
1697 /*
1698  * 'ipu' class
1699  * imaging processor unit
1700  */
1702 static struct omap_hwmod_class_sysconfig omap54xx_ipu_sysc = {
1703         .rev_offs       = 0x0000,
1704         .sysc_offs      = 0x0010,
1705         .syss_offs      = 0x0014,
1706         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1707                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1708                            SYSS_HAS_RESET_STATUS),
1709         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1710         .sysc_fields    = &omap_hwmod_sysc_type1,
1711 };
1713 static struct omap_hwmod_class omap54xx_ipu_hwmod_class = {
1714         .name   = "ipu",
1715         .sysc   = &omap54xx_ipu_sysc,
1716 };
1718 /* ipu */
1719 static struct omap_hwmod_irq_info omap54xx_ipu_irqs[] = {
1720         { .irq = 100 + OMAP54XX_IRQ_GIC_START },
1721         { .irq = -1 }
1722 };
1724 static struct omap_hwmod_rst_info omap54xx_ipu_resets[] = {
1725         { .name = "cpu0", .rst_shift = 0 },
1726         { .name = "cpu1", .rst_shift = 1 },
1727         { .name = "mmu_cache", .rst_shift = 2 },
1728 };
1730 static struct omap_hwmod omap54xx_ipu_hwmod = {
1731         .name           = "ipu",
1732         .class          = &omap54xx_ipu_hwmod_class,
1733         .clkdm_name     = "ipu_clkdm",
1734         .mpu_irqs       = omap54xx_ipu_irqs,
1735         .rst_lines      = omap54xx_ipu_resets,
1736         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_ipu_resets),
1737         .main_clk       = "dpll_core_h22x2_ck",
1738         .prcm = {
1739                 .omap4 = {
1740                         .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
1741                         .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
1742                         .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
1743                         .modulemode   = MODULEMODE_HWCTRL,
1744                 },
1745         },
1746 };
1748 /*
1749  * 'intc' class
1750  * nested vectored interrupt controller
1751  */
1753 static struct omap_hwmod_class omap54xx_intc_hwmod_class = {
1754         .name   = "intc",
1755 };
1757 /* intc_ipu_c0 */
1758 static struct omap_hwmod omap54xx_intc_ipu_c0_hwmod = {
1759         .name           = "intc_ipu_c0",
1760         .class          = &omap54xx_intc_hwmod_class,
1761         .clkdm_name     = "ipu_clkdm",
1762         .main_clk       = "dpll_core_h22x2_ck",
1763         .prcm = {
1764                 .omap4 = {
1765                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1766                 },
1767         },
1768 };
1770 /* intc_ipu_c1 */
1771 static struct omap_hwmod omap54xx_intc_ipu_c1_hwmod = {
1772         .name           = "intc_ipu_c1",
1773         .class          = &omap54xx_intc_hwmod_class,
1774         .clkdm_name     = "ipu_clkdm",
1775         .main_clk       = "dpll_core_h22x2_ck",
1776         .prcm = {
1777                 .omap4 = {
1778                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1779                 },
1780         },
1781 };
1783 /*
1784  * 'iss' class
1785  * external images sensor pixel data processor
1786  */
1788 static struct omap_hwmod_class_sysconfig omap54xx_iss_sysc = {
1789         .rev_offs       = 0x0000,
1790         .sysc_offs      = 0x0010,
1791         /*
1792          * ISS needs 100 OCP clk cycles delay after a softreset before
1793          * accessing sysconfig again.
1794          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1795          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1796          *
1797          * TODO: Indicate errata when available.
1798          */
1799         .srst_udelay    = 2,
1800         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1801                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1802         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1803                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1804                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1805         .sysc_fields    = &omap_hwmod_sysc_type2,
1806 };
1808 static struct omap_hwmod_class omap54xx_iss_hwmod_class = {
1809         .name   = "iss",
1810         .sysc   = &omap54xx_iss_sysc,
1811 };
1813 /* iss */
1814 static struct omap_hwmod_irq_info omap54xx_iss_irqs[] = {
1815         { .irq = 24 + OMAP54XX_IRQ_GIC_START },
1816         { .irq = -1 }
1817 };
1819 static struct omap_hwmod_dma_info omap54xx_iss_sdma_reqs[] = {
1820         { .name = "1", .dma_req = 8 + OMAP54XX_DMA_REQ_START },
1821         { .name = "2", .dma_req = 9 + OMAP54XX_DMA_REQ_START },
1822         { .name = "3", .dma_req = 11 + OMAP54XX_DMA_REQ_START },
1823         { .name = "4", .dma_req = 12 + OMAP54XX_DMA_REQ_START },
1824         { .name = "5", .dma_req = 30 + OMAP54XX_DMA_REQ_START },
1825         { .name = "6", .dma_req = 31 + OMAP54XX_DMA_REQ_START },
1826         { .name = "7", .dma_req = 125 + OMAP54XX_DMA_REQ_START },
1827         { .name = "8", .dma_req = 126 + OMAP54XX_DMA_REQ_START },
1828         { .dma_req = -1 }
1829 };
1831 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1832         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1833 };
1835 static struct omap_hwmod omap54xx_iss_hwmod = {
1836         .name           = "iss",
1837         .class          = &omap54xx_iss_hwmod_class,
1838         .clkdm_name     = "cam_clkdm",
1839         .flags          = HWMOD_INIT_NO_RESET,
1840         .mpu_irqs       = omap54xx_iss_irqs,
1841         .sdma_reqs      = omap54xx_iss_sdma_reqs,
1842         .main_clk       = "dpll_core_h22x2_ck",
1843         .prcm = {
1844                 .omap4 = {
1845                         .clkctrl_offs = OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET,
1846                         .context_offs = OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET,
1847                         .modulemode   = MODULEMODE_SWCTRL,
1848                 },
1849         },
1850         .opt_clks       = iss_opt_clks,
1851         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1852 };
1854 /*
1855  * 'iva' class
1856  * multi-standard video encoder/decoder hardware accelerator
1857  */
1859 static struct omap_hwmod_class_sysconfig omap54xx_iva_sysc = {
1860         .rev_offs       = 0x0000,
1861         .sysc_offs      = 0x0010,
1862         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1863         .idlemodes      = (SIDLE_NO | SIDLE_SMART | MSTANDBY_NO |
1864                            MSTANDBY_SMART),
1865         .sysc_fields    = &omap_hwmod_sysc_type2,
1866 };
1868 static struct omap_hwmod_class omap54xx_iva_hwmod_class = {
1869         .name   = "iva",
1870         .sysc   = &omap54xx_iva_sysc,
1871 };
1873 /* iva */
1874 static struct omap_hwmod_irq_info omap54xx_iva_irqs[] = {
1875         { .name = "sync_1", .irq = 103 + OMAP54XX_IRQ_GIC_START },
1876         { .name = "sync_0", .irq = 104 + OMAP54XX_IRQ_GIC_START },
1877         { .name = "mailbox_0", .irq = 107 + OMAP54XX_IRQ_GIC_START },
1878         { .irq = -1 }
1879 };
1881 static struct omap_hwmod_rst_info omap54xx_iva_resets[] = {
1882         { .name = "seq0", .rst_shift = 0 },
1883         { .name = "seq1", .rst_shift = 1 },
1884         { .name = "logic", .rst_shift = 2 },
1885 };
1887 static struct omap_hwmod omap54xx_iva_hwmod = {
1888         .name           = "iva",
1889         .class          = &omap54xx_iva_hwmod_class,
1890         .clkdm_name     = "iva_clkdm",
1891         .mpu_irqs       = omap54xx_iva_irqs,
1892         .rst_lines      = omap54xx_iva_resets,
1893         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_iva_resets),
1894         .main_clk       = "dpll_iva_h12x2_ck",
1895         .prcm = {
1896                 .omap4 = {
1897                         .clkctrl_offs = OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET,
1898                         .rstctrl_offs = OMAP54XX_RM_IVA_RSTCTRL_OFFSET,
1899                         .context_offs = OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET,
1900                         .modulemode   = MODULEMODE_HWCTRL,
1901                 },
1902         },
1903 };
1905 /*
1906  * 'kbd' class
1907  * keyboard controller
1908  */
1910 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
1911         .rev_offs       = 0x0000,
1912         .sysc_offs      = 0x0010,
1913         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1914                            SYSC_HAS_SOFTRESET),
1915         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1916         .sysc_fields    = &omap_hwmod_sysc_type1,
1917 };
1919 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
1920         .name   = "kbd",
1921         .sysc   = &omap54xx_kbd_sysc,
1922 };
1924 /* kbd */
1925 static struct omap_hwmod_irq_info omap54xx_kbd_irqs[] = {
1926         { .irq = 120 + OMAP54XX_IRQ_GIC_START },
1927         { .irq = -1 }
1928 };
1930 static struct omap_hwmod omap54xx_kbd_hwmod = {
1931         .name           = "kbd",
1932         .class          = &omap54xx_kbd_hwmod_class,
1933         .clkdm_name     = "wkupaon_clkdm",
1934         .mpu_irqs       = omap54xx_kbd_irqs,
1935         .main_clk       = "sys_32k_ck",
1936         .prcm = {
1937                 .omap4 = {
1938                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
1939                         .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
1940                         .modulemode   = MODULEMODE_SWCTRL,
1941                 },
1942         },
1943 };
1945 /*
1946  * 'mailbox' class
1947  * mailbox module allowing communication between the on-chip processors
1948  * useusing a queued mailbox-interrupt mechanism.
1949  */
1951 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
1952         .rev_offs       = 0x0000,
1953         .sysc_offs      = 0x0010,
1954         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1955                            SYSC_HAS_SOFTRESET),
1956         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1957         .sysc_fields    = &omap_hwmod_sysc_type2,
1958 };
1960 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
1961         .name   = "mailbox",
1962         .sysc   = &omap54xx_mailbox_sysc,
1963 };
1965 /* mailbox */
1966 static struct omap_mbox_dev_info omap54xx_mbox_info[] = {
1967         { .name = "mbox-ipu", .tx_id = 0, .rx_id = 1 },
1968         { .name = "mbox-dsp", .tx_id = 3, .rx_id = 2 },
1969 };
1971 static struct omap_mbox_pdata omap54xx_mbox_attrs = {
1972         .intr_type      = MBOX_INTR_CFG_TYPE2,
1973         .info_cnt       = ARRAY_SIZE(omap54xx_mbox_info),
1974         .info           = omap54xx_mbox_info,
1975 };
1977 static struct omap_hwmod_irq_info omap54xx_mailbox_irqs[] = {
1978         { .irq = 26 + OMAP54XX_IRQ_GIC_START },
1979         { .irq = -1 }
1980 };
1982 static struct omap_hwmod omap54xx_mailbox_hwmod = {
1983         .name           = "mailbox",
1984         .class          = &omap54xx_mailbox_hwmod_class,
1985         .clkdm_name     = "l4cfg_clkdm",
1986         .mpu_irqs       = omap54xx_mailbox_irqs,
1987         .main_clk       = "l4_root_clk_div",
1988         .prcm = {
1989                 .omap4 = {
1990                         .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1991                         .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1992                 },
1993         },
1994         .dev_attr       = &omap54xx_mbox_attrs,
1995 };
1997 /*
1998  * 'mcasp' class
1999  * multi-channel audio serial port controller
2000  */
2002 static struct omap_hwmod_class_sysconfig omap54xx_mcasp_sysc = {
2003         .sysc_offs      = 0x0004,
2004         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2005         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2006         .sysc_fields    = &omap_hwmod_sysc_type3,
2007 };
2009 static struct omap_hwmod_class omap54xx_mcasp_hwmod_class = {
2010         .name   = "mcasp",
2011         .sysc   = &omap54xx_mcasp_sysc,
2012 };
2014 /* mcasp */
2015 static struct omap_hwmod_irq_info omap54xx_mcasp_irqs[] = {
2016         { .name = "arevt", .irq = 108 + OMAP54XX_IRQ_GIC_START },
2017         { .name = "axevt", .irq = 109 + OMAP54XX_IRQ_GIC_START },
2018         { .irq = -1 }
2019 };
2021 static struct omap_hwmod_dma_info omap54xx_mcasp_sdma_reqs[] = {
2022         { .name = "axevt", .dma_req = 7 + OMAP54XX_DMA_REQ_START },
2023         { .name = "arevt", .dma_req = 10 + OMAP54XX_DMA_REQ_START },
2024         { .dma_req = -1 }
2025 };
2027 static struct omap_hwmod omap54xx_mcasp_hwmod = {
2028         .name           = "mcasp",
2029         .class          = &omap54xx_mcasp_hwmod_class,
2030         .clkdm_name     = "abe_clkdm",
2031         .flags          = HWMOD_SWSUP_SIDLE,
2032         .mpu_irqs       = omap54xx_mcasp_irqs,
2033         .sdma_reqs      = omap54xx_mcasp_sdma_reqs,
2034         .main_clk       = "mcasp_gfclk",
2035         .prcm = {
2036                 .omap4 = {
2037                         .clkctrl_offs = OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET,
2038                         .context_offs = OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET,
2039                         .modulemode   = MODULEMODE_SWCTRL,
2040                 },
2041         },
2042 };
2044 /*
2045  * 'mcbsp' class
2046  * multi channel buffered serial port controller
2047  */
2049 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
2050         .sysc_offs      = 0x008c,
2051         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2052                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2053         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2054         .sysc_fields    = &omap_hwmod_sysc_type1,
2055 };
2057 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
2058         .name   = "mcbsp",
2059         .sysc   = &omap54xx_mcbsp_sysc,
2060         .rev    = MCBSP_CONFIG_TYPE4,
2061 };
2063 /* mcbsp1 */
2064 static struct omap_hwmod_irq_info omap54xx_mcbsp1_irqs[] = {
2065         { .name = "common", .irq = 17 + OMAP54XX_IRQ_GIC_START },
2066         { .irq = -1 }
2067 };
2069 static struct omap_hwmod_dma_info omap54xx_mcbsp1_sdma_reqs[] = {
2070         { .name = "tx", .dma_req = 32 + OMAP54XX_DMA_REQ_START },
2071         { .name = "rx", .dma_req = 33 + OMAP54XX_DMA_REQ_START },
2072         { .dma_req = -1 }
2073 };
2075 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
2076         { .role = "pad_fck", .clk = "pad_clks_ck" },
2077         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
2078 };
2080 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
2081         .name           = "mcbsp1",
2082         .class          = &omap54xx_mcbsp_hwmod_class,
2083         .clkdm_name     = "abe_clkdm",
2084         .mpu_irqs       = omap54xx_mcbsp1_irqs,
2085         .sdma_reqs      = omap54xx_mcbsp1_sdma_reqs,
2086         .main_clk       = "mcbsp1_gfclk",
2087         .prcm = {
2088                 .omap4 = {
2089                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
2090                         .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
2091                         .modulemode   = MODULEMODE_SWCTRL,
2092                 },
2093         },
2094         .opt_clks       = mcbsp1_opt_clks,
2095         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
2096 };
2098 /* mcbsp2 */
2099 static struct omap_hwmod_irq_info omap54xx_mcbsp2_irqs[] = {
2100         { .name = "common", .irq = 22 + OMAP54XX_IRQ_GIC_START },
2101         { .irq = -1 }
2102 };
2104 static struct omap_hwmod_dma_info omap54xx_mcbsp2_sdma_reqs[] = {
2105         { .name = "tx", .dma_req = 16 + OMAP54XX_DMA_REQ_START },
2106         { .name = "rx", .dma_req = 17 + OMAP54XX_DMA_REQ_START },
2107         { .dma_req = -1 }
2108 };
2110 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2111         { .role = "pad_fck", .clk = "pad_clks_ck" },
2112         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2113 };
2115 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
2116         .name           = "mcbsp2",
2117         .class          = &omap54xx_mcbsp_hwmod_class,
2118         .clkdm_name     = "abe_clkdm",
2119         .mpu_irqs       = omap54xx_mcbsp2_irqs,
2120         .sdma_reqs      = omap54xx_mcbsp2_sdma_reqs,
2121         .main_clk       = "mcbsp2_gfclk",
2122         .prcm = {
2123                 .omap4 = {
2124                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
2125                         .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2126                         .modulemode   = MODULEMODE_SWCTRL,
2127                 },
2128         },
2129         .opt_clks       = mcbsp2_opt_clks,
2130         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2131 };
2133 /* mcbsp3 */
2134 static struct omap_hwmod_irq_info omap54xx_mcbsp3_irqs[] = {
2135         { .name = "common", .irq = 23 + OMAP54XX_IRQ_GIC_START },
2136         { .irq = -1 }
2137 };
2139 static struct omap_hwmod_dma_info omap54xx_mcbsp3_sdma_reqs[] = {
2140         { .name = "tx", .dma_req = 18 + OMAP54XX_DMA_REQ_START },
2141         { .name = "rx", .dma_req = 19 + OMAP54XX_DMA_REQ_START },
2142         { .dma_req = -1 }
2143 };
2145 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2146         { .role = "pad_fck", .clk = "pad_clks_ck" },
2147         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2148 };
2150 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
2151         .name           = "mcbsp3",
2152         .class          = &omap54xx_mcbsp_hwmod_class,
2153         .clkdm_name     = "abe_clkdm",
2154         .mpu_irqs       = omap54xx_mcbsp3_irqs,
2155         .sdma_reqs      = omap54xx_mcbsp3_sdma_reqs,
2156         .main_clk       = "mcbsp3_gfclk",
2157         .prcm = {
2158                 .omap4 = {
2159                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
2160                         .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2161                         .modulemode   = MODULEMODE_SWCTRL,
2162                 },
2163         },
2164         .opt_clks       = mcbsp3_opt_clks,
2165         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2166 };
2168 /*
2169  * 'mcpdm' class
2170  * multi channel pdm controller (proprietary interface with phoenix power
2171  * ic)
2172  */
2174 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
2175         .rev_offs       = 0x0000,
2176         .sysc_offs      = 0x0010,
2177         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2178                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2179         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2180                            SIDLE_SMART_WKUP),
2181         .sysc_fields    = &omap_hwmod_sysc_type2,
2182 };
2184 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
2185         .name   = "mcpdm",
2186         .sysc   = &omap54xx_mcpdm_sysc,
2187 };
2189 /* mcpdm */
2190 static struct omap_hwmod_irq_info omap54xx_mcpdm_irqs[] = {
2191         { .irq = 112 + OMAP54XX_IRQ_GIC_START },
2192         { .irq = -1 }
2193 };
2195 static struct omap_hwmod_dma_info omap54xx_mcpdm_sdma_reqs[] = {
2196         { .name = "up_link", .dma_req = 64 + OMAP54XX_DMA_REQ_START },
2197         { .name = "dn_link", .dma_req = 65 + OMAP54XX_DMA_REQ_START },
2198         { .dma_req = -1 }
2199 };
2201 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
2202         .name           = "mcpdm",
2203         .class          = &omap54xx_mcpdm_hwmod_class,
2204         .clkdm_name     = "abe_clkdm",
2205         /*
2206          * It's suspected that the McPDM requires an off-chip main
2207          * functional clock, controlled via I2C.  This IP block is
2208          * currently reset very early during boot, before I2C is
2209          * available, so it doesn't seem that we have any choice in
2210          * the kernel other than to avoid resetting it.  XXX This is
2211          * really a hardware issue workaround: every IP block should
2212          * be able to source its main functional clock from either
2213          * on-chip or off-chip sources.  McPDM seems to be the only
2214          * current exception.
2215          */
2217         .flags          = HWMOD_EXT_OPT_MAIN_CLK,
2218         .mpu_irqs       = omap54xx_mcpdm_irqs,
2219         .sdma_reqs      = omap54xx_mcpdm_sdma_reqs,
2220         .main_clk       = "pad_clks_ck",
2221         .prcm = {
2222                 .omap4 = {
2223                         .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
2224                         .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
2225                         .modulemode   = MODULEMODE_SWCTRL,
2226                 },
2227         },
2228 };
2230 /*
2231  * 'mcspi' class
2232  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2233  * bus
2234  */
2236 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
2237         .rev_offs       = 0x0000,
2238         .sysc_offs      = 0x0010,
2239         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2240                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2241         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2242                            SIDLE_SMART_WKUP),
2243         .sysc_fields    = &omap_hwmod_sysc_type2,
2244 };
2246 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
2247         .name   = "mcspi",
2248         .sysc   = &omap54xx_mcspi_sysc,
2249         .rev    = OMAP4_MCSPI_REV,
2250 };
2252 /* mcspi1 */
2253 static struct omap_hwmod_irq_info omap54xx_mcspi1_irqs[] = {
2254         { .irq = 65 + OMAP54XX_IRQ_GIC_START },
2255         { .irq = -1 }
2256 };
2258 static struct omap_hwmod_dma_info omap54xx_mcspi1_sdma_reqs[] = {
2259         { .name = "tx0", .dma_req = 34 + OMAP54XX_DMA_REQ_START },
2260         { .name = "rx0", .dma_req = 35 + OMAP54XX_DMA_REQ_START },
2261         { .name = "tx1", .dma_req = 36 + OMAP54XX_DMA_REQ_START },
2262         { .name = "rx1", .dma_req = 37 + OMAP54XX_DMA_REQ_START },
2263         { .name = "tx2", .dma_req = 38 + OMAP54XX_DMA_REQ_START },
2264         { .name = "rx2", .dma_req = 39 + OMAP54XX_DMA_REQ_START },
2265         { .name = "tx3", .dma_req = 40 + OMAP54XX_DMA_REQ_START },
2266         { .name = "rx3", .dma_req = 41 + OMAP54XX_DMA_REQ_START },
2267         { .dma_req = -1 }
2268 };
2270 /* mcspi1 dev_attr */
2271 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2272         .num_chipselect = 4,
2273 };
2275 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
2276         .name           = "mcspi1",
2277         .class          = &omap54xx_mcspi_hwmod_class,
2278         .clkdm_name     = "l4per_clkdm",
2279         .mpu_irqs       = omap54xx_mcspi1_irqs,
2280         .sdma_reqs      = omap54xx_mcspi1_sdma_reqs,
2281         .main_clk       = "func_48m_fclk",
2282         .prcm = {
2283                 .omap4 = {
2284                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2285                         .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2286                         .modulemode   = MODULEMODE_SWCTRL,
2287                 },
2288         },
2289         .dev_attr       = &mcspi1_dev_attr,
2290 };
2292 /* mcspi2 */
2293 static struct omap_hwmod_irq_info omap54xx_mcspi2_irqs[] = {
2294         { .irq = 66 + OMAP54XX_IRQ_GIC_START },
2295         { .irq = -1 }
2296 };
2298 static struct omap_hwmod_dma_info omap54xx_mcspi2_sdma_reqs[] = {
2299         { .name = "tx0", .dma_req = 42 + OMAP54XX_DMA_REQ_START },
2300         { .name = "rx0", .dma_req = 43 + OMAP54XX_DMA_REQ_START },
2301         { .name = "tx1", .dma_req = 44 + OMAP54XX_DMA_REQ_START },
2302         { .name = "rx1", .dma_req = 45 + OMAP54XX_DMA_REQ_START },
2303         { .dma_req = -1 }
2304 };
2306 /* mcspi2 dev_attr */
2307 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2308         .num_chipselect = 2,
2309 };
2311 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
2312         .name           = "mcspi2",
2313         .class          = &omap54xx_mcspi_hwmod_class,
2314         .clkdm_name     = "l4per_clkdm",
2315         .mpu_irqs       = omap54xx_mcspi2_irqs,
2316         .sdma_reqs      = omap54xx_mcspi2_sdma_reqs,
2317         .main_clk       = "func_48m_fclk",
2318         .prcm = {
2319                 .omap4 = {
2320                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2321                         .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2322                         .modulemode   = MODULEMODE_SWCTRL,
2323                 },
2324         },
2325         .dev_attr       = &mcspi2_dev_attr,
2326 };
2328 /* mcspi3 */
2329 static struct omap_hwmod_irq_info omap54xx_mcspi3_irqs[] = {
2330         { .irq = 91 + OMAP54XX_IRQ_GIC_START },
2331         { .irq = -1 }
2332 };
2334 static struct omap_hwmod_dma_info omap54xx_mcspi3_sdma_reqs[] = {
2335         { .name = "tx0", .dma_req = 14 + OMAP54XX_DMA_REQ_START },
2336         { .name = "rx0", .dma_req = 15 + OMAP54XX_DMA_REQ_START },
2337         { .dma_req = -1 }
2338 };
2340 /* mcspi3 dev_attr */
2341 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2342         .num_chipselect = 2,
2343 };
2345 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
2346         .name           = "mcspi3",
2347         .class          = &omap54xx_mcspi_hwmod_class,
2348         .clkdm_name     = "l4per_clkdm",
2349         .mpu_irqs       = omap54xx_mcspi3_irqs,
2350         .sdma_reqs      = omap54xx_mcspi3_sdma_reqs,
2351         .main_clk       = "func_48m_fclk",
2352         .prcm = {
2353                 .omap4 = {
2354                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2355                         .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2356                         .modulemode   = MODULEMODE_SWCTRL,
2357                 },
2358         },
2359         .dev_attr       = &mcspi3_dev_attr,
2360 };
2362 /* mcspi4 */
2363 static struct omap_hwmod_irq_info omap54xx_mcspi4_irqs[] = {
2364         { .irq = 48 + OMAP54XX_IRQ_GIC_START },
2365         { .irq = -1 }
2366 };
2368 static struct omap_hwmod_dma_info omap54xx_mcspi4_sdma_reqs[] = {
2369         { .name = "tx0", .dma_req = 69 + OMAP54XX_DMA_REQ_START },
2370         { .name = "rx0", .dma_req = 70 + OMAP54XX_DMA_REQ_START },
2371         { .dma_req = -1 }
2372 };
2374 /* mcspi4 dev_attr */
2375 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2376         .num_chipselect = 1,
2377 };
2379 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
2380         .name           = "mcspi4",
2381         .class          = &omap54xx_mcspi_hwmod_class,
2382         .clkdm_name     = "l4per_clkdm",
2383         .mpu_irqs       = omap54xx_mcspi4_irqs,
2384         .sdma_reqs      = omap54xx_mcspi4_sdma_reqs,
2385         .main_clk       = "func_48m_fclk",
2386         .prcm = {
2387                 .omap4 = {
2388                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2389                         .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2390                         .modulemode   = MODULEMODE_SWCTRL,
2391                 },
2392         },
2393         .dev_attr       = &mcspi4_dev_attr,
2394 };
2396 /*
2397  * 'mmc' class
2398  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2399  */
2401 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
2402         .rev_offs       = 0x0000,
2403         .sysc_offs      = 0x0010,
2404         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2405                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2406                            SYSC_HAS_SOFTRESET),
2407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2408                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2409                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2410         .sysc_fields    = &omap_hwmod_sysc_type2,
2411 };
2413 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
2414         .name   = "mmc",
2415         .sysc   = &omap54xx_mmc_sysc,
2416 };
2418 /* mmc1 */
2419 static struct omap_hwmod_irq_info omap54xx_mmc1_irqs[] = {
2420         { .irq = 83 + OMAP54XX_IRQ_GIC_START },
2421         { .irq = -1 }
2422 };
2424 static struct omap_hwmod_dma_info omap54xx_mmc1_sdma_reqs[] = {
2425         { .name = "tx", .dma_req = 60 + OMAP54XX_DMA_REQ_START },
2426         { .name = "rx", .dma_req = 61 + OMAP54XX_DMA_REQ_START },
2427         { .dma_req = -1 }
2428 };
2430 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
2431         { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
2432 };
2434 /* mmc1 dev_attr */
2435 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2436         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2437 };
2439 static struct omap_hwmod omap54xx_mmc1_hwmod = {
2440         .name           = "mmc1",
2441         .class          = &omap54xx_mmc_hwmod_class,
2442         .clkdm_name     = "l3init_clkdm",
2443         .mpu_irqs       = omap54xx_mmc1_irqs,
2444         .sdma_reqs      = omap54xx_mmc1_sdma_reqs,
2445         .main_clk       = "mmc1_fclk",
2446         .prcm = {
2447                 .omap4 = {
2448                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2449                         .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2450                         .modulemode   = MODULEMODE_SWCTRL,
2451                 },
2452         },
2453         .opt_clks       = mmc1_opt_clks,
2454         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
2455         .dev_attr       = &mmc1_dev_attr,
2456 };
2458 /* mmc2 */
2459 static struct omap_hwmod_irq_info omap54xx_mmc2_irqs[] = {
2460         { .irq = 86 + OMAP54XX_IRQ_GIC_START },
2461         { .irq = -1 }
2462 };
2464 static struct omap_hwmod_dma_info omap54xx_mmc2_sdma_reqs[] = {
2465         { .name = "tx", .dma_req = 46 + OMAP54XX_DMA_REQ_START },
2466         { .name = "rx", .dma_req = 47 + OMAP54XX_DMA_REQ_START },
2467         { .dma_req = -1 }
2468 };
2470 static struct omap_hwmod omap54xx_mmc2_hwmod = {
2471         .name           = "mmc2",
2472         .class          = &omap54xx_mmc_hwmod_class,
2473         .clkdm_name     = "l3init_clkdm",
2474         .mpu_irqs       = omap54xx_mmc2_irqs,
2475         .sdma_reqs      = omap54xx_mmc2_sdma_reqs,
2476         .main_clk       = "mmc2_fclk",
2477         .prcm = {
2478                 .omap4 = {
2479                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2480                         .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2481                         .modulemode   = MODULEMODE_SWCTRL,
2482                 },
2483         },
2484 };
2486 /* mmc3 */
2487 static struct omap_hwmod_irq_info omap54xx_mmc3_irqs[] = {
2488         { .irq = 94 + OMAP54XX_IRQ_GIC_START },
2489         { .irq = -1 }
2490 };
2492 static struct omap_hwmod_dma_info omap54xx_mmc3_sdma_reqs[] = {
2493         { .name = "tx", .dma_req = 76 + OMAP54XX_DMA_REQ_START },
2494         { .name = "rx", .dma_req = 77 + OMAP54XX_DMA_REQ_START },
2495         { .dma_req = -1 }
2496 };
2498 static struct omap_hwmod omap54xx_mmc3_hwmod = {
2499         .name           = "mmc3",
2500         .class          = &omap54xx_mmc_hwmod_class,
2501         .clkdm_name     = "l4per_clkdm",
2502         .mpu_irqs       = omap54xx_mmc3_irqs,
2503         .sdma_reqs      = omap54xx_mmc3_sdma_reqs,
2504         .main_clk       = "func_48m_fclk",
2505         .prcm = {
2506                 .omap4 = {
2507                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
2508                         .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
2509                         .modulemode   = MODULEMODE_SWCTRL,
2510                 },
2511         },
2512 };
2514 /* mmc4 */
2515 static struct omap_hwmod_irq_info omap54xx_mmc4_irqs[] = {
2516         { .irq = 96 + OMAP54XX_IRQ_GIC_START },
2517         { .irq = -1 }
2518 };
2520 static struct omap_hwmod_dma_info omap54xx_mmc4_sdma_reqs[] = {
2521         { .name = "tx", .dma_req = 56 + OMAP54XX_DMA_REQ_START },
2522         { .name = "rx", .dma_req = 57 + OMAP54XX_DMA_REQ_START },
2523         { .dma_req = -1 }
2524 };
2526 static struct omap_hwmod omap54xx_mmc4_hwmod = {
2527         .name           = "mmc4",
2528         .class          = &omap54xx_mmc_hwmod_class,
2529         .clkdm_name     = "l4per_clkdm",
2530         .mpu_irqs       = omap54xx_mmc4_irqs,
2531         .sdma_reqs      = omap54xx_mmc4_sdma_reqs,
2532         .main_clk       = "func_48m_fclk",
2533         .prcm = {
2534                 .omap4 = {
2535                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
2536                         .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
2537                         .modulemode   = MODULEMODE_SWCTRL,
2538                 },
2539         },
2540 };
2542 /* mmc5 */
2543 static struct omap_hwmod_irq_info omap54xx_mmc5_irqs[] = {
2544         { .irq = 59 + OMAP54XX_IRQ_GIC_START },
2545         { .irq = -1 }
2546 };
2548 static struct omap_hwmod_dma_info omap54xx_mmc5_sdma_reqs[] = {
2549         { .name = "tx", .dma_req = 58 + OMAP54XX_DMA_REQ_START },
2550         { .name = "rx", .dma_req = 59 + OMAP54XX_DMA_REQ_START },
2551         { .dma_req = -1 }
2552 };
2554 static struct omap_hwmod omap54xx_mmc5_hwmod = {
2555         .name           = "mmc5",
2556         .class          = &omap54xx_mmc_hwmod_class,
2557         .clkdm_name     = "l4per_clkdm",
2558         .mpu_irqs       = omap54xx_mmc5_irqs,
2559         .sdma_reqs      = omap54xx_mmc5_sdma_reqs,
2560         .main_clk       = "func_96m_fclk",
2561         .prcm = {
2562                 .omap4 = {
2563                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
2564                         .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
2565                         .modulemode   = MODULEMODE_SWCTRL,
2566                 },
2567         },
2568 };
2570 /*
2571  * 'mpu' class
2572  * mpu sub-system
2573  */
2575 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
2576         .name   = "mpu",
2577 };
2579 /* mpu */
2580 static struct omap_hwmod_irq_info omap54xx_mpu_irqs[] = {
2581         { .name = "mpu_cluster", .irq = 132 + OMAP54XX_IRQ_GIC_START },
2582         { .name = "wd_timer_mpu_c0", .irq = 139 + OMAP54XX_IRQ_GIC_START },
2583         { .name = "wd_timer_mpu_c1", .irq = 140 + OMAP54XX_IRQ_GIC_START },
2584         { .irq = -1 }
2585 };
2587 static struct omap_hwmod omap54xx_mpu_hwmod = {
2588         .name           = "mpu",
2589         .class          = &omap54xx_mpu_hwmod_class,
2590         .clkdm_name     = "mpu_clkdm",
2591         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2592         .mpu_irqs       = omap54xx_mpu_irqs,
2593         .main_clk       = "dpll_mpu_m2_ck",
2594         .prcm = {
2595                 .omap4 = {
2596                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
2597                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
2598                 },
2599         },
2600 };
2602 /*
2603  * 'ocmc_ram' class
2604  * top-level core on-chip ram
2605  */
2607 static struct omap_hwmod_class omap54xx_ocmc_ram_hwmod_class = {
2608         .name   = "ocmc_ram",
2609 };
2611 /* ocmc_ram */
2612 static struct omap_hwmod omap54xx_ocmc_ram_hwmod = {
2613         .name           = "ocmc_ram",
2614         .class          = &omap54xx_ocmc_ram_hwmod_class,
2615         .clkdm_name     = "l3main2_clkdm",
2616         .main_clk       = "l3_iclk_div",
2617         .prcm = {
2618                 .omap4 = {
2619                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET,
2620                         .context_offs = OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET,
2621                 },
2622         },
2623 };
2625 /*
2626  * 'ocp2scp' class
2627  * bridge to transform ocp interface protocol to scp (serial control port)
2628  * protocol
2629  */
2631 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
2632         .rev_offs       = 0x0000,
2633         .sysc_offs      = 0x0010,
2634         .syss_offs      = 0x0014,
2635         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2636                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2637         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2638         .sysc_fields    = &omap_hwmod_sysc_type1,
2639 };
2641 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
2642         .name   = "ocp2scp",
2643         .sysc   = &omap54xx_ocp2scp_sysc,
2644 };
2646 /* ocp2scp1 */
2647 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
2648         .name           = "ocp2scp1",
2649         .class          = &omap54xx_ocp2scp_hwmod_class,
2650         .clkdm_name     = "l3init_clkdm",
2651         .main_clk       = "l4_root_clk_div",
2652         .prcm = {
2653                 .omap4 = {
2654                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
2655                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
2656                         .modulemode   = MODULEMODE_HWCTRL,
2657                 },
2658         },
2659 };
2661 static struct resource omap54xx_sata_phy_addrs[] = {
2662         {
2663                 .name           = "sata_phy_rx",
2664                 .start          = 0x4A096000,
2665                 .end            = 0x4A096080,
2666                 .flags          = IORESOURCE_MEM,
2667         },
2668         {
2669                 .name           = "sata_phy_tx",
2670                 .start          = 0x4A096400,
2671                 .end            = 0x4A096464,
2672                 .flags          = IORESOURCE_MEM,
2673         },
2674         {
2675                 .name           = "sata_pll",
2676                 .start          = 0x4A096800,
2677                 .end            = 0x4A096840,
2678                 .flags          = IORESOURCE_MEM,
2679         },
2680         { }
2681 };
2683 static struct omap_ocp2scp_dev ocp2scp3_dev_attr[] = {
2684         {
2685                 .drv_name       = "omap-sata",
2686                 .res            = omap54xx_sata_phy_addrs,
2687         },
2688         { }
2689 };
2691 /* ocp2scp3 */
2692 static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
2693 static struct omap_hwmod_addr_space omap54xx_ocp2scp3_addrs[] = {
2694         {
2695                 .name           = "ocp2scp3",
2696                 .pa_start       = 0x4a090000,
2697                 .pa_end         = 0x4a09001f,
2698                 .flags          = ADDR_TYPE_RT
2699         },
2700         { }
2701 };
2703 /* l4_cfg -> ocp2scp3 */
2704 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
2705         .master         = &omap54xx_l4_cfg_hwmod,
2706         .slave          = &omap54xx_ocp2scp3_hwmod,
2707         .clk            = "l4_root_clk_div",
2708         .addr           = omap54xx_ocp2scp3_addrs,
2709         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2710 };
2712 static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
2713         .name           = "ocp2scp3",
2714         .class          = &omap54xx_ocp2scp_hwmod_class,
2715         .clkdm_name     = "l3init_clkdm",
2716         .prcm = {
2717                 .omap4 = {
2718                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2719                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2720                         .modulemode   = MODULEMODE_HWCTRL,
2721                 },
2722         },
2723         .dev_attr       = ocp2scp3_dev_attr,
2724 };
2726 /*
2727  * 'sata' class
2728  * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
2729  */
2731 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2732         .sysc_offs      = 0x0000,
2733         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2734         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2735                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2736                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2737         .sysc_fields    = &omap_hwmod_sysc_type2,
2738 };
2740 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2741         .name   = "sata",
2742         .sysc   = &omap54xx_sata_sysc,
2743 };
2745 /* sata */
2746 static struct omap_hwmod_irq_info omap54xx_sata_irqs[] = {
2747         { .irq = 54 + OMAP54XX_IRQ_GIC_START },
2748         { .irq = -1 }
2749 };
2751 static struct omap_hwmod_opt_clk sata_opt_clks[] = {
2752         { .role = "ref_clk", .clk = "sata_ref_clk" },
2753 };
2755 static struct omap_hwmod omap54xx_sata_hwmod = {
2756         .name           = "sata",
2757         .class          = &omap54xx_sata_hwmod_class,
2758         .clkdm_name     = "l3init_clkdm",
2759         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2760         .mpu_irqs       = omap54xx_sata_irqs,
2761         .main_clk       = "func_48m_fclk",
2762         .prcm = {
2763                 .omap4 = {
2764                         .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2765                         .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2766                         .modulemode   = MODULEMODE_SWCTRL,
2767                 },
2768         },
2769         .opt_clks       = sata_opt_clks,
2770         .opt_clks_cnt   = ARRAY_SIZE(sata_opt_clks),
2771 };
2773 /*
2774  * 'scrm' class
2775  * system clock and reset manager
2776  */
2778 static struct omap_hwmod_class omap54xx_scrm_hwmod_class = {
2779         .name   = "scrm",
2780 };
2782 /* scrm */
2783 static struct omap_hwmod omap54xx_scrm_hwmod = {
2784         .name           = "scrm",
2785         .class          = &omap54xx_scrm_hwmod_class,
2786         .clkdm_name     = "wkupaon_clkdm",
2787         .prcm = {
2788                 .omap4 = {
2789                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET,
2790                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2791                 },
2792         },
2793 };
2795 /*
2796  * 'slimbus' class
2797  * bidirectional, multi-drop, multi-channel two-line serial interface between
2798  * the device and external components
2799  */
2801 static struct omap_hwmod_class_sysconfig omap54xx_slimbus_sysc = {
2802         .rev_offs       = 0x0000,
2803         .sysc_offs      = 0x0010,
2804         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2805                            SYSC_HAS_SOFTRESET),
2806         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2807                            SIDLE_SMART_WKUP),
2808         .sysc_fields    = &omap_hwmod_sysc_type2,
2809 };
2811 static struct omap_hwmod_class omap54xx_slimbus_hwmod_class = {
2812         .name   = "slimbus",
2813         .sysc   = &omap54xx_slimbus_sysc,
2814 };
2816 /* slimbus1 */
2817 static struct omap_hwmod_irq_info omap54xx_slimbus1_irqs[] = {
2818         { .irq = 97 + OMAP54XX_IRQ_GIC_START },
2819         { .irq = -1 }
2820 };
2822 static struct omap_hwmod_dma_info omap54xx_slimbus1_sdma_reqs[] = {
2823         { .name = "tx0", .dma_req = 84 + OMAP54XX_DMA_REQ_START },
2824         { .name = "tx1", .dma_req = 85 + OMAP54XX_DMA_REQ_START },
2825         { .name = "tx2", .dma_req = 86 + OMAP54XX_DMA_REQ_START },
2826         { .name = "tx3", .dma_req = 87 + OMAP54XX_DMA_REQ_START },
2827         { .name = "rx0", .dma_req = 88 + OMAP54XX_DMA_REQ_START },
2828         { .name = "rx1", .dma_req = 89 + OMAP54XX_DMA_REQ_START },
2829         { .name = "rx2", .dma_req = 90 + OMAP54XX_DMA_REQ_START },
2830         { .name = "rx3", .dma_req = 91 + OMAP54XX_DMA_REQ_START },
2831         { .dma_req = -1 }
2832 };
2834 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2835         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2836 };
2838 static struct omap_hwmod omap54xx_slimbus1_hwmod = {
2839         .name           = "slimbus1",
2840         .class          = &omap54xx_slimbus_hwmod_class,
2841         .clkdm_name     = "abe_clkdm",
2842         .mpu_irqs       = omap54xx_slimbus1_irqs,
2843         .sdma_reqs      = omap54xx_slimbus1_sdma_reqs,
2844         .main_clk       = "abe_iclk",
2845         .prcm = {
2846                 .omap4 = {
2847                         .clkctrl_offs = OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET,
2848                         .context_offs = OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET,
2849                         .modulemode   = MODULEMODE_SWCTRL,
2850                 },
2851         },
2852         .opt_clks       = slimbus1_opt_clks,
2853         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2854 };
2856 /*
2857  * 'smartreflex' class
2858  * smartreflex module (monitor silicon performance and outputs a measure of
2859  * performance error)
2860  */
2862 /* The IP is not compliant to type1 / type2 scheme */
2863 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2864         .sidle_shift    = 24,
2865         .enwkup_shift   = 26,
2866 };
2868 static struct omap_hwmod_class_sysconfig omap54xx_smartreflex_sysc = {
2869         .sysc_offs      = 0x0038,
2870         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2871         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2872                            SIDLE_SMART_WKUP),
2873         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2874 };
2876 static struct omap_hwmod_class omap54xx_smartreflex_hwmod_class = {
2877         .name   = "smartreflex",
2878         .sysc   = &omap54xx_smartreflex_sysc,
2879         .rev    = 2,
2880 };
2882 /* smartreflex_core */
2883 static struct omap_hwmod_irq_info omap54xx_smartreflex_core_irqs[] = {
2884         { .irq = 19 + OMAP54XX_IRQ_GIC_START },
2885         { .irq = -1 }
2886 };
2888 /* smartreflex_core dev_attr */
2889 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2890         .sensor_voltdm_name     = "core",
2891 };
2893 static struct omap_hwmod omap54xx_smartreflex_core_hwmod = {
2894         .name           = "smartreflex_core",
2895         .class          = &omap54xx_smartreflex_hwmod_class,
2896         .clkdm_name     = "coreaon_clkdm",
2897         .mpu_irqs       = omap54xx_smartreflex_core_irqs,
2898         .main_clk       = "wkupaon_iclk_mux",
2899         .prcm = {
2900                 .omap4 = {
2901                         .clkctrl_offs = OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2902                         .context_offs = OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2903                         .modulemode   = MODULEMODE_SWCTRL,
2904                 },
2905         },
2906         .dev_attr       = &smartreflex_core_dev_attr,
2907 };
2909 /* smartreflex_mm */
2910 static struct omap_hwmod_irq_info omap54xx_smartreflex_mm_irqs[] = {
2911         { .irq = 102 + OMAP54XX_IRQ_GIC_START },
2912         { .irq = -1 }
2913 };
2915 /* smartreflex_mm dev_attr */
2916 static struct omap_smartreflex_dev_attr smartreflex_mm_dev_attr = {
2917         .sensor_voltdm_name     = "mm",
2918 };
2920 static struct omap_hwmod omap54xx_smartreflex_mm_hwmod = {
2921         .name           = "smartreflex_mm",
2922         .class          = &omap54xx_smartreflex_hwmod_class,
2923         .clkdm_name     = "coreaon_clkdm",
2924         .mpu_irqs       = omap54xx_smartreflex_mm_irqs,
2925         .main_clk       = "wkupaon_iclk_mux",
2926         .prcm = {
2927                 .omap4 = {
2928                         .clkctrl_offs = OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET,
2929                         .context_offs = OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET,
2930                         .modulemode   = MODULEMODE_SWCTRL,
2931                 },
2932         },
2933         .dev_attr       = &smartreflex_mm_dev_attr,
2934 };
2936 /* smartreflex_mpu */
2937 static struct omap_hwmod_irq_info omap54xx_smartreflex_mpu_irqs[] = {
2938         { .irq = 18 + OMAP54XX_IRQ_GIC_START },
2939         { .irq = -1 }
2940 };
2942 /* smartreflex_mpu dev_attr */
2943 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2944         .sensor_voltdm_name     = "mpu",
2945 };
2947 static struct omap_hwmod omap54xx_smartreflex_mpu_hwmod = {
2948         .name           = "smartreflex_mpu",
2949         .class          = &omap54xx_smartreflex_hwmod_class,
2950         .clkdm_name     = "coreaon_clkdm",
2951         .mpu_irqs       = omap54xx_smartreflex_mpu_irqs,
2952         .main_clk       = "wkupaon_iclk_mux",
2953         .prcm = {
2954                 .omap4 = {
2955                         .clkctrl_offs = OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2956                         .context_offs = OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2957                         .modulemode   = MODULEMODE_SWCTRL,
2958                 },
2959         },
2960         .dev_attr       = &smartreflex_mpu_dev_attr,
2961 };
2963 /*
2964  * 'spinlock' class
2965  * spinlock provides hardware assistance for synchronizing the processes
2966  * running on multiple processors
2967  */
2969 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
2970         .rev_offs       = 0x0000,
2971         .sysc_offs      = 0x0010,
2972         .syss_offs      = 0x0014,
2973         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2974                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2975                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2976         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2977                            SIDLE_SMART_WKUP),
2978         .sysc_fields    = &omap_hwmod_sysc_type1,
2979 };
2981 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
2982         .name   = "spinlock",
2983         .sysc   = &omap54xx_spinlock_sysc,
2984 };
2986 /* spinlock */
2987 static struct omap_hwmod omap54xx_spinlock_hwmod = {
2988         .name           = "spinlock",
2989         .class          = &omap54xx_spinlock_hwmod_class,
2990         .clkdm_name     = "l4cfg_clkdm",
2991         .main_clk       = "l4_root_clk_div",
2992         .prcm = {
2993                 .omap4 = {
2994                         .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2995                         .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2996                 },
2997         },
2998 };
3000 /*
3001  * 'timer' class
3002  * general purpose timer module with accurate 1ms tick
3003  * This class contains several variants: ['timer_1ms', 'timer']
3004  */
3006 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
3007         .rev_offs       = 0x0000,
3008         .sysc_offs      = 0x0010,
3009         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3010                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3011         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3012                            SIDLE_SMART_WKUP),
3013         .sysc_fields    = &omap_hwmod_sysc_type2,
3014         .clockact       = CLOCKACT_TEST_ICLK,
3015 };
3017 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
3018         .name   = "timer",
3019         .sysc   = &omap54xx_timer_1ms_sysc,
3020 };
3022 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
3023         .rev_offs       = 0x0000,
3024         .sysc_offs      = 0x0010,
3025         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3026                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3027         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3028                            SIDLE_SMART_WKUP),
3029         .sysc_fields    = &omap_hwmod_sysc_type2,
3030 };
3032 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
3033         .name   = "timer",
3034         .sysc   = &omap54xx_timer_sysc,
3035 };
3037 /* timer1 */
3038 static struct omap_hwmod_irq_info omap54xx_timer1_irqs[] = {
3039         { .irq = 37 + OMAP54XX_IRQ_GIC_START },
3040         { .irq = -1 }
3041 };
3043 static struct omap_hwmod omap54xx_timer1_hwmod = {
3044         .name           = "timer1",
3045         .class          = &omap54xx_timer_1ms_hwmod_class,
3046         .clkdm_name     = "wkupaon_clkdm",
3047         .mpu_irqs       = omap54xx_timer1_irqs,
3048         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3049         .main_clk       = "timer1_gfclk_mux",
3050         .prcm = {
3051                 .omap4 = {
3052                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
3053                         .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
3054                         .modulemode   = MODULEMODE_SWCTRL,
3055                 },
3056         },
3057 };
3059 /* timer2 */
3060 static struct omap_hwmod_irq_info omap54xx_timer2_irqs[] = {
3061         { .irq = 38 + OMAP54XX_IRQ_GIC_START },
3062         { .irq = -1 }
3063 };
3065 static struct omap_hwmod omap54xx_timer2_hwmod = {
3066         .name           = "timer2",
3067         .class          = &omap54xx_timer_1ms_hwmod_class,
3068 &nbs