1 /*
2 * Hardware modules present on the OMAP54xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/platform_data/omap_ocp2scp.h>
24 #include <linux/i2c-omap.h>
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <linux/platform_data/mailbox-omap.h>
30 #include <plat/dmtimer.h>
32 #include "omap_hwmod.h"
33 #include "omap_hwmod_common_data.h"
34 #include "cm1_54xx.h"
35 #include "cm2_54xx.h"
36 #include "prm54xx.h"
37 #include "prm-regbits-54xx.h"
38 #include "i2c.h"
39 #include "mmc.h"
40 #include "wd_timer.h"
42 /* Base offset for all OMAP5 interrupts external to MPUSS */
43 #define OMAP54XX_IRQ_GIC_START 32
45 /* Base offset for all OMAP5 dma requests */
46 #define OMAP54XX_DMA_REQ_START 1
49 /*
50 * IP blocks
51 */
53 /*
54 * 'dmm' class
55 * instance(s): dmm
56 */
57 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
58 .name = "dmm",
59 };
61 /* dmm */
62 static struct omap_hwmod_irq_info omap54xx_dmm_irqs[] = {
63 { .irq = 113 + OMAP54XX_IRQ_GIC_START },
64 { .irq = -1 }
65 };
67 static struct omap_hwmod omap54xx_dmm_hwmod = {
68 .name = "dmm",
69 .class = &omap54xx_dmm_hwmod_class,
70 .clkdm_name = "emif_clkdm",
71 .mpu_irqs = omap54xx_dmm_irqs,
72 .prcm = {
73 .omap4 = {
74 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
75 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
76 },
77 },
78 };
80 /*
81 * 'emif_ocp_fw' class
82 * instance(s): emif_ocp_fw
83 */
84 static struct omap_hwmod_class omap54xx_emif_ocp_fw_hwmod_class = {
85 .name = "emif_ocp_fw",
86 };
88 /* emif_ocp_fw */
89 static struct omap_hwmod omap54xx_emif_ocp_fw_hwmod = {
90 .name = "emif_ocp_fw",
91 .class = &omap54xx_emif_ocp_fw_hwmod_class,
92 .clkdm_name = "emif_clkdm",
93 .prcm = {
94 .omap4 = {
95 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
96 .context_offs = OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
97 },
98 },
99 };
101 /*
102 * 'l3' class
103 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
104 */
105 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
106 .name = "l3",
107 };
109 /* l3_instr */
110 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
111 .name = "l3_instr",
112 .class = &omap54xx_l3_hwmod_class,
113 .clkdm_name = "l3instr_clkdm",
114 .prcm = {
115 .omap4 = {
116 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
117 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
118 .modulemode = MODULEMODE_HWCTRL,
119 },
120 },
121 };
123 /* l3_main_1 */
124 static struct omap_hwmod_irq_info omap54xx_l3_main_1_irqs[] = {
125 { .name = "dbg_err", .irq = 9 + OMAP54XX_IRQ_GIC_START },
126 { .name = "app_err", .irq = 10 + OMAP54XX_IRQ_GIC_START },
127 { .name = "stat_alarm", .irq = 16 + OMAP54XX_IRQ_GIC_START },
128 { .irq = -1 }
129 };
131 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
132 .name = "l3_main_1",
133 .class = &omap54xx_l3_hwmod_class,
134 .clkdm_name = "l3main1_clkdm",
135 .mpu_irqs = omap54xx_l3_main_1_irqs,
136 .prcm = {
137 .omap4 = {
138 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
139 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
140 },
141 },
142 };
144 /* l3_main_2 */
145 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
146 .name = "l3_main_2",
147 .class = &omap54xx_l3_hwmod_class,
148 .clkdm_name = "l3main2_clkdm",
149 .prcm = {
150 .omap4 = {
151 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
152 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
153 },
154 },
155 };
157 /* l3_main_3 */
158 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
159 .name = "l3_main_3",
160 .class = &omap54xx_l3_hwmod_class,
161 .clkdm_name = "l3instr_clkdm",
162 .prcm = {
163 .omap4 = {
164 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
165 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
166 .modulemode = MODULEMODE_HWCTRL,
167 },
168 },
169 };
171 /*
172 * 'l4' class
173 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
174 */
175 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
176 .name = "l4",
177 };
179 /* l4_abe */
180 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
181 .name = "l4_abe",
182 .class = &omap54xx_l4_hwmod_class,
183 .clkdm_name = "abe_clkdm",
184 .prcm = {
185 .omap4 = {
186 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
187 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
188 },
189 },
190 };
192 /* l4_cfg */
193 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
194 .name = "l4_cfg",
195 .class = &omap54xx_l4_hwmod_class,
196 .clkdm_name = "l4cfg_clkdm",
197 .prcm = {
198 .omap4 = {
199 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
200 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
201 },
202 },
203 };
205 /* l4_per */
206 static struct omap_hwmod omap54xx_l4_per_hwmod = {
207 .name = "l4_per",
208 .class = &omap54xx_l4_hwmod_class,
209 .clkdm_name = "l4per_clkdm",
210 .prcm = {
211 .omap4 = {
212 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
213 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
214 },
215 },
216 };
218 /* l4_wkup */
219 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
220 .name = "l4_wkup",
221 .class = &omap54xx_l4_hwmod_class,
222 .clkdm_name = "wkupaon_clkdm",
223 .prcm = {
224 .omap4 = {
225 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
226 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
227 },
228 },
229 };
231 /*
232 * 'mpu_bus' class
233 * instance(s): mpu_private
234 */
235 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
236 .name = "mpu_bus",
237 };
239 /* mpu_private */
240 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
241 .name = "mpu_private",
242 .class = &omap54xx_mpu_bus_hwmod_class,
243 .clkdm_name = "mpu_clkdm",
244 .prcm = {
245 .omap4 = {
246 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
247 },
248 },
249 };
251 /*
252 * 'ocp_wp_noc' class
253 * instance(s): ocp_wp_noc
254 */
255 static struct omap_hwmod_class omap54xx_ocp_wp_noc_hwmod_class = {
256 .name = "ocp_wp_noc",
257 };
259 /* ocp_wp_noc */
260 static struct omap_hwmod omap54xx_ocp_wp_noc_hwmod = {
261 .name = "ocp_wp_noc",
262 .class = &omap54xx_ocp_wp_noc_hwmod_class,
263 .clkdm_name = "l3instr_clkdm",
264 .prcm = {
265 .omap4 = {
266 .clkctrl_offs = OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET,
267 .context_offs = OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET,
268 .modulemode = MODULEMODE_HWCTRL,
269 },
270 },
271 };
273 /*
274 * 'aess' class
275 * audio engine sub system
276 */
278 static struct omap_hwmod_class_sysconfig omap54xx_aess_sysc = {
279 .rev_offs = 0x0000,
280 .sysc_offs = 0x0010,
281 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
282 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
283 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
284 MSTANDBY_SMART_WKUP),
285 .sysc_fields = &omap_hwmod_sysc_type2,
286 };
288 static struct omap_hwmod_class omap54xx_aess_hwmod_class = {
289 .name = "aess",
290 .sysc = &omap54xx_aess_sysc,
291 };
293 /* aess */
294 static struct omap_hwmod_irq_info omap54xx_aess_irqs[] = {
295 { .irq = 99 + OMAP54XX_IRQ_GIC_START },
296 { .irq = -1 }
297 };
299 static struct omap_hwmod_dma_info omap54xx_aess_sdma_reqs[] = {
300 { .name = "fifo0", .dma_req = 100 + OMAP54XX_DMA_REQ_START },
301 { .name = "fifo1", .dma_req = 101 + OMAP54XX_DMA_REQ_START },
302 { .name = "fifo2", .dma_req = 102 + OMAP54XX_DMA_REQ_START },
303 { .name = "fifo3", .dma_req = 103 + OMAP54XX_DMA_REQ_START },
304 { .name = "fifo4", .dma_req = 104 + OMAP54XX_DMA_REQ_START },
305 { .name = "fifo5", .dma_req = 105 + OMAP54XX_DMA_REQ_START },
306 { .name = "fifo6", .dma_req = 106 + OMAP54XX_DMA_REQ_START },
307 { .name = "fifo7", .dma_req = 107 + OMAP54XX_DMA_REQ_START },
308 { .dma_req = -1 }
309 };
311 static struct omap_hwmod omap54xx_aess_hwmod = {
312 .name = "aess",
313 .class = &omap54xx_aess_hwmod_class,
314 .clkdm_name = "abe_clkdm",
315 .mpu_irqs = omap54xx_aess_irqs,
316 .sdma_reqs = omap54xx_aess_sdma_reqs,
317 .main_clk = "aess_fclk",
318 .prcm = {
319 .omap4 = {
320 .clkctrl_offs = OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET,
321 .context_offs = OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET,
322 .modulemode = MODULEMODE_SWCTRL,
323 },
324 },
325 };
327 /*
328 * 'bb2d' class
329 * bit blit 2d accelerator
330 */
332 static struct omap_hwmod_class omap54xx_bb2d_hwmod_class = {
333 .name = "bb2d",
334 };
336 /* bb2d */
337 static struct omap_hwmod_irq_info omap54xx_bb2d_irqs[] = {
338 { .irq = 125 + OMAP54XX_IRQ_GIC_START },
339 { .irq = -1 }
340 };
342 static struct omap_hwmod omap54xx_bb2d_hwmod = {
343 .name = "bb2d",
344 .class = &omap54xx_bb2d_hwmod_class,
345 .clkdm_name = "dss_clkdm",
346 .mpu_irqs = omap54xx_bb2d_irqs,
347 .main_clk = "dpll_core_h24x2_ck",
348 .prcm = {
349 .omap4 = {
350 .clkctrl_offs = OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
351 .context_offs = OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET,
352 .modulemode = MODULEMODE_SWCTRL,
353 },
354 },
355 };
357 /*
358 * 'c2c' class
359 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
360 * soc
361 */
363 static struct omap_hwmod_class_sysconfig omap54xx_c2c_sysc = {
364 .rev_offs = 0x0000,
365 .syss_offs = 0x0008,
366 .sysc_flags = SYSS_HAS_RESET_STATUS,
367 };
369 static struct omap_hwmod_class omap54xx_c2c_hwmod_class = {
370 .name = "c2c",
371 .sysc = &omap54xx_c2c_sysc,
372 };
374 /* c2c */
375 static struct omap_hwmod_irq_info omap54xx_c2c_irqs[] = {
376 { .irq = 88 + OMAP54XX_IRQ_GIC_START },
377 { .irq = -1 }
378 };
380 static struct omap_hwmod_dma_info omap54xx_c2c_sdma_reqs[] = {
381 { .dma_req = 68 + OMAP54XX_DMA_REQ_START },
382 { .dma_req = -1 }
383 };
385 static struct omap_hwmod omap54xx_c2c_hwmod = {
386 .name = "c2c",
387 .class = &omap54xx_c2c_hwmod_class,
388 .clkdm_name = "c2c_clkdm",
389 .mpu_irqs = omap54xx_c2c_irqs,
390 .sdma_reqs = omap54xx_c2c_sdma_reqs,
391 .main_clk = "c2c_fclk",
392 .prcm = {
393 .omap4 = {
394 .clkctrl_offs = OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET,
395 .context_offs = OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET,
396 },
397 },
398 };
400 /*
401 * 'counter' class
402 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
403 */
405 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
406 .rev_offs = 0x0000,
407 .sysc_offs = 0x0010,
408 .sysc_flags = SYSC_HAS_SIDLEMODE,
409 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
410 .sysc_fields = &omap_hwmod_sysc_type1,
411 };
413 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
414 .name = "counter",
415 .sysc = &omap54xx_counter_sysc,
416 };
418 /* counter_32k */
419 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
420 .name = "counter_32k",
421 .class = &omap54xx_counter_hwmod_class,
422 .clkdm_name = "wkupaon_clkdm",
423 .flags = HWMOD_SWSUP_SIDLE,
424 .main_clk = "wkupaon_iclk_mux",
425 .prcm = {
426 .omap4 = {
427 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
428 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
429 },
430 },
431 };
433 /*
434 * 'ctrl_module' class
435 * omap5430 core control module + omap5430 wkup control module
436 */
438 static struct omap_hwmod_class_sysconfig omap54xx_ctrl_module_sysc = {
439 .rev_offs = 0x0000,
440 };
442 static struct omap_hwmod_class omap54xx_ctrl_module_hwmod_class = {
443 .name = "ctrl_module",
444 .sysc = &omap54xx_ctrl_module_sysc,
445 };
447 /* ctrl_module_core */
448 static struct omap_hwmod_irq_info omap54xx_ctrl_module_core_irqs[] = {
449 { .name = "sec_evts", .irq = 8 + OMAP54XX_IRQ_GIC_START },
450 { .name = "thermal_alert", .irq = 126 + OMAP54XX_IRQ_GIC_START },
451 { .irq = -1 }
452 };
454 static struct omap_hwmod omap54xx_ctrl_module_core_hwmod = {
455 .name = "ctrl_module_core",
456 .class = &omap54xx_ctrl_module_hwmod_class,
457 .clkdm_name = "l4cfg_clkdm",
458 .mpu_irqs = omap54xx_ctrl_module_core_irqs,
459 .prcm = {
460 .omap4 = {
461 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
462 },
463 },
464 };
466 /* ctrl_module_wkup */
467 static struct omap_hwmod omap54xx_ctrl_module_wkup_hwmod = {
468 .name = "ctrl_module_wkup",
469 .class = &omap54xx_ctrl_module_hwmod_class,
470 .clkdm_name = "wkupaon_clkdm",
471 .prcm = {
472 .omap4 = {
473 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
474 },
475 },
476 };
478 /*
479 * 'dma' class
480 * dma controller for data exchange between memory to memory (i.e. internal or
481 * external memory) and gp peripherals to memory or memory to gp peripherals
482 */
484 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
485 .rev_offs = 0x0000,
486 .sysc_offs = 0x002c,
487 .syss_offs = 0x0028,
488 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
489 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
490 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
491 SYSS_HAS_RESET_STATUS),
492 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
493 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
494 .sysc_fields = &omap_hwmod_sysc_type1,
495 };
497 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
498 .name = "dma",
499 .sysc = &omap54xx_dma_sysc,
500 };
502 /* dma dev_attr */
503 static struct omap_dma_dev_attr dma_dev_attr = {
504 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
505 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
506 .lch_count = 32,
507 };
509 /* dma_system */
510 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
511 { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
512 { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
513 { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
514 { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
515 { .irq = -1 }
516 };
518 static struct omap_hwmod omap54xx_dma_system_hwmod = {
519 .name = "dma_system",
520 .class = &omap54xx_dma_hwmod_class,
521 .clkdm_name = "dma_clkdm",
522 .mpu_irqs = omap54xx_dma_system_irqs,
523 .main_clk = "l3_iclk_div",
524 .prcm = {
525 .omap4 = {
526 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
527 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
528 },
529 },
530 .dev_attr = &dma_dev_attr,
531 };
533 /*
534 * 'dmic' class
535 * digital microphone controller
536 */
538 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
539 .rev_offs = 0x0000,
540 .sysc_offs = 0x0010,
541 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
542 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
543 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
544 SIDLE_SMART_WKUP),
545 .sysc_fields = &omap_hwmod_sysc_type2,
546 };
548 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
549 .name = "dmic",
550 .sysc = &omap54xx_dmic_sysc,
551 };
553 /* dmic */
554 static struct omap_hwmod_irq_info omap54xx_dmic_irqs[] = {
555 { .irq = 114 + OMAP54XX_IRQ_GIC_START },
556 { .irq = -1 }
557 };
559 static struct omap_hwmod_dma_info omap54xx_dmic_sdma_reqs[] = {
560 { .dma_req = 66 + OMAP54XX_DMA_REQ_START },
561 { .dma_req = -1 }
562 };
564 static struct omap_hwmod omap54xx_dmic_hwmod = {
565 .name = "dmic",
566 .class = &omap54xx_dmic_hwmod_class,
567 .clkdm_name = "abe_clkdm",
568 .mpu_irqs = omap54xx_dmic_irqs,
569 .sdma_reqs = omap54xx_dmic_sdma_reqs,
570 .main_clk = "dmic_gfclk",
571 .prcm = {
572 .omap4 = {
573 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
574 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
575 .modulemode = MODULEMODE_SWCTRL,
576 },
577 },
578 };
580 /*
581 * 'dsp' class
582 * dsp sub-system
583 */
585 static struct omap_hwmod_class omap54xx_dsp_hwmod_class = {
586 .name = "dsp",
587 };
589 /* dsp */
590 static struct omap_hwmod_irq_info omap54xx_dsp_irqs[] = {
591 { .irq = 28 + OMAP54XX_IRQ_GIC_START },
592 { .irq = -1 }
593 };
595 static struct omap_hwmod_rst_info omap54xx_dsp_resets[] = {
596 { .name = "dsp", .rst_shift = 0 },
597 { .name = "mmu_cache", .rst_shift = 1 },
598 };
600 static struct omap_hwmod omap54xx_dsp_hwmod = {
601 .name = "dsp",
602 .class = &omap54xx_dsp_hwmod_class,
603 .clkdm_name = "dsp_clkdm",
604 .mpu_irqs = omap54xx_dsp_irqs,
605 .rst_lines = omap54xx_dsp_resets,
606 .rst_lines_cnt = ARRAY_SIZE(omap54xx_dsp_resets),
607 .main_clk = "dpll_iva_h11x2_ck",
608 .prcm = {
609 .omap4 = {
610 .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
611 .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
612 .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
613 .modulemode = MODULEMODE_HWCTRL,
614 },
615 },
616 };
618 /*
619 * 'dss' class
620 * display sub-system
621 */
623 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
624 .rev_offs = 0x0000,
625 .syss_offs = 0x0014,
626 .sysc_flags = SYSS_HAS_RESET_STATUS,
627 };
629 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
630 .name = "dss",
631 .sysc = &omap54xx_dss_sysc,
632 .reset = omap_dss_reset,
633 };
635 /* dss */
636 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
637 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
638 { .role = "sys_clk", .clk = "dss_sys_clk" },
639 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
640 };
642 static struct omap_hwmod omap54xx_dss_hwmod = {
643 .name = "dss_core",
644 .class = &omap54xx_dss_hwmod_class,
645 .clkdm_name = "dss_clkdm",
646 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
647 .main_clk = "dss_dss_clk",
648 .prcm = {
649 .omap4 = {
650 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
651 .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
652 .modulemode = MODULEMODE_SWCTRL,
653 },
654 },
655 .opt_clks = dss_opt_clks,
656 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
657 };
659 /*
660 * 'dispc' class
661 * display controller
662 */
664 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
665 .rev_offs = 0x0000,
666 .sysc_offs = 0x0010,
667 .syss_offs = 0x0014,
668 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
669 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
670 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
671 SYSS_HAS_RESET_STATUS),
672 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
673 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
674 .sysc_fields = &omap_hwmod_sysc_type1,
675 };
677 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
678 .name = "dispc",
679 .sysc = &omap54xx_dispc_sysc,
680 };
682 /* dss_dispc */
683 static struct omap_hwmod_irq_info omap54xx_dss_dispc_irqs[] = {
684 { .irq = 25 + OMAP54XX_IRQ_GIC_START },
685 { .irq = -1 }
686 };
688 static struct omap_hwmod_dma_info omap54xx_dss_dispc_sdma_reqs[] = {
689 { .dma_req = 5 + OMAP54XX_DMA_REQ_START },
690 { .dma_req = -1 }
691 };
693 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
694 { .role = "sys_clk", .clk = "dss_sys_clk" },
695 };
697 /* dss_dispc dev_attr */
698 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
699 .has_framedonetv_irq = 1,
700 .manager_count = 4,
701 };
703 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
704 .name = "dss_dispc",
705 .class = &omap54xx_dispc_hwmod_class,
706 .clkdm_name = "dss_clkdm",
707 .mpu_irqs = omap54xx_dss_dispc_irqs,
708 .sdma_reqs = omap54xx_dss_dispc_sdma_reqs,
709 .main_clk = "dss_dss_clk",
710 .prcm = {
711 .omap4 = {
712 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
713 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
714 },
715 },
716 .opt_clks = dss_dispc_opt_clks,
717 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
718 .dev_attr = &dss_dispc_dev_attr,
719 };
721 /*
722 * 'dsi1' class
723 * display serial interface controller
724 */
726 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
727 .rev_offs = 0x0000,
728 .sysc_offs = 0x0010,
729 .syss_offs = 0x0014,
730 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
731 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
732 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
733 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
734 .sysc_fields = &omap_hwmod_sysc_type1,
735 };
737 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
738 .name = "dsi1",
739 .sysc = &omap54xx_dsi1_sysc,
740 };
742 /* dss_dsi1_a */
743 static struct omap_hwmod_irq_info omap54xx_dss_dsi1_a_irqs[] = {
744 { .irq = 53 + OMAP54XX_IRQ_GIC_START },
745 { .irq = -1 }
746 };
748 static struct omap_hwmod_dma_info omap54xx_dss_dsi1_a_sdma_reqs[] = {
749 { .dma_req = 74 + OMAP54XX_DMA_REQ_START },
750 { .dma_req = -1 }
751 };
753 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
754 { .role = "sys_clk", .clk = "dss_sys_clk" },
755 };
757 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
758 .name = "dss_dsi1_a",
759 .class = &omap54xx_dsi1_hwmod_class,
760 .clkdm_name = "dss_clkdm",
761 .mpu_irqs = omap54xx_dss_dsi1_a_irqs,
762 .sdma_reqs = omap54xx_dss_dsi1_a_sdma_reqs,
763 .main_clk = "dss_dss_clk",
764 .prcm = {
765 .omap4 = {
766 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
767 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
768 },
769 },
770 .opt_clks = dss_dsi1_a_opt_clks,
771 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks),
772 };
774 /* dss_dsi1_b */
775 static struct omap_hwmod omap54xx_dss_dsi1_b_hwmod = {
776 .name = "dss_dsi1_b",
777 .class = &omap54xx_dsi1_hwmod_class,
778 .clkdm_name = "dss_clkdm",
779 .main_clk = "dss_dss_clk",
780 .prcm = {
781 .omap4 = {
782 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
783 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
784 },
785 },
786 };
788 /* dss_dsi1_c */
789 static struct omap_hwmod_irq_info omap54xx_dss_dsi1_c_irqs[] = {
790 { .irq = 55 + OMAP54XX_IRQ_GIC_START },
791 { .irq = -1 }
792 };
794 static struct omap_hwmod_dma_info omap54xx_dss_dsi1_c_sdma_reqs[] = {
795 { .dma_req = 83 + OMAP54XX_DMA_REQ_START },
796 { .dma_req = -1 }
797 };
799 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
800 { .role = "sys_clk", .clk = "dss_sys_clk" },
801 };
803 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
804 .name = "dss_dsi1_c",
805 .class = &omap54xx_dsi1_hwmod_class,
806 .clkdm_name = "dss_clkdm",
807 .mpu_irqs = omap54xx_dss_dsi1_c_irqs,
808 .sdma_reqs = omap54xx_dss_dsi1_c_sdma_reqs,
809 .main_clk = "dss_dss_clk",
810 .prcm = {
811 .omap4 = {
812 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
813 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
814 },
815 },
816 .opt_clks = dss_dsi1_c_opt_clks,
817 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks),
818 };
820 /*
821 * 'hdmi' class
822 * hdmi controller
823 */
825 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
826 .rev_offs = 0x0000,
827 .sysc_offs = 0x0010,
828 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
829 SYSC_HAS_SOFTRESET),
830 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
831 SIDLE_SMART_WKUP),
832 .sysc_fields = &omap_hwmod_sysc_type2,
833 };
835 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
836 .name = "hdmi",
837 .sysc = &omap54xx_hdmi_sysc,
838 };
840 /* dss_hdmi */
841 static struct omap_hwmod_irq_info omap54xx_dss_hdmi_irqs[] = {
842 { .irq = 101 + OMAP54XX_IRQ_GIC_START },
843 { .irq = -1 }
844 };
846 static struct omap_hwmod_dma_info omap54xx_dss_hdmi_sdma_reqs[] = {
847 { .dma_req = 75 + OMAP54XX_DMA_REQ_START },
848 { .dma_req = -1 }
849 };
851 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
852 { .role = "sys_clk", .clk = "dss_sys_clk" },
853 };
855 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
856 .name = "dss_hdmi",
857 .class = &omap54xx_hdmi_hwmod_class,
858 .clkdm_name = "dss_clkdm",
859 .mpu_irqs = omap54xx_dss_hdmi_irqs,
860 .sdma_reqs = omap54xx_dss_hdmi_sdma_reqs,
861 .main_clk = "dss_48mhz_clk",
862 .prcm = {
863 .omap4 = {
864 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
865 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
866 },
867 },
868 .opt_clks = dss_hdmi_opt_clks,
869 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
870 };
872 /*
873 * 'rfbi' class
874 * remote frame buffer interface
875 */
877 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
878 .rev_offs = 0x0000,
879 .sysc_offs = 0x0010,
880 .syss_offs = 0x0014,
881 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
882 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
883 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
884 .sysc_fields = &omap_hwmod_sysc_type1,
885 };
887 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
888 .name = "rfbi",
889 .sysc = &omap54xx_rfbi_sysc,
890 };
892 /* dss_rfbi */
893 static struct omap_hwmod_dma_info omap54xx_dss_rfbi_sdma_reqs[] = {
894 { .dma_req = 13 + OMAP54XX_DMA_REQ_START },
895 { .dma_req = -1 }
896 };
898 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
899 { .role = "ick", .clk = "l3_iclk_div" },
900 };
902 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
903 .name = "dss_rfbi",
904 .class = &omap54xx_rfbi_hwmod_class,
905 .clkdm_name = "dss_clkdm",
906 .sdma_reqs = omap54xx_dss_rfbi_sdma_reqs,
907 .prcm = {
908 .omap4 = {
909 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
910 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
911 },
912 },
913 .opt_clks = dss_rfbi_opt_clks,
914 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
915 };
917 /*
918 * 'elm' class
919 * bch error location module
920 */
922 static struct omap_hwmod_class_sysconfig omap54xx_elm_sysc = {
923 .rev_offs = 0x0000,
924 .sysc_offs = 0x0010,
925 .syss_offs = 0x0014,
926 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
927 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
928 SYSS_HAS_RESET_STATUS),
929 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
930 .sysc_fields = &omap_hwmod_sysc_type1,
931 };
933 static struct omap_hwmod_class omap54xx_elm_hwmod_class = {
934 .name = "elm",
935 .sysc = &omap54xx_elm_sysc,
936 };
938 /* elm */
939 static struct omap_hwmod_irq_info omap54xx_elm_irqs[] = {
940 { .irq = 4 + OMAP54XX_IRQ_GIC_START },
941 { .irq = -1 }
942 };
944 static struct omap_hwmod omap54xx_elm_hwmod = {
945 .name = "elm",
946 .class = &omap54xx_elm_hwmod_class,
947 .clkdm_name = "l4per_clkdm",
948 .mpu_irqs = omap54xx_elm_irqs,
949 .main_clk = "l4_root_clk_div",
950 .prcm = {
951 .omap4 = {
952 .clkctrl_offs = OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
953 .context_offs = OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET,
954 },
955 },
956 };
958 /*
959 * 'emif' class
960 * external memory interface no1 (wrapper)
961 */
963 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
964 .rev_offs = 0x0000,
965 };
967 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
968 .name = "emif",
969 .sysc = &omap54xx_emif_sysc,
970 };
972 /* emif1 */
973 static struct omap_hwmod_irq_info omap54xx_emif1_irqs[] = {
974 { .irq = 110 + OMAP54XX_IRQ_GIC_START },
975 { .irq = -1 }
976 };
978 static struct omap_hwmod omap54xx_emif1_hwmod = {
979 .name = "emif1",
980 .class = &omap54xx_emif_hwmod_class,
981 .clkdm_name = "emif_clkdm",
982 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
983 .mpu_irqs = omap54xx_emif1_irqs,
984 .main_clk = "dpll_core_h11x2_ck",
985 .prcm = {
986 .omap4 = {
987 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
988 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
989 .modulemode = MODULEMODE_HWCTRL,
990 },
991 },
992 };
994 /* emif2 */
995 static struct omap_hwmod_irq_info omap54xx_emif2_irqs[] = {
996 { .irq = 111 + OMAP54XX_IRQ_GIC_START },
997 { .irq = -1 }
998 };
1000 static struct omap_hwmod omap54xx_emif2_hwmod = {
1001 .name = "emif2",
1002 .class = &omap54xx_emif_hwmod_class,
1003 .clkdm_name = "emif_clkdm",
1004 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1005 .mpu_irqs = omap54xx_emif2_irqs,
1006 .main_clk = "dpll_core_h11x2_ck",
1007 .prcm = {
1008 .omap4 = {
1009 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
1010 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
1011 .modulemode = MODULEMODE_HWCTRL,
1012 },
1013 },
1014 };
1016 /*
1017 * 'fdif' class
1018 * face detection hw accelerator module
1019 */
1021 static struct omap_hwmod_class_sysconfig omap54xx_fdif_sysc = {
1022 .rev_offs = 0x0000,
1023 .sysc_offs = 0x0010,
1024 /*
1025 * FDIF needs 100 OCP clk cycles delay after a softreset before
1026 * accessing sysconfig again.
1027 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1028 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1029 *
1030 * TODO: Indicate errata when available.
1031 */
1032 .srst_udelay = 2,
1033 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1034 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1035 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1036 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1037 .sysc_fields = &omap_hwmod_sysc_type2,
1038 };
1040 static struct omap_hwmod_class omap54xx_fdif_hwmod_class = {
1041 .name = "fdif",
1042 .sysc = &omap54xx_fdif_sysc,
1043 };
1045 /* fdif */
1046 static struct omap_hwmod_irq_info omap54xx_fdif_irqs[] = {
1047 { .irq = 69 + OMAP54XX_IRQ_GIC_START },
1048 { .irq = -1 }
1049 };
1051 static struct omap_hwmod omap54xx_fdif_hwmod = {
1052 .name = "fdif",
1053 .class = &omap54xx_fdif_hwmod_class,
1054 .clkdm_name = "cam_clkdm",
1055 .mpu_irqs = omap54xx_fdif_irqs,
1056 .main_clk = "fdif_fclk",
1057 .prcm = {
1058 .omap4 = {
1059 .clkctrl_offs = OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET,
1060 .context_offs = OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET,
1061 .modulemode = MODULEMODE_SWCTRL,
1062 },
1063 },
1064 };
1066 /*
1067 * 'gpio' class
1068 * general purpose io module
1069 */
1071 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
1072 .rev_offs = 0x0000,
1073 .sysc_offs = 0x0010,
1074 .syss_offs = 0x0114,
1075 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1076 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1077 SYSS_HAS_RESET_STATUS),
1078 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1079 SIDLE_SMART_WKUP),
1080 .sysc_fields = &omap_hwmod_sysc_type1,
1081 };
1083 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
1084 .name = "gpio",
1085 .sysc = &omap54xx_gpio_sysc,
1086 .rev = 2,
1087 };
1089 /* gpio dev_attr */
1090 static struct omap_gpio_dev_attr gpio_dev_attr = {
1091 .bank_width = 32,
1092 .dbck_flag = true,
1093 };
1095 /* gpio1 */
1096 static struct omap_hwmod_irq_info omap54xx_gpio1_irqs[] = {
1097 { .irq = 29 + OMAP54XX_IRQ_GIC_START },
1098 { .irq = -1 }
1099 };
1101 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1102 { .role = "dbclk", .clk = "gpio1_dbclk" },
1103 };
1105 static struct omap_hwmod omap54xx_gpio1_hwmod = {
1106 .name = "gpio1",
1107 .class = &omap54xx_gpio_hwmod_class,
1108 .clkdm_name = "wkupaon_clkdm",
1109 .mpu_irqs = omap54xx_gpio1_irqs,
1110 .main_clk = "wkupaon_iclk_mux",
1111 .prcm = {
1112 .omap4 = {
1113 .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
1114 .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
1115 .modulemode = MODULEMODE_HWCTRL,
1116 },
1117 },
1118 .opt_clks = gpio1_opt_clks,
1119 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1120 .dev_attr = &gpio_dev_attr,
1121 };
1123 /* gpio2 */
1124 static struct omap_hwmod_irq_info omap54xx_gpio2_irqs[] = {
1125 { .irq = 30 + OMAP54XX_IRQ_GIC_START },
1126 { .irq = -1 }
1127 };
1129 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1130 { .role = "dbclk", .clk = "gpio2_dbclk" },
1131 };
1133 static struct omap_hwmod omap54xx_gpio2_hwmod = {
1134 .name = "gpio2",
1135 .class = &omap54xx_gpio_hwmod_class,
1136 .clkdm_name = "l4per_clkdm",
1137 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1138 .mpu_irqs = omap54xx_gpio2_irqs,
1139 .main_clk = "l4_root_clk_div",
1140 .prcm = {
1141 .omap4 = {
1142 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1143 .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1144 .modulemode = MODULEMODE_HWCTRL,
1145 },
1146 },
1147 .opt_clks = gpio2_opt_clks,
1148 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1149 .dev_attr = &gpio_dev_attr,
1150 };
1152 /* gpio3 */
1153 static struct omap_hwmod_irq_info omap54xx_gpio3_irqs[] = {
1154 { .irq = 31 + OMAP54XX_IRQ_GIC_START },
1155 { .irq = -1 }
1156 };
1158 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1159 { .role = "dbclk", .clk = "gpio3_dbclk" },
1160 };
1162 static struct omap_hwmod omap54xx_gpio3_hwmod = {
1163 .name = "gpio3",
1164 .class = &omap54xx_gpio_hwmod_class,
1165 .clkdm_name = "l4per_clkdm",
1166 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1167 .mpu_irqs = omap54xx_gpio3_irqs,
1168 .main_clk = "l4_root_clk_div",
1169 .prcm = {
1170 .omap4 = {
1171 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1172 .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1173 .modulemode = MODULEMODE_HWCTRL,
1174 },
1175 },
1176 .opt_clks = gpio3_opt_clks,
1177 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1178 .dev_attr = &gpio_dev_attr,
1179 };
1181 /* gpio4 */
1182 static struct omap_hwmod_irq_info omap54xx_gpio4_irqs[] = {
1183 { .irq = 32 + OMAP54XX_IRQ_GIC_START },
1184 { .irq = -1 }
1185 };
1187 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1188 { .role = "dbclk", .clk = "gpio4_dbclk" },
1189 };
1191 static struct omap_hwmod omap54xx_gpio4_hwmod = {
1192 .name = "gpio4",
1193 .class = &omap54xx_gpio_hwmod_class,
1194 .clkdm_name = "l4per_clkdm",
1195 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1196 .mpu_irqs = omap54xx_gpio4_irqs,
1197 .main_clk = "l4_root_clk_div",
1198 .prcm = {
1199 .omap4 = {
1200 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1201 .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1202 .modulemode = MODULEMODE_HWCTRL,
1203 },
1204 },
1205 .opt_clks = gpio4_opt_clks,
1206 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1207 .dev_attr = &gpio_dev_attr,
1208 };
1210 /* gpio5 */
1211 static struct omap_hwmod_irq_info omap54xx_gpio5_irqs[] = {
1212 { .irq = 33 + OMAP54XX_IRQ_GIC_START },
1213 { .irq = -1 }
1214 };
1216 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1217 { .role = "dbclk", .clk = "gpio5_dbclk" },
1218 };
1220 static struct omap_hwmod omap54xx_gpio5_hwmod = {
1221 .name = "gpio5",
1222 .class = &omap54xx_gpio_hwmod_class,
1223 .clkdm_name = "l4per_clkdm",
1224 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1225 .mpu_irqs = omap54xx_gpio5_irqs,
1226 .main_clk = "l4_root_clk_div",
1227 .prcm = {
1228 .omap4 = {
1229 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1230 .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1231 .modulemode = MODULEMODE_HWCTRL,
1232 },
1233 },
1234 .opt_clks = gpio5_opt_clks,
1235 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1236 .dev_attr = &gpio_dev_attr,
1237 };
1239 /* gpio6 */
1240 static struct omap_hwmod_irq_info omap54xx_gpio6_irqs[] = {
1241 { .irq = 34 + OMAP54XX_IRQ_GIC_START },
1242 { .irq = -1 }
1243 };
1245 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1246 { .role = "dbclk", .clk = "gpio6_dbclk" },
1247 };
1249 static struct omap_hwmod omap54xx_gpio6_hwmod = {
1250 .name = "gpio6",
1251 .class = &omap54xx_gpio_hwmod_class,
1252 .clkdm_name = "l4per_clkdm",
1253 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1254 .mpu_irqs = omap54xx_gpio6_irqs,
1255 .main_clk = "l4_root_clk_div",
1256 .prcm = {
1257 .omap4 = {
1258 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1259 .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1260 .modulemode = MODULEMODE_HWCTRL,
1261 },
1262 },
1263 .opt_clks = gpio6_opt_clks,
1264 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1265 .dev_attr = &gpio_dev_attr,
1266 };
1268 /* gpio7 */
1269 static struct omap_hwmod_irq_info omap54xx_gpio7_irqs[] = {
1270 { .irq = 35 + OMAP54XX_IRQ_GIC_START },
1271 { .irq = -1 }
1272 };
1274 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
1275 { .role = "dbclk", .clk = "gpio7_dbclk" },
1276 };
1278 static struct omap_hwmod omap54xx_gpio7_hwmod = {
1279 .name = "gpio7",
1280 .class = &omap54xx_gpio_hwmod_class,
1281 .clkdm_name = "l4per_clkdm",
1282 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1283 .mpu_irqs = omap54xx_gpio7_irqs,
1284 .main_clk = "l4_root_clk_div",
1285 .prcm = {
1286 .omap4 = {
1287 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
1288 .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
1289 .modulemode = MODULEMODE_HWCTRL,
1290 },
1291 },
1292 .opt_clks = gpio7_opt_clks,
1293 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
1294 .dev_attr = &gpio_dev_attr,
1295 };
1297 /* gpio8 */
1298 static struct omap_hwmod_irq_info omap54xx_gpio8_irqs[] = {
1299 { .irq = 121 + OMAP54XX_IRQ_GIC_START },
1300 { .irq = -1 }
1301 };
1303 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
1304 { .role = "dbclk", .clk = "gpio8_dbclk" },
1305 };
1307 static struct omap_hwmod omap54xx_gpio8_hwmod = {
1308 .name = "gpio8",
1309 .class = &omap54xx_gpio_hwmod_class,
1310 .clkdm_name = "l4per_clkdm",
1311 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1312 .mpu_irqs = omap54xx_gpio8_irqs,
1313 .main_clk = "l4_root_clk_div",
1314 .prcm = {
1315 .omap4 = {
1316 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1317 .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1318 .modulemode = MODULEMODE_HWCTRL,
1319 },
1320 },
1321 .opt_clks = gpio8_opt_clks,
1322 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
1323 .dev_attr = &gpio_dev_attr,
1324 };
1326 /*
1327 * 'gpmc' class
1328 * general purpose memory controller
1329 */
1331 static struct omap_hwmod_class_sysconfig omap54xx_gpmc_sysc = {
1332 .rev_offs = 0x0000,
1333 .sysc_offs = 0x0010,
1334 .syss_offs = 0x0014,
1335 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1336 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1337 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1338 .sysc_fields = &omap_hwmod_sysc_type1,
1339 };
1341 static struct omap_hwmod_class omap54xx_gpmc_hwmod_class = {
1342 .name = "gpmc",
1343 .sysc = &omap54xx_gpmc_sysc,
1344 };
1346 /* gpmc */
1347 static struct omap_hwmod_irq_info omap54xx_gpmc_irqs[] = {
1348 { .irq = 20 + OMAP54XX_IRQ_GIC_START },
1349 { .irq = -1 }
1350 };
1352 static struct omap_hwmod_dma_info omap54xx_gpmc_sdma_reqs[] = {
1353 { .dma_req = 3 + OMAP54XX_DMA_REQ_START },
1354 { .dma_req = -1 }
1355 };
1357 static struct omap_hwmod omap54xx_gpmc_hwmod = {
1358 .name = "gpmc",
1359 .class = &omap54xx_gpmc_hwmod_class,
1360 .clkdm_name = "l3main2_clkdm",
1361 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1362 .mpu_irqs = omap54xx_gpmc_irqs,
1363 .sdma_reqs = omap54xx_gpmc_sdma_reqs,
1364 .main_clk = "l3_iclk_div",
1365 .prcm = {
1366 .omap4 = {
1367 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET,
1368 .context_offs = OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET,
1369 .modulemode = MODULEMODE_HWCTRL,
1370 },
1371 },
1372 };
1374 /*
1375 * 'gpu' class
1376 * 2d/3d graphics accelerator
1377 */
1379 static struct omap_hwmod_class_sysconfig omap54xx_gpu_sysc = {
1380 .rev_offs = 0x0000,
1381 .sysc_offs = 0x0010,
1382 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1383 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1384 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1385 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1386 .sysc_fields = &omap_hwmod_sysc_type2,
1387 };
1389 static struct omap_hwmod_class omap54xx_gpu_hwmod_class = {
1390 .name = "gpu",
1391 .sysc = &omap54xx_gpu_sysc,
1392 };
1394 /* gpu */
1395 static struct omap_hwmod_irq_info omap54xx_gpu_irqs[] = {
1396 { .irq = 21 + OMAP54XX_IRQ_GIC_START },
1397 { .irq = -1 }
1398 };
1400 static struct omap_hwmod omap54xx_gpu_hwmod = {
1401 .name = "gpu",
1402 .class = &omap54xx_gpu_hwmod_class,
1403 .clkdm_name = "gpu_clkdm",
1404 .mpu_irqs = omap54xx_gpu_irqs,
1405 .main_clk = "gpu_core_gclk_mux",
1406 .prcm = {
1407 .omap4 = {
1408 .clkctrl_offs = OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET,
1409 .context_offs = OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET,
1410 .modulemode = MODULEMODE_SWCTRL,
1411 },
1412 },
1413 };
1415 /*
1416 * 'hdq1w' class
1417 * hdq / 1-wire serial interface controller
1418 */
1420 static struct omap_hwmod_class_sysconfig omap54xx_hdq1w_sysc = {
1421 .rev_offs = 0x0000,
1422 .sysc_offs = 0x0014,
1423 .syss_offs = 0x0018,
1424 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1425 SYSS_HAS_RESET_STATUS),
1426 .sysc_fields = &omap_hwmod_sysc_type1,
1427 };
1429 static struct omap_hwmod_class omap54xx_hdq1w_hwmod_class = {
1430 .name = "hdq1w",
1431 .sysc = &omap54xx_hdq1w_sysc,
1432 };
1434 /* hdq1w */
1435 static struct omap_hwmod_irq_info omap54xx_hdq1w_irqs[] = {
1436 { .irq = 58 + OMAP54XX_IRQ_GIC_START },
1437 { .irq = -1 }
1438 };
1440 static struct omap_hwmod omap54xx_hdq1w_hwmod = {
1441 .name = "hdq1w",
1442 .class = &omap54xx_hdq1w_hwmod_class,
1443 .clkdm_name = "l4per_clkdm",
1444 .flags = HWMOD_INIT_NO_RESET,
1445 .mpu_irqs = omap54xx_hdq1w_irqs,
1446 .main_clk = "func_12m_fclk",
1447 .prcm = {
1448 .omap4 = {
1449 .clkctrl_offs = OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1450 .context_offs = OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1451 .modulemode = MODULEMODE_SWCTRL,
1452 },
1453 },
1454 };
1456 /*
1457 * 'hsi' class
1458 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1459 * serial if)
1460 */
1462 static struct omap_hwmod_class_sysconfig omap54xx_hsi_sysc = {
1463 .rev_offs = 0x0000,
1464 .sysc_offs = 0x0010,
1465 .syss_offs = 0x0014,
1466 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1467 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1468 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1469 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1470 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1471 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1472 .sysc_fields = &omap_hwmod_sysc_type1,
1473 };
1475 static struct omap_hwmod_class omap54xx_hsi_hwmod_class = {
1476 .name = "hsi",
1477 .sysc = &omap54xx_hsi_sysc,
1478 };
1480 /* hsi */
1481 static struct omap_hwmod_irq_info omap54xx_hsi_irqs[] = {
1482 { .name = "mpu_p1", .irq = 67 + OMAP54XX_IRQ_GIC_START },
1483 { .name = "mpu_p2", .irq = 68 + OMAP54XX_IRQ_GIC_START },
1484 { .name = "mpu_dma", .irq = 71 + OMAP54XX_IRQ_GIC_START },
1485 { .irq = -1 }
1486 };
1488 static struct omap_hwmod omap54xx_hsi_hwmod = {
1489 .name = "hsi",
1490 .class = &omap54xx_hsi_hwmod_class,
1491 .clkdm_name = "l3init_clkdm",
1492 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1493 .mpu_irqs = omap54xx_hsi_irqs,
1494 .main_clk = "hsi_fclk",
1495 .prcm = {
1496 .omap4 = {
1497 .clkctrl_offs = OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1498 .context_offs = OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET,
1499 .modulemode = MODULEMODE_HWCTRL,
1500 },
1501 },
1502 };
1504 /*
1505 * 'i2c' class
1506 * multimaster high-speed i2c controller
1507 */
1509 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
1510 .sysc_offs = 0x0010,
1511 .syss_offs = 0x0090,
1512 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1513 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1514 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1515 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1516 SIDLE_SMART_WKUP),
1517 .clockact = CLOCKACT_TEST_ICLK,
1518 .sysc_fields = &omap_hwmod_sysc_type1,
1519 };
1521 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
1522 .name = "i2c",
1523 .sysc = &omap54xx_i2c_sysc,
1524 .reset = &omap_i2c_reset,
1525 .rev = OMAP_I2C_IP_VERSION_2,
1526 };
1528 /* i2c dev_attr */
1529 static struct omap_i2c_dev_attr i2c_dev_attr = {
1530 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1531 };
1533 /* i2c1 */
1534 static struct omap_hwmod_irq_info omap54xx_i2c1_irqs[] = {
1535 { .irq = 56 + OMAP54XX_IRQ_GIC_START },
1536 { .irq = -1 }
1537 };
1539 static struct omap_hwmod_dma_info omap54xx_i2c1_sdma_reqs[] = {
1540 { .name = "tx", .dma_req = 26 + OMAP54XX_DMA_REQ_START },
1541 { .name = "rx", .dma_req = 27 + OMAP54XX_DMA_REQ_START },
1542 { .dma_req = -1 }
1543 };
1545 static struct omap_hwmod omap54xx_i2c1_hwmod = {
1546 .name = "i2c1",
1547 .class = &omap54xx_i2c_hwmod_class,
1548 .clkdm_name = "l4per_clkdm",
1549 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1550 .mpu_irqs = omap54xx_i2c1_irqs,
1551 .sdma_reqs = omap54xx_i2c1_sdma_reqs,
1552 .main_clk = "func_96m_fclk",
1553 .prcm = {
1554 .omap4 = {
1555 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1556 .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1557 .modulemode = MODULEMODE_SWCTRL,
1558 },
1559 },
1560 .dev_attr = &i2c_dev_attr,
1561 };
1563 /* i2c2 */
1564 static struct omap_hwmod_irq_info omap54xx_i2c2_irqs[] = {
1565 { .irq = 57 + OMAP54XX_IRQ_GIC_START },
1566 { .irq = -1 }
1567 };
1569 static struct omap_hwmod_dma_info omap54xx_i2c2_sdma_reqs[] = {
1570 { .name = "tx", .dma_req = 28 + OMAP54XX_DMA_REQ_START },
1571 { .name = "rx", .dma_req = 29 + OMAP54XX_DMA_REQ_START },
1572 { .dma_req = -1 }
1573 };
1575 static struct omap_hwmod omap54xx_i2c2_hwmod = {
1576 .name = "i2c2",
1577 .class = &omap54xx_i2c_hwmod_class,
1578 .clkdm_name = "l4per_clkdm",
1579 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1580 .mpu_irqs = omap54xx_i2c2_irqs,
1581 .sdma_reqs = omap54xx_i2c2_sdma_reqs,
1582 .main_clk = "func_96m_fclk",
1583 .prcm = {
1584 .omap4 = {
1585 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1586 .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1587 .modulemode = MODULEMODE_SWCTRL,
1588 },
1589 },
1590 .dev_attr = &i2c_dev_attr,
1591 };
1593 /* i2c3 */
1594 static struct omap_hwmod_irq_info omap54xx_i2c3_irqs[] = {
1595 { .irq = 61 + OMAP54XX_IRQ_GIC_START },
1596 { .irq = -1 }
1597 };
1599 static struct omap_hwmod_dma_info omap54xx_i2c3_sdma_reqs[] = {
1600 { .name = "tx", .dma_req = 24 + OMAP54XX_DMA_REQ_START },
1601 { .name = "rx", .dma_req = 25 + OMAP54XX_DMA_REQ_START },
1602 { .dma_req = -1 }
1603 };
1605 static struct omap_hwmod omap54xx_i2c3_hwmod = {
1606 .name = "i2c3",
1607 .class = &omap54xx_i2c_hwmod_class,
1608 .clkdm_name = "l4per_clkdm",
1609 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1610 .mpu_irqs = omap54xx_i2c3_irqs,
1611 .sdma_reqs = omap54xx_i2c3_sdma_reqs,
1612 .main_clk = "func_96m_fclk",
1613 .prcm = {
1614 .omap4 = {
1615 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1616 .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1617 .modulemode = MODULEMODE_SWCTRL,
1618 },
1619 },
1620 .dev_attr = &i2c_dev_attr,
1621 };
1623 /* i2c4 */
1624 static struct omap_hwmod_irq_info omap54xx_i2c4_irqs[] = {
1625 { .irq = 62 + OMAP54XX_IRQ_GIC_START },
1626 { .irq = -1 }
1627 };
1629 static struct omap_hwmod_dma_info omap54xx_i2c4_sdma_reqs[] = {
1630 { .name = "tx", .dma_req = 123 + OMAP54XX_DMA_REQ_START },
1631 { .name = "rx", .dma_req = 124 + OMAP54XX_DMA_REQ_START },
1632 { .dma_req = -1 }
1633 };
1635 static struct omap_hwmod omap54xx_i2c4_hwmod = {
1636 .name = "i2c4",
1637 .class = &omap54xx_i2c_hwmod_class,
1638 .clkdm_name = "l4per_clkdm",
1639 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1640 .mpu_irqs = omap54xx_i2c4_irqs,
1641 .sdma_reqs = omap54xx_i2c4_sdma_reqs,
1642 .main_clk = "func_96m_fclk",
1643 .prcm = {
1644 .omap4 = {
1645 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1646 .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1647 .modulemode = MODULEMODE_SWCTRL,
1648 },
1649 },
1650 .dev_attr = &i2c_dev_attr,
1651 };
1653 /* i2c5 */
1654 static struct omap_hwmod_irq_info omap54xx_i2c5_irqs[] = {
1655 { .irq = 60 + OMAP54XX_IRQ_GIC_START },
1656 { .irq = -1 }
1657 };
1659 static struct omap_hwmod omap54xx_i2c5_hwmod = {
1660 .name = "i2c5",
1661 .class = &omap54xx_i2c_hwmod_class,
1662 .clkdm_name = "l4per_clkdm",
1663 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1664 .mpu_irqs = omap54xx_i2c5_irqs,
1665 .main_clk = "func_96m_fclk",
1666 .prcm = {
1667 .omap4 = {
1668 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
1669 .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
1670 .modulemode = MODULEMODE_SWCTRL,
1671 },
1672 },
1673 .dev_attr = &i2c_dev_attr,
1674 };
1676 /*
1677 * 'ipu' class
1678 * imaging processor unit
1679 */
1681 static struct omap_hwmod_class_sysconfig omap54xx_ipu_sysc = {
1682 .rev_offs = 0x0000,
1683 .sysc_offs = 0x0010,
1684 .syss_offs = 0x0014,
1685 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1686 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1687 SYSS_HAS_RESET_STATUS),
1688 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1689 .sysc_fields = &omap_hwmod_sysc_type1,
1690 };
1692 static struct omap_hwmod_class omap54xx_ipu_hwmod_class = {
1693 .name = "ipu",
1694 .sysc = &omap54xx_ipu_sysc,
1695 };
1697 /* ipu */
1698 static struct omap_hwmod_irq_info omap54xx_ipu_irqs[] = {
1699 { .irq = 100 + OMAP54XX_IRQ_GIC_START },
1700 { .irq = -1 }
1701 };
1703 static struct omap_hwmod_rst_info omap54xx_ipu_resets[] = {
1704 { .name = "cpu0", .rst_shift = 0 },
1705 { .name = "cpu1", .rst_shift = 1 },
1706 { .name = "mmu_cache", .rst_shift = 2 },
1707 };
1709 static struct omap_hwmod omap54xx_ipu_hwmod = {
1710 .name = "ipu",
1711 .class = &omap54xx_ipu_hwmod_class,
1712 .clkdm_name = "ipu_clkdm",
1713 .mpu_irqs = omap54xx_ipu_irqs,
1714 .rst_lines = omap54xx_ipu_resets,
1715 .rst_lines_cnt = ARRAY_SIZE(omap54xx_ipu_resets),
1716 .main_clk = "dpll_core_h22x2_ck",
1717 .prcm = {
1718 .omap4 = {
1719 .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
1720 .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
1721 .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
1722 .modulemode = MODULEMODE_HWCTRL,
1723 },
1724 },
1725 };
1727 /*
1728 * 'intc' class
1729 * nested vectored interrupt controller
1730 */
1732 static struct omap_hwmod_class omap54xx_intc_hwmod_class = {
1733 .name = "intc",
1734 };
1736 /* intc_ipu_c0 */
1737 static struct omap_hwmod omap54xx_intc_ipu_c0_hwmod = {
1738 .name = "intc_ipu_c0",
1739 .class = &omap54xx_intc_hwmod_class,
1740 .clkdm_name = "ipu_clkdm",
1741 .main_clk = "dpll_core_h22x2_ck",
1742 .prcm = {
1743 .omap4 = {
1744 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1745 },
1746 },
1747 };
1749 /* intc_ipu_c1 */
1750 static struct omap_hwmod omap54xx_intc_ipu_c1_hwmod = {
1751 .name = "intc_ipu_c1",
1752 .class = &omap54xx_intc_hwmod_class,
1753 .clkdm_name = "ipu_clkdm",
1754 .main_clk = "dpll_core_h22x2_ck",
1755 .prcm = {
1756 .omap4 = {
1757 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1758 },
1759 },
1760 };
1762 /*
1763 * 'iss' class
1764 * external images sensor pixel data processor
1765 */
1767 static struct omap_hwmod_class_sysconfig omap54xx_iss_sysc = {
1768 .rev_offs = 0x0000,
1769 .sysc_offs = 0x0010,
1770 /*
1771 * ISS needs 100 OCP clk cycles delay after a softreset before
1772 * accessing sysconfig again.
1773 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1774 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1775 *
1776 * TODO: Indicate errata when available.
1777 */
1778 .srst_udelay = 2,
1779 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1780 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1781 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1782 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1783 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1784 .sysc_fields = &omap_hwmod_sysc_type2,
1785 };
1787 static struct omap_hwmod_class omap54xx_iss_hwmod_class = {
1788 .name = "iss",
1789 .sysc = &omap54xx_iss_sysc,
1790 };
1792 /* iss */
1793 static struct omap_hwmod_irq_info omap54xx_iss_irqs[] = {
1794 { .irq = 24 + OMAP54XX_IRQ_GIC_START },
1795 { .irq = -1 }
1796 };
1798 static struct omap_hwmod_dma_info omap54xx_iss_sdma_reqs[] = {
1799 { .name = "1", .dma_req = 8 + OMAP54XX_DMA_REQ_START },
1800 { .name = "2", .dma_req = 9 + OMAP54XX_DMA_REQ_START },
1801 { .name = "3", .dma_req = 11 + OMAP54XX_DMA_REQ_START },
1802 { .name = "4", .dma_req = 12 + OMAP54XX_DMA_REQ_START },
1803 { .name = "5", .dma_req = 30 + OMAP54XX_DMA_REQ_START },
1804 { .name = "6", .dma_req = 31 + OMAP54XX_DMA_REQ_START },
1805 { .name = "7", .dma_req = 125 + OMAP54XX_DMA_REQ_START },
1806 { .name = "8", .dma_req = 126 + OMAP54XX_DMA_REQ_START },
1807 { .dma_req = -1 }
1808 };
1810 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1811 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1812 };
1814 static struct omap_hwmod omap54xx_iss_hwmod = {
1815 .name = "iss",
1816 .class = &omap54xx_iss_hwmod_class,
1817 .clkdm_name = "cam_clkdm",
1818 .flags = HWMOD_INIT_NO_RESET,
1819 .mpu_irqs = omap54xx_iss_irqs,
1820 .sdma_reqs = omap54xx_iss_sdma_reqs,
1821 .main_clk = "dpll_core_h22x2_ck",
1822 .prcm = {
1823 .omap4 = {
1824 .clkctrl_offs = OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET,
1825 .context_offs = OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET,
1826 .modulemode = MODULEMODE_SWCTRL,
1827 },
1828 },
1829 .opt_clks = iss_opt_clks,
1830 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1831 };
1833 /*
1834 * 'iva' class
1835 * multi-standard video encoder/decoder hardware accelerator
1836 */
1838 static struct omap_hwmod_class_sysconfig omap54xx_iva_sysc = {
1839 .rev_offs = 0x0000,
1840 .sysc_offs = 0x0010,
1841 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1842 .idlemodes = (SIDLE_NO | SIDLE_SMART | MSTANDBY_NO |
1843 MSTANDBY_SMART),
1844 .sysc_fields = &omap_hwmod_sysc_type2,
1845 };
1847 static struct omap_hwmod_class omap54xx_iva_hwmod_class = {
1848 .name = "iva",
1849 .sysc = &omap54xx_iva_sysc,
1850 };
1852 /* iva */
1853 static struct omap_hwmod_irq_info omap54xx_iva_irqs[] = {
1854 { .name = "sync_1", .irq = 103 + OMAP54XX_IRQ_GIC_START },
1855 { .name = "sync_0", .irq = 104 + OMAP54XX_IRQ_GIC_START },
1856 { .name = "mailbox_0", .irq = 107 + OMAP54XX_IRQ_GIC_START },
1857 { .irq = -1 }
1858 };
1860 static struct omap_hwmod_rst_info omap54xx_iva_resets[] = {
1861 { .name = "seq0", .rst_shift = 0 },
1862 { .name = "seq1", .rst_shift = 1 },
1863 { .name = "logic", .rst_shift = 2 },
1864 };
1866 static struct omap_hwmod omap54xx_iva_hwmod = {
1867 .name = "iva",
1868 .class = &omap54xx_iva_hwmod_class,
1869 .clkdm_name = "iva_clkdm",
1870 .mpu_irqs = omap54xx_iva_irqs,
1871 .rst_lines = omap54xx_iva_resets,
1872 .rst_lines_cnt = ARRAY_SIZE(omap54xx_iva_resets),
1873 .main_clk = "dpll_iva_h12x2_ck",
1874 .prcm = {
1875 .omap4 = {
1876 .clkctrl_offs = OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET,
1877 .rstctrl_offs = OMAP54XX_RM_IVA_RSTCTRL_OFFSET,
1878 .context_offs = OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET,
1879 .modulemode = MODULEMODE_HWCTRL,
1880 },
1881 },
1882 };
1884 /*
1885 * 'kbd' class
1886 * keyboard controller
1887 */
1889 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
1890 .rev_offs = 0x0000,
1891 .sysc_offs = 0x0010,
1892 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1893 SYSC_HAS_SOFTRESET),
1894 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1895 .sysc_fields = &omap_hwmod_sysc_type1,
1896 };
1898 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
1899 .name = "kbd",
1900 .sysc = &omap54xx_kbd_sysc,
1901 };
1903 /* kbd */
1904 static struct omap_hwmod_irq_info omap54xx_kbd_irqs[] = {
1905 { .irq = 120 + OMAP54XX_IRQ_GIC_START },
1906 { .irq = -1 }
1907 };
1909 static struct omap_hwmod omap54xx_kbd_hwmod = {
1910 .name = "kbd",
1911 .class = &omap54xx_kbd_hwmod_class,
1912 .clkdm_name = "wkupaon_clkdm",
1913 .mpu_irqs = omap54xx_kbd_irqs,
1914 .main_clk = "sys_32k_ck",
1915 .prcm = {
1916 .omap4 = {
1917 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
1918 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
1919 .modulemode = MODULEMODE_SWCTRL,
1920 },
1921 },
1922 };
1924 /*
1925 * 'mailbox' class
1926 * mailbox module allowing communication between the on-chip processors
1927 * useusing a queued mailbox-interrupt mechanism.
1928 */
1930 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
1931 .rev_offs = 0x0000,
1932 .sysc_offs = 0x0010,
1933 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1934 SYSC_HAS_SOFTRESET),
1935 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1936 .sysc_fields = &omap_hwmod_sysc_type2,
1937 };
1939 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
1940 .name = "mailbox",
1941 .sysc = &omap54xx_mailbox_sysc,
1942 };
1944 /* mailbox */
1945 static struct omap_mbox_dev_info omap54xx_mbox_info[] = {
1946 { .name = "mbox-ipu", .tx_id = 0, .rx_id = 1 },
1947 { .name = "mbox-dsp", .tx_id = 3, .rx_id = 2 },
1948 };
1950 static struct omap_mbox_pdata omap54xx_mbox_attrs = {
1951 .intr_type = MBOX_INTR_CFG_TYPE2,
1952 .info_cnt = ARRAY_SIZE(omap54xx_mbox_info),
1953 .info = omap54xx_mbox_info,
1954 };
1956 static struct omap_hwmod_irq_info omap54xx_mailbox_irqs[] = {
1957 { .irq = 26 + OMAP54XX_IRQ_GIC_START },
1958 { .irq = -1 }
1959 };
1961 static struct omap_hwmod omap54xx_mailbox_hwmod = {
1962 .name = "mailbox",
1963 .class = &omap54xx_mailbox_hwmod_class,
1964 .clkdm_name = "l4cfg_clkdm",
1965 .mpu_irqs = omap54xx_mailbox_irqs,
1966 .main_clk = "l4_root_clk_div",
1967 .prcm = {
1968 .omap4 = {
1969 .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1970 .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1971 },
1972 },
1973 .dev_attr = &omap54xx_mbox_attrs,
1974 };
1976 /*
1977 * 'mcasp' class
1978 * multi-channel audio serial port controller
1979 */
1981 static struct omap_hwmod_class_sysconfig omap54xx_mcasp_sysc = {
1982 .sysc_offs = 0x0004,
1983 .sysc_flags = SYSC_HAS_SIDLEMODE,
1984 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1985 .sysc_fields = &omap_hwmod_sysc_type3,
1986 };
1988 static struct omap_hwmod_class omap54xx_mcasp_hwmod_class = {
1989 .name = "mcasp",
1990 .sysc = &omap54xx_mcasp_sysc,
1991 };
1993 /* mcasp */
1994 static struct omap_hwmod_irq_info omap54xx_mcasp_irqs[] = {
1995 { .name = "arevt", .irq = 108 + OMAP54XX_IRQ_GIC_START },
1996 { .name = "axevt", .irq = 109 + OMAP54XX_IRQ_GIC_START },
1997 { .irq = -1 }
1998 };
2000 static struct omap_hwmod_dma_info omap54xx_mcasp_sdma_reqs[] = {
2001 { .name = "axevt", .dma_req = 7 + OMAP54XX_DMA_REQ_START },
2002 { .name = "arevt", .dma_req = 10 + OMAP54XX_DMA_REQ_START },
2003 { .dma_req = -1 }
2004 };
2006 static struct omap_hwmod omap54xx_mcasp_hwmod = {
2007 .name = "mcasp",
2008 .class = &omap54xx_mcasp_hwmod_class,
2009 .clkdm_name = "abe_clkdm",
2010 .flags = HWMOD_SWSUP_SIDLE,
2011 .mpu_irqs = omap54xx_mcasp_irqs,
2012 .sdma_reqs = omap54xx_mcasp_sdma_reqs,
2013 .main_clk = "mcasp_gfclk",
2014 .prcm = {
2015 .omap4 = {
2016 .clkctrl_offs = OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET,
2017 .context_offs = OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET,
2018 .modulemode = MODULEMODE_SWCTRL,
2019 },
2020 },
2021 };
2023 /*
2024 * 'mcbsp' class
2025 * multi channel buffered serial port controller
2026 */
2028 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
2029 .sysc_offs = 0x008c,
2030 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2031 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2032 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2033 .sysc_fields = &omap_hwmod_sysc_type1,
2034 };
2036 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
2037 .name = "mcbsp",
2038 .sysc = &omap54xx_mcbsp_sysc,
2039 .rev = MCBSP_CONFIG_TYPE4,
2040 };
2042 /* mcbsp1 */
2043 static struct omap_hwmod_irq_info omap54xx_mcbsp1_irqs[] = {
2044 { .name = "common", .irq = 17 + OMAP54XX_IRQ_GIC_START },
2045 { .irq = -1 }
2046 };
2048 static struct omap_hwmod_dma_info omap54xx_mcbsp1_sdma_reqs[] = {
2049 { .name = "tx", .dma_req = 32 + OMAP54XX_DMA_REQ_START },
2050 { .name = "rx", .dma_req = 33 + OMAP54XX_DMA_REQ_START },
2051 { .dma_req = -1 }
2052 };
2054 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
2055 { .role = "pad_fck", .clk = "pad_clks_ck" },
2056 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
2057 };
2059 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
2060 .name = "mcbsp1",
2061 .class = &omap54xx_mcbsp_hwmod_class,
2062 .clkdm_name = "abe_clkdm",
2063 .mpu_irqs = omap54xx_mcbsp1_irqs,
2064 .sdma_reqs = omap54xx_mcbsp1_sdma_reqs,
2065 .main_clk = "mcbsp1_gfclk",
2066 .prcm = {
2067 .omap4 = {
2068 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
2069 .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
2070 .modulemode = MODULEMODE_SWCTRL,
2071 },
2072 },
2073 .opt_clks = mcbsp1_opt_clks,
2074 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
2075 };
2077 /* mcbsp2 */
2078 static struct omap_hwmod_irq_info omap54xx_mcbsp2_irqs[] = {
2079 { .name = "common", .irq = 22 + OMAP54XX_IRQ_GIC_START },
2080 { .irq = -1 }
2081 };
2083 static struct omap_hwmod_dma_info omap54xx_mcbsp2_sdma_reqs[] = {
2084 { .name = "tx", .dma_req = 16 + OMAP54XX_DMA_REQ_START },
2085 { .name = "rx", .dma_req = 17 + OMAP54XX_DMA_REQ_START },
2086 { .dma_req = -1 }
2087 };
2089 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2090 { .role = "pad_fck", .clk = "pad_clks_ck" },
2091 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2092 };
2094 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
2095 .name = "mcbsp2",
2096 .class = &omap54xx_mcbsp_hwmod_class,
2097 .clkdm_name = "abe_clkdm",
2098 .mpu_irqs = omap54xx_mcbsp2_irqs,
2099 .sdma_reqs = omap54xx_mcbsp2_sdma_reqs,
2100 .main_clk = "mcbsp2_gfclk",
2101 .prcm = {
2102 .omap4 = {
2103 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
2104 .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2105 .modulemode = MODULEMODE_SWCTRL,
2106 },
2107 },
2108 .opt_clks = mcbsp2_opt_clks,
2109 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
2110 };
2112 /* mcbsp3 */
2113 static struct omap_hwmod_irq_info omap54xx_mcbsp3_irqs[] = {
2114 { .name = "common", .irq = 23 + OMAP54XX_IRQ_GIC_START },
2115 { .irq = -1 }
2116 };
2118 static struct omap_hwmod_dma_info omap54xx_mcbsp3_sdma_reqs[] = {
2119 { .name = "tx", .dma_req = 18 + OMAP54XX_DMA_REQ_START },
2120 { .name = "rx", .dma_req = 19 + OMAP54XX_DMA_REQ_START },
2121 { .dma_req = -1 }
2122 };
2124 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2125 { .role = "pad_fck", .clk = "pad_clks_ck" },
2126 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2127 };
2129 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
2130 .name = "mcbsp3",
2131 .class = &omap54xx_mcbsp_hwmod_class,
2132 .clkdm_name = "abe_clkdm",
2133 .mpu_irqs = omap54xx_mcbsp3_irqs,
2134 .sdma_reqs = omap54xx_mcbsp3_sdma_reqs,
2135 .main_clk = "mcbsp3_gfclk",
2136 .prcm = {
2137 .omap4 = {
2138 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
2139 .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2140 .modulemode = MODULEMODE_SWCTRL,
2141 },
2142 },
2143 .opt_clks = mcbsp3_opt_clks,
2144 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
2145 };
2147 /*
2148 * 'mcpdm' class
2149 * multi channel pdm controller (proprietary interface with phoenix power
2150 * ic)
2151 */
2153 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
2154 .rev_offs = 0x0000,
2155 .sysc_offs = 0x0010,
2156 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2157 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2158 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2159 SIDLE_SMART_WKUP),
2160 .sysc_fields = &omap_hwmod_sysc_type2,
2161 };
2163 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
2164 .name = "mcpdm",
2165 .sysc = &omap54xx_mcpdm_sysc,
2166 };
2168 /* mcpdm */
2169 static struct omap_hwmod_irq_info omap54xx_mcpdm_irqs[] = {
2170 { .irq = 112 + OMAP54XX_IRQ_GIC_START },
2171 { .irq = -1 }
2172 };
2174 static struct omap_hwmod_dma_info omap54xx_mcpdm_sdma_reqs[] = {
2175 { .name = "up_link", .dma_req = 64 + OMAP54XX_DMA_REQ_START },
2176 { .name = "dn_link", .dma_req = 65 + OMAP54XX_DMA_REQ_START },
2177 { .dma_req = -1 }
2178 };
2180 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
2181 .name = "mcpdm",
2182 .class = &omap54xx_mcpdm_hwmod_class,
2183 .clkdm_name = "abe_clkdm",
2184 /*
2185 * It's suspected that the McPDM requires an off-chip main
2186 * functional clock, controlled via I2C. This IP block is
2187 * currently reset very early during boot, before I2C is
2188 * available, so it doesn't seem that we have any choice in
2189 * the kernel other than to avoid resetting it. XXX This is
2190 * really a hardware issue workaround: every IP block should
2191 * be able to source its main functional clock from either
2192 * on-chip or off-chip sources. McPDM seems to be the only
2193 * current exception.
2194 */
2196 .flags = HWMOD_EXT_OPT_MAIN_CLK,
2197 .mpu_irqs = omap54xx_mcpdm_irqs,
2198 .sdma_reqs = omap54xx_mcpdm_sdma_reqs,
2199 .main_clk = "pad_clks_ck",
2200 .prcm = {
2201 .omap4 = {
2202 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
2203 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
2204 .modulemode = MODULEMODE_SWCTRL,
2205 },
2206 },
2207 };
2209 /*
2210 * 'mcspi' class
2211 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2212 * bus
2213 */
2215 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
2216 .rev_offs = 0x0000,
2217 .sysc_offs = 0x0010,
2218 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2219 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2220 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2221 SIDLE_SMART_WKUP),
2222 .sysc_fields = &omap_hwmod_sysc_type2,
2223 };
2225 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
2226 .name = "mcspi",
2227 .sysc = &omap54xx_mcspi_sysc,
2228 .rev = OMAP4_MCSPI_REV,
2229 };
2231 /* mcspi1 */
2232 static struct omap_hwmod_irq_info omap54xx_mcspi1_irqs[] = {
2233 { .irq = 65 + OMAP54XX_IRQ_GIC_START },
2234 { .irq = -1 }
2235 };
2237 static struct omap_hwmod_dma_info omap54xx_mcspi1_sdma_reqs[] = {
2238 { .name = "tx0", .dma_req = 34 + OMAP54XX_DMA_REQ_START },
2239 { .name = "rx0", .dma_req = 35 + OMAP54XX_DMA_REQ_START },
2240 { .name = "tx1", .dma_req = 36 + OMAP54XX_DMA_REQ_START },
2241 { .name = "rx1", .dma_req = 37 + OMAP54XX_DMA_REQ_START },
2242 { .name = "tx2", .dma_req = 38 + OMAP54XX_DMA_REQ_START },
2243 { .name = "rx2", .dma_req = 39 + OMAP54XX_DMA_REQ_START },
2244 { .name = "tx3", .dma_req = 40 + OMAP54XX_DMA_REQ_START },
2245 { .name = "rx3", .dma_req = 41 + OMAP54XX_DMA_REQ_START },
2246 { .dma_req = -1 }
2247 };
2249 /* mcspi1 dev_attr */
2250 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2251 .num_chipselect = 4,
2252 };
2254 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
2255 .name = "mcspi1",
2256 .class = &omap54xx_mcspi_hwmod_class,
2257 .clkdm_name = "l4per_clkdm",
2258 .mpu_irqs = omap54xx_mcspi1_irqs,
2259 .sdma_reqs = omap54xx_mcspi1_sdma_reqs,
2260 .main_clk = "func_48m_fclk",
2261 .prcm = {
2262 .omap4 = {
2263 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2264 .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2265 .modulemode = MODULEMODE_SWCTRL,
2266 },
2267 },
2268 .dev_attr = &mcspi1_dev_attr,
2269 };
2271 /* mcspi2 */
2272 static struct omap_hwmod_irq_info omap54xx_mcspi2_irqs[] = {
2273 { .irq = 66 + OMAP54XX_IRQ_GIC_START },
2274 { .irq = -1 }
2275 };
2277 static struct omap_hwmod_dma_info omap54xx_mcspi2_sdma_reqs[] = {
2278 { .name = "tx0", .dma_req = 42 + OMAP54XX_DMA_REQ_START },
2279 { .name = "rx0", .dma_req = 43 + OMAP54XX_DMA_REQ_START },
2280 { .name = "tx1", .dma_req = 44 + OMAP54XX_DMA_REQ_START },
2281 { .name = "rx1", .dma_req = 45 + OMAP54XX_DMA_REQ_START },
2282 { .dma_req = -1 }
2283 };
2285 /* mcspi2 dev_attr */
2286 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2287 .num_chipselect = 2,
2288 };
2290 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
2291 .name = "mcspi2",
2292 .class = &omap54xx_mcspi_hwmod_class,
2293 .clkdm_name = "l4per_clkdm",
2294 .mpu_irqs = omap54xx_mcspi2_irqs,
2295 .sdma_reqs = omap54xx_mcspi2_sdma_reqs,
2296 .main_clk = "func_48m_fclk",
2297 .prcm = {
2298 .omap4 = {
2299 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2300 .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2301 .modulemode = MODULEMODE_SWCTRL,
2302 },
2303 },
2304 .dev_attr = &mcspi2_dev_attr,
2305 };
2307 /* mcspi3 */
2308 static struct omap_hwmod_irq_info omap54xx_mcspi3_irqs[] = {
2309 { .irq = 91 + OMAP54XX_IRQ_GIC_START },
2310 { .irq = -1 }
2311 };
2313 static struct omap_hwmod_dma_info omap54xx_mcspi3_sdma_reqs[] = {
2314 { .name = "tx0", .dma_req = 14 + OMAP54XX_DMA_REQ_START },
2315 { .name = "rx0", .dma_req = 15 + OMAP54XX_DMA_REQ_START },
2316 { .dma_req = -1 }
2317 };
2319 /* mcspi3 dev_attr */
2320 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2321 .num_chipselect = 2,
2322 };
2324 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
2325 .name = "mcspi3",
2326 .class = &omap54xx_mcspi_hwmod_class,
2327 .clkdm_name = "l4per_clkdm",
2328 .mpu_irqs = omap54xx_mcspi3_irqs,
2329 .sdma_reqs = omap54xx_mcspi3_sdma_reqs,
2330 .main_clk = "func_48m_fclk",
2331 .prcm = {
2332 .omap4 = {
2333 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2334 .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2335 .modulemode = MODULEMODE_SWCTRL,
2336 },
2337 },
2338 .dev_attr = &mcspi3_dev_attr,
2339 };
2341 /* mcspi4 */
2342 static struct omap_hwmod_irq_info omap54xx_mcspi4_irqs[] = {
2343 { .irq = 48 + OMAP54XX_IRQ_GIC_START },
2344 { .irq = -1 }
2345 };
2347 static struct omap_hwmod_dma_info omap54xx_mcspi4_sdma_reqs[] = {
2348 { .name = "tx0", .dma_req = 69 + OMAP54XX_DMA_REQ_START },
2349 { .name = "rx0", .dma_req = 70 + OMAP54XX_DMA_REQ_START },
2350 { .dma_req = -1 }
2351 };
2353 /* mcspi4 dev_attr */
2354 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2355 .num_chipselect = 1,
2356 };
2358 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
2359 .name = "mcspi4",
2360 .class = &omap54xx_mcspi_hwmod_class,
2361 .clkdm_name = "l4per_clkdm",
2362 .mpu_irqs = omap54xx_mcspi4_irqs,
2363 .sdma_reqs = omap54xx_mcspi4_sdma_reqs,
2364 .main_clk = "func_48m_fclk",
2365 .prcm = {
2366 .omap4 = {
2367 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2368 .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2369 .modulemode = MODULEMODE_SWCTRL,
2370 },
2371 },
2372 .dev_attr = &mcspi4_dev_attr,
2373 };
2375 /*
2376 * 'mmc' class
2377 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2378 */
2380 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
2381 .rev_offs = 0x0000,
2382 .sysc_offs = 0x0010,
2383 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2384 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2385 SYSC_HAS_SOFTRESET),
2386 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2387 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2388 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2389 .sysc_fields = &omap_hwmod_sysc_type2,
2390 };
2392 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
2393 .name = "mmc",
2394 .sysc = &omap54xx_mmc_sysc,
2395 };
2397 /* mmc1 */
2398 static struct omap_hwmod_irq_info omap54xx_mmc1_irqs[] = {
2399 { .irq = 83 + OMAP54XX_IRQ_GIC_START },
2400 { .irq = -1 }
2401 };
2403 static struct omap_hwmod_dma_info omap54xx_mmc1_sdma_reqs[] = {
2404 { .name = "tx", .dma_req = 60 + OMAP54XX_DMA_REQ_START },
2405 { .name = "rx", .dma_req = 61 + OMAP54XX_DMA_REQ_START },
2406 { .dma_req = -1 }
2407 };
2409 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
2410 { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
2411 };
2413 /* mmc1 dev_attr */
2414 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2415 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2416 };
2418 static struct omap_hwmod omap54xx_mmc1_hwmod = {
2419 .name = "mmc1",
2420 .class = &omap54xx_mmc_hwmod_class,
2421 .clkdm_name = "l3init_clkdm",
2422 .mpu_irqs = omap54xx_mmc1_irqs,
2423 .sdma_reqs = omap54xx_mmc1_sdma_reqs,
2424 .main_clk = "mmc1_fclk",
2425 .prcm = {
2426 .omap4 = {
2427 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2428 .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2429 .modulemode = MODULEMODE_SWCTRL,
2430 },
2431 },
2432 .opt_clks = mmc1_opt_clks,
2433 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
2434 .dev_attr = &mmc1_dev_attr,
2435 };
2437 /* mmc2 */
2438 static struct omap_hwmod_irq_info omap54xx_mmc2_irqs[] = {
2439 { .irq = 86 + OMAP54XX_IRQ_GIC_START },
2440 { .irq = -1 }
2441 };
2443 static struct omap_hwmod_dma_info omap54xx_mmc2_sdma_reqs[] = {
2444 { .name = "tx", .dma_req = 46 + OMAP54XX_DMA_REQ_START },
2445 { .name = "rx", .dma_req = 47 + OMAP54XX_DMA_REQ_START },
2446 { .dma_req = -1 }
2447 };
2449 static struct omap_hwmod omap54xx_mmc2_hwmod = {
2450 .name = "mmc2",
2451 .class = &omap54xx_mmc_hwmod_class,
2452 .clkdm_name = "l3init_clkdm",
2453 .mpu_irqs = omap54xx_mmc2_irqs,
2454 .sdma_reqs = omap54xx_mmc2_sdma_reqs,
2455 .main_clk = "mmc2_fclk",
2456 .prcm = {
2457 .omap4 = {
2458 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2459 .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2460 .modulemode = MODULEMODE_SWCTRL,
2461 },
2462 },
2463 };
2465 /* mmc3 */
2466 static struct omap_hwmod_irq_info omap54xx_mmc3_irqs[] = {
2467 { .irq = 94 + OMAP54XX_IRQ_GIC_START },
2468 { .irq = -1 }
2469 };
2471 static struct omap_hwmod_dma_info omap54xx_mmc3_sdma_reqs[] = {
2472 { .name = "tx", .dma_req = 76 + OMAP54XX_DMA_REQ_START },
2473 { .name = "rx", .dma_req = 77 + OMAP54XX_DMA_REQ_START },
2474 { .dma_req = -1 }
2475 };
2477 static struct omap_hwmod omap54xx_mmc3_hwmod = {
2478 .name = "mmc3",
2479 .class = &omap54xx_mmc_hwmod_class,
2480 .clkdm_name = "l4per_clkdm",
2481 .mpu_irqs = omap54xx_mmc3_irqs,
2482 .sdma_reqs = omap54xx_mmc3_sdma_reqs,
2483 .main_clk = "func_48m_fclk",
2484 .prcm = {
2485 .omap4 = {
2486 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
2487 .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
2488 .modulemode = MODULEMODE_SWCTRL,
2489 },
2490 },
2491 };
2493 /* mmc4 */
2494 static struct omap_hwmod_irq_info omap54xx_mmc4_irqs[] = {
2495 { .irq = 96 + OMAP54XX_IRQ_GIC_START },
2496 { .irq = -1 }
2497 };
2499 static struct omap_hwmod_dma_info omap54xx_mmc4_sdma_reqs[] = {
2500 { .name = "tx", .dma_req = 56 + OMAP54XX_DMA_REQ_START },
2501 { .name = "rx", .dma_req = 57 + OMAP54XX_DMA_REQ_START },
2502 { .dma_req = -1 }
2503 };
2505 static struct omap_hwmod omap54xx_mmc4_hwmod = {
2506 .name = "mmc4",
2507 .class = &omap54xx_mmc_hwmod_class,
2508 .clkdm_name = "l4per_clkdm",
2509 .mpu_irqs = omap54xx_mmc4_irqs,
2510 .sdma_reqs = omap54xx_mmc4_sdma_reqs,
2511 .main_clk = "func_48m_fclk",
2512 .prcm = {
2513 .omap4 = {
2514 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
2515 .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
2516 .modulemode = MODULEMODE_SWCTRL,
2517 },
2518 },
2519 };
2521 /* mmc5 */
2522 static struct omap_hwmod_irq_info omap54xx_mmc5_irqs[] = {
2523 { .irq = 59 + OMAP54XX_IRQ_GIC_START },
2524 { .irq = -1 }
2525 };
2527 static struct omap_hwmod_dma_info omap54xx_mmc5_sdma_reqs[] = {
2528 { .name = "tx", .dma_req = 58 + OMAP54XX_DMA_REQ_START },
2529 { .name = "rx", .dma_req = 59 + OMAP54XX_DMA_REQ_START },
2530 { .dma_req = -1 }
2531 };
2533 static struct omap_hwmod omap54xx_mmc5_hwmod = {
2534 .name = "mmc5",
2535 .class = &omap54xx_mmc_hwmod_class,
2536 .clkdm_name = "l4per_clkdm",
2537 .mpu_irqs = omap54xx_mmc5_irqs,
2538 .sdma_reqs = omap54xx_mmc5_sdma_reqs,
2539 .main_clk = "func_96m_fclk",
2540 .prcm = {
2541 .omap4 = {
2542 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
2543 .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
2544 .modulemode = MODULEMODE_SWCTRL,
2545 },
2546 },
2547 };
2549 /*
2550 * 'mpu' class
2551 * mpu sub-system
2552 */
2554 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
2555 .name = "mpu",
2556 };
2558 /* mpu */
2559 static struct omap_hwmod_irq_info omap54xx_mpu_irqs[] = {
2560 { .name = "mpu_cluster", .irq = 132 + OMAP54XX_IRQ_GIC_START },
2561 { .name = "wd_timer_mpu_c0", .irq = 139 + OMAP54XX_IRQ_GIC_START },
2562 { .name = "wd_timer_mpu_c1", .irq = 140 + OMAP54XX_IRQ_GIC_START },
2563 { .irq = -1 }
2564 };
2566 static struct omap_hwmod omap54xx_mpu_hwmod = {
2567 .name = "mpu",
2568 .class = &omap54xx_mpu_hwmod_class,
2569 .clkdm_name = "mpu_clkdm",
2570 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2571 .mpu_irqs = omap54xx_mpu_irqs,
2572 .main_clk = "dpll_mpu_m2_ck",
2573 .prcm = {
2574 .omap4 = {
2575 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
2576 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
2577 },
2578 },
2579 };
2581 /*
2582 * 'ocmc_ram' class
2583 * top-level core on-chip ram
2584 */
2586 static struct omap_hwmod_class omap54xx_ocmc_ram_hwmod_class = {
2587 .name = "ocmc_ram",
2588 };
2590 /* ocmc_ram */
2591 static struct omap_hwmod omap54xx_ocmc_ram_hwmod = {
2592 .name = "ocmc_ram",
2593 .class = &omap54xx_ocmc_ram_hwmod_class,
2594 .clkdm_name = "l3main2_clkdm",
2595 .main_clk = "l3_iclk_div",
2596 .prcm = {
2597 .omap4 = {
2598 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET,
2599 .context_offs = OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET,
2600 },
2601 },
2602 };
2604 /*
2605 * 'ocp2scp' class
2606 * bridge to transform ocp interface protocol to scp (serial control port)
2607 * protocol
2608 */
2610 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
2611 .rev_offs = 0x0000,
2612 .sysc_offs = 0x0010,
2613 .syss_offs = 0x0014,
2614 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2615 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2616 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2617 .sysc_fields = &omap_hwmod_sysc_type1,
2618 };
2620 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
2621 .name = "ocp2scp",
2622 .sysc = &omap54xx_ocp2scp_sysc,
2623 };
2625 /* ocp2scp1 */
2626 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
2627 .name = "ocp2scp1",
2628 .class = &omap54xx_ocp2scp_hwmod_class,
2629 .clkdm_name = "l3init_clkdm",
2630 .main_clk = "l4_root_clk_div",
2631 .prcm = {
2632 .omap4 = {
2633 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
2634 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
2635 .modulemode = MODULEMODE_HWCTRL,
2636 },
2637 },
2638 };
2640 static struct resource omap54xx_sata_phy_addrs[] = {
2641 {
2642 .name = "sata_phy_rx",
2643 .start = 0x4A096000,
2644 .end = 0x4A096080,
2645 .flags = IORESOURCE_MEM,
2646 },
2647 {
2648 .name = "sata_phy_tx",
2649 .start = 0x4A096400,
2650 .end = 0x4A096464,
2651 .flags = IORESOURCE_MEM,
2652 },
2653 {
2654 .name = "sata_pll",
2655 .start = 0x4A096800,
2656 .end = 0x4A096840,
2657 .flags = IORESOURCE_MEM,
2658 },
2659 { }
2660 };
2662 static struct omap_ocp2scp_dev ocp2scp3_dev_attr[] = {
2663 {
2664 .drv_name = "omap-sata",
2665 .res = omap54xx_sata_phy_addrs,
2666 },
2667 { }
2668 };
2670 /* ocp2scp3 */
2671 static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
2672 static struct omap_hwmod_addr_space omap54xx_ocp2scp3_addrs[] = {
2673 {
2674 .name = "ocp2scp3",
2675 .pa_start = 0x4a090000,
2676 .pa_end = 0x4a09001f,
2677 .flags = ADDR_TYPE_RT
2678 },
2679 { }
2680 };
2682 /* l4_cfg -> ocp2scp3 */
2683 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
2684 .master = &omap54xx_l4_cfg_hwmod,
2685 .slave = &omap54xx_ocp2scp3_hwmod,
2686 .clk = "l4_root_clk_div",
2687 .addr = omap54xx_ocp2scp3_addrs,
2688 .user = OCP_USER_MPU | OCP_USER_SDMA,
2689 };
2691 static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
2692 .name = "ocp2scp3",
2693 .class = &omap54xx_ocp2scp_hwmod_class,
2694 .clkdm_name = "l3init_clkdm",
2695 .prcm = {
2696 .omap4 = {
2697 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2698 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2699 .modulemode = MODULEMODE_HWCTRL,
2700 },
2701 },
2702 .dev_attr = ocp2scp3_dev_attr,
2703 };
2705 /*
2706 * 'sata' class
2707 * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
2708 */
2710 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2711 .sysc_offs = 0x0000,
2712 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2713 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2714 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2715 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2716 .sysc_fields = &omap_hwmod_sysc_type2,
2717 };
2719 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2720 .name = "sata",
2721 .sysc = &omap54xx_sata_sysc,
2722 };
2724 /* sata */
2725 static struct omap_hwmod_irq_info omap54xx_sata_irqs[] = {
2726 { .irq = 54 + OMAP54XX_IRQ_GIC_START },
2727 { .irq = -1 }
2728 };
2730 static struct omap_hwmod_opt_clk sata_opt_clks[] = {
2731 { .role = "ref_clk", .clk = "sata_ref_clk" },
2732 };
2734 static struct omap_hwmod omap54xx_sata_hwmod = {
2735 .name = "sata",
2736 .class = &omap54xx_sata_hwmod_class,
2737 .clkdm_name = "l3init_clkdm",
2738 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2739 .mpu_irqs = omap54xx_sata_irqs,
2740 .main_clk = "func_48m_fclk",
2741 .prcm = {
2742 .omap4 = {
2743 .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2744 .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2745 .modulemode = MODULEMODE_SWCTRL,
2746 },
2747 },
2748 .opt_clks = sata_opt_clks,
2749 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
2750 };
2752 /*
2753 * 'scrm' class
2754 * system clock and reset manager
2755 */
2757 static struct omap_hwmod_class omap54xx_scrm_hwmod_class = {
2758 .name = "scrm",
2759 };
2761 /* scrm */
2762 static struct omap_hwmod omap54xx_scrm_hwmod = {
2763 .name = "scrm",
2764 .class = &omap54xx_scrm_hwmod_class,
2765 .clkdm_name = "wkupaon_clkdm",
2766 .prcm = {
2767 .omap4 = {
2768 .clkctrl_offs = OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET,
2769 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2770 },
2771 },
2772 };
2774 /*
2775 * 'slimbus' class
2776 * bidirectional, multi-drop, multi-channel two-line serial interface between
2777 * the device and external components
2778 */
2780 static struct omap_hwmod_class_sysconfig omap54xx_slimbus_sysc = {
2781 .rev_offs = 0x0000,
2782 .sysc_offs = 0x0010,
2783 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2784 SYSC_HAS_SOFTRESET),
2785 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2786 SIDLE_SMART_WKUP),
2787 .sysc_fields = &omap_hwmod_sysc_type2,
2788 };
2790 static struct omap_hwmod_class omap54xx_slimbus_hwmod_class = {
2791 .name = "slimbus",
2792 .sysc = &omap54xx_slimbus_sysc,
2793 };
2795 /* slimbus1 */
2796 static struct omap_hwmod_irq_info omap54xx_slimbus1_irqs[] = {
2797 { .irq = 97 + OMAP54XX_IRQ_GIC_START },
2798 { .irq = -1 }
2799 };
2801 static struct omap_hwmod_dma_info omap54xx_slimbus1_sdma_reqs[] = {
2802 { .name = "tx0", .dma_req = 84 + OMAP54XX_DMA_REQ_START },
2803 { .name = "tx1", .dma_req = 85 + OMAP54XX_DMA_REQ_START },
2804 { .name = "tx2", .dma_req = 86 + OMAP54XX_DMA_REQ_START },
2805 { .name = "tx3", .dma_req = 87 + OMAP54XX_DMA_REQ_START },
2806 { .name = "rx0", .dma_req = 88 + OMAP54XX_DMA_REQ_START },
2807 { .name = "rx1", .dma_req = 89 + OMAP54XX_DMA_REQ_START },
2808 { .name = "rx2", .dma_req = 90 + OMAP54XX_DMA_REQ_START },
2809 { .name = "rx3", .dma_req = 91 + OMAP54XX_DMA_REQ_START },
2810 { .dma_req = -1 }
2811 };
2813 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2814 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2815 };
2817 static struct omap_hwmod omap54xx_slimbus1_hwmod = {
2818 .name = "slimbus1",
2819 .class = &omap54xx_slimbus_hwmod_class,
2820 .clkdm_name = "abe_clkdm",
2821 .mpu_irqs = omap54xx_slimbus1_irqs,
2822 .sdma_reqs = omap54xx_slimbus1_sdma_reqs,
2823 .main_clk = "abe_iclk",
2824 .prcm = {
2825 .omap4 = {
2826 .clkctrl_offs = OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET,
2827 .context_offs = OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET,
2828 .modulemode = MODULEMODE_SWCTRL,
2829 },
2830 },
2831 .opt_clks = slimbus1_opt_clks,
2832 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2833 };
2835 /*
2836 * 'smartreflex' class
2837 * smartreflex module (monitor silicon performance and outputs a measure of
2838 * performance error)
2839 */
2841 /* The IP is not compliant to type1 / type2 scheme */
2842 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2843 .sidle_shift = 24,
2844 .enwkup_shift = 26,
2845 };
2847 static struct omap_hwmod_class_sysconfig omap54xx_smartreflex_sysc = {
2848 .sysc_offs = 0x0038,
2849 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2850 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2851 SIDLE_SMART_WKUP),
2852 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2853 };
2855 static struct omap_hwmod_class omap54xx_smartreflex_hwmod_class = {
2856 .name = "smartreflex",
2857 .sysc = &omap54xx_smartreflex_sysc,
2858 .rev = 2,
2859 };
2861 /* smartreflex_core */
2862 static struct omap_hwmod_irq_info omap54xx_smartreflex_core_irqs[] = {
2863 { .irq = 19 + OMAP54XX_IRQ_GIC_START },
2864 { .irq = -1 }
2865 };
2867 /* smartreflex_core dev_attr */
2868 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2869 .sensor_voltdm_name = "core",
2870 };
2872 static struct omap_hwmod omap54xx_smartreflex_core_hwmod = {
2873 .name = "smartreflex_core",
2874 .class = &omap54xx_smartreflex_hwmod_class,
2875 .clkdm_name = "coreaon_clkdm",
2876 .mpu_irqs = omap54xx_smartreflex_core_irqs,
2877 .main_clk = "wkupaon_iclk_mux",
2878 .prcm = {
2879 .omap4 = {
2880 .clkctrl_offs = OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2881 .context_offs = OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2882 .modulemode = MODULEMODE_SWCTRL,
2883 },
2884 },
2885 .dev_attr = &smartreflex_core_dev_attr,
2886 };
2888 /* smartreflex_mm */
2889 static struct omap_hwmod_irq_info omap54xx_smartreflex_mm_irqs[] = {
2890 { .irq = 102 + OMAP54XX_IRQ_GIC_START },
2891 { .irq = -1 }
2892 };
2894 /* smartreflex_mm dev_attr */
2895 static struct omap_smartreflex_dev_attr smartreflex_mm_dev_attr = {
2896 .sensor_voltdm_name = "mm",
2897 };
2899 static struct omap_hwmod omap54xx_smartreflex_mm_hwmod = {
2900 .name = "smartreflex_mm",
2901 .class = &omap54xx_smartreflex_hwmod_class,
2902 .clkdm_name = "coreaon_clkdm",
2903 .mpu_irqs = omap54xx_smartreflex_mm_irqs,
2904 .main_clk = "wkupaon_iclk_mux",
2905 .prcm = {
2906 .omap4 = {
2907 .clkctrl_offs = OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET,
2908 .context_offs = OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET,
2909 .modulemode = MODULEMODE_SWCTRL,
2910 },
2911 },
2912 .dev_attr = &smartreflex_mm_dev_attr,
2913 };
2915 /* smartreflex_mpu */
2916 static struct omap_hwmod_irq_info omap54xx_smartreflex_mpu_irqs[] = {
2917 { .irq = 18 + OMAP54XX_IRQ_GIC_START },
2918 { .irq = -1 }
2919 };
2921 /* smartreflex_mpu dev_attr */
2922 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2923 .sensor_voltdm_name = "mpu",
2924 };
2926 static struct omap_hwmod omap54xx_smartreflex_mpu_hwmod = {
2927 .name = "smartreflex_mpu",
2928 .class = &omap54xx_smartreflex_hwmod_class,
2929 .clkdm_name = "coreaon_clkdm",
2930 .mpu_irqs = omap54xx_smartreflex_mpu_irqs,
2931 .main_clk = "wkupaon_iclk_mux",
2932 .prcm = {
2933 .omap4 = {
2934 .clkctrl_offs = OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2935 .context_offs = OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2936 .modulemode = MODULEMODE_SWCTRL,
2937 },
2938 },
2939 .dev_attr = &smartreflex_mpu_dev_attr,
2940 };
2942 /*
2943 * 'spinlock' class
2944 * spinlock provides hardware assistance for synchronizing the processes
2945 * running on multiple processors
2946 */
2948 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
2949 .rev_offs = 0x0000,
2950 .sysc_offs = 0x0010,
2951 .syss_offs = 0x0014,
2952 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2953 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2954 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2955 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2956 SIDLE_SMART_WKUP),
2957 .sysc_fields = &omap_hwmod_sysc_type1,
2958 };
2960 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
2961 .name = "spinlock",
2962 .sysc = &omap54xx_spinlock_sysc,
2963 };
2965 /* spinlock */
2966 static struct omap_hwmod omap54xx_spinlock_hwmod = {
2967 .name = "spinlock",
2968 .class = &omap54xx_spinlock_hwmod_class,
2969 .clkdm_name = "l4cfg_clkdm",
2970 .main_clk = "l4_root_clk_div",
2971 .prcm = {
2972 .omap4 = {
2973 .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2974 .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2975 },
2976 },
2977 };
2979 /*
2980 * 'timer' class
2981 * general purpose timer module with accurate 1ms tick
2982 * This class contains several variants: ['timer_1ms', 'timer']
2983 */
2985 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
2986 .rev_offs = 0x0000,
2987 .sysc_offs = 0x0010,
2988 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2989 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2990 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2991 SIDLE_SMART_WKUP),
2992 .sysc_fields = &omap_hwmod_sysc_type2,
2993 .clockact = CLOCKACT_TEST_ICLK,
2994 };
2996 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
2997 .name = "timer",
2998 .sysc = &omap54xx_timer_1ms_sysc,
2999 };
3001 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
3002 .rev_offs = 0x0000,
3003 .sysc_offs = 0x0010,
3004 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3005 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3006 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3007 SIDLE_SMART_WKUP),
3008 .sysc_fields = &omap_hwmod_sysc_type2,
3009 };
3011 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
3012 .name = "timer",
3013 .sysc = &omap54xx_timer_sysc,
3014 };
3016 /* timer1 */
3017 static struct omap_hwmod_irq_info omap54xx_timer1_irqs[] = {
3018 { .irq = 37 + OMAP54XX_IRQ_GIC_START },
3019 { .irq = -1 }
3020 };
3022 static struct omap_hwmod omap54xx_timer1_hwmod = {
3023 .name = "timer1",
3024 .class = &omap54xx_timer_1ms_hwmod_class,
3025 .clkdm_name = "wkupaon_clkdm",
3026 .mpu_irqs = omap54xx_timer1_irqs,
3027 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3028 .main_clk = "timer1_gfclk_mux",
3029 .prcm = {
3030 .omap4 = {
3031 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
3032 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
3033 .modulemode = MODULEMODE_SWCTRL,
3034 },
3035 },
3036 };
3038 /* timer2 */
3039 static struct omap_hwmod_irq_info omap54xx_timer2_irqs[] = {
3040 { .irq = 38 + OMAP54XX_IRQ_GIC_START },
3041 { .irq = -1 }
3042 };
3044 static struct omap_hwmod omap54xx_timer2_hwmod = {
3045 .name = "timer2",
3046 .class = &omap54xx_timer_1ms_hwmod_class,
3047 .clkdm_name = "l4per_clkdm",
3048 .mpu_irqs = omap54xx_timer2_irqs,
3049 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3050 .main_clk = "timer2_gfclk_mux",
3051 .prcm = {
3052 .omap4 = {
3053 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
3054 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
3055 .modulemode = MODULEMODE_SWCTRL,
3056 },
3057 },
3058 };
3060 /* timer3 */
3061 static struct omap_hwmod_irq_info omap54xx_timer3_irqs[] = {
3062 { .irq = 39 + OMAP54XX_IRQ_GIC_START },
3063 { .irq = -1 }
3064 };
3066 static struct omap_hwmod omap54xx_timer3_hwmod = {
3067 .name = "timer3",
3068 .class = &omap54xx_timer_hwmod_class,
3069 .clkdm_name = "l4per_clkdm",
3070 .mpu_irqs = omap54xx_timer3_irqs,
3071 .main_clk = "timer3_gfclk_mux",
3072 .prcm = {
3073 .omap4 = {
3074 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
3075 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
3076 .modulemode = MODULEMODE_SWCTRL,
3077 },
3078 },
3079 };
3081 /* timer4 */
3082 static struct omap_hwmod_irq_info omap54xx_timer4_irqs[] = {
3083 { .irq = 40 + OMAP54XX_IRQ_GIC_START },
3084 { .irq = -1 }
3085 };
3087 static struct omap_hwmod omap54xx_timer4_hwmod = {
3088 .name = "timer4",
3089 .class = &omap54xx_timer_hwmod_class,
3090 .clkdm_name = "l4per_clkdm",
3091 .mpu_irqs = omap54xx_timer4_irqs,
3092 .main_clk = "timer4_gfclk_mux",
3093 .prcm = {
3094 .omap4 = {
3095 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
3096 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
3097 .modulemode = MODULEMODE_SWCTRL,
3098 },
3099 },
3100 };
3102 /* timer5 */
3103 static struct omap_hwmod_irq_info omap54xx_timer5_irqs[] = {
3104 { .irq = 41 + OMAP54XX_IRQ_GIC_START },
3105 { .irq = -1 }
3106 };
3108 static struct omap_hwmod omap54xx_timer5_hwmod = {
3109 .name = "timer5",
3110 .class = &omap54xx_timer_hwmod_class,
3111 .clkdm_name = "abe_clkdm",
3112 .mpu_irqs = omap54xx_timer5_irqs,
3113 .main_clk = "timer5_gfclk_mux",
3114 .prcm = {
3115 .omap4 = {
3116 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
3117 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
3118 .modulemode = MODULEMODE_SWCTRL,
3119 },
3120 },
3121 };
3123 /* timer6 */
3124 static struct omap_hwmod_irq_info omap54xx_timer6_irqs[] = {
3125 { .irq = 42 + OMAP54XX_IRQ_GIC_START },
3126 { .irq = -1 }
3127 };
3129 static struct omap_hwmod omap54xx_timer6_hwmod = {
3130 .name = "timer6",
3131 .class = &omap54xx_timer_hwmod_class,
3132 .clkdm_name = "abe_clkdm",
3133 .mpu_irqs = omap54xx_timer6_irqs,
3134 .main_clk = "timer6_gfclk_mux",
3135 .prcm = {
3136 .omap4 = {
3137 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
3138 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
3139 .modulemode = MODULEMODE_SWCTRL,
3140 },
3141 },
3142 };
3144 /* timer7 */
3145 static struct omap_hwmod_irq_info omap54xx_timer7_irqs[] = {
3146 { .irq = 43 + OMAP54XX_IRQ_GIC_START },
3147 { .irq = -1 }
3148 };
3150 static struct omap_hwmod omap54xx_timer7_hwmod = {
3151 .name = "timer7",
3152 .class = &omap54xx_timer_hwmod_class,
3153 .clkdm_name = "abe_clkdm",
3154 .mpu_irqs = omap54xx_timer7_irqs,
3155 .main_clk = "timer7_gfclk_mux",
3156 .prcm = {
3157 .omap4 = {
3158 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
3159 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
3160 .modulemode = MODULEMODE_SWCTRL,
3161 },
3162 },
3163 };
3165 /* timer8 */
3166 static struct omap_hwmod_irq_info omap54xx_timer8_irqs[] = {
3167 { .irq = 44 + OMAP54XX_IRQ_GIC_START },
3168 { .irq = -1 }
3169 };
3171 static struct omap_hwmod omap54xx_timer8_hwmod = {
3172 .name = "timer8",
3173 .class = &omap54xx_timer_hwmod_class,
3174 .clkdm_name = "abe_clkdm",
3175 .mpu_irqs = omap54xx_timer8_irqs,
3176 .main_clk = "timer8_gfclk_mux",
3177 .prcm = {
3178 .omap4 = {
3179 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
3180 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
3181 .modulemode = MODULEMODE_SWCTRL,
3182 },
3183 },
3184 };
3186 /* timer9 */
3187 static struct omap_hwmod_irq_info omap54xx_timer9_irqs[] = {
3188 { .irq = 45 + OMAP54XX_IRQ_GIC_START },
3189 { .irq = -1 }
3190 };
3192 static struct omap_hwmod omap54xx_timer9_hwmod = {
3193 .name = "timer9",
3194 .class = &omap54xx_timer_hwmod_class,
3195 .clkdm_name = "l4per_clkdm",
3196 .mpu_irqs = omap54xx_timer9_irqs,
3197 .main_clk = "timer9_gfclk_mux",
3198 .prcm = {
3199 .omap4 = {
3200 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
3201 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
3202 .modulemode = MODULEMODE_SWCTRL,
3203 },
3204 },
3205 };
3207 /* timer10 */
3208 static struct omap_hwmod_irq_info omap54xx_timer10_irqs[] = {
3209 { .irq = 46 + OMAP54XX_IRQ_GIC_START },
3210 { .irq = -1 }
3211 };
3213 static struct omap_hwmod omap54xx_timer10_hwmod = {
3214 .name = "timer10",
3215 .class = &omap54xx_timer_1ms_hwmod_class,
3216 .clkdm_name = "l4per_clkdm",
3217 .mpu_irqs = omap54xx_timer10_irqs,
3218 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3219 .main_clk = "timer10_gfclk_mux",
3220 .prcm = {
3221 .omap4 = {
3222 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
3223 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
3224 .modulemode = MODULEMODE_SWCTRL,
3225 },
3226 },
3227 };
3229 /* timer11 */
3230 static struct omap_hwmod_irq_info omap54xx_timer11_irqs[] = {
3231 { .irq = 47 + OMAP54XX_IRQ_GIC_START },
3232 { .irq = -1 }
3233 };
3235 static struct omap_hwmod omap54xx_timer11_hwmod = {
3236 .name = "timer11",
3237 .class = &omap54xx_timer_hwmod_class,
3238 .clkdm_name = "l4per_clkdm",
3239 .mpu_irqs = omap54xx_timer11_irqs,
3240 .main_clk = "timer11_gfclk_mux",
3241 .prcm = {
3242 .omap4 = {
3243 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
3244 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
3245 .modulemode = MODULEMODE_SWCTRL,
3246 },
3247 },
3248 };
3250 /*
3251 * 'uart' class
3252 * universal asynchronous receiver/transmitter (uart)
3253 */
3255 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
3256 .rev_offs = 0x0050,
3257 .sysc_offs = 0x0054,
3258 .syss_offs = 0x0058,
3259 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3260 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3261 SYSS_HAS_RESET_STATUS),
3262 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3263 SIDLE_SMART_WKUP),
3264 .sysc_fields = &omap_hwmod_sysc_type1,
3265 };
3267 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
3268 .name = "uart",
3269 .sysc = &omap54xx_uart_sysc,
3270 };
3272 /* uart1 */
3273 static struct omap_hwmod_irq_info omap54xx_uart1_irqs[] = {
3274 { .irq = 72 + OMAP54XX_IRQ_GIC_START },
3275 { .irq = -1 }
3276 };
3278 static struct omap_hwmod_dma_info omap54xx_uart1_sdma_reqs[] = {
3279 { .name = "tx", .dma_req = 48 + OMAP54XX_DMA_REQ_START },
3280 { .name = "rx", .dma_req = 49 + OMAP54XX_DMA_REQ_START },
3281 { .dma_req = -1 }
3282 };
3284 static struct omap_hwmod omap54xx_uart1_hwmod = {
3285 .name = "uart1",
3286 .class = &omap54xx_uart_hwmod_class,
3287 .clkdm_name = "l4per_clkdm",
3288 .mpu_irqs = omap54xx_uart1_irqs,
3289 .sdma_reqs = omap54xx_uart1_sdma_reqs,
3290 .main_clk = "func_48m_fclk",
3291 .flags = HWMOD_SWSUP_SIDLE_ACT,
3292 .prcm = {
3293 .omap4 = {
3294 .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
3295 .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
3296 .modulemode = MODULEMODE_SWCTRL,
3297 },
3298 },
3299 };
3301 /* uart2 */
3302 static struct omap_hwmod_irq_info omap54xx_uart2_irqs[] = {
3303 { .irq = 73 + OMAP54XX_IRQ_GIC_START },
3304 { .irq = -1 }
3305 };
3307 static struct omap_hwmod_dma_info omap54xx_uart2_sdma_reqs[] = {
3308 { .name = "tx", .dma_req = 50 + OMAP54XX_DMA_REQ_START },
3309 { .name = "rx", .dma_req = 51 + OMAP54XX_DMA_REQ_START },
3310 { .dma_req = -1 }
3311 };
3313 static struct omap_hwmod omap54xx_uart2_hwmod = {
3314 .name = "uart2",
3315 .class = &omap54xx_uart_hwmod_class,
3316 .clkdm_name = "l4per_clkdm",
3317 .mpu_irqs = omap54xx_uart2_irqs,
3318 .sdma_reqs = omap54xx_uart2_sdma_reqs,
3319 .main_clk = "func_48m_fclk",
3320 .flags = HWMOD_SWSUP_SIDLE_ACT,
3321 .prcm = {
3322 .omap4 = {
3323 .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
3324 .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
3325 .modulemode = MODULEMODE_SWCTRL,
3326 },
3327 },
3328 };
3330 /* uart3 */
3331 static struct omap_hwmod_irq_info omap54xx_uart3_irqs[] = {
3332 { .irq = 74 + OMAP54XX_IRQ_GIC_START },
3333 { .irq = -1 }
3334 };
3336 static struct omap_hwmod_dma_info omap54xx_uart3_sdma_reqs[] = {
3337 { .name = "tx", .dma_req = 52 + OMAP54XX_DMA_REQ_START },
3338 { .name = "rx", .dma_req = 53 + OMAP54XX_DMA_REQ_START },
3339 { .dma_req = -1 }
3340 };
3342 static struct omap_hwmod omap54xx_uart3_hwmod = {
3343 .name = "uart3",
3344 .class = &omap54xx_uart_hwmod_class,
3345 .clkdm_name = "l4per_clkdm",
3346 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
3347 HWMOD_SWSUP_SIDLE_ACT,
3348 .mpu_irqs = omap54xx_uart3_irqs,
3349 .sdma_reqs = omap54xx_uart3_sdma_reqs,
3350 .main_clk = "func_48m_fclk",
3351 .prcm = {
3352 .omap4 = {
3353 .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
3354 .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
3355 .modulemode = MODULEMODE_SWCTRL,
3356 },
3357 },
3358 };
3360 /* uart4 */
3361 static struct omap_hwmod_irq_info omap54xx_uart4_irqs[] = {
3362 { .irq = 70 + OMAP54XX_IRQ_GIC_START },
3363 { .irq = -1 }
3364 };
3366 static struct omap_hwmod_dma_info omap54xx_uart4_sdma_reqs[] = {
3367 { .name = "tx", .dma_req = 54 + OMAP54XX_DMA_REQ_START },
3368 { .name = "rx", .dma_req = 55 + OMAP54XX_DMA_REQ_START },
3369 { .dma_req = -1 }
3370 };
3372 static struct omap_hwmod omap54xx_uart4_hwmod = {
3373 .name = "uart4",
3374 .class = &omap54xx_uart_hwmod_class,
3375 .clkdm_name = "l4per_clkdm",
3376 .mpu_irqs = omap54xx_uart4_irqs,
3377 .sdma_reqs = omap54xx_uart4_sdma_reqs,
3378 .main_clk = "func_48m_fclk",
3379 .flags = HWMOD_SWSUP_SIDLE_ACT,
3380 .prcm = {
3381 .omap4 = {
3382 .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
3383 .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
3384 .modulemode = MODULEMODE_SWCTRL,
3385 },
3386 },
3387 };
3389 /* uart5 */
3390 static struct omap_hwmod_irq_info omap54xx_uart5_irqs[] = {
3391 { .irq = 105 + OMAP54XX_IRQ_GIC_START },
3392 { .irq = -1 }
3393 };
3395 static struct omap_hwmod_dma_info omap54xx_uart5_sdma_reqs[] = {
3396 { .name = "tx", .dma_req = 62 + OMAP54XX_DMA_REQ_START },
3397 { .name = "rx", .dma_req = 63 + OMAP54XX_DMA_REQ_START },
3398 { .dma_req = -1 }
3399 };
3401 static struct omap_hwmod omap54xx_uart5_hwmod = {
3402 .name = "uart5",
3403 .class = &omap54xx_uart_hwmod_class,
3404 .clkdm_name = "l4per_clkdm",
3405 .mpu_irqs = omap54xx_uart5_irqs,
3406 .sdma_reqs = omap54xx_uart5_sdma_reqs,
3407 .main_clk = "func_48m_fclk",
3408 .flags = HWMOD_SWSUP_SIDLE_ACT,
3409 .prcm = {
3410 .omap4 = {
3411 .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
3412 .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
3413 .modulemode = MODULEMODE_SWCTRL,
3414 },
3415 },
3416 };
3418 /* uart6 */
3419 static struct omap_hwmod_irq_info omap54xx_uart6_irqs[] = {
3420 { .irq = 106 + OMAP54XX_IRQ_GIC_START },
3421 { .irq = -1 }
3422 };
3424 static struct omap_hwmod_dma_info omap54xx_uart6_sdma_reqs[] = {
3425 { .name = "tx", .dma_req = 78 + OMAP54XX_DMA_REQ_START },
3426 { .name = "rx", .dma_req = 79 + OMAP54XX_DMA_REQ_START },
3427 { .dma_req = -1 }
3428 };
3430 static struct omap_hwmod omap54xx_uart6_hwmod = {
3431 .name = "uart6",
3432 .class = &omap54xx_uart_hwmod_class,
3433 .clkdm_name = "l4per_clkdm",
3434 .mpu_irqs = omap54xx_uart6_irqs,
3435 .sdma_reqs = omap54xx_uart6_sdma_reqs,
3436 .main_clk = "func_48m_fclk",
3437 .flags = HWMOD_SWSUP_SIDLE_ACT,
3438 .prcm = {
3439 .omap4 = {
3440 .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
3441 .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
3442 .modulemode = MODULEMODE_SWCTRL,
3443 },
3444 },
3445 };
3447 /*
3448 * 'usb_host_hs' class
3449 * high-speed multi-port usb host controller
3450 */
3452 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
3453 .rev_offs = 0x0000,
3454 .sysc_offs = 0x0010,
3455 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
3456 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3457 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3458 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3459 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3460 .sysc_fields = &omap_hwmod_sysc_type2,
3461 };
3463 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
3464 .name = "usb_host_hs",
3465 .sysc = &omap54xx_usb_host_hs_sysc,
3466 };
3468 /* usb_host_hs */
3469 static struct omap_hwmod_irq_info omap54xx_usb_host_hs_irqs[] = {
3470 { .name = "ohci-irq", .irq = 76 + OMAP54XX_IRQ_GIC_START },
3471 { .name = "ehci-irq", .irq = 77 + OMAP54XX_IRQ_GIC_START },
3472 { .irq = -1 }
3473 };
3475 static struct omap_hwmod_opt_clk usb_host_hs_opt_clks[] = {
3476 { .role = "hsic60m_p2_clk", .clk = "usb_host_hs_hsic60m_p2_clk" },
3477 { .role = "hsic60m_p3_clk", .clk = "usb_host_hs_hsic60m_p3_clk" },
3478 { .role = "utmi_p1_clk", .clk = "usb_host_hs_utmi_p1_clk" },
3479 { .role = "utmi_p2_clk", .clk = "usb_host_hs_utmi_p2_clk" },
3480 { .role = "utmi_p3_clk", .clk = "usb_host_hs_utmi_p3_clk" },
3481 { .role = "hsic480m_p1_clk", .clk = "usb_host_hs_hsic480m_p1_clk" },
3482 { .role = "hsic60m_p1_clk", .clk = "usb_host_hs_hsic60m_p1_clk" },
3483 { .role = "hsic480m_p3_clk", .clk = "usb_host_hs_hsic480m_p3_clk" },
3484 { .role = "hsic480m_p2_clk", .clk = "usb_host_hs_hsic480m_p2_clk" },
3485 };
3487 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
3488 .name = "usb_host_hs",
3489 .class = &omap54xx_usb_host_hs_hwmod_class,
3490 .clkdm_name = "l3init_clkdm",
3491 /*
3492 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3493 * id: i660
3494 *
3495 * Description:
3496 * In the following configuration :
3497 * - USBHOST module is set to smart-idle mode
3498 * - PRCM asserts idle_req to the USBHOST module ( This typically
3499 * happens when the system is going to a low power mode : all ports
3500 * have been suspended, the master part of the USBHOST module has
3501 * entered the standby state, and SW has cut the functional clocks)
3502 * - an USBHOST interrupt occurs before the module is able to answer
3503 * idle_ack, typically a remote wakeup IRQ.
3504 * Then the USB HOST module will enter a deadlock situation where it
3505 * is no more accessible nor functional.
3506 *
3507 * Workaround:
3508 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3509 */
3511 /*
3512 * Errata: USB host EHCI may stall when entering smart-standby mode
3513 * Id: i571
3514 *
3515 * Description:
3516 * When the USBHOST module is set to smart-standby mode, and when it is
3517 * ready to enter the standby state (i.e. all ports are suspended and
3518 * all attached devices are in suspend mode), then it can wrongly assert
3519 * the Mstandby signal too early while there are still some residual OCP
3520 * transactions ongoing. If this condition occurs, the internal state
3521 * machine may go to an undefined state and the USB link may be stuck
3522 * upon the next resume.
3523 *
3524 * Workaround:
3525 * Don't use smart standby; use only force standby,
3526 * hence HWMOD_SWSUP_MSTANDBY
3527 */
3529 /*
3530 * During system boot; If the hwmod framework resets the module
3531 * the module will have smart idle settings; which can lead to deadlock
3532 * (above Errata Id:i660); so, dont reset the module during boot;
3533 * Use HWMOD_INIT_NO_RESET.
3534 */
3536 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3537 HWMOD_INIT_NO_RESET,
3538 .mpu_irqs = omap54xx_usb_host_hs_irqs,
3539 .main_clk = "l3init_60m_fclk",
3540 .prcm = {
3541 .omap4 = {
3542 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
3543 .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
3544 .modulemode = MODULEMODE_SWCTRL,
3545 },
3546 },
3547 .opt_clks = usb_host_hs_opt_clks,
3548 .opt_clks_cnt = ARRAY_SIZE(usb_host_hs_opt_clks),
3549 };
3551 /*
3552 * 'usb_otg_ss' class
3553 * 2.0 super speed (usb_otg_ss) controller
3554 */
3556 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
3557 .rev_offs = 0x0000,
3558 .sysc_offs = 0x0010,
3559 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
3560 SYSC_HAS_SIDLEMODE),
3561 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3562 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3563 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3564 .sysc_fields = &omap_hwmod_sysc_type2,
3565 };
3567 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
3568 .name = "usb_otg_ss",
3569 .sysc = &omap54xx_usb_otg_ss_sysc,
3570 };
3572 /* usb_otg_ss */
3573 static struct omap_hwmod_irq_info omap54xx_usb_otg_ss_irqs[] = {
3574 { .name = "core", .irq = 92 + OMAP54XX_IRQ_GIC_START },
3575 { .name = "wrp", .irq = 93 + OMAP54XX_IRQ_GIC_START },
3576 { .irq = -1 }
3577 };
3579 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
3580 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
3581 };
3583 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
3584 .name = "usb_otg_ss",
3585 .class = &omap54xx_usb_otg_ss_hwmod_class,
3586 .clkdm_name = "l3init_clkdm",
3587 .flags = HWMOD_SWSUP_SIDLE,
3588 .mpu_irqs = omap54xx_usb_otg_ss_irqs,
3589 .main_clk = "dpll_core_h13x2_ck",
3590 .prcm = {
3591 .omap4 = {
3592 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
3593 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
3594 .modulemode = MODULEMODE_HWCTRL,
3595 },
3596 },
3597 .opt_clks = usb_otg_ss_opt_clks,
3598 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
3599 };
3601 /*
3602 * 'usb_tll_hs' class
3603 * usb_tll_hs module is the adapter on the usb_host_hs ports
3604 */
3606 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
3607 .rev_offs = 0x0000,
3608 .sysc_offs = 0x0010,
3609 .syss_offs = 0x0014,
3610 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3611 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3612 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3613 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3614 .sysc_fields = &omap_hwmod_sysc_type1,
3615 };
3617 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
3618 .name = "usb_tll_hs",
3619 .sysc = &omap54xx_usb_tll_hs_sysc,
3620 };
3622 /* usb_tll_hs */
3623 static struct omap_hwmod_irq_info omap54xx_usb_tll_hs_irqs[] = {
3624 { .irq = 78 + OMAP54XX_IRQ_GIC_START },
3625 { .irq = -1 }
3626 };
3628 static struct omap_hwmod_opt_clk usb_tll_hs_opt_clks[] = {
3629 { .role = "usb_ch2_clk", .clk = "usb_tll_hs_usb_ch2_clk" },
3630 { .role = "usb_ch0_clk", .clk = "usb_tll_hs_usb_ch0_clk" },
3631 { .role = "usb_ch1_clk", .clk = "usb_tll_hs_usb_ch1_clk" },
3632 };
3634 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
3635 .name = "usb_tll_hs",
3636 .class = &omap54xx_usb_tll_hs_hwmod_class,
3637 .clkdm_name = "l3init_clkdm",
3638 .mpu_irqs = omap54xx_usb_tll_hs_irqs,
3639 .main_clk = "l4_root_clk_div",
3640 .prcm = {
3641 .omap4 = {
3642 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
3643 .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
3644 .modulemode = MODULEMODE_HWCTRL,
3645 },
3646 },
3647 .opt_clks = usb_tll_hs_opt_clks,
3648 .opt_clks_cnt = ARRAY_SIZE(usb_tll_hs_opt_clks),
3649 };
3651 /*
3652 * 'wd_timer' class
3653 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3654 * overflow condition
3655 */
3657 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
3658 .rev_offs = 0x0000,
3659 .sysc_offs = 0x0010,
3660 .syss_offs = 0x0014,
3661 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3662 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3663 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3664 SIDLE_SMART_WKUP),
3665 .sysc_fields = &omap_hwmod_sysc_type1,
3666 };
3668 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
3669 .name = "wd_timer",
3670 .sysc = &omap54xx_wd_timer_sysc,
3671 .pre_shutdown = &omap2_wd_timer_disable,
3672 };
3674 /* wd_timer2 */
3675 static struct omap_hwmod_irq_info omap54xx_wd_timer2_irqs[] = {
3676 { .irq = 80 + OMAP54XX_IRQ_GIC_START },
3677 { .irq = -1 }
3678 };
3680 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
3681 .name = "wd_timer2",
3682 .class = &omap54xx_wd_timer_hwmod_class,
3683 .clkdm_name = "wkupaon_clkdm",
3684 .mpu_irqs = omap54xx_wd_timer2_irqs,
3685 .main_clk = "sys_32k_ck",
3686 .prcm = {
3687 .omap4 = {
3688 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
3689 .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
3690 .modulemode = MODULEMODE_SWCTRL,
3691 },
3692 },
3693 };
3695 /* wd_timer3 */
3696 static struct omap_hwmod_irq_info omap54xx_wd_timer3_irqs[] = {
3697 { .irq = 36 + OMAP54XX_IRQ_GIC_START },
3698 { .irq = -1 }
3699 };
3701 static struct omap_hwmod omap54xx_wd_timer3_hwmod = {
3702 .name = "wd_timer3",
3703 .class = &omap54xx_wd_timer_hwmod_class,
3704 .clkdm_name = "abe_clkdm",
3705 .mpu_irqs = omap54xx_wd_timer3_irqs,
3706 .main_clk = "sys_32k_ck",
3707 .prcm = {
3708 .omap4 = {
3709 .clkctrl_offs = OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET,
3710 .context_offs = OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET,
3711 .modulemode = MODULEMODE_SWCTRL,
3712 },
3713 },
3714 };
3717 /*
3718 * Interfaces
3719 */
3721 static struct omap_hwmod_addr_space omap54xx_dmm_addrs[] = {
3722 {
3723 .pa_start = 0x4e000000,
3724 .pa_end = 0x4e0007ff,
3725 .flags = ADDR_TYPE_RT
3726 },
3727 { }
3728 };
3730 /* l3_main_1 -> dmm */
3731 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
3732 .master = &omap54xx_l3_main_1_hwmod,
3733 .slave = &omap54xx_dmm_hwmod,
3734 .clk = "l3_iclk_div",
3735 .addr = omap54xx_dmm_addrs,
3736 .user = OCP_USER_SDMA,
3737 };
3739 /* dmm -> emif_ocp_fw */
3740 static struct omap_hwmod_ocp_if omap54xx_dmm__emif_ocp_fw = {
3741 .master = &omap54xx_dmm_hwmod,
3742 .slave = &omap54xx_emif_ocp_fw_hwmod,
3743 .clk = "l3_iclk_div",
3744 .user = OCP_USER_MPU | OCP_USER_SDMA,
3745 };
3747 static struct omap_hwmod_addr_space omap54xx_emif_ocp_fw_addrs[] = {
3748 {
3749 .pa_start = 0x4a20c000,
3750 .pa_end = 0x4a20c0ff,
3751 },
3752 { }
3753 };
3755 /* l4_cfg -> emif_ocp_fw */
3756 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__emif_ocp_fw = {
3757 .master = &omap54xx_l4_cfg_hwmod,
3758 .slave = &omap54xx_emif_ocp_fw_hwmod,
3759 .clk = "l3_iclk_div",
3760 .addr = omap54xx_emif_ocp_fw_addrs,
3761 .user = OCP_USER_MPU,
3762 };
3764 /* l3_main_3 -> l3_instr */
3765 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
3766 .master = &omap54xx_l3_main_3_hwmod,
3767 .slave = &omap54xx_l3_instr_hwmod,
3768 .clk = "l3_iclk_div",
3769 .user = OCP_USER_MPU | OCP_USER_SDMA,
3770 };
3772 /* ocp_wp_noc -> l3_instr */
3773 static struct omap_hwmod_ocp_if omap54xx_ocp_wp_noc__l3_instr = {
3774 .master = &omap54xx_ocp_wp_noc_hwmod,
3775 .slave = &omap54xx_l3_instr_hwmod,
3776 .clk = "l3_iclk_div",
3777 .user = OCP_USER_MPU | OCP_USER_SDMA,
3778 };
3780 /* l3_main_2 -> l3_main_1 */
3781 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
3782 .master = &omap54xx_l3_main_2_hwmod,
3783 .slave = &omap54xx_l3_main_1_hwmod,
3784 .clk = "l3_iclk_div",
3785 .user = OCP_USER_MPU | OCP_USER_SDMA,
3786 };
3788 /* l4_cfg -> l3_main_1 */
3789 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
3790 .master = &omap54xx_l4_cfg_hwmod,
3791 .slave = &omap54xx_l3_main_1_hwmod,
3792 .clk = "l3_iclk_div",
3793 .user = OCP_USER_MPU | OCP_USER_SDMA,
3794 };
3796 static struct omap_hwmod_addr_space omap54xx_l3_main_1_addrs[] = {
3797 {
3798 .pa_start = 0x44000000,
3799 .pa_end = 0x44001fff,
3800 },
3801 { }
3802 };
3804 /* mpu -> l3_main_1 */
3805 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
3806 .master = &omap54xx_mpu_hwmod,
3807 .slave = &omap54xx_l3_main_1_hwmod,
3808 .clk = "l3_iclk_div",
3809 .addr = omap54xx_l3_main_1_addrs,
3810 .user = OCP_USER_MPU,
3811 };
3813 static struct omap_hwmod_addr_space omap54xx_l3_main_2_addrs[] = {
3814 {
3815 .pa_start = 0x44800000,
3816 .pa_end = 0x44802fff,
3817 },
3818 { }
3819 };
3821 /* l3_main_1 -> l3_main_2 */
3822 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
3823 .master = &omap54xx_l3_main_1_hwmod,
3824 .slave = &omap54xx_l3_main_2_hwmod,
3825 .clk = "l3_iclk_div",
3826 .addr = omap54xx_l3_main_2_addrs,
3827 .user = OCP_USER_MPU,
3828 };
3830 /* l4_cfg -> l3_main_2 */
3831 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
3832 .master = &omap54xx_l4_cfg_hwmod,
3833 .slave = &omap54xx_l3_main_2_hwmod,
3834 .clk = "l3_iclk_div",
3835 .user = OCP_USER_MPU | OCP_USER_SDMA,
3836 };
3838 static struct omap_hwmod_addr_space omap54xx_l3_main_3_addrs[] = {
3839 {
3840 .pa_start = 0x45000000,
3841 .pa_end = 0x45003fff,
3842 },
3843 { }
3844 };
3846 /* l3_main_1 -> l3_main_3 */
3847 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
3848 .master = &omap54xx_l3_main_1_hwmod,
3849 .slave = &omap54xx_l3_main_3_hwmod,
3850 .clk = "l3_iclk_div",
3851 .addr = omap54xx_l3_main_3_addrs,
3852 .user = OCP_USER_MPU,
3853 };
3855 /* l3_main_2 -> l3_main_3 */
3856 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
3857 .master = &omap54xx_l3_main_2_hwmod,
3858 .slave = &omap54xx_l3_main_3_hwmod,
3859 .clk = "l3_iclk_div",
3860 .user = OCP_USER_MPU | OCP_USER_SDMA,
3861 };
3863 /* l4_cfg -> l3_main_3 */
3864 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
3865 .master = &omap54xx_l4_cfg_hwmod,
3866 .slave = &omap54xx_l3_main_3_hwmod,
3867 .clk = "l3_iclk_div",
3868 .user = OCP_USER_MPU | OCP_USER_SDMA,
3869 };
3871 /* l3_main_1 -> l4_abe */
3872 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
3873 .master = &omap54xx_l3_main_1_hwmod,
3874 .slave = &omap54xx_l4_abe_hwmod,
3875 .clk = "abe_iclk",
3876 .user = OCP_USER_MPU | OCP_USER_SDMA,
3877 };
3879 /* mpu -> l4_abe */
3880 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
3881 .master = &omap54xx_mpu_hwmod,
3882 .slave = &omap54xx_l4_abe_hwmod,
3883 .clk = "abe_iclk",
3884 .user = OCP_USER_MPU | OCP_USER_SDMA,
3885 };
3887 /* l3_main_1 -> l4_cfg */
3888 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
3889 .master = &omap54xx_l3_main_1_hwmod,
3890 .slave = &omap54xx_l4_cfg_hwmod,
3891 .clk = "l4_root_clk_div",
3892 .user = OCP_USER_MPU | OCP_USER_SDMA,
3893 };
3895 /* l3_main_2 -> l4_per */
3896 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
3897 .master = &omap54xx_l3_main_2_hwmod,
3898 .slave = &omap54xx_l4_per_hwmod,
3899 .clk = "l4_root_clk_div",
3900 .user = OCP_USER_MPU | OCP_USER_SDMA,
3901 };
3903 /* l3_main_1 -> l4_wkup */
3904 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
3905 .master = &omap54xx_l3_main_1_hwmod,
3906 .slave = &omap54xx_l4_wkup_hwmod,
3907 .clk = "wkupaon_iclk_mux",
3908 .user = OCP_USER_MPU | OCP_USER_SDMA,
3909 };
3911 /* mpu -> mpu_private */
3912 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
3913 .master = &omap54xx_mpu_hwmod,
3914 .slave = &omap54xx_mpu_private_hwmod,
3915 .clk = "l3_iclk_div",
3916 .user = OCP_USER_MPU | OCP_USER_SDMA,
3917 };
3919 /* l3_main_3 -> ocp_wp_noc */
3920 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__ocp_wp_noc = {
3921 .master = &omap54xx_l3_main_3_hwmod,
3922 .slave = &omap54xx_ocp_wp_noc_hwmod,
3923 .clk = "l3_iclk_div",
3924 .user = OCP_USER_MPU | OCP_USER_SDMA,
3925 };
3927 static struct omap_hwmod_addr_space omap54xx_ocp_wp_noc_addrs[] = {
3928 {
3929 .pa_start = 0x4a102000,
3930 .pa_end = 0x4a10207f,
3931 .flags = ADDR_TYPE_RT
3932 },
3933 { }
3934 };
3936 /* l4_cfg -> ocp_wp_noc */
3937 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp_wp_noc = {
3938 .master = &omap54xx_l4_cfg_hwmod,
3939 .slave = &omap54xx_ocp_wp_noc_hwmod,
3940 .clk = "l3_iclk_div",
3941 .addr = omap54xx_ocp_wp_noc_addrs,
3942 .user = OCP_USER_MPU,
3943 };
3945 static struct omap_hwmod_addr_space omap54xx_aess_addrs[] = {
3946 {
3947 .name = "aess",
3948 .pa_start = 0x401f1000,
3949 .pa_end = 0x401f13ff,
3950 .flags = ADDR_TYPE_RT
3951 },
3952 { }
3953 };
3955 /* l4_abe -> aess */
3956 static struct omap_hwmod_ocp_if omap54xx_l4_abe__aess = {
3957 .master = &omap54xx_l4_abe_hwmod,
3958 .slave = &omap54xx_aess_hwmod,
3959 .clk = "abe_iclk",
3960 .addr = omap54xx_aess_addrs,
3961 .user = OCP_USER_MPU,
3962 };
3964 /* l3_main_2 -> bb2d */
3965 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__bb2d = {
3966 .master = &omap54xx_l3_main_2_hwmod,
3967 .slave = &omap54xx_bb2d_hwmod,
3968 .clk = "l3_iclk_div",
3969 .user = OCP_USER_MPU | OCP_USER_SDMA,
3970 };
3972 static struct omap_hwmod_addr_space omap54xx_c2c_addrs[] = {
3973 {
3974 .pa_start = 0x5c000000,
3975 .pa_end = 0x5c0000ff,
3976 .flags = ADDR_TYPE_RT
3977 },
3978 { }
3979 };
3981 /* l3_main_2 -> c2c */
3982 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__c2c = {
3983 .master = &omap54xx_l3_main_2_hwmod,
3984 .slave = &omap54xx_c2c_hwmod,
3985 .clk = "c2c_fclk",
3986 .addr = omap54xx_c2c_addrs,
3987 .user = OCP_USER_MPU | OCP_USER_SDMA,
3988 };
3990 static struct omap_hwmod_addr_space omap54xx_counter_32k_addrs[] = {
3991 {
3992 .pa_start = 0x4ae04000,
3993 .pa_end = 0x4ae0403f,
3994 .flags = ADDR_TYPE_RT
3995 },
3996 { }
3997 };
3999 /* l4_wkup -> counter_32k */
4000 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
4001 .master = &omap54xx_l4_wkup_hwmod,
4002 .slave = &omap54xx_counter_32k_hwmod,
4003 .clk = "wkupaon_iclk_mux",
4004 .addr = omap54xx_counter_32k_addrs,
4005 .user = OCP_USER_MPU | OCP_USER_SDMA,
4006 };
4008 static struct omap_hwmod_addr_space omap54xx_ctrl_module_core_addrs[] = {
4009 {
4010 .name = "omap_control_core_core",
4011 .pa_start = 0x4a002000,
4012 .pa_end = 0x4a0027ff,
4013 .flags = ADDR_TYPE_RT
4014 },
4015 {
4016 .name = "omap_control_core_pad",
4017 .pa_start = 0x4a002800,
4018 .pa_end = 0x4a002fff,
4019 .flags = ADDR_TYPE_RT
4020 },
4021 { }
4022 };
4024 /* l4_cfg -> ctrl_module_core */
4025 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ctrl_module_core = {
4026 .master = &omap54xx_l4_cfg_hwmod,
4027 .slave = &omap54xx_ctrl_module_core_hwmod,
4028 .clk = "l4_root_clk_div",
4029 .addr = omap54xx_ctrl_module_core_addrs,
4030 .user = OCP_USER_MPU | OCP_USER_SDMA,
4031 };
4033 static struct omap_hwmod_addr_space omap54xx_ctrl_module_wkup_addrs[] = {
4034 {
4035 .name = "omap_control_wkup_core",
4036 .pa_start = 0x4ae0c000,
4037 .pa_end = 0x4ae0c7ff,
4038 .flags = ADDR_TYPE_RT
4039 },
4040 {
4041 .name = "omap_control_wkup_pad",
4042 .pa_start = 0x4ae0c800,
4043 .pa_end = 0x4ae0cfff,
4044 .flags = ADDR_TYPE_RT
4045 },
4046 { }
4047 };
4049 /* l4_wkup -> ctrl_module_wkup */
4050 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__ctrl_module_wkup = {
4051 .master = &omap54xx_l4_wkup_hwmod,
4052 .slave = &omap54xx_ctrl_module_wkup_hwmod,
4053 .clk = "wkupaon_iclk_mux",
4054 .addr = omap54xx_ctrl_module_wkup_addrs,
4055 .user = OCP_USER_MPU | OCP_USER_SDMA,
4056 };
4058 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
4059 {
4060 .pa_start = 0x4a056000,
4061 .pa_end = 0x4a056fff,
4062 .flags = ADDR_TYPE_RT
4063 },
4064 { }
4065 };
4067 /* l4_cfg -> dma_system */
4068 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
4069 .master = &omap54xx_l4_cfg_hwmod,
4070 .slave = &omap54xx_dma_system_hwmod,
4071 .clk = "l4_root_clk_div",
4072 .addr = omap54xx_dma_system_addrs,
4073 .user = OCP_USER_MPU | OCP_USER_SDMA,
4074 };
4076 static struct omap_hwmod_addr_space omap54xx_dmic_addrs[] = {
4077 {
4078 .name = "mpu",
4079 .pa_start = 0x4012e000,
4080 .pa_end = 0x4012e07f,
4081 .flags = ADDR_TYPE_RT
4082 },
4083 { }
4084 };
4086 /* l4_abe -> dmic */
4087 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
4088 .master = &omap54xx_l4_abe_hwmod,
4089 .slave = &omap54xx_dmic_hwmod,
4090 .clk = "abe_iclk",
4091 .addr = omap54xx_dmic_addrs,
4092 .user = OCP_USER_MPU,
4093 };
4095 /* l4_cfg -> dsp */
4096 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dsp = {
4097 .master = &omap54xx_l4_cfg_hwmod,
4098 .slave = &omap54xx_dsp_hwmod,
4099 .clk = "l4_root_clk_div",
4100 .user = OCP_USER_MPU | OCP_USER_SDMA,
4101 };
4103 static struct omap_hwmod_addr_space omap54xx_dss_addrs[] = {
4104 {
4105 .pa_start = 0x58000000,
4106 .pa_end = 0x5800007f,
4107 .flags = ADDR_TYPE_RT
4108 },
4109 { }
4110 };
4112 /* l3_main_2 -> dss */
4113 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
4114 .master = &omap54xx_l3_main_2_hwmod,
4115 .slave = &omap54xx_dss_hwmod,
4116 .clk = "l3_iclk_div",
4117 .addr = omap54xx_dss_addrs,
4118 .user = OCP_USER_MPU | OCP_USER_SDMA,
4119 };
4121 static struct omap_hwmod_addr_space omap54xx_dss_dispc_addrs[] = {
4122 {
4123 .pa_start = 0x58001000,
4124 .pa_end = 0x58001fff,
4125 .flags = ADDR_TYPE_RT
4126 },
4127 { }
4128 };
4130 /* l3_main_2 -> dss_dispc */
4131 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
4132 .master = &omap54xx_l3_main_2_hwmod,
4133 .slave = &omap54xx_dss_dispc_hwmod,
4134 .clk = "l3_iclk_div",
4135 .addr = omap54xx_dss_dispc_addrs,
4136 .user = OCP_USER_MPU | OCP_USER_SDMA,
4137 };
4139 static struct omap_hwmod_addr_space omap54xx_dss_dsi1_a_addrs[] = {
4140 {
4141 .pa_start = 0x58004000,
4142 .pa_end = 0x580041ff,
4143 .flags = ADDR_TYPE_RT
4144 },
4145 { }
4146 };
4148 /* l3_main_2 -> dss_dsi1_a */
4149 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
4150 .master = &omap54xx_l3_main_2_hwmod,
4151 .slave = &omap54xx_dss_dsi1_a_hwmod,
4152 .clk = "l3_iclk_div",
4153 .addr = omap54xx_dss_dsi1_a_addrs,
4154 .user = OCP_USER_MPU | OCP_USER_SDMA,
4155 };
4157 static struct omap_hwmod_addr_space omap54xx_dss_dsi1_b_addrs[] = {
4158 {
4159 .pa_start = 0x58005000,
4160 .pa_end = 0x580051ff,
4161 .flags = ADDR_TYPE_RT
4162 },
4163 { }
4164 };
4166 /* l3_main_2 -> dss_dsi1_b */
4167 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_b = {
4168 .master = &omap54xx_l3_main_2_hwmod,
4169 .slave = &omap54xx_dss_dsi1_b_hwmod,
4170 .clk = "l3_iclk_div",
4171 .addr = omap54xx_dss_dsi1_b_addrs,
4172 .user = OCP_USER_MPU | OCP_USER_SDMA,
4173 };
4175 static struct omap_hwmod_addr_space omap54xx_dss_dsi1_c_addrs[] = {
4176 {
4177 .pa_start = 0x58009000,
4178 .pa_end = 0x580091ff,
4179 .flags = ADDR_TYPE_RT
4180 },
4181 { }
4182 };
4184 /* l3_main_2 -> dss_dsi1_c */
4185 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
4186 .master = &omap54xx_l3_main_2_hwmod,
4187 .slave = &omap54xx_dss_dsi1_c_hwmod,
4188 .clk = "l3_iclk_div",
4189 .addr = omap54xx_dss_dsi1_c_addrs,
4190 .user = OCP_USER_MPU | OCP_USER_SDMA,
4191 };
4193 static struct omap_hwmod_addr_space omap54xx_dss_hdmi_addrs[] = {
4194 {
4195 .name = "hdmi_wp",
4196 .pa_start = 0x58040000,
4197 .pa_end = 0x580400ff,
4198 .flags = ADDR_TYPE_RT
4199 },
4200 {
4201 .name = "pllctrl",
4202 .pa_start = 0x58040200,
4203 .pa_end = 0x5804023f,
4204 },
4205 {
4206 .name = "hdmitxphy",
4207 .pa_start = 0x58040300,
4208 .pa_end = 0x5804033f,
4209 },
4210 {
4211 .name = "hdmi_core",
4212 .pa_start = 0x58060000,
4213 .pa_end = 0x58078fff,
4214 },
4215 { }
4216 };
4218 /* l3_main_2 -> dss_hdmi */
4219 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
4220 .master = &omap54xx_l3_main_2_hwmod,
4221 .slave = &omap54xx_dss_hdmi_hwmod,
4222 .clk = "l3_iclk_div",
4223 .addr = omap54xx_dss_hdmi_addrs,
4224 .user = OCP_USER_MPU | OCP_USER_SDMA,
4225 };
4227 static struct omap_hwmod_addr_space omap54xx_dss_rfbi_addrs[] = {
4228 {
4229 .pa_start = 0x58002000,
4230 .pa_end = 0x580020ff,
4231 .flags = ADDR_TYPE_RT
4232 },
4233 { }
4234 };
4236 /* l3_main_2 -> dss_rfbi */
4237 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
4238 .master = &omap54xx_l3_main_2_hwmod,
4239 .slave = &omap54xx_dss_rfbi_hwmod,
4240 .clk = "l3_iclk_div",
4241 .addr = omap54xx_dss_rfbi_addrs,
4242 .user = OCP_USER_MPU | OCP_USER_SDMA,
4243 };
4245 static struct omap_hwmod_addr_space omap54xx_elm_addrs[] = {
4246 {
4247 .pa_start = 0x48078000,
4248 .pa_end = 0x48078fff,
4249 .flags = ADDR_TYPE_RT
4250 },
4251 { }
4252 };
4254 /* l4_per -> elm */
4255 static struct omap_hwmod_ocp_if omap54xx_l4_per__elm = {
4256 .master = &omap54xx_l4_per_hwmod,
4257 .slave = &omap54xx_elm_hwmod,
4258 .clk = "l4_root_clk_div",
4259 .addr = omap54xx_elm_addrs,
4260 .user = OCP_USER_MPU | OCP_USER_SDMA,
4261 };
4263 /* emif_ocp_fw -> emif1 */
4264 static struct omap_hwmod_ocp_if omap54xx_emif_ocp_fw__emif1 = {
4265 .master = &omap54xx_emif_ocp_fw_hwmod,
4266 .slave = &omap54xx_emif1_hwmod,
4267 .clk = "dpll_core_h11x2_ck",
4268 .user = OCP_USER_MPU | OCP_USER_SDMA,
4269 };
4271 static struct omap_hwmod_addr_space omap54xx_emif1_addrs[] = {
4272 {
4273 .pa_start = 0x4c000000,
4274 .pa_end = 0x4c0003ff,
4275 .flags = ADDR_TYPE_RT
4276 },
4277 { }
4278 };
4280 /* mpu -> emif1 */
4281 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
4282 .master = &omap54xx_mpu_hwmod,
4283 .slave = &omap54xx_emif1_hwmod,
4284 .clk = "dpll_core_h11x2_ck",
4285 .addr = omap54xx_emif1_addrs,
4286 .user = OCP_USER_MPU,
4287 };
4289 /* emif_ocp_fw -> emif2 */
4290 static struct omap_hwmod_ocp_if omap54xx_emif_ocp_fw__emif2 = {
4291 .master = &omap54xx_emif_ocp_fw_hwmod,
4292 .slave = &omap54xx_emif2_hwmod,
4293 .clk = "dpll_core_h11x2_ck",
4294 .user = OCP_USER_MPU | OCP_USER_SDMA,
4295 };
4297 static struct omap_hwmod_addr_space omap54xx_emif2_addrs[] = {
4298 {
4299 .pa_start = 0x4d000000,
4300 .pa_end = 0x4d0003ff,
4301 .flags = ADDR_TYPE_RT
4302 },
4303 { }
4304 };
4306 /* mpu -> emif2 */
4307 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
4308 .master = &omap54xx_mpu_hwmod,
4309 .slave = &omap54xx_emif2_hwmod,
4310 .clk = "dpll_core_h11x2_ck",
4311 .addr = omap54xx_emif2_addrs,
4312 .user = OCP_USER_MPU,
4313 };
4315 static struct omap_hwmod_addr_space omap54xx_fdif_addrs[] = {
4316 {
4317 .pa_start = 0x4a10a000,
4318 .pa_end = 0x4a10a3ff,
4319 .flags = ADDR_TYPE_RT
4320 },
4321 { }
4322 };
4324 /* l4_cfg -> fdif */
4325 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__fdif = {
4326 .master = &omap54xx_l4_cfg_hwmod,
4327 .slave = &omap54xx_fdif_hwmod,
4328 .clk = "l4_root_clk_div",
4329 .addr = omap54xx_fdif_addrs,
4330 .user = OCP_USER_MPU | OCP_USER_SDMA,
4331 };
4333 static struct omap_hwmod_addr_space omap54xx_gpio1_addrs[] = {
4334 {
4335 .pa_start = 0x4ae10000,
4336 .pa_end = 0x4ae101ff,
4337 .flags = ADDR_TYPE_RT
4338 },
4339 { }
4340 };
4342 /* l4_wkup -> gpio1 */
4343 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
4344 .master = &omap54xx_l4_wkup_hwmod,
4345 .slave = &omap54xx_gpio1_hwmod,
4346 .clk = "wkupaon_iclk_mux",
4347 .addr = omap54xx_gpio1_addrs,
4348 .user = OCP_USER_MPU | OCP_USER_SDMA,
4349 };
4351 static struct omap_hwmod_addr_space omap54xx_gpio2_addrs[] = {
4352 {
4353 .pa_start = 0x48055000,
4354 .pa_end = 0x480551ff,
4355 .flags = ADDR_TYPE_RT
4356 },
4357 { }
4358 };
4360 /* l4_per -> gpio2 */
4361 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
4362 .master = &omap54xx_l4_per_hwmod,
4363 .slave = &omap54xx_gpio2_hwmod,
4364 .clk = "l4_root_clk_div",
4365 .addr = omap54xx_gpio2_addrs,
4366 .user = OCP_USER_MPU | OCP_USER_SDMA,
4367 };
4369 static struct omap_hwmod_addr_space omap54xx_gpio3_addrs[] = {
4370 {
4371 .pa_start = 0x48057000,
4372 .pa_end = 0x480571ff,
4373 .flags = ADDR_TYPE_RT
4374 },
4375 { }
4376 };
4378 /* l4_per -> gpio3 */
4379 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
4380 .master = &omap54xx_l4_per_hwmod,
4381 .slave = &omap54xx_gpio3_hwmod,
4382 .clk = "l4_root_clk_div",
4383 .addr = omap54xx_gpio3_addrs,
4384 .user = OCP_USER_MPU | OCP_USER_SDMA,
4385 };
4387 static struct omap_hwmod_addr_space omap54xx_gpio4_addrs[] = {
4388 {
4389 .pa_start = 0x48059000,
4390 .pa_end = 0x480591ff,
4391 .flags = ADDR_TYPE_RT
4392 },
4393 { }
4394 };
4396 /* l4_per -> gpio4 */
4397 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
4398 .master = &omap54xx_l4_per_hwmod,
4399 .slave = &omap54xx_gpio4_hwmod,
4400 .clk = "l4_root_clk_div",
4401 .addr = omap54xx_gpio4_addrs,
4402 .user = OCP_USER_MPU | OCP_USER_SDMA,
4403 };
4405 static struct omap_hwmod_addr_space omap54xx_gpio5_addrs[] = {
4406 {
4407 .pa_start = 0x4805b000,
4408 .pa_end = 0x4805b1ff,
4409 .flags = ADDR_TYPE_RT
4410 },
4411 { }
4412 };
4414 /* l4_per -> gpio5 */
4415 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
4416 .master = &omap54xx_l4_per_hwmod,
4417 .slave = &omap54xx_gpio5_hwmod,
4418 .clk = "l4_root_clk_div",
4419 .addr = omap54xx_gpio5_addrs,
4420 .user = OCP_USER_MPU | OCP_USER_SDMA,
4421 };
4423 static struct omap_hwmod_addr_space omap54xx_gpio6_addrs[] = {
4424 {
4425 .pa_start = 0x4805d000,
4426 .pa_end = 0x4805d1ff,
4427 .flags = ADDR_TYPE_RT
4428 },
4429 { }
4430 };
4432 /* l4_per -> gpio6 */
4433 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
4434 .master = &omap54xx_l4_per_hwmod,
4435 .slave = &omap54xx_gpio6_hwmod,
4436 .clk = "l4_root_clk_div",
4437 .addr = omap54xx_gpio6_addrs,
4438 .user = OCP_USER_MPU | OCP_USER_SDMA,
4439 };
4441 static struct omap_hwmod_addr_space omap54xx_gpio7_addrs[] = {
4442 {
4443 .pa_start = 0x48051000,
4444 .pa_end = 0x480511ff,
4445 .flags = ADDR_TYPE_RT
4446 },
4447 { }
4448 };
4450 /* l4_per -> gpio7 */
4451 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
4452 .master = &omap54xx_l4_per_hwmod,
4453 .slave = &omap54xx_gpio7_hwmod,
4454 .clk = "l4_root_clk_div",
4455 .addr = omap54xx_gpio7_addrs,
4456 .user = OCP_USER_MPU | OCP_USER_SDMA,
4457 };
4459 static struct omap_hwmod_addr_space omap54xx_gpio8_addrs[] = {
4460 {
4461 .pa_start = 0x48053000,
4462 .pa_end = 0x480531ff,
4463 .flags = ADDR_TYPE_RT
4464 },
4465 { }
4466 };
4468 /* l4_per -> gpio8 */
4469 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
4470 .master = &omap54xx_l4_per_hwmod,
4471 .slave = &omap54xx_gpio8_hwmod,
4472 .clk = "l4_root_clk_div",
4473 .addr = omap54xx_gpio8_addrs,
4474 .user = OCP_USER_MPU | OCP_USER_SDMA,
4475 };
4477 static struct omap_hwmod_addr_space omap54xx_gpmc_addrs[] = {
4478 {
4479 .pa_start = 0x50000000,
4480 .pa_end = 0x500003ff,
4481 .flags = ADDR_TYPE_RT
4482 },
4483 { }
4484 };
4486 /* l3_main_2 -> gpmc */
4487 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__gpmc = {
4488 .master = &omap54xx_l3_main_2_hwmod,
4489 .slave = &omap54xx_gpmc_hwmod,
4490 .clk = "l3_iclk_div",
4491 .addr = omap54xx_gpmc_addrs,
4492 .user = OCP_USER_MPU | OCP_USER_SDMA,
4493 };
4495 static struct omap_hwmod_addr_space omap54xx_gpu_addrs[] = {
4496 {
4497 .name = "klio",
4498 .pa_start = 0x56000000,
4499 .pa_end = 0x56001fff,
4500 },
4501 {
4502 .name = "hydra2",
4503 .pa_start = 0x56004000,
4504 .pa_end = 0x56004fff,
4505 },
4506 {
4507 .name = "klio_0",
4508 .pa_start = 0x56008000,
4509 .pa_end = 0x56009fff,
4510 },
4511 {
4512 .name = "klio_1",
4513 .pa_start = 0x5600c000,
4514 .pa_end = 0x5600dfff,
4515 },
4516 {
4517 .name = "klio_hl",
4518 .pa_start = 0x5600fe00,
4519 .pa_end = 0x5600ffff,
4520 .flags = ADDR_TYPE_RT
4521 },
4522 { }
4523 };
4525 /* l3_main_2 -> gpu */
4526 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__gpu = {
4527 .master = &omap54xx_l3_main_2_hwmod,
4528 .slave = &omap54xx_gpu_hwmod,
4529 .clk = "gpu_l3_iclk",
4530 .addr = omap54xx_gpu_addrs,
4531 .user = OCP_USER_MPU | OCP_USER_SDMA,
4532 };
4534 static struct omap_hwmod_addr_space omap54xx_hdq1w_addrs[] = {
4535 {
4536 .pa_start = 0x480b2000,
4537 .pa_end = 0x480b201f,
4538 .flags = ADDR_TYPE_RT
4539 },
4540 { }
4541 };
4543 /* l4_per -> hdq1w */
4544 static struct omap_hwmod_ocp_if omap54xx_l4_per__hdq1w = {
4545 .master = &omap54xx_l4_per_hwmod,
4546 .slave = &omap54xx_hdq1w_hwmod,
4547 .clk = "l4_root_clk_div",
4548 .addr = omap54xx_hdq1w_addrs,
4549 .user = OCP_USER_MPU | OCP_USER_SDMA,
4550 };
4552 static struct omap_hwmod_addr_space omap54xx_hsi_addrs[] = {
4553 {
4554 .name = "system_32",
4555 .pa_start = 0x4a058000,
4556 .pa_end = 0x4a059fff,
4557 .flags = ADDR_TYPE_RT
4558 },
4559 {
4560 .name = "dte_channels",
4561 .pa_start = 0x4a059800,
4562 .pa_end = 0x4a059bff,
4563 },
4564 {
4565 .name = "hsi_32",
4566 .pa_start = 0x4a05a000,
4567 .pa_end = 0x4a05bfff,
4568 },
4569 { }
4570 };
4572 /* l4_cfg -> hsi */
4573 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__hsi = {
4574 .master = &omap54xx_l4_cfg_hwmod,
4575 .slave = &omap54xx_hsi_hwmod,
4576 .clk = "l3_iclk_div",
4577 .addr = omap54xx_hsi_addrs,
4578 .user = OCP_USER_MPU | OCP_USER_SDMA,
4579 };
4581 static struct omap_hwmod_addr_space omap54xx_i2c1_addrs[] = {
4582 {
4583 .pa_start = 0x48070000,
4584 .pa_end = 0x480700ff,
4585 .flags = ADDR_TYPE_RT
4586 },
4587 { }
4588 };
4590 /* l4_per -> i2c1 */
4591 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
4592 .master = &omap54xx_l4_per_hwmod,
4593 .slave = &omap54xx_i2c1_hwmod,
4594 .clk = "l4_root_clk_div",
4595 .addr = omap54xx_i2c1_addrs,
4596 .user = OCP_USER_MPU | OCP_USER_SDMA,
4597 };
4599 static struct omap_hwmod_addr_space omap54xx_i2c2_addrs[] = {
4600 {
4601 .pa_start = 0x48072000,
4602 .pa_end = 0x480720ff,
4603 .flags = ADDR_TYPE_RT
4604 },
4605 { }
4606 };
4608 /* l4_per -> i2c2 */
4609 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
4610 .master = &omap54xx_l4_per_hwmod,
4611 .slave = &omap54xx_i2c2_hwmod,
4612 .clk = "l4_root_clk_div",
4613 .addr = omap54xx_i2c2_addrs,
4614 .user = OCP_USER_MPU | OCP_USER_SDMA,
4615 };
4617 static struct omap_hwmod_addr_space omap54xx_i2c3_addrs[] = {
4618 {
4619 .pa_start = 0x48060000,
4620 .pa_end = 0x480600ff,
4621 .flags = ADDR_TYPE_RT
4622 },
4623 { }
4624 };
4626 /* l4_per -> i2c3 */
4627 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
4628 .master = &omap54xx_l4_per_hwmod,
4629 .slave = &omap54xx_i2c3_hwmod,
4630 .clk = "l4_root_clk_div",
4631 .addr = omap54xx_i2c3_addrs,
4632 .user = OCP_USER_MPU | OCP_USER_SDMA,
4633 };
4635 static struct omap_hwmod_addr_space omap54xx_i2c4_addrs[] = {
4636 {
4637 .pa_start = 0x4807a000,
4638 .pa_end = 0x4807a0ff,
4639 .flags = ADDR_TYPE_RT
4640 },
4641 { }
4642 };
4644 /* l4_per -> i2c4 */
4645 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
4646 .master = &omap54xx_l4_per_hwmod,
4647 .slave = &omap54xx_i2c4_hwmod,
4648 .clk = "l4_root_clk_div",
4649 .addr = omap54xx_i2c4_addrs,
4650 .user = OCP_USER_MPU | OCP_USER_SDMA,
4651 };
4653 static struct omap_hwmod_addr_space omap54xx_i2c5_addrs[] = {
4654 {
4655 .pa_start = 0x4807c000,
4656 .pa_end = 0x4807c0ff,
4657 .flags = ADDR_TYPE_RT
4658 },
4659 { }
4660 };
4662 /* l4_per -> i2c5 */
4663 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
4664 .master = &omap54xx_l4_per_hwmod,
4665 .slave = &omap54xx_i2c5_hwmod,
4666 .clk = "l4_root_clk_div",
4667 .addr = omap54xx_i2c5_addrs,
4668 .user = OCP_USER_MPU | OCP_USER_SDMA,
4669 };
4671 static struct omap_hwmod_addr_space omap54xx_ipu_addrs[] = {
4672 {
4673 .name = "unicache_mmu",
4674 .pa_start = 0x55080800,
4675 .pa_end = 0x55080fff,
4676 },
4677 {
4678 .name = "teslass_mmu",
4679 .pa_start = 0x55082000,
4680 .pa_end = 0x550820ff,
4681 .flags = ADDR_TYPE_RT
4682 },
4683 { }
4684 };
4686 /* l3_main_2 -> ipu */
4687 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__ipu = {
4688 .master = &omap54xx_l3_main_2_hwmod,
4689 .slave = &omap54xx_ipu_hwmod,
4690 .clk = "l3_iclk_div",
4691 .addr = omap54xx_ipu_addrs,
4692 .user = OCP_USER_MPU | OCP_USER_SDMA,
4693 };
4695 static struct omap_hwmod_addr_space omap54xx_intc_ipu_c0_addrs[] = {
4696 {
4697 .pa_start = 0x48211000,
4698 .pa_end = 0x48211fff,
4699 },
4700 { }
4701 };
4703 /* l3_main_2 -> intc_ipu_c0 */
4704 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__intc_ipu_c0 = {
4705 .master = &omap54xx_l3_main_2_hwmod,
4706 .slave = &omap54xx_intc_ipu_c0_hwmod,
4707 .clk = "l3_iclk_div",
4708 .addr = omap54xx_intc_ipu_c0_addrs,
4709 .user = OCP_USER_MPU | OCP_USER_SDMA,
4710 };
4712 static struct omap_hwmod_addr_space omap54xx_intc_ipu_c1_addrs[] = {
4713 {
4714 .pa_start = 0x48211000,
4715 .pa_end = 0x48211fff,
4716 },
4717 { }
4718 };
4720 /* l3_main_2 -> intc_ipu_c1 */
4721 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__intc_ipu_c1 = {
4722 .master = &omap54xx_l3_main_2_hwmod,
4723 .slave = &omap54xx_intc_ipu_c1_hwmod,
4724 .clk = "l3_iclk_div",
4725 .addr = omap54xx_intc_ipu_c1_addrs,
4726 .user = OCP_USER_MPU | OCP_USER_SDMA,
4727 };
4729 static struct omap_hwmod_addr_space omap54xx_iss_addrs[] = {
4730 {
4731 .pa_start = 0x52000000,
4732 .pa_end = 0x520000ff,
4733 .flags = ADDR_TYPE_RT
4734 },
4735 { }
4736 };
4738 /* l3_main_2 -> iss */
4739 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__iss = {
4740 .master = &omap54xx_l3_main_2_hwmod,
4741 .slave = &omap54xx_iss_hwmod,
4742 .clk = "dpll_core_h23x2_ck",
4743 .addr = omap54xx_iss_addrs,
4744 .user = OCP_USER_MPU | OCP_USER_SDMA,
4745 };
4747 static struct omap_hwmod_addr_space omap54xx_iva_addrs[] = {
4748 {
4749 .pa_start = 0x5a05a400,
4750 .pa_end = 0x5a05a47f,
4751 .flags = ADDR_TYPE_RT
4752 },
4753 { }
4754 };
4756 /* l3_main_2 -> iva */
4757 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__iva = {
4758 .master = &omap54xx_l3_main_2_hwmod,
4759 .slave = &omap54xx_iva_hwmod,
4760 .clk = "l3_iclk_div",
4761 .addr = omap54xx_iva_addrs,
4762 .user = OCP_USER_MPU | OCP_USER_SDMA,
4763 };
4765 static struct omap_hwmod_addr_space omap54xx_kbd_addrs[] = {
4766 {
4767 .pa_start = 0x4ae1c000,
4768 .pa_end = 0x4ae1c07f,
4769 .flags = ADDR_TYPE_RT
4770 },
4771 { }
4772 };
4774 /* l4_wkup -> kbd */
4775 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
4776 .master = &omap54xx_l4_wkup_hwmod,
4777 .slave = &omap54xx_kbd_hwmod,
4778 .clk = "wkupaon_iclk_mux",
4779 .addr = omap54xx_kbd_addrs,
4780 .user = OCP_USER_MPU | OCP_USER_SDMA,
4781 };
4783 static struct omap_hwmod_addr_space omap54xx_mailbox_addrs[] = {
4784 {
4785 .pa_start = 0x4a0f4000,
4786 .pa_end = 0x4a0f41ff,
4787 .flags = ADDR_TYPE_RT
4788 },
4789 { }
4790 };
4792 /* l4_cfg -> mailbox */
4793 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
4794 .master = &omap54xx_l4_cfg_hwmod,
4795 .slave = &omap54xx_mailbox_hwmod,
4796 .clk = "l4_root_clk_div",
4797 .addr = omap54xx_mailbox_addrs,
4798 .user = OCP_USER_MPU | OCP_USER_SDMA,
4799 };
4801 static struct omap_hwmod_addr_space omap54xx_mcasp_addrs[] = {
4802 {
4803 .name = "cfg",
4804 .pa_start = 0x40128000,
4805 .pa_end = 0x401283ff,
4806 .flags = ADDR_TYPE_RT
4807 },
4808 {
4809 .name = "dat",
4810 .pa_start = 0x4012a000,
4811 .pa_end = 0x4012a3ff,
4812 .flags = ADDR_TYPE_RT
4813 },
4814 { }
4815 };
4817 /* l4_abe -> mcasp */
4818 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcasp = {
4819 .master = &omap54xx_l4_abe_hwmod,
4820 .slave = &omap54xx_mcasp_hwmod,
4821 .clk = "abe_iclk",
4822 .addr = omap54xx_mcasp_addrs,
4823 .user = OCP_USER_MPU,
4824 };
4826 static struct omap_hwmod_addr_space omap54xx_mcbsp1_addrs[] = {
4827 {
4828 .name = "mpu",
4829 .pa_start = 0x40122000,
4830 .pa_end = 0x401220ff,
4831 .flags = ADDR_TYPE_RT
4832 },
4833 { }
4834 };
4836 /* l4_abe -> mcbsp1 */
4837 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
4838 .master = &omap54xx_l4_abe_hwmod,
4839 .slave = &omap54xx_mcbsp1_hwmod,
4840 .clk = "abe_iclk",
4841 .addr = omap54xx_mcbsp1_addrs,
4842 .user = OCP_USER_MPU,
4843 };
4845 static struct omap_hwmod_addr_space omap54xx_mcbsp2_addrs[] = {
4846 {
4847 .name = "mpu",
4848 .pa_start = 0x40124000,
4849 .pa_end = 0x401240ff,
4850 .flags = ADDR_TYPE_RT
4851 },
4852 { }
4853 };
4855 /* l4_abe -> mcbsp2 */
4856 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
4857 .master = &omap54xx_l4_abe_hwmod,
4858 .slave = &omap54xx_mcbsp2_hwmod,
4859 .clk = "abe_iclk",
4860 .addr = omap54xx_mcbsp2_addrs,
4861 .user = OCP_USER_MPU,
4862 };
4864 static struct omap_hwmod_addr_space omap54xx_mcbsp3_addrs[] = {
4865 {
4866 .name = "mpu",
4867 .pa_start = 0x40126000,
4868 .pa_end = 0x401260ff,
4869 .flags = ADDR_TYPE_RT
4870 },
4871 { }
4872 };
4874 /* l4_abe -> mcbsp3 */
4875 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
4876 .master = &omap54xx_l4_abe_hwmod,
4877 .slave = &omap54xx_mcbsp3_hwmod,
4878 .clk = "abe_iclk",
4879 .addr = omap54xx_mcbsp3_addrs,
4880 .user = OCP_USER_MPU,
4881 };
4883 static struct omap_hwmod_addr_space omap54xx_mcpdm_addrs[] = {
4884 {
4885 .name = "mpu",
4886 .pa_start = 0x40132000,
4887 .pa_end = 0x4013207f,
4888 .flags = ADDR_TYPE_RT
4889 },
4890 { }
4891 };
4893 /* l4_abe -> mcpdm */
4894 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
4895 .master = &omap54xx_l4_abe_hwmod,
4896 .slave = &omap54xx_mcpdm_hwmod,
4897 .clk = "abe_iclk",
4898 .addr = omap54xx_mcpdm_addrs,
4899 .user = OCP_USER_MPU,
4900 };
4902 static struct omap_hwmod_addr_space omap54xx_mcspi1_addrs[] = {
4903 {
4904 .pa_start = 0x48098000,
4905 .pa_end = 0x480981ff,
4906 .flags = ADDR_TYPE_RT
4907 },
4908 { }
4909 };
4911 /* l4_per -> mcspi1 */
4912 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
4913 .master = &omap54xx_l4_per_hwmod,
4914 .slave = &omap54xx_mcspi1_hwmod,
4915 .clk = "l4_root_clk_div",
4916 .addr = omap54xx_mcspi1_addrs,
4917 .user = OCP_USER_MPU | OCP_USER_SDMA,
4918 };
4920 static struct omap_hwmod_addr_space omap54xx_mcspi2_addrs[] = {
4921 {
4922 .pa_start = 0x4809a000,
4923 .pa_end = 0x4809a1ff,
4924 .flags = ADDR_TYPE_RT
4925 },
4926 { }
4927 };
4929 /* l4_per -> mcspi2 */
4930 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
4931 .master = &omap54xx_l4_per_hwmod,
4932 .slave = &omap54xx_mcspi2_hwmod,
4933 .clk = "l4_root_clk_div",
4934 .addr = omap54xx_mcspi2_addrs,
4935 .user = OCP_USER_MPU | OCP_USER_SDMA,
4936 };
4938 static struct omap_hwmod_addr_space omap54xx_mcspi3_addrs[] = {
4939 {
4940 .pa_start = 0x480b8000,
4941 .pa_end = 0x480b81ff,
4942 .flags = ADDR_TYPE_RT
4943 },
4944 { }
4945 };
4947 /* l4_per -> mcspi3 */
4948 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
4949 .master = &omap54xx_l4_per_hwmod,
4950 .slave = &omap54xx_mcspi3_hwmod,
4951 .clk = "l4_root_clk_div",
4952 .addr = omap54xx_mcspi3_addrs,
4953 .user = OCP_USER_MPU | OCP_USER_SDMA,
4954 };
4956 static struct omap_hwmod_addr_space omap54xx_mcspi4_addrs[] = {
4957 {
4958 .pa_start = 0x480ba000,
4959 .pa_end = 0x480ba1ff,
4960 .flags = ADDR_TYPE_RT
4961 },
4962 { }
4963 };
4965 /* l4_per -> mcspi4 */
4966 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
4967 .master = &omap54xx_l4_per_hwmod,
4968 .slave = &omap54xx_mcspi4_hwmod,
4969 .clk = "l4_root_clk_div",
4970 .addr = omap54xx_mcspi4_addrs,
4971 .user = OCP_USER_MPU | OCP_USER_SDMA,
4972 };
4974 static struct omap_hwmod_addr_space omap54xx_mmc1_addrs[] = {
4975 {
4976 .pa_start = 0x4809c000,
4977 .pa_end = 0x4809c3ff,
4978 .flags = ADDR_TYPE_RT
4979 },
4980 { }
4981 };
4983 /* l4_per -> mmc1 */
4984 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
4985 .master = &omap54xx_l4_per_hwmod,
4986 .slave = &omap54xx_mmc1_hwmod,
4987 .clk = "l3_iclk_div",
4988 .addr = omap54xx_mmc1_addrs,
4989 .user = OCP_USER_MPU | OCP_USER_SDMA,
4990 };
4992 static struct omap_hwmod_addr_space omap54xx_mmc2_addrs[] = {
4993 {
4994 .pa_start = 0x480b4000,
4995 .pa_end = 0x480b43ff,
4996 .flags = ADDR_TYPE_RT
4997 },
4998 { }
4999 };
5001 /* l4_per -> mmc2 */
5002 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
5003 .master = &omap54xx_l4_per_hwmod,
5004 .slave = &omap54xx_mmc2_hwmod,
5005 .clk = "l3_iclk_div",
5006 .addr = omap54xx_mmc2_addrs,
5007 .user = OCP_USER_MPU | OCP_USER_SDMA,
5008 };
5010 static struct omap_hwmod_addr_space omap54xx_mmc3_addrs[] = {
5011 {
5012 .pa_start = 0x480ad000,
5013 .pa_end = 0x480ad3ff,
5014 .flags = ADDR_TYPE_RT
5015 },
5016 { }
5017 };
5019 /* l4_per -> mmc3 */
5020 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
5021 .master = &omap54xx_l4_per_hwmod,
5022 .slave = &omap54xx_mmc3_hwmod,
5023 .clk = "l4_root_clk_div",
5024 .addr = omap54xx_mmc3_addrs,
5025 .user = OCP_USER_MPU | OCP_USER_SDMA,
5026 };
5028 static struct omap_hwmod_addr_space omap54xx_mmc4_addrs[] = {
5029 {
5030 .pa_start = 0x480d1000,
5031 .pa_end = 0x480d13ff,
5032 .flags = ADDR_TYPE_RT
5033 },
5034 { }
5035 };
5037 /* l4_per -> mmc4 */
5038 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
5039 .master = &omap54xx_l4_per_hwmod,
5040 .slave = &omap54xx_mmc4_hwmod,
5041 .clk = "l4_root_clk_div",
5042 .addr = omap54xx_mmc4_addrs,
5043 .user = OCP_USER_MPU | OCP_USER_SDMA,
5044 };
5046 static struct omap_hwmod_addr_space omap54xx_mmc5_addrs[] = {
5047 {
5048 .pa_start = 0x480d5000,
5049 .pa_end = 0x480d53ff,
5050 .flags = ADDR_TYPE_RT
5051 },
5052 { }
5053 };
5055 /* l4_per -> mmc5 */
5056 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
5057 .master = &omap54xx_l4_per_hwmod,
5058 .slave = &omap54xx_mmc5_hwmod,
5059 .clk = "l4_root_clk_div",
5060 .addr = omap54xx_mmc5_addrs,
5061 .user = OCP_USER_MPU | OCP_USER_SDMA,
5062 };
5064 static struct omap_hwmod_addr_space omap54xx_mpu_addrs[] = {
5065 {
5066 .pa_start = 0x48211000,
5067 .pa_end = 0x482af27f,
5068 },
5069 { }
5070 };
5072 /* l4_cfg -> mpu */
5073 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
5074 .master = &omap54xx_l4_cfg_hwmod,
5075 .slave = &omap54xx_mpu_hwmod,
5076 .clk = "l4_root_clk_div",
5077 .addr = omap54xx_mpu_addrs,
5078 .user = OCP_USER_MPU | OCP_USER_SDMA,
5079 };
5081 /* l3_main_2 -> ocmc_ram */
5082 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__ocmc_ram = {
5083 .master = &omap54xx_l3_main_2_hwmod,
5084 .slave = &omap54xx_ocmc_ram_hwmod,
5085 .clk = "l3_iclk_div",
5086 .user = OCP_USER_MPU | OCP_USER_SDMA,
5087 };
5089 static struct omap_hwmod_addr_space omap54xx_ocp2scp1_addrs[] = {
5090 {
5091 .pa_start = 0x4a080000,
5092 .pa_end = 0x4a08001f,
5093 .flags = ADDR_TYPE_RT
5094 },
5095 { }
5096 };
5098 /* l4_cfg -> ocp2scp1 */
5099 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
5100 .master = &omap54xx_l4_cfg_hwmod,
5101 .slave = &omap54xx_ocp2scp1_hwmod,
5102 .clk = "l4_root_clk_div",
5103 .addr = omap54xx_ocp2scp1_addrs,
5104 .user = OCP_USER_MPU | OCP_USER_SDMA,
5105 };
5107 static struct omap_hwmod_addr_space omap54xx_sata_addrs[] = {
5108 {
5109 .name = "ahci",
5110 .pa_start = 0x4a140000,
5111 .pa_end = 0x4a1401ff,
5112 },
5113 {
5114 .name = "sysc",
5115 .pa_start = 0x4a141100,
5116 .pa_end = 0x4a141107,
5117 .flags = ADDR_TYPE_RT
5118 },
5119 { }
5120 };
5122 /* l4_cfg -> sata */
5123 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
5124 .master = &omap54xx_l4_cfg_hwmod,
5125 .slave = &omap54xx_sata_hwmod,
5126 .clk = "l3_iclk_div",
5127 .addr = omap54xx_sata_addrs,
5128 .user = OCP_USER_MPU | OCP_USER_SDMA,
5129 };
5131 static struct omap_hwmod_addr_space omap54xx_scrm_addrs[] = {
5132 {
5133 .pa_start = 0x4ae0a000,
5134 .pa_end = 0x4ae0a7ff,
5135 },
5136 { }
5137 };
5139 /* l4_wkup -> scrm */
5140 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__scrm = {
5141 .master = &omap54xx_l4_wkup_hwmod,
5142 .slave = &omap54xx_scrm_hwmod,
5143 .clk = "wkupaon_iclk_mux",
5144 .addr = omap54xx_scrm_addrs,
5145 .user = OCP_USER_MPU | OCP_USER_SDMA,
5146 };
5148 static struct omap_hwmod_addr_space omap54xx_slimbus1_addrs[] = {
5149 {
5150 .name = "mpu",
5151 .pa_start = 0x4012c000,
5152 .pa_end = 0x4012c3ff,
5153 .flags = ADDR_TYPE_RT
5154 },
5155 { }
5156 };
5158 /* l4_abe -> slimbus1 */
5159 static struct omap_hwmod_ocp_if omap54xx_l4_abe__slimbus1 = {
5160 .master = &omap54xx_l4_abe_hwmod,
5161 .slave = &omap54xx_slimbus1_hwmod,
5162 .clk = "abe_iclk",
5163 .addr = omap54xx_slimbus1_addrs,
5164 .user = OCP_USER_MPU,
5165 };
5167 static struct omap_hwmod_addr_space omap54xx_smartreflex_core_addrs[] = {
5168 {
5169 .pa_start = 0x4a0dd000,
5170 .pa_end = 0x4a0dd03f,
5171 .flags = ADDR_TYPE_RT
5172 },
5173 { }
5174 };
5176 /* l4_cfg -> smartreflex_core */
5177 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__smartreflex_core = {
5178 .master = &omap54xx_l4_cfg_hwmod,
5179 .slave = &omap54xx_smartreflex_core_hwmod,
5180 .clk = "l4_root_clk_div",
5181 .addr = omap54xx_smartreflex_core_addrs,
5182 .user = OCP_USER_MPU | OCP_USER_SDMA,
5183 };
5185 static struct omap_hwmod_addr_space omap54xx_smartreflex_mm_addrs[] = {
5186 {
5187 .pa_start = 0x4a0db000,
5188 .pa_end = 0x4a0db03f,
5189 .flags = ADDR_TYPE_RT
5190 },
5191 { }
5192 };
5194 /* l4_cfg -> smartreflex_mm */
5195 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__smartreflex_mm = {
5196 .master = &omap54xx_l4_cfg_hwmod,
5197 .slave = &omap54xx_smartreflex_mm_hwmod,
5198 .clk = "l4_root_clk_div",
5199 .addr = omap54xx_smartreflex_mm_addrs,
5200 .user = OCP_USER_MPU | OCP_USER_SDMA,
5201 };
5203 static struct omap_hwmod_addr_space omap54xx_smartreflex_mpu_addrs[] = {
5204 {
5205 .pa_start = 0x4a0d9000,
5206 .pa_end = 0x4a0d903f,
5207 .flags = ADDR_TYPE_RT
5208 },
5209 { }
5210 };
5212 /* l4_cfg -> smartreflex_mpu */
5213 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__smartreflex_mpu = {
5214 .master = &omap54xx_l4_cfg_hwmod,
5215 .slave = &omap54xx_smartreflex_mpu_hwmod,
5216 .clk = "l4_root_clk_div",
5217 .addr = omap54xx_smartreflex_mpu_addrs,
5218 .user = OCP_USER_MPU | OCP_USER_SDMA,
5219 };
5221 static struct omap_hwmod_addr_space omap54xx_spinlock_addrs[] = {
5222 {
5223 .pa_start = 0x4a0f6000,
5224 .pa_end = 0x4a0f6fff,
5225 .flags = ADDR_TYPE_RT
5226 },
5227 { }
5228 };
5230 /* l4_cfg -> spinlock */
5231 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
5232 .master = &omap54xx_l4_cfg_hwmod,
5233 .slave = &omap54xx_spinlock_hwmod,
5234 .clk = "l4_root_clk_div",
5235 .addr = omap54xx_spinlock_addrs,
5236 .user = OCP_USER_MPU | OCP_USER_SDMA,
5237 };
5239 static struct omap_hwmod_addr_space omap54xx_timer1_addrs[] = {
5240 {
5241 .pa_start = 0x4ae18000,
5242 .pa_end = 0x4ae1807f,
5243 .flags = ADDR_TYPE_RT
5244 },
5245 { }
5246 };
5248 /* l4_wkup -> timer1 */
5249 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
5250 .master = &omap54xx_l4_wkup_hwmod,
5251 .slave = &omap54xx_timer1_hwmod,
5252 .clk = "wkupaon_iclk_mux",
5253 .addr = omap54xx_timer1_addrs,
5254 .user = OCP_USER_MPU | OCP_USER_SDMA,
5255 };
5257 static struct omap_hwmod_addr_space omap54xx_timer2_addrs[] = {
5258 {
5259 .pa_start = 0x48032000,
5260 .pa_end = 0x4803207f,
5261 .flags = ADDR_TYPE_RT
5262 },
5263 { }
5264 };
5266 /* l4_per -> timer2 */
5267 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
5268 .master = &omap54xx_l4_per_hwmod,
5269 .slave = &omap54xx_timer2_hwmod,
5270 .clk = "l4_root_clk_div",
5271 .addr = omap54xx_timer2_addrs,
5272 .user = OCP_USER_MPU | OCP_USER_SDMA,
5273 };
5275 static struct omap_hwmod_addr_space omap54xx_timer3_addrs[] = {
5276 {
5277 .pa_start = 0x48034000,
5278 .pa_end = 0x4803407f,
5279 .flags = ADDR_TYPE_RT
5280 },
5281 { }
5282 };
5284 /* l4_per -> timer3 */
5285 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
5286 .master = &omap54xx_l4_per_hwmod,
5287 .slave = &omap54xx_timer3_hwmod,
5288 .clk = "l4_root_clk_div",
5289 .addr = omap54xx_timer3_addrs,
5290 .user = OCP_USER_MPU | OCP_USER_SDMA,
5291 };
5293 static struct omap_hwmod_addr_space omap54xx_timer4_addrs[] = {
5294 {
5295 .pa_start = 0x48036000,
5296 .pa_end = 0x4803607f,
5297 .flags = ADDR_TYPE_RT
5298 },
5299 { }
5300 };
5302 /* l4_per -> timer4 */
5303 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
5304 .master = &omap54xx_l4_per_hwmod,
5305 .slave = &omap54xx_timer4_hwmod,
5306 .clk = "l4_root_clk_div",
5307 .addr = omap54xx_timer4_addrs,
5308 .user = OCP_USER_MPU | OCP_USER_SDMA,
5309 };
5311 static struct omap_hwmod_addr_space omap54xx_timer5_addrs[] = {
5312 {
5313 .name = "mpu",
5314 .pa_start = 0x40138000,
5315 .pa_end = 0x4013807f,
5316 .flags = ADDR_TYPE_RT
5317 },
5318 { }
5319 };
5321 /* l4_abe -> timer5 */
5322 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
5323 .master = &omap54xx_l4_abe_hwmod,
5324 .slave = &omap54xx_timer5_hwmod,
5325 .clk = "abe_iclk",
5326 .addr = omap54xx_timer5_addrs,
5327 .user = OCP_USER_MPU,
5328 };
5330 static struct omap_hwmod_addr_space omap54xx_timer6_addrs[] = {
5331 {
5332 .name = "mpu",
5333 .pa_start = 0x4013a000,
5334 .pa_end = 0x4013a07f,
5335 .flags = ADDR_TYPE_RT
5336 },
5337 { }
5338 };
5340 /* l4_abe -> timer6 */
5341 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
5342 .master = &omap54xx_l4_abe_hwmod,
5343 .slave = &omap54xx_timer6_hwmod,
5344 .clk = "abe_iclk",
5345 .addr = omap54xx_timer6_addrs,
5346 .user = OCP_USER_MPU,
5347 };
5349 static struct omap_hwmod_addr_space omap54xx_timer7_addrs[] = {
5350 {
5351 .name = "mpu",
5352 .pa_start = 0x4013c000,
5353 .pa_end = 0x4013c07f,
5354 .flags = ADDR_TYPE_RT
5355 },
5356 { }
5357 };
5359 /* l4_abe -> timer7 */
5360 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
5361 .master = &omap54xx_l4_abe_hwmod,
5362 .slave = &omap54xx_timer7_hwmod,
5363 .clk = "abe_iclk",
5364 .addr = omap54xx_timer7_addrs,
5365 .user = OCP_USER_MPU,
5366 };
5368 static struct omap_hwmod_addr_space omap54xx_timer8_addrs[] = {
5369 {
5370 .name = "mpu",
5371 .pa_start = 0x4013e000,
5372 .pa_end = 0x4013e07f,
5373 .flags = ADDR_TYPE_RT
5374 },
5375 { }
5376 };
5378 /* l4_abe -> timer8 */
5379 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
5380 .master = &omap54xx_l4_abe_hwmod,
5381 .slave = &omap54xx_timer8_hwmod,
5382 .clk = "abe_iclk",
5383 .addr = omap54xx_timer8_addrs,
5384 .user = OCP_USER_MPU,
5385 };
5387 static struct omap_hwmod_addr_space omap54xx_timer9_addrs[] = {
5388 {
5389 .pa_start = 0x4803e000,
5390 .pa_end = 0x4803e07f,
5391 .flags = ADDR_TYPE_RT
5392 },
5393 { }
5394 };
5396 /* l4_per -> timer9 */
5397 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
5398 .master = &omap54xx_l4_per_hwmod,
5399 .slave = &omap54xx_timer9_hwmod,
5400 .clk = "l4_root_clk_div",
5401 .addr = omap54xx_timer9_addrs,
5402 .user = OCP_USER_MPU | OCP_USER_SDMA,
5403 };
5405 static struct omap_hwmod_addr_space omap54xx_timer10_addrs[] = {
5406 {
5407 .pa_start = 0x48086000,
5408 .pa_end = 0x4808607f,
5409 .flags = ADDR_TYPE_RT
5410 },
5411 { }
5412 };
5414 /* l4_per -> timer10 */
5415 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
5416 .master = &omap54xx_l4_per_hwmod,
5417 .slave = &omap54xx_timer10_hwmod,
5418 .clk = "l4_root_clk_div",
5419 .addr = omap54xx_timer10_addrs,
5420 .user = OCP_USER_MPU | OCP_USER_SDMA,
5421 };
5423 static struct omap_hwmod_addr_space omap54xx_timer11_addrs[] = {
5424 {
5425 .pa_start = 0x48088000,
5426 .pa_end = 0x4808807f,
5427 .flags = ADDR_TYPE_RT
5428 },
5429 { }
5430 };
5432 /* l4_per -> timer11 */
5433 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
5434 .master = &omap54xx_l4_per_hwmod,
5435 .slave = &omap54xx_timer11_hwmod,
5436 .clk = "l4_root_clk_div",
5437 .addr = omap54xx_timer11_addrs,
5438 .user = OCP_USER_MPU | OCP_USER_SDMA,
5439 };
5441 static struct omap_hwmod_addr_space omap54xx_uart1_addrs[] = {
5442 {
5443 .pa_start = 0x4806a000,
5444 .pa_end = 0x4806a0ff,
5445 .flags = ADDR_TYPE_RT
5446 },
5447 { }
5448 };
5450 /* l4_per -> uart1 */
5451 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
5452 .master = &omap54xx_l4_per_hwmod,
5453 .slave = &omap54xx_uart1_hwmod,
5454 .clk = "l4_root_clk_div",
5455 .addr = omap54xx_uart1_addrs,
5456 .user = OCP_USER_MPU | OCP_USER_SDMA,
5457 };
5459 static struct omap_hwmod_addr_space omap54xx_uart2_addrs[] = {
5460 {
5461 .pa_start = 0x4806c000,
5462 .pa_end = 0x4806c0ff,
5463 .flags = ADDR_TYPE_RT
5464 },
5465 { }
5466 };
5468 /* l4_per -> uart2 */
5469 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
5470 .master = &omap54xx_l4_per_hwmod,
5471 .slave = &omap54xx_uart2_hwmod,
5472 .clk = "l4_root_clk_div",
5473 .addr = omap54xx_uart2_addrs,
5474 .user = OCP_USER_MPU | OCP_USER_SDMA,
5475 };
5477 static struct omap_hwmod_addr_space omap54xx_uart3_addrs[] = {
5478 {
5479 .pa_start = 0x48020000,
5480 .pa_end = 0x480200ff,
5481 .flags = ADDR_TYPE_RT
5482 },
5483 { }
5484 };
5486 /* l4_per -> uart3 */
5487 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
5488 .master = &omap54xx_l4_per_hwmod,
5489 .slave = &omap54xx_uart3_hwmod,
5490 .clk = "l4_root_clk_div",
5491 .addr = omap54xx_uart3_addrs,
5492 .user = OCP_USER_MPU | OCP_USER_SDMA,
5493 };
5495 static struct omap_hwmod_addr_space omap54xx_uart4_addrs[] = {
5496 {
5497 .pa_start = 0x4806e000,
5498 .pa_end = 0x4806e0ff,
5499 .flags = ADDR_TYPE_RT
5500 },
5501 { }
5502 };
5504 /* l4_per -> uart4 */
5505 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
5506 .master = &omap54xx_l4_per_hwmod,
5507 .slave = &omap54xx_uart4_hwmod,
5508 .clk = "l4_root_clk_div",
5509 .addr = omap54xx_uart4_addrs,
5510 .user = OCP_USER_MPU | OCP_USER_SDMA,
5511 };
5513 static struct omap_hwmod_addr_space omap54xx_uart5_addrs[] = {
5514 {
5515 .pa_start = 0x48066000,
5516 .pa_end = 0x480660ff,
5517 .flags = ADDR_TYPE_RT
5518 },
5519 { }
5520 };
5522 /* l4_per -> uart5 */
5523 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
5524 .master = &omap54xx_l4_per_hwmod,
5525 .slave = &omap54xx_uart5_hwmod,
5526 .clk = "l4_root_clk_div",
5527 .addr = omap54xx_uart5_addrs,
5528 .user = OCP_USER_MPU | OCP_USER_SDMA,
5529 };
5531 static struct omap_hwmod_addr_space omap54xx_uart6_addrs[] = {
5532 {
5533 .pa_start = 0x48068000,
5534 .pa_end = 0x480680ff,
5535 .flags = ADDR_TYPE_RT
5536 },
5537 { }
5538 };
5540 /* l4_per -> uart6 */
5541 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
5542 .master = &omap54xx_l4_per_hwmod,
5543 .slave = &omap54xx_uart6_hwmod,
5544 .clk = "l4_root_clk_div",
5545 .addr = omap54xx_uart6_addrs,
5546 .user = OCP_USER_MPU | OCP_USER_SDMA,
5547 };
5549 static struct omap_hwmod_addr_space omap54xx_usb_host_hs_addrs[] = {
5550 {
5551 .name = "uhh",
5552 .pa_start = 0x4a064000,
5553 .pa_end = 0x4a0647ff,
5554 .flags = ADDR_TYPE_RT
5555 },
5556 {
5557 .name = "ohci",
5558 .pa_start = 0x4a064800,
5559 .pa_end = 0x4a06487f,
5560 },
5561 {
5562 .name = "ehci",
5563 .pa_start = 0x4a064c00,
5564 .pa_end = 0x4a064cff,
5565 },
5566 { }
5567 };
5569 /* l4_cfg -> usb_host_hs */
5570 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
5571 .master = &omap54xx_l4_cfg_hwmod,
5572 .slave = &omap54xx_usb_host_hs_hwmod,
5573 .clk = "l3_iclk_div",
5574 .addr = omap54xx_usb_host_hs_addrs,
5575 .user = OCP_USER_MPU | OCP_USER_SDMA,
5576 };
5578 static struct omap_hwmod_addr_space omap54xx_usb_otg_ss_addrs[] = {
5579 {
5580 .name = "wrapper",
5581 .pa_start = 0x4a020000,
5582 .pa_end = 0x4a0201ff,
5583 .flags = ADDR_TYPE_RT
5584 },
5585 {
5586 .name = "dwc_usb3",
5587 .pa_start = 0x4a030000,
5588 .pa_end = 0x4a0300ff,
5589 },
5590 { }
5591 };
5593 /* l4_cfg -> usb_otg_ss */
5594 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
5595 .master = &omap54xx_l4_cfg_hwmod,
5596 .slave = &omap54xx_usb_otg_ss_hwmod,
5597 .clk = "dpll_core_h13x2_ck",
5598 .addr = omap54xx_usb_otg_ss_addrs,
5599 .user = OCP_USER_MPU | OCP_USER_SDMA,
5600 };
5602 static struct omap_hwmod_addr_space omap54xx_usb_tll_hs_addrs[] = {
5603 {
5604 .name = "tll",
5605 .pa_start = 0x4a062000,
5606 .pa_end = 0x4a062fff,
5607 .flags = ADDR_TYPE_RT
5608 },
5609 { }
5610 };
5612 /* l4_cfg -> usb_tll_hs */
5613 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
5614 .master = &omap54xx_l4_cfg_hwmod,
5615 .slave = &omap54xx_usb_tll_hs_hwmod,
5616 .clk = "l4_root_clk_div",
5617 .addr = omap54xx_usb_tll_hs_addrs,
5618 .user = OCP_USER_MPU | OCP_USER_SDMA,
5619 };
5621 static struct omap_hwmod_addr_space omap54xx_wd_timer2_addrs[] = {
5622 {
5623 .pa_start = 0x4ae14000,
5624 .pa_end = 0x4ae1407f,
5625 .flags = ADDR_TYPE_RT
5626 },
5627 { }
5628 };
5630 /* l4_wkup -> wd_timer2 */
5631 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
5632 .master = &omap54xx_l4_wkup_hwmod,
5633 .slave = &omap54xx_wd_timer2_hwmod,
5634 .clk = "wkupaon_iclk_mux",
5635 .addr = omap54xx_wd_timer2_addrs,
5636 .user = OCP_USER_MPU | OCP_USER_SDMA,
5637 };
5639 static struct omap_hwmod_addr_space omap54xx_wd_timer3_addrs[] = {
5640 {
5641 .name = "mpu",
5642 .pa_start = 0x40130000,
5643 .pa_end = 0x4013007f,
5644 .flags = ADDR_TYPE_RT
5645 },
5646 { }
5647 };
5649 /* l4_abe -> wd_timer3 */
5650 static struct omap_hwmod_ocp_if omap54xx_l4_abe__wd_timer3 = {
5651 .master = &omap54xx_l4_abe_hwmod,
5652 .slave = &omap54xx_wd_timer3_hwmod,
5653 .clk = "abe_iclk",
5654 .addr = omap54xx_wd_timer3_addrs,
5655 .user = OCP_USER_MPU,
5656 };
5658 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
5659 &omap54xx_l3_main_1__dmm,
5660 &omap54xx_dmm__emif_ocp_fw,
5661 &omap54xx_l4_cfg__emif_ocp_fw,
5662 &omap54xx_l3_main_3__l3_instr,
5663 &omap54xx_ocp_wp_noc__l3_instr,
5664 &omap54xx_l3_main_2__l3_main_1,
5665 &omap54xx_l4_cfg__l3_main_1,
5666 &omap54xx_mpu__l3_main_1,
5667 &omap54xx_l3_main_1__l3_main_2,
5668 &omap54xx_l4_cfg__l3_main_2,
5669 &omap54xx_l3_main_1__l3_main_3,
5670 &omap54xx_l3_main_2__l3_main_3,
5671 &omap54xx_l4_cfg__l3_main_3,
5672 &omap54xx_l3_main_1__l4_abe,
5673 &omap54xx_mpu__l4_abe,
5674 &omap54xx_l3_main_1__l4_cfg,
5675 &omap54xx_l3_main_2__l4_per,
5676 &omap54xx_l3_main_1__l4_wkup,
5677 &omap54xx_mpu__mpu_private,
5678 &omap54xx_l3_main_3__ocp_wp_noc,
5679 &omap54xx_l4_cfg__ocp_wp_noc,
5680 &omap54xx_l4_abe__aess,
5681 &omap54xx_l3_main_2__bb2d,
5682 &omap54xx_l3_main_2__c2c,
5683 &omap54xx_l4_wkup__counter_32k,
5684 &omap54xx_l4_cfg__ctrl_module_core,
5685 &omap54xx_l4_wkup__ctrl_module_wkup,
5686 &omap54xx_l4_cfg__dma_system,
5687 &omap54xx_l4_abe__dmic,
5688 &omap54xx_l4_cfg__dsp,
5689 &omap54xx_l3_main_2__dss,
5690 &omap54xx_l3_main_2__dss_dispc,
5691 &omap54xx_l3_main_2__dss_dsi1_a,
5692 &omap54xx_l3_main_2__dss_dsi1_b,
5693 &omap54xx_l3_main_2__dss_dsi1_c,
5694 &omap54xx_l3_main_2__dss_hdmi,
5695 &omap54xx_l3_main_2__dss_rfbi,
5696 &omap54xx_l4_per__elm,
5697 &omap54xx_emif_ocp_fw__emif1,
5698 &omap54xx_mpu__emif1,
5699 &omap54xx_emif_ocp_fw__emif2,
5700 &omap54xx_mpu__emif2,
5701 &omap54xx_l4_cfg__fdif,
5702 &omap54xx_l4_wkup__gpio1,
5703 &omap54xx_l4_per__gpio2,
5704 &omap54xx_l4_per__gpio3,
5705 &omap54xx_l4_per__gpio4,
5706 &omap54xx_l4_per__gpio5,
5707 &omap54xx_l4_per__gpio6,
5708 &omap54xx_l4_per__gpio7,
5709 &omap54xx_l4_per__gpio8,
5710 &omap54xx_l3_main_2__gpmc,
5711 &omap54xx_l3_main_2__gpu,
5712 &omap54xx_l4_per__hdq1w,
5713 &omap54xx_l4_cfg__hsi,
5714 &omap54xx_l4_per__i2c1,
5715 &omap54xx_l4_per__i2c2,
5716 &omap54xx_l4_per__i2c3,
5717 &omap54xx_l4_per__i2c4,
5718 &omap54xx_l4_per__i2c5,
5719 &omap54xx_l3_main_2__ipu,
5720 &omap54xx_l3_main_2__intc_ipu_c0,
5721 &omap54xx_l3_main_2__intc_ipu_c1,
5722 &omap54xx_l3_main_2__iss,
5723 &omap54xx_l3_main_2__iva,
5724 &omap54xx_l4_wkup__kbd,
5725 &omap54xx_l4_cfg__mailbox,
5726 &omap54xx_l4_abe__mcasp,
5727 &omap54xx_l4_abe__mcbsp1,
5728 &omap54xx_l4_abe__mcbsp2,
5729 &omap54xx_l4_abe__mcbsp3,
5730 &omap54xx_l4_abe__mcpdm,
5731 &omap54xx_l4_per__mcspi1,
5732 &omap54xx_l4_per__mcspi2,
5733 &omap54xx_l4_per__mcspi3,
5734 &omap54xx_l4_per__mcspi4,
5735 &omap54xx_l4_per__mmc1,
5736 &omap54xx_l4_per__mmc2,
5737 &omap54xx_l4_per__mmc3,
5738 &omap54xx_l4_per__mmc4,
5739 &omap54xx_l4_per__mmc5,
5740 &omap54xx_l4_cfg__mpu,
5741 &omap54xx_l3_main_2__ocmc_ram,
5742 &omap54xx_l4_cfg__ocp2scp1,
5743 &omap54xx_l4_cfg__ocp2scp3,
5744 &omap54xx_l4_cfg__sata,
5745 &omap54xx_l4_wkup__scrm,
5746 &omap54xx_l4_abe__slimbus1,
5747 &omap54xx_l4_cfg__smartreflex_core,
5748 &omap54xx_l4_cfg__smartreflex_mm,
5749 &omap54xx_l4_cfg__smartreflex_mpu,
5750 &omap54xx_l4_cfg__spinlock,
5751 &omap54xx_l4_wkup__timer1,
5752 &omap54xx_l4_per__timer2,
5753 &omap54xx_l4_per__timer3,
5754 &omap54xx_l4_per__timer4,
5755 &omap54xx_l4_abe__timer5,
5756 &omap54xx_l4_abe__timer6,
5757 &omap54xx_l4_abe__timer7,
5758 &omap54xx_l4_abe__timer8,
5759 &omap54xx_l4_per__timer9,
5760 &omap54xx_l4_per__timer10,
5761 &omap54xx_l4_per__timer11,
5762 &omap54xx_l4_per__uart1,
5763 &omap54xx_l4_per__uart2,
5764 &omap54xx_l4_per__uart3,
5765 &omap54xx_l4_per__uart4,
5766 &omap54xx_l4_per__uart5,
5767 &omap54xx_l4_per__uart6,
5768 &omap54xx_l4_cfg__usb_host_hs,
5769 &omap54xx_l4_cfg__usb_otg_ss,
5770 &omap54xx_l4_cfg__usb_tll_hs,
5771 &omap54xx_l4_wkup__wd_timer2,
5772 &omap54xx_l4_abe__wd_timer3,
5773 NULL,
5774 };
5776 int __init omap54xx_hwmod_init(void)
5777 {
5778 omap_hwmod_init();
5779 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
5780 }