arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP54xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/power/smartreflex.h>
  23 #include <linux/platform_data/omap_ocp2scp.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "cm1_54xx.h"
  34 #include "cm2_54xx.h"
  35 #include "prm54xx.h"
  36 #include "prm-regbits-54xx.h"
  37 #include "i2c.h"
  38 #include "mmc.h"
  39 #include "wd_timer.h"
  40
  41 /* Base offset for all OMAP5 interrupts external to MPUSS */
  42 #define OMAP54XX_IRQ_GIC_START  32
  43
  44 /* Base offset for all OMAP5 dma requests */
  45 #define OMAP54XX_DMA_REQ_START  1
  46
  47
  48 /*
  49  * IP blocks
  50  */
  51
  52 /*
  53  * 'dmm' class
  54  * instance(s): dmm
  55  */
  56 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
  57         .name   = "dmm",
  58 };
  59
  60 /* dmm */
  61 static struct omap_hwmod_irq_info omap54xx_dmm_irqs[] = {
  62         { .irq = 113 + OMAP54XX_IRQ_GIC_START },
  63         { .irq = -1 }
  64 };
  65
  66 static struct omap_hwmod omap54xx_dmm_hwmod = {
  67         .name           = "dmm",
  68         .class          = &omap54xx_dmm_hwmod_class,
  69         .clkdm_name     = "emif_clkdm",
  70         .mpu_irqs       = omap54xx_dmm_irqs,
  71         .prcm = {
  72                 .omap4 = {
  73                         .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  74                         .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  75                 },
  76         },
  77 };
  78
  79 /*
  80  * 'emif_ocp_fw' class
  81  * instance(s): emif_ocp_fw
  82  */
  83 static struct omap_hwmod_class omap54xx_emif_ocp_fw_hwmod_class = {
  84         .name   = "emif_ocp_fw",
  85 };
  86
  87 /* emif_ocp_fw */
  88 static struct omap_hwmod omap54xx_emif_ocp_fw_hwmod = {
  89         .name           = "emif_ocp_fw",
  90         .class          = &omap54xx_emif_ocp_fw_hwmod_class,
  91         .clkdm_name     = "emif_clkdm",
  92         .prcm = {
  93                 .omap4 = {
  94                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
  95                         .context_offs = OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
  96                 },
  97         },
  98 };
  99
 100 /*
 101  * 'l3' class
 102  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 103  */
 104 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
 105         .name   = "l3",
 106 };
 107
 108 /* l3_instr */
 109 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
 110         .name           = "l3_instr",
 111         .class          = &omap54xx_l3_hwmod_class,
 112         .clkdm_name     = "l3instr_clkdm",
 113         .prcm = {
 114                 .omap4 = {
 115                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 116                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 117                         .modulemode   = MODULEMODE_HWCTRL,
 118                 },
 119         },
 120 };
 121
 122 /* l3_main_1 */
 123 static struct omap_hwmod_irq_info omap54xx_l3_main_1_irqs[] = {
 124         { .name = "dbg_err", .irq = 9 + OMAP54XX_IRQ_GIC_START },
 125         { .name = "app_err", .irq = 10 + OMAP54XX_IRQ_GIC_START },
 126         { .name = "stat_alarm", .irq = 16 + OMAP54XX_IRQ_GIC_START },
 127         { .irq = -1 }
 128 };
 129
 130 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
 131         .name           = "l3_main_1",
 132         .class          = &omap54xx_l3_hwmod_class,
 133         .clkdm_name     = "l3main1_clkdm",
 134         .mpu_irqs       = omap54xx_l3_main_1_irqs,
 135         .prcm = {
 136                 .omap4 = {
 137                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
 138                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
 139                 },
 140         },
 141 };
 142
 143 /* l3_main_2 */
 144 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
 145         .name           = "l3_main_2",
 146         .class          = &omap54xx_l3_hwmod_class,
 147         .clkdm_name     = "l3main2_clkdm",
 148         .prcm = {
 149                 .omap4 = {
 150                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
 151                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
 152                 },
 153         },
 154 };
 155
 156 /* l3_main_3 */
 157 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
 158         .name           = "l3_main_3",
 159         .class          = &omap54xx_l3_hwmod_class,
 160         .clkdm_name     = "l3instr_clkdm",
 161         .prcm = {
 162                 .omap4 = {
 163                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
 164                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
 165                         .modulemode   = MODULEMODE_HWCTRL,
 166                 },
 167         },
 168 };
 169
 170 /*
 171  * 'l4' class
 172  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 173  */
 174 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 175         .name   = "l4",
 176 };
 177
 178 /* l4_abe */
 179 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
 180         .name           = "l4_abe",
 181         .class          = &omap54xx_l4_hwmod_class,
 182         .clkdm_name     = "abe_clkdm",
 183         .prcm = {
 184                 .omap4 = {
 185                         .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
 186                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 187                 },
 188         },
 189 };
 190
 191 /* l4_cfg */
 192 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 193         .name           = "l4_cfg",
 194         .class          = &omap54xx_l4_hwmod_class,
 195         .clkdm_name     = "l4cfg_clkdm",
 196         .prcm = {
 197                 .omap4 = {
 198                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 199                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 200                 },
 201         },
 202 };
 203
 204 /* l4_per */
 205 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 206         .name           = "l4_per",
 207         .class          = &omap54xx_l4_hwmod_class,
 208         .clkdm_name     = "l4per_clkdm",
 209         .prcm = {
 210                 .omap4 = {
 211                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 212                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 213                 },
 214         },
 215 };
 216
 217 /* l4_wkup */
 218 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 219         .name           = "l4_wkup",
 220         .class          = &omap54xx_l4_hwmod_class,
 221         .clkdm_name     = "wkupaon_clkdm",
 222         .prcm = {
 223                 .omap4 = {
 224                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 225                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 226                 },
 227         },
 228 };
 229
 230 /*
 231  * 'mpu_bus' class
 232  * instance(s): mpu_private
 233  */
 234 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
 235         .name   = "mpu_bus",
 236 };
 237
 238 /* mpu_private */
 239 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
 240         .name           = "mpu_private",
 241         .class          = &omap54xx_mpu_bus_hwmod_class,
 242         .clkdm_name     = "mpu_clkdm",
 243         .prcm = {
 244                 .omap4 = {
 245                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 246                 },
 247         },
 248 };
 249
 250 /*
 251  * 'ocp_wp_noc' class
 252  * instance(s): ocp_wp_noc
 253  */
 254 static struct omap_hwmod_class omap54xx_ocp_wp_noc_hwmod_class = {
 255         .name   = "ocp_wp_noc",
 256 };
 257
 258 /* ocp_wp_noc */
 259 static struct omap_hwmod omap54xx_ocp_wp_noc_hwmod = {
 260         .name           = "ocp_wp_noc",
 261         .class          = &omap54xx_ocp_wp_noc_hwmod_class,
 262         .clkdm_name     = "l3instr_clkdm",
 263         .prcm = {
 264                 .omap4 = {
 265                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET,
 266                         .context_offs = OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET,
 267                         .modulemode   = MODULEMODE_HWCTRL,
 268                 },
 269         },
 270 };
 271
 272 /*
 273  * 'aess' class
 274  * audio engine sub system
 275  */
 276
 277 static struct omap_hwmod_class_sysconfig omap54xx_aess_sysc = {
 278         .rev_offs       = 0x0000,
 279         .sysc_offs      = 0x0010,
 280         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 281         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 282                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 283                            MSTANDBY_SMART_WKUP),
 284         .sysc_fields    = &omap_hwmod_sysc_type2,
 285 };
 286
 287 static struct omap_hwmod_class omap54xx_aess_hwmod_class = {
 288         .name   = "aess",
 289         .sysc   = &omap54xx_aess_sysc,
 290 };
 291
 292 /* aess */
 293 static struct omap_hwmod_irq_info omap54xx_aess_irqs[] = {
 294         { .irq = 99 + OMAP54XX_IRQ_GIC_START },
 295         { .irq = -1 }
 296 };
 297
 298 static struct omap_hwmod_dma_info omap54xx_aess_sdma_reqs[] = {
 299         { .name = "fifo0", .dma_req = 100 + OMAP54XX_DMA_REQ_START },
 300         { .name = "fifo1", .dma_req = 101 + OMAP54XX_DMA_REQ_START },
 301         { .name = "fifo2", .dma_req = 102 + OMAP54XX_DMA_REQ_START },
 302         { .name = "fifo3", .dma_req = 103 + OMAP54XX_DMA_REQ_START },
 303         { .name = "fifo4", .dma_req = 104 + OMAP54XX_DMA_REQ_START },
 304         { .name = "fifo5", .dma_req = 105 + OMAP54XX_DMA_REQ_START },
 305         { .name = "fifo6", .dma_req = 106 + OMAP54XX_DMA_REQ_START },
 306         { .name = "fifo7", .dma_req = 107 + OMAP54XX_DMA_REQ_START },
 307         { .dma_req = -1 }
 308 };
 309
 310 static struct omap_hwmod omap54xx_aess_hwmod = {
 311         .name           = "aess",
 312         .class          = &omap54xx_aess_hwmod_class,
 313         .clkdm_name     = "abe_clkdm",
 314         .mpu_irqs       = omap54xx_aess_irqs,
 315         .sdma_reqs      = omap54xx_aess_sdma_reqs,
 316         .main_clk       = "aess_fclk",
 317         .prcm = {
 318                 .omap4 = {
 319                         .clkctrl_offs = OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET,
 320                         .context_offs = OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET,
 321                         .modulemode   = MODULEMODE_SWCTRL,
 322                 },
 323         },
 324 };
 325
 326 /*
 327  * 'bb2d' class
 328  * bit blit 2d accelerator
 329  */
 330
 331 static struct omap_hwmod_class omap54xx_bb2d_hwmod_class = {
 332         .name   = "bb2d",
 333 };
 334
 335 /* bb2d */
 336 static struct omap_hwmod_irq_info omap54xx_bb2d_irqs[] = {
 337         { .irq = 125 + OMAP54XX_IRQ_GIC_START },
 338         { .irq = -1 }
 339 };
 340
 341 static struct omap_hwmod omap54xx_bb2d_hwmod = {
 342         .name           = "bb2d",
 343         .class          = &omap54xx_bb2d_hwmod_class,
 344         .clkdm_name     = "dss_clkdm",
 345         .mpu_irqs       = omap54xx_bb2d_irqs,
 346         .main_clk       = "dpll_core_h24x2_ck",
 347         .prcm = {
 348                 .omap4 = {
 349                         .clkctrl_offs = OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 350                         .context_offs = OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 351                         .modulemode   = MODULEMODE_SWCTRL,
 352                 },
 353         },
 354 };
 355
 356 /*
 357  * 'c2c' class
 358  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 359  * soc
 360  */
 361
 362 static struct omap_hwmod_class_sysconfig omap54xx_c2c_sysc = {
 363         .rev_offs       = 0x0000,
 364         .syss_offs      = 0x0008,
 365         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 366 };
 367
 368 static struct omap_hwmod_class omap54xx_c2c_hwmod_class = {
 369         .name   = "c2c",
 370         .sysc   = &omap54xx_c2c_sysc,
 371 };
 372
 373 /* c2c */
 374 static struct omap_hwmod_irq_info omap54xx_c2c_irqs[] = {
 375         { .irq = 88 + OMAP54XX_IRQ_GIC_START },
 376         { .irq = -1 }
 377 };
 378
 379 static struct omap_hwmod_dma_info omap54xx_c2c_sdma_reqs[] = {
 380         { .dma_req = 68 + OMAP54XX_DMA_REQ_START },
 381         { .dma_req = -1 }
 382 };
 383
 384 static struct omap_hwmod omap54xx_c2c_hwmod = {
 385         .name           = "c2c",
 386         .class          = &omap54xx_c2c_hwmod_class,
 387         .clkdm_name     = "c2c_clkdm",
 388         .mpu_irqs       = omap54xx_c2c_irqs,
 389         .sdma_reqs      = omap54xx_c2c_sdma_reqs,
 390         .main_clk       = "c2c_fclk",
 391         .prcm = {
 392                 .omap4 = {
 393                         .clkctrl_offs = OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET,
 394                         .context_offs = OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET,
 395                 },
 396         },
 397 };
 398
 399 /*
 400  * 'counter' class
 401  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 402  */
 403
 404 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
 405         .rev_offs       = 0x0000,
 406         .sysc_offs      = 0x0010,
 407         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 408         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 409         .sysc_fields    = &omap_hwmod_sysc_type1,
 410 };
 411
 412 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
 413         .name   = "counter",
 414         .sysc   = &omap54xx_counter_sysc,
 415 };
 416
 417 /* counter_32k */
 418 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
 419         .name           = "counter_32k",
 420         .class          = &omap54xx_counter_hwmod_class,
 421         .clkdm_name     = "wkupaon_clkdm",
 422         .flags          = HWMOD_SWSUP_SIDLE,
 423         .main_clk       = "wkupaon_iclk_mux",
 424         .prcm = {
 425                 .omap4 = {
 426                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 427                         .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 428                 },
 429         },
 430 };
 431
 432 /*
 433  * 'ctrl_module' class
 434  * omap5430 core control module + omap5430 wkup control module
 435  */
 436
 437 static struct omap_hwmod_class_sysconfig omap54xx_ctrl_module_sysc = {
 438         .rev_offs       = 0x0000,
 439 };
 440
 441 static struct omap_hwmod_class omap54xx_ctrl_module_hwmod_class = {
 442         .name   = "ctrl_module",
 443         .sysc   = &omap54xx_ctrl_module_sysc,
 444 };
 445
 446 /* ctrl_module_core */
 447 static struct omap_hwmod_irq_info omap54xx_ctrl_module_core_irqs[] = {
 448         { .name = "sec_evts", .irq = 8 + OMAP54XX_IRQ_GIC_START },
 449         { .name = "thermal_alert", .irq = 126 + OMAP54XX_IRQ_GIC_START },
 450         { .irq = -1 }
 451 };
 452
 453 static struct omap_hwmod omap54xx_ctrl_module_core_hwmod = {
 454         .name           = "ctrl_module_core",
 455         .class          = &omap54xx_ctrl_module_hwmod_class,
 456         .clkdm_name     = "l4cfg_clkdm",
 457         .mpu_irqs       = omap54xx_ctrl_module_core_irqs,
 458         .prcm = {
 459                 .omap4 = {
 460                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 461                 },
 462         },
 463 };
 464
 465 /* ctrl_module_wkup */
 466 static struct omap_hwmod omap54xx_ctrl_module_wkup_hwmod = {
 467         .name           = "ctrl_module_wkup",
 468         .class          = &omap54xx_ctrl_module_hwmod_class,
 469         .clkdm_name     = "wkupaon_clkdm",
 470         .prcm = {
 471                 .omap4 = {
 472                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 473                 },
 474         },
 475 };
 476
 477 /*
 478  * 'dma' class
 479  * dma controller for data exchange between memory to memory (i.e. internal or
 480  * external memory) and gp peripherals to memory or memory to gp peripherals
 481  */
 482
 483 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
 484         .rev_offs       = 0x0000,
 485         .sysc_offs      = 0x002c,
 486         .syss_offs      = 0x0028,
 487         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 488                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 489                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 490                            SYSS_HAS_RESET_STATUS),
 491         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 492                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 493         .sysc_fields    = &omap_hwmod_sysc_type1,
 494 };
 495
 496 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
 497         .name   = "dma",
 498         .sysc   = &omap54xx_dma_sysc,
 499 };
 500
 501 /* dma dev_attr */
 502 static struct omap_dma_dev_attr dma_dev_attr = {
 503         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 504                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 505         .lch_count      = 32,
 506 };
 507
 508 /* dma_system */
 509 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
 510         { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
 511         { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
 512         { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
 513         { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
 514         { .irq = -1 }
 515 };
 516
 517 static struct omap_hwmod omap54xx_dma_system_hwmod = {
 518         .name           = "dma_system",
 519         .class          = &omap54xx_dma_hwmod_class,
 520         .clkdm_name     = "dma_clkdm",
 521         .mpu_irqs       = omap54xx_dma_system_irqs,
 522         .main_clk       = "l3_iclk_div",
 523         .prcm = {
 524                 .omap4 = {
 525                         .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 526                         .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 527                 },
 528         },
 529         .dev_attr       = &dma_dev_attr,
 530 };
 531
 532 /*
 533  * 'dmic' class
 534  * digital microphone controller
 535  */
 536
 537 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
 538         .rev_offs       = 0x0000,
 539         .sysc_offs      = 0x0010,
 540         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 541                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 542         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 543                            SIDLE_SMART_WKUP),
 544         .sysc_fields    = &omap_hwmod_sysc_type2,
 545 };
 546
 547 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
 548         .name   = "dmic",
 549         .sysc   = &omap54xx_dmic_sysc,
 550 };
 551
 552 /* dmic */
 553 static struct omap_hwmod_irq_info omap54xx_dmic_irqs[] = {
 554         { .irq = 114 + OMAP54XX_IRQ_GIC_START },
 555         { .irq = -1 }
 556 };
 557
 558 static struct omap_hwmod_dma_info omap54xx_dmic_sdma_reqs[] = {
 559         { .dma_req = 66 + OMAP54XX_DMA_REQ_START },
 560         { .dma_req = -1 }
 561 };
 562
 563 static struct omap_hwmod omap54xx_dmic_hwmod = {
 564         .name           = "dmic",
 565         .class          = &omap54xx_dmic_hwmod_class,
 566         .clkdm_name     = "abe_clkdm",
 567         .mpu_irqs       = omap54xx_dmic_irqs,
 568         .sdma_reqs      = omap54xx_dmic_sdma_reqs,
 569         .main_clk       = "dmic_gfclk",
 570         .prcm = {
 571                 .omap4 = {
 572                         .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
 573                         .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
 574                         .modulemode   = MODULEMODE_SWCTRL,
 575                 },
 576         },
 577 };
 578
 579 /*
 580  * 'dsp' class
 581  * dsp sub-system
 582  */
 583
 584 static struct omap_hwmod_class omap54xx_dsp_hwmod_class = {
 585         .name   = "dsp",
 586 };
 587
 588 /* dsp */
 589 static struct omap_hwmod_irq_info omap54xx_dsp_irqs[] = {
 590         { .irq = 28 + OMAP54XX_IRQ_GIC_START },
 591         { .irq = -1 }
 592 };
 593
 594 static struct omap_hwmod_rst_info omap54xx_dsp_resets[] = {
 595         { .name = "dsp", .rst_shift = 0 },
 596         { .name = "mmu_cache", .rst_shift = 1 },
 597 };
 598
 599 static struct omap_hwmod omap54xx_dsp_hwmod = {
 600         .name           = "dsp",
 601         .class          = &omap54xx_dsp_hwmod_class,
 602         .clkdm_name     = "dsp_clkdm",
 603         .mpu_irqs       = omap54xx_dsp_irqs,
 604         .rst_lines      = omap54xx_dsp_resets,
 605         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_dsp_resets),
 606         .main_clk       = "dpll_iva_h11x2_ck",
 607         .prcm = {
 608                 .omap4 = {
 609                         .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
 610                         .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
 611                         .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
 612                         .modulemode   = MODULEMODE_HWCTRL,
 613                 },
 614         },
 615 };
 616
 617 /*
 618  * 'dss' class
 619  * display sub-system
 620  */
 621
 622 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
 623         .rev_offs       = 0x0000,
 624         .syss_offs      = 0x0014,
 625         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 626 };
 627
 628 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
 629         .name   = "dss",
 630         .sysc   = &omap54xx_dss_sysc,
 631         .reset  = omap_dss_reset,
 632 };
 633
 634 /* dss */
 635 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 636         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 637         { .role = "sys_clk", .clk = "dss_sys_clk" },
 638         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 639 };
 640
 641 static struct omap_hwmod omap54xx_dss_hwmod = {
 642         .name           = "dss_core",
 643         .class          = &omap54xx_dss_hwmod_class,
 644         .clkdm_name     = "dss_clkdm",
 645         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 646         .main_clk       = "dss_dss_clk",
 647         .prcm = {
 648                 .omap4 = {
 649                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 650                         .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
 651                         .modulemode   = MODULEMODE_SWCTRL,
 652                 },
 653         },
 654         .opt_clks       = dss_opt_clks,
 655         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 656 };
 657
 658 /*
 659  * 'dispc' class
 660  * display controller
 661  */
 662
 663 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
 664         .rev_offs       = 0x0000,
 665         .sysc_offs      = 0x0010,
 666         .syss_offs      = 0x0014,
 667         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 668                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 669                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 670                            SYSS_HAS_RESET_STATUS),
 671         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 672                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 673         .sysc_fields    = &omap_hwmod_sysc_type1,
 674 };
 675
 676 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
 677         .name   = "dispc",
 678         .sysc   = &omap54xx_dispc_sysc,
 679 };
 680
 681 /* dss_dispc */
 682 static struct omap_hwmod_irq_info omap54xx_dss_dispc_irqs[] = {
 683         { .irq = 25 + OMAP54XX_IRQ_GIC_START },
 684         { .irq = -1 }
 685 };
 686
 687 static struct omap_hwmod_dma_info omap54xx_dss_dispc_sdma_reqs[] = {
 688         { .dma_req = 5 + OMAP54XX_DMA_REQ_START },
 689         { .dma_req = -1 }
 690 };
 691
 692 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
 693         { .role = "sys_clk", .clk = "dss_sys_clk" },
 694 };
 695
 696 /* dss_dispc dev_attr */
 697 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 698         .has_framedonetv_irq    = 1,
 699         .manager_count          = 4,
 700 };
 701
 702 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
 703         .name           = "dss_dispc",
 704         .class          = &omap54xx_dispc_hwmod_class,
 705         .clkdm_name     = "dss_clkdm",
 706         .mpu_irqs       = omap54xx_dss_dispc_irqs,
 707         .sdma_reqs      = omap54xx_dss_dispc_sdma_reqs,
 708         .main_clk       = "dss_dss_clk",
 709         .prcm = {
 710                 .omap4 = {
 711                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 712                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 713                 },
 714         },
 715         .opt_clks       = dss_dispc_opt_clks,
 716         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
 717         .dev_attr       = &dss_dispc_dev_attr,
 718 };
 719
 720 /*
 721  * 'dsi1' class
 722  * display serial interface controller
 723  */
 724
 725 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
 726         .rev_offs       = 0x0000,
 727         .sysc_offs      = 0x0010,
 728         .syss_offs      = 0x0014,
 729         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 730                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 731                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 732         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 733         .sysc_fields    = &omap_hwmod_sysc_type1,
 734 };
 735
 736 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
 737         .name   = "dsi1",
 738         .sysc   = &omap54xx_dsi1_sysc,
 739 };
 740
 741 /* dss_dsi1_a */
 742 static struct omap_hwmod_irq_info omap54xx_dss_dsi1_a_irqs[] = {
 743         { .irq = 53 + OMAP54XX_IRQ_GIC_START },
 744         { .irq = -1 }
 745 };
 746
 747 static struct omap_hwmod_dma_info omap54xx_dss_dsi1_a_sdma_reqs[] = {
 748         { .dma_req = 74 + OMAP54XX_DMA_REQ_START },
 749         { .dma_req = -1 }
 750 };
 751
 752 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
 753         { .role = "sys_clk", .clk = "dss_sys_clk" },
 754 };
 755
 756 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
 757         .name           = "dss_dsi1_a",
 758         .class          = &omap54xx_dsi1_hwmod_class,
 759         .clkdm_name     = "dss_clkdm",
 760         .mpu_irqs       = omap54xx_dss_dsi1_a_irqs,
 761         .sdma_reqs      = omap54xx_dss_dsi1_a_sdma_reqs,
 762         .main_clk       = "dss_dss_clk",
 763         .prcm = {
 764                 .omap4 = {
 765                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 766                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 767                 },
 768         },
 769         .opt_clks       = dss_dsi1_a_opt_clks,
 770         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_a_opt_clks),
 771 };
 772
 773 /* dss_dsi1_b */
 774 static struct omap_hwmod omap54xx_dss_dsi1_b_hwmod = {
 775         .name           = "dss_dsi1_b",
 776         .class          = &omap54xx_dsi1_hwmod_class,
 777         .clkdm_name     = "dss_clkdm",
 778         .main_clk       = "dss_dss_clk",
 779         .prcm = {
 780                 .omap4 = {
 781                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 782                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 783                 },
 784         },
 785 };
 786
 787 /* dss_dsi1_c */
 788 static struct omap_hwmod_irq_info omap54xx_dss_dsi1_c_irqs[] = {
 789         { .irq = 55 + OMAP54XX_IRQ_GIC_START },
 790         { .irq = -1 }
 791 };
 792
 793 static struct omap_hwmod_dma_info omap54xx_dss_dsi1_c_sdma_reqs[] = {
 794         { .dma_req = 83 + OMAP54XX_DMA_REQ_START },
 795         { .dma_req = -1 }
 796 };
 797
 798 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
 799         { .role = "sys_clk", .clk = "dss_sys_clk" },
 800 };
 801
 802 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
 803         .name           = "dss_dsi1_c",
 804         .class          = &omap54xx_dsi1_hwmod_class,
 805         .clkdm_name     = "dss_clkdm",
 806         .mpu_irqs       = omap54xx_dss_dsi1_c_irqs,
 807         .sdma_reqs      = omap54xx_dss_dsi1_c_sdma_reqs,
 808         .main_clk       = "dss_dss_clk",
 809         .prcm = {
 810                 .omap4 = {
 811                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 812                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 813                 },
 814         },
 815         .opt_clks       = dss_dsi1_c_opt_clks,
 816         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_c_opt_clks),
 817 };
 818
 819 /*
 820  * 'hdmi' class
 821  * hdmi controller
 822  */
 823
 824 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
 825         .rev_offs       = 0x0000,
 826         .sysc_offs      = 0x0010,
 827         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 828                            SYSC_HAS_SOFTRESET),
 829         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 830                            SIDLE_SMART_WKUP),
 831         .sysc_fields    = &omap_hwmod_sysc_type2,
 832 };
 833
 834 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
 835         .name   = "hdmi",
 836         .sysc   = &omap54xx_hdmi_sysc,
 837 };
 838
 839 /* dss_hdmi */
 840 static struct omap_hwmod_irq_info omap54xx_dss_hdmi_irqs[] = {
 841         { .irq = 101 + OMAP54XX_IRQ_GIC_START },
 842         { .irq = -1 }
 843 };
 844
 845 static struct omap_hwmod_dma_info omap54xx_dss_hdmi_sdma_reqs[] = {
 846         { .dma_req = 75 + OMAP54XX_DMA_REQ_START },
 847         { .dma_req = -1 }
 848 };
 849
 850 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 851         { .role = "sys_clk", .clk = "dss_sys_clk" },
 852 };
 853
 854 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
 855         .name           = "dss_hdmi",
 856         .class          = &omap54xx_hdmi_hwmod_class,
 857         .clkdm_name     = "dss_clkdm",
 858         .mpu_irqs       = omap54xx_dss_hdmi_irqs,
 859         .sdma_reqs      = omap54xx_dss_hdmi_sdma_reqs,
 860         .main_clk       = "dss_48mhz_clk",
 861         .prcm = {
 862                 .omap4 = {
 863                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 864                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 865                 },
 866         },
 867         .opt_clks       = dss_hdmi_opt_clks,
 868         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 869 };
 870
 871 /*
 872  * 'rfbi' class
 873  * remote frame buffer interface
 874  */
 875
 876 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
 877         .rev_offs       = 0x0000,
 878         .sysc_offs      = 0x0010,
 879         .syss_offs      = 0x0014,
 880         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 881                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 882         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 883         .sysc_fields    = &omap_hwmod_sysc_type1,
 884 };
 885
 886 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
 887         .name   = "rfbi",
 888         .sysc   = &omap54xx_rfbi_sysc,
 889 };
 890
 891 /* dss_rfbi */
 892 static struct omap_hwmod_dma_info omap54xx_dss_rfbi_sdma_reqs[] = {
 893         { .dma_req = 13 + OMAP54XX_DMA_REQ_START },
 894         { .dma_req = -1 }
 895 };
 896
 897 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 898         { .role = "ick", .clk = "l3_iclk_div" },
 899 };
 900
 901 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
 902         .name           = "dss_rfbi",
 903         .class          = &omap54xx_rfbi_hwmod_class,
 904         .clkdm_name     = "dss_clkdm",
 905         .sdma_reqs      = omap54xx_dss_rfbi_sdma_reqs,
 906         .prcm = {
 907                 .omap4 = {
 908                         .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 909                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 910                 },
 911         },
 912         .opt_clks       = dss_rfbi_opt_clks,
 913         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 914 };
 915
 916 /*
 917  * 'elm' class
 918  * bch error location module
 919  */
 920
 921 static struct omap_hwmod_class_sysconfig omap54xx_elm_sysc = {
 922         .rev_offs       = 0x0000,
 923         .sysc_offs      = 0x0010,
 924         .syss_offs      = 0x0014,
 925         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 926                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 927                            SYSS_HAS_RESET_STATUS),
 928         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 929         .sysc_fields    = &omap_hwmod_sysc_type1,
 930 };
 931
 932 static struct omap_hwmod_class omap54xx_elm_hwmod_class = {
 933         .name   = "elm",
 934         .sysc   = &omap54xx_elm_sysc,
 935 };
 936
 937 /* elm */
 938 static struct omap_hwmod_irq_info omap54xx_elm_irqs[] = {
 939         { .irq = 4 + OMAP54XX_IRQ_GIC_START },
 940         { .irq = -1 }
 941 };
 942
 943 static struct omap_hwmod omap54xx_elm_hwmod = {
 944         .name           = "elm",
 945         .class          = &omap54xx_elm_hwmod_class,
 946         .clkdm_name     = "l4per_clkdm",
 947         .mpu_irqs       = omap54xx_elm_irqs,
 948         .main_clk       = "l4_root_clk_div",
 949         .prcm = {
 950                 .omap4 = {
 951                         .clkctrl_offs = OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 952                         .context_offs = OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 953                 },
 954         },
 955 };
 956
 957 /*
 958  * 'emif' class
 959  * external memory interface no1 (wrapper)
 960  */
 961
 962 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
 963         .rev_offs       = 0x0000,
 964 };
 965
 966 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
 967         .name   = "emif",
 968         .sysc   = &omap54xx_emif_sysc,
 969 };
 970
 971 /* emif1 */
 972 static struct omap_hwmod_irq_info omap54xx_emif1_irqs[] = {
 973         { .irq = 110 + OMAP54XX_IRQ_GIC_START },
 974         { .irq = -1 }
 975 };
 976
 977 static struct omap_hwmod omap54xx_emif1_hwmod = {
 978         .name           = "emif1",
 979         .class          = &omap54xx_emif_hwmod_class,
 980         .clkdm_name     = "emif_clkdm",
 981         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 982         .mpu_irqs       = omap54xx_emif1_irqs,
 983         .main_clk       = "dpll_core_h11x2_ck",
 984         .prcm = {
 985                 .omap4 = {
 986                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
 987                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
 988                         .modulemode   = MODULEMODE_HWCTRL,
 989                 },
 990         },
 991 };
 992
 993 /* emif2 */
 994 static struct omap_hwmod_irq_info omap54xx_emif2_irqs[] = {
 995         { .irq = 111 + OMAP54XX_IRQ_GIC_START },
 996         { .irq = -1 }
 997 };
 998
 999 static struct omap_hwmod omap54xx_emif2_hwmod = {
1000         .name           = "emif2",
1001         .class          = &omap54xx_emif_hwmod_class,
1002         .clkdm_name     = "emif_clkdm",
1003         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1004         .mpu_irqs       = omap54xx_emif2_irqs,
1005         .main_clk       = "dpll_core_h11x2_ck",
1006         .prcm = {
1007                 .omap4 = {
1008                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
1009                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
1010                         .modulemode   = MODULEMODE_HWCTRL,
1011                 },
1012         },
1013 };
1014
1015 /*
1016  * 'fdif' class
1017  * face detection hw accelerator module
1018  */
1019
1020 static struct omap_hwmod_class_sysconfig omap54xx_fdif_sysc = {
1021         .rev_offs       = 0x0000,
1022         .sysc_offs      = 0x0010,
1023         /*
1024          * FDIF needs 100 OCP clk cycles delay after a softreset before
1025          * accessing sysconfig again.
1026          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1027          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1028          *
1029          * TODO: Indicate errata when available.
1030          */
1031         .srst_udelay    = 2,
1032         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1033                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1034         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1035                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1036         .sysc_fields    = &omap_hwmod_sysc_type2,
1037 };
1038
1039 static struct omap_hwmod_class omap54xx_fdif_hwmod_class = {
1040         .name   = "fdif",
1041         .sysc   = &omap54xx_fdif_sysc,
1042 };
1043
1044 /* fdif */
1045 static struct omap_hwmod_irq_info omap54xx_fdif_irqs[] = {
1046         { .irq = 69 + OMAP54XX_IRQ_GIC_START },
1047         { .irq = -1 }
1048 };
1049
1050 static struct omap_hwmod omap54xx_fdif_hwmod = {
1051         .name           = "fdif",
1052         .class          = &omap54xx_fdif_hwmod_class,
1053         .clkdm_name     = "cam_clkdm",
1054         .mpu_irqs       = omap54xx_fdif_irqs,
1055         .main_clk       = "fdif_fclk",
1056         .prcm = {
1057                 .omap4 = {
1058                         .clkctrl_offs = OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET,
1059                         .context_offs = OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET,
1060                         .modulemode   = MODULEMODE_SWCTRL,
1061                 },
1062         },
1063 };
1064
1065 /*
1066  * 'gpio' class
1067  * general purpose io module
1068  */
1069
1070 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
1071         .rev_offs       = 0x0000,
1072         .sysc_offs      = 0x0010,
1073         .syss_offs      = 0x0114,
1074         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1075                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1076                            SYSS_HAS_RESET_STATUS),
1077         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1078                            SIDLE_SMART_WKUP),
1079         .sysc_fields    = &omap_hwmod_sysc_type1,
1080 };
1081
1082 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
1083         .name   = "gpio",
1084         .sysc   = &omap54xx_gpio_sysc,
1085         .rev    = 2,
1086 };
1087
1088 /* gpio dev_attr */
1089 static struct omap_gpio_dev_attr gpio_dev_attr = {
1090         .bank_width     = 32,
1091         .dbck_flag      = true,
1092 };
1093
1094 /* gpio1 */
1095 static struct omap_hwmod_irq_info omap54xx_gpio1_irqs[] = {
1096         { .irq = 29 + OMAP54XX_IRQ_GIC_START },
1097         { .irq = -1 }
1098 };
1099
1100 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1101         { .role = "dbclk", .clk = "gpio1_dbclk" },
1102 };
1103
1104 static struct omap_hwmod omap54xx_gpio1_hwmod = {
1105         .name           = "gpio1",
1106         .class          = &omap54xx_gpio_hwmod_class,
1107         .clkdm_name     = "wkupaon_clkdm",
1108         .mpu_irqs       = omap54xx_gpio1_irqs,
1109         .main_clk       = "wkupaon_iclk_mux",
1110         .prcm = {
1111                 .omap4 = {
1112                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
1113                         .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
1114                         .modulemode   = MODULEMODE_HWCTRL,
1115                 },
1116         },
1117         .opt_clks       = gpio1_opt_clks,
1118         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1119         .dev_attr       = &gpio_dev_attr,
1120 };
1121
1122 /* gpio2 */
1123 static struct omap_hwmod_irq_info omap54xx_gpio2_irqs[] = {
1124         { .irq = 30 + OMAP54XX_IRQ_GIC_START },
1125         { .irq = -1 }
1126 };
1127
1128 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1129         { .role = "dbclk", .clk = "gpio2_dbclk" },
1130 };
1131
1132 static struct omap_hwmod omap54xx_gpio2_hwmod = {
1133         .name           = "gpio2",
1134         .class          = &omap54xx_gpio_hwmod_class,
1135         .clkdm_name     = "l4per_clkdm",
1136         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1137         .mpu_irqs       = omap54xx_gpio2_irqs,
1138         .main_clk       = "l4_root_clk_div",
1139         .prcm = {
1140                 .omap4 = {
1141                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1142                         .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1143                         .modulemode   = MODULEMODE_HWCTRL,
1144                 },
1145         },
1146         .opt_clks       = gpio2_opt_clks,
1147         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1148         .dev_attr       = &gpio_dev_attr,
1149 };
1150
1151 /* gpio3 */
1152 static struct omap_hwmod_irq_info omap54xx_gpio3_irqs[] = {
1153         { .irq = 31 + OMAP54XX_IRQ_GIC_START },
1154         { .irq = -1 }
1155 };
1156
1157 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1158         { .role = "dbclk", .clk = "gpio3_dbclk" },
1159 };
1160
1161 static struct omap_hwmod omap54xx_gpio3_hwmod = {
1162         .name           = "gpio3",
1163         .class          = &omap54xx_gpio_hwmod_class,
1164         .clkdm_name     = "l4per_clkdm",
1165         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1166         .mpu_irqs       = omap54xx_gpio3_irqs,
1167         .main_clk       = "l4_root_clk_div",
1168         .prcm = {
1169                 .omap4 = {
1170                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1171                         .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1172                         .modulemode   = MODULEMODE_HWCTRL,
1173                 },
1174         },
1175         .opt_clks       = gpio3_opt_clks,
1176         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1177         .dev_attr       = &gpio_dev_attr,
1178 };
1179
1180 /* gpio4 */
1181 static struct omap_hwmod_irq_info omap54xx_gpio4_irqs[] = {
1182         { .irq = 32 + OMAP54XX_IRQ_GIC_START },
1183         { .irq = -1 }
1184 };
1185
1186 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1187         { .role = "dbclk", .clk = "gpio4_dbclk" },
1188 };
1189
1190 static struct omap_hwmod omap54xx_gpio4_hwmod = {
1191         .name           = "gpio4",
1192         .class          = &omap54xx_gpio_hwmod_class,
1193         .clkdm_name     = "l4per_clkdm",
1194         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1195         .mpu_irqs       = omap54xx_gpio4_irqs,
1196         .main_clk       = "l4_root_clk_div",
1197         .prcm = {
1198                 .omap4 = {
1199                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1200                         .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1201                         .modulemode   = MODULEMODE_HWCTRL,
1202                 },
1203         },
1204         .opt_clks       = gpio4_opt_clks,
1205         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1206         .dev_attr       = &gpio_dev_attr,
1207 };
1208
1209 /* gpio5 */
1210 static struct omap_hwmod_irq_info omap54xx_gpio5_irqs[] = {
1211         { .irq = 33 + OMAP54XX_IRQ_GIC_START },
1212         { .irq = -1 }
1213 };
1214
1215 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1216         { .role = "dbclk", .clk = "gpio5_dbclk" },
1217 };
1218
1219 static struct omap_hwmod omap54xx_gpio5_hwmod = {
1220         .name           = "gpio5",
1221         .class          = &omap54xx_gpio_hwmod_class,
1222         .clkdm_name     = "l4per_clkdm",
1223         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1224         .mpu_irqs       = omap54xx_gpio5_irqs,
1225         .main_clk       = "l4_root_clk_div",
1226         .prcm = {
1227                 .omap4 = {
1228                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1229                         .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1230                         .modulemode   = MODULEMODE_HWCTRL,
1231                 },
1232         },
1233         .opt_clks       = gpio5_opt_clks,
1234         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1235         .dev_attr       = &gpio_dev_attr,
1236 };
1237
1238 /* gpio6 */
1239 static struct omap_hwmod_irq_info omap54xx_gpio6_irqs[] = {
1240         { .irq = 34 + OMAP54XX_IRQ_GIC_START },
1241         { .irq = -1 }
1242 };
1243
1244 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1245         { .role = "dbclk", .clk = "gpio6_dbclk" },
1246 };
1247
1248 static struct omap_hwmod omap54xx_gpio6_hwmod = {
1249         .name           = "gpio6",
1250         .class          = &omap54xx_gpio_hwmod_class,
1251         .clkdm_name     = "l4per_clkdm",
1252         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1253         .mpu_irqs       = omap54xx_gpio6_irqs,
1254         .main_clk       = "l4_root_clk_div",
1255         .prcm = {
1256                 .omap4 = {
1257                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1258                         .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1259                         .modulemode   = MODULEMODE_HWCTRL,
1260                 },
1261         },
1262         .opt_clks       = gpio6_opt_clks,
1263         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1264         .dev_attr       = &gpio_dev_attr,
1265 };
1266
1267 /* gpio7 */
1268 static struct omap_hwmod_irq_info omap54xx_gpio7_irqs[] = {
1269         { .irq = 35 + OMAP54XX_IRQ_GIC_START },
1270         { .irq = -1 }
1271 };
1272
1273 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
1274         { .role = "dbclk", .clk = "gpio7_dbclk" },
1275 };
1276
1277 static struct omap_hwmod omap54xx_gpio7_hwmod = {
1278         .name           = "gpio7",
1279         .class          = &omap54xx_gpio_hwmod_class,
1280         .clkdm_name     = "l4per_clkdm",
1281         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1282         .mpu_irqs       = omap54xx_gpio7_irqs,
1283         .main_clk       = "l4_root_clk_div",
1284         .prcm = {
1285                 .omap4 = {
1286                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
1287                         .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
1288                         .modulemode   = MODULEMODE_HWCTRL,
1289                 },
1290         },
1291         .opt_clks       = gpio7_opt_clks,
1292         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
1293         .dev_attr       = &gpio_dev_attr,
1294 };
1295
1296 /* gpio8 */
1297 static struct omap_hwmod_irq_info omap54xx_gpio8_irqs[] = {
1298         { .irq = 121 + OMAP54XX_IRQ_GIC_START },
1299         { .irq = -1 }
1300 };
1301
1302 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
1303         { .role = "dbclk", .clk = "gpio8_dbclk" },
1304 };
1305
1306 static struct omap_hwmod omap54xx_gpio8_hwmod = {
1307         .name           = "gpio8",
1308         .class          = &omap54xx_gpio_hwmod_class,
1309         .clkdm_name     = "l4per_clkdm",
1310         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1311         .mpu_irqs       = omap54xx_gpio8_irqs,
1312         .main_clk       = "l4_root_clk_div",
1313         .prcm = {
1314                 .omap4 = {
1315                         .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1316                         .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1317                         .modulemode   = MODULEMODE_HWCTRL,
1318                 },
1319         },
1320         .opt_clks       = gpio8_opt_clks,
1321         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
1322         .dev_attr       = &gpio_dev_attr,
1323 };
1324
1325 /*
1326  * 'gpmc' class
1327  * general purpose memory controller
1328  */
1329
1330 static struct omap_hwmod_class_sysconfig omap54xx_gpmc_sysc = {
1331         .rev_offs       = 0x0000,
1332         .sysc_offs      = 0x0010,
1333         .syss_offs      = 0x0014,
1334         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1335                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1336         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1337         .sysc_fields    = &omap_hwmod_sysc_type1,
1338 };
1339
1340 static struct omap_hwmod_class omap54xx_gpmc_hwmod_class = {
1341         .name   = "gpmc",
1342         .sysc   = &omap54xx_gpmc_sysc,
1343 };
1344
1345 /* gpmc */
1346 static struct omap_hwmod_irq_info omap54xx_gpmc_irqs[] = {
1347         { .irq = 20 + OMAP54XX_IRQ_GIC_START },
1348         { .irq = -1 }
1349 };
1350
1351 static struct omap_hwmod_dma_info omap54xx_gpmc_sdma_reqs[] = {
1352         { .dma_req = 3 + OMAP54XX_DMA_REQ_START },
1353         { .dma_req = -1 }
1354 };
1355
1356 static struct omap_hwmod omap54xx_gpmc_hwmod = {
1357         .name           = "gpmc",
1358         .class          = &omap54xx_gpmc_hwmod_class,
1359         .clkdm_name     = "l3main2_clkdm",
1360         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1361         .mpu_irqs       = omap54xx_gpmc_irqs,
1362         .sdma_reqs      = omap54xx_gpmc_sdma_reqs,
1363         .main_clk       = "l3_iclk_div",
1364         .prcm = {
1365                 .omap4 = {
1366                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET,
1367                         .context_offs = OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET,
1368                         .modulemode   = MODULEMODE_HWCTRL,
1369                 },
1370         },
1371 };
1372
1373 /*
1374  * 'gpu' class
1375  * 2d/3d graphics accelerator
1376  */
1377
1378 static struct omap_hwmod_class_sysconfig omap54xx_gpu_sysc = {
1379         .rev_offs       = 0x0000,
1380         .sysc_offs      = 0x0010,
1381         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1382         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1383                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1384                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1385         .sysc_fields    = &omap_hwmod_sysc_type2,
1386 };
1387
1388 static struct omap_hwmod_class omap54xx_gpu_hwmod_class = {
1389         .name   = "gpu",
1390         .sysc   = &omap54xx_gpu_sysc,
1391 };
1392
1393 /* gpu */
1394 static struct omap_hwmod_irq_info omap54xx_gpu_irqs[] = {
1395         { .irq = 21 + OMAP54XX_IRQ_GIC_START },
1396         { .irq = -1 }
1397 };
1398
1399 static struct omap_hwmod omap54xx_gpu_hwmod = {
1400         .name           = "gpu",
1401         .class          = &omap54xx_gpu_hwmod_class,
1402         .clkdm_name     = "gpu_clkdm",
1403         .mpu_irqs       = omap54xx_gpu_irqs,
1404         .main_clk       = "gpu_core_gclk_mux",
1405         .prcm = {
1406                 .omap4 = {
1407                         .clkctrl_offs = OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET,
1408                         .context_offs = OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET,
1409                         .modulemode   = MODULEMODE_SWCTRL,
1410                 },
1411         },
1412 };
1413
1414 /*
1415  * 'hdq1w' class
1416  * hdq / 1-wire serial interface controller
1417  */
1418
1419 static struct omap_hwmod_class_sysconfig omap54xx_hdq1w_sysc = {
1420         .rev_offs       = 0x0000,
1421         .sysc_offs      = 0x0014,
1422         .syss_offs      = 0x0018,
1423         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1424                            SYSS_HAS_RESET_STATUS),
1425         .sysc_fields    = &omap_hwmod_sysc_type1,
1426 };
1427
1428 static struct omap_hwmod_class omap54xx_hdq1w_hwmod_class = {
1429         .name   = "hdq1w",
1430         .sysc   = &omap54xx_hdq1w_sysc,
1431 };
1432
1433 /* hdq1w */
1434 static struct omap_hwmod_irq_info omap54xx_hdq1w_irqs[] = {
1435         { .irq = 58 + OMAP54XX_IRQ_GIC_START },
1436         { .irq = -1 }
1437 };
1438
1439 static struct omap_hwmod omap54xx_hdq1w_hwmod = {
1440         .name           = "hdq1w",
1441         .class          = &omap54xx_hdq1w_hwmod_class,
1442         .clkdm_name     = "l4per_clkdm",
1443         .flags          = HWMOD_INIT_NO_RESET,
1444         .mpu_irqs       = omap54xx_hdq1w_irqs,
1445         .main_clk       = "func_12m_fclk",
1446         .prcm = {
1447                 .omap4 = {
1448                         .clkctrl_offs = OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1449                         .context_offs = OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1450                         .modulemode   = MODULEMODE_SWCTRL,
1451                 },
1452         },
1453 };
1454
1455 /*
1456  * 'hsi' class
1457  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1458  * serial if)
1459  */
1460
1461 static struct omap_hwmod_class_sysconfig omap54xx_hsi_sysc = {
1462         .rev_offs       = 0x0000,
1463         .sysc_offs      = 0x0010,
1464         .syss_offs      = 0x0014,
1465         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1466                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1467                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1468         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1469                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1470                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1471         .sysc_fields    = &omap_hwmod_sysc_type1,
1472 };
1473
1474 static struct omap_hwmod_class omap54xx_hsi_hwmod_class = {
1475         .name   = "hsi",
1476         .sysc   = &omap54xx_hsi_sysc,
1477 };
1478
1479 /* hsi */
1480 static struct omap_hwmod_irq_info omap54xx_hsi_irqs[] = {
1481         { .name = "mpu_p1", .irq = 67 + OMAP54XX_IRQ_GIC_START },
1482         { .name = "mpu_p2", .irq = 68 + OMAP54XX_IRQ_GIC_START },
1483         { .name = "mpu_dma", .irq = 71 + OMAP54XX_IRQ_GIC_START },
1484         { .irq = -1 }
1485 };
1486
1487 static struct omap_hwmod omap54xx_hsi_hwmod = {
1488         .name           = "hsi",
1489         .class          = &omap54xx_hsi_hwmod_class,
1490         .clkdm_name     = "l3init_clkdm",
1491         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1492         .mpu_irqs       = omap54xx_hsi_irqs,
1493         .main_clk       = "hsi_fclk",
1494         .prcm = {
1495                 .omap4 = {
1496                         .clkctrl_offs = OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1497                         .context_offs = OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET,
1498                         .modulemode   = MODULEMODE_HWCTRL,
1499                 },
1500         },
1501 };
1502
1503 /*
1504  * 'i2c' class
1505  * multimaster high-speed i2c controller
1506  */
1507
1508 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
1509         .sysc_offs      = 0x0010,
1510         .syss_offs      = 0x0090,
1511         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1512                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1513                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1514         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1515                            SIDLE_SMART_WKUP),
1516         .clockact       = CLOCKACT_TEST_ICLK,
1517         .sysc_fields    = &omap_hwmod_sysc_type1,
1518 };
1519
1520 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
1521         .name   = "i2c",
1522         .sysc   = &omap54xx_i2c_sysc,
1523         .reset  = &omap_i2c_reset,
1524         .rev    = OMAP_I2C_IP_VERSION_2,
1525 };
1526
1527 /* i2c dev_attr */
1528 static struct omap_i2c_dev_attr i2c_dev_attr = {
1529         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1530 };
1531
1532 /* i2c1 */
1533 static struct omap_hwmod_irq_info omap54xx_i2c1_irqs[] = {
1534         { .irq = 56 + OMAP54XX_IRQ_GIC_START },
1535         { .irq = -1 }
1536 };
1537
1538 static struct omap_hwmod_dma_info omap54xx_i2c1_sdma_reqs[] = {
1539         { .name = "tx", .dma_req = 26 + OMAP54XX_DMA_REQ_START },
1540         { .name = "rx", .dma_req = 27 + OMAP54XX_DMA_REQ_START },
1541         { .dma_req = -1 }
1542 };
1543
1544 static struct omap_hwmod omap54xx_i2c1_hwmod = {
1545         .name           = "i2c1",
1546         .class          = &omap54xx_i2c_hwmod_class,
1547         .clkdm_name     = "l4per_clkdm",
1548         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1549         .mpu_irqs       = omap54xx_i2c1_irqs,
1550         .sdma_reqs      = omap54xx_i2c1_sdma_reqs,
1551         .main_clk       = "func_96m_fclk",
1552         .prcm = {
1553                 .omap4 = {
1554                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1555                         .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1556                         .modulemode   = MODULEMODE_SWCTRL,
1557                 },
1558         },
1559         .dev_attr       = &i2c_dev_attr,
1560 };
1561
1562 /* i2c2 */
1563 static struct omap_hwmod_irq_info omap54xx_i2c2_irqs[] = {
1564         { .irq = 57 + OMAP54XX_IRQ_GIC_START },
1565         { .irq = -1 }
1566 };
1567
1568 static struct omap_hwmod_dma_info omap54xx_i2c2_sdma_reqs[] = {
1569         { .name = "tx", .dma_req = 28 + OMAP54XX_DMA_REQ_START },
1570         { .name = "rx", .dma_req = 29 + OMAP54XX_DMA_REQ_START },
1571         { .dma_req = -1 }
1572 };
1573
1574 static struct omap_hwmod omap54xx_i2c2_hwmod = {
1575         .name           = "i2c2",
1576         .class          = &omap54xx_i2c_hwmod_class,
1577         .clkdm_name     = "l4per_clkdm",
1578         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1579         .mpu_irqs       = omap54xx_i2c2_irqs,
1580         .sdma_reqs      = omap54xx_i2c2_sdma_reqs,
1581         .main_clk       = "func_96m_fclk",
1582         .prcm = {
1583                 .omap4 = {
1584                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1585                         .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1586                         .modulemode   = MODULEMODE_SWCTRL,
1587                 },
1588         },
1589         .dev_attr       = &i2c_dev_attr,
1590 };
1591
1592 /* i2c3 */
1593 static struct omap_hwmod_irq_info omap54xx_i2c3_irqs[] = {
1594         { .irq = 61 + OMAP54XX_IRQ_GIC_START },
1595         { .irq = -1 }
1596 };
1597
1598 static struct omap_hwmod_dma_info omap54xx_i2c3_sdma_reqs[] = {
1599         { .name = "tx", .dma_req = 24 + OMAP54XX_DMA_REQ_START },
1600         { .name = "rx", .dma_req = 25 + OMAP54XX_DMA_REQ_START },
1601         { .dma_req = -1 }
1602 };
1603
1604 static struct omap_hwmod omap54xx_i2c3_hwmod = {
1605         .name           = "i2c3",
1606         .class          = &omap54xx_i2c_hwmod_class,
1607         .clkdm_name     = "l4per_clkdm",
1608         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1609         .mpu_irqs       = omap54xx_i2c3_irqs,
1610         .sdma_reqs      = omap54xx_i2c3_sdma_reqs,
1611         .main_clk       = "func_96m_fclk",
1612         .prcm = {
1613                 .omap4 = {
1614                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1615                         .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1616                         .modulemode   = MODULEMODE_SWCTRL,
1617                 },
1618         },
1619         .dev_attr       = &i2c_dev_attr,
1620 };
1621
1622 /* i2c4 */
1623 static struct omap_hwmod_irq_info omap54xx_i2c4_irqs[] = {
1624         { .irq = 62 + OMAP54XX_IRQ_GIC_START },
1625         { .irq = -1 }
1626 };
1627
1628 static struct omap_hwmod_dma_info omap54xx_i2c4_sdma_reqs[] = {
1629         { .name = "tx", .dma_req = 123 + OMAP54XX_DMA_REQ_START },
1630         { .name = "rx", .dma_req = 124 + OMAP54XX_DMA_REQ_START },
1631         { .dma_req = -1 }
1632 };
1633
1634 static struct omap_hwmod omap54xx_i2c4_hwmod = {
1635         .name           = "i2c4",
1636         .class          = &omap54xx_i2c_hwmod_class,
1637         .clkdm_name     = "l4per_clkdm",
1638         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1639         .mpu_irqs       = omap54xx_i2c4_irqs,
1640         .sdma_reqs      = omap54xx_i2c4_sdma_reqs,
1641         .main_clk       = "func_96m_fclk",
1642         .prcm = {
1643                 .omap4 = {
1644                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1645                         .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1646                         .modulemode   = MODULEMODE_SWCTRL,
1647                 },
1648         },
1649         .dev_attr       = &i2c_dev_attr,
1650 };
1651
1652 /* i2c5 */
1653 static struct omap_hwmod_irq_info omap54xx_i2c5_irqs[] = {
1654         { .irq = 60 + OMAP54XX_IRQ_GIC_START },
1655         { .irq = -1 }
1656 };
1657
1658 static struct omap_hwmod omap54xx_i2c5_hwmod = {
1659         .name           = "i2c5",
1660         .class          = &omap54xx_i2c_hwmod_class,
1661         .clkdm_name     = "l4per_clkdm",
1662         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1663         .mpu_irqs       = omap54xx_i2c5_irqs,
1664         .main_clk       = "func_96m_fclk",
1665         .prcm = {
1666                 .omap4 = {
1667                         .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
1668                         .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
1669                         .modulemode   = MODULEMODE_SWCTRL,
1670                 },
1671         },
1672         .dev_attr       = &i2c_dev_attr,
1673 };
1674
1675 /*
1676  * 'ipu' class
1677  * imaging processor unit
1678  */
1679
1680 static struct omap_hwmod_class_sysconfig omap54xx_ipu_sysc = {
1681         .rev_offs       = 0x0000,
1682         .sysc_offs      = 0x0010,
1683         .syss_offs      = 0x0014,
1684         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1685                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1686                            SYSS_HAS_RESET_STATUS),
1687         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1688         .sysc_fields    = &omap_hwmod_sysc_type1,
1689 };
1690
1691 static struct omap_hwmod_class omap54xx_ipu_hwmod_class = {
1692         .name   = "ipu",
1693         .sysc   = &omap54xx_ipu_sysc,
1694 };
1695
1696 /* ipu */
1697 static struct omap_hwmod_irq_info omap54xx_ipu_irqs[] = {
1698         { .irq = 100 + OMAP54XX_IRQ_GIC_START },
1699         { .irq = -1 }
1700 };
1701
1702 static struct omap_hwmod_rst_info omap54xx_ipu_resets[] = {
1703         { .name = "cpu0", .rst_shift = 0 },
1704         { .name = "cpu1", .rst_shift = 1 },
1705         { .name = "mmu_cache", .rst_shift = 2 },
1706 };
1707
1708 static struct omap_hwmod omap54xx_ipu_hwmod = {
1709         .name           = "ipu",
1710         .class          = &omap54xx_ipu_hwmod_class,
1711         .clkdm_name     = "ipu_clkdm",
1712         .mpu_irqs       = omap54xx_ipu_irqs,
1713         .rst_lines      = omap54xx_ipu_resets,
1714         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_ipu_resets),
1715         .main_clk       = "dpll_core_h22x2_ck",
1716         .prcm = {
1717                 .omap4 = {
1718                         .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
1719                         .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
1720                         .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
1721                         .modulemode   = MODULEMODE_HWCTRL,
1722                 },
1723         },
1724 };
1725
1726 /*
1727  * 'intc' class
1728  * nested vectored interrupt controller
1729  */
1730
1731 static struct omap_hwmod_class omap54xx_intc_hwmod_class = {
1732         .name   = "intc",
1733 };
1734
1735 /* intc_ipu_c0 */
1736 static struct omap_hwmod omap54xx_intc_ipu_c0_hwmod = {
1737         .name           = "intc_ipu_c0",
1738         .class          = &omap54xx_intc_hwmod_class,
1739         .clkdm_name     = "ipu_clkdm",
1740         .main_clk       = "dpll_core_h22x2_ck",
1741         .prcm = {
1742                 .omap4 = {
1743                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1744                 },
1745         },
1746 };
1747
1748 /* intc_ipu_c1 */
1749 static struct omap_hwmod omap54xx_intc_ipu_c1_hwmod = {
1750         .name           = "intc_ipu_c1",
1751         .class          = &omap54xx_intc_hwmod_class,
1752         .clkdm_name     = "ipu_clkdm",
1753         .main_clk       = "dpll_core_h22x2_ck",
1754         .prcm = {
1755                 .omap4 = {
1756                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1757                 },
1758         },
1759 };
1760
1761 /*
1762  * 'iss' class
1763  * external images sensor pixel data processor
1764  */
1765
1766 static struct omap_hwmod_class_sysconfig omap54xx_iss_sysc = {
1767         .rev_offs       = 0x0000,
1768         .sysc_offs      = 0x0010,
1769         /*
1770          * ISS needs 100 OCP clk cycles delay after a softreset before
1771          * accessing sysconfig again.
1772          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1773          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1774          *
1775          * TODO: Indicate errata when available.
1776          */
1777         .srst_udelay    = 2,
1778         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1779                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1780         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1781                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1782                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1783         .sysc_fields    = &omap_hwmod_sysc_type2,
1784 };
1785
1786 static struct omap_hwmod_class omap54xx_iss_hwmod_class = {
1787         .name   = "iss",
1788         .sysc   = &omap54xx_iss_sysc,
1789 };
1790
1791 /* iss */
1792 static struct omap_hwmod_irq_info omap54xx_iss_irqs[] = {
1793         { .irq = 24 + OMAP54XX_IRQ_GIC_START },
1794         { .irq = -1 }
1795 };
1796
1797 static struct omap_hwmod_dma_info omap54xx_iss_sdma_reqs[] = {
1798         { .name = "1", .dma_req = 8 + OMAP54XX_DMA_REQ_START },
1799         { .name = "2", .dma_req = 9 + OMAP54XX_DMA_REQ_START },
1800         { .name = "3", .dma_req = 11 + OMAP54XX_DMA_REQ_START },
1801         { .name = "4", .dma_req = 12 + OMAP54XX_DMA_REQ_START },
1802         { .name = "5", .dma_req = 30 + OMAP54XX_DMA_REQ_START },
1803         { .name = "6", .dma_req = 31 + OMAP54XX_DMA_REQ_START },
1804         { .name = "7", .dma_req = 125 + OMAP54XX_DMA_REQ_START },
1805         { .name = "8", .dma_req = 126 + OMAP54XX_DMA_REQ_START },
1806         { .dma_req = -1 }
1807 };
1808
1809 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1810         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1811 };
1812
1813 static struct omap_hwmod omap54xx_iss_hwmod = {
1814         .name           = "iss",
1815         .class          = &omap54xx_iss_hwmod_class,
1816         .clkdm_name     = "cam_clkdm",
1817         .flags          = HWMOD_INIT_NO_RESET,
1818         .mpu_irqs       = omap54xx_iss_irqs,
1819         .sdma_reqs      = omap54xx_iss_sdma_reqs,
1820         .main_clk       = "dpll_core_h22x2_ck",
1821         .prcm = {
1822                 .omap4 = {
1823                         .clkctrl_offs = OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET,
1824                         .context_offs = OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET,
1825                         .modulemode   = MODULEMODE_SWCTRL,
1826                 },
1827         },
1828         .opt_clks       = iss_opt_clks,
1829         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1830 };
1831
1832 /*
1833  * 'iva' class
1834  * multi-standard video encoder/decoder hardware accelerator
1835  */
1836
1837 static struct omap_hwmod_class_sysconfig omap54xx_iva_sysc = {
1838         .rev_offs       = 0x0000,
1839         .sysc_offs      = 0x0010,
1840         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1841         .idlemodes      = (SIDLE_NO | SIDLE_SMART | MSTANDBY_NO |
1842                            MSTANDBY_SMART),
1843         .sysc_fields    = &omap_hwmod_sysc_type2,
1844 };
1845
1846 static struct omap_hwmod_class omap54xx_iva_hwmod_class = {
1847         .name   = "iva",
1848         .sysc   = &omap54xx_iva_sysc,
1849 };
1850
1851 /* iva */
1852 static struct omap_hwmod_irq_info omap54xx_iva_irqs[] = {
1853         { .name = "sync_1", .irq = 103 + OMAP54XX_IRQ_GIC_START },
1854         { .name = "sync_0", .irq = 104 + OMAP54XX_IRQ_GIC_START },
1855         { .name = "mailbox_0", .irq = 107 + OMAP54XX_IRQ_GIC_START },
1856         { .irq = -1 }
1857 };
1858
1859 static struct omap_hwmod_rst_info omap54xx_iva_resets[] = {
1860         { .name = "seq0", .rst_shift = 0 },
1861         { .name = "seq1", .rst_shift = 1 },
1862         { .name = "logic", .rst_shift = 2 },
1863 };
1864
1865 static struct omap_hwmod omap54xx_iva_hwmod = {
1866         .name           = "iva",
1867         .class          = &omap54xx_iva_hwmod_class,
1868         .clkdm_name     = "iva_clkdm",
1869         .mpu_irqs       = omap54xx_iva_irqs,
1870         .rst_lines      = omap54xx_iva_resets,
1871         .rst_lines_cnt  = ARRAY_SIZE(omap54xx_iva_resets),
1872         .main_clk       = "dpll_iva_h12x2_ck",
1873         .prcm = {
1874                 .omap4 = {
1875                         .clkctrl_offs = OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET,
1876                         .rstctrl_offs = OMAP54XX_RM_IVA_RSTCTRL_OFFSET,
1877                         .context_offs = OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET,
1878                         .modulemode   = MODULEMODE_HWCTRL,
1879                 },
1880         },
1881 };
1882
1883 /*
1884  * 'kbd' class
1885  * keyboard controller
1886  */
1887
1888 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
1889         .rev_offs       = 0x0000,
1890         .sysc_offs      = 0x0010,
1891         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1892                            SYSC_HAS_SOFTRESET),
1893         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1894         .sysc_fields    = &omap_hwmod_sysc_type1,
1895 };
1896
1897 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
1898         .name   = "kbd",
1899         .sysc   = &omap54xx_kbd_sysc,
1900 };
1901
1902 /* kbd */
1903 static struct omap_hwmod_irq_info omap54xx_kbd_irqs[] = {
1904         { .irq = 120 + OMAP54XX_IRQ_GIC_START },
1905         { .irq = -1 }
1906 };
1907
1908 static struct omap_hwmod omap54xx_kbd_hwmod = {
1909         .name           = "kbd",
1910         .class          = &omap54xx_kbd_hwmod_class,
1911         .clkdm_name     = "wkupaon_clkdm",
1912         .mpu_irqs       = omap54xx_kbd_irqs,
1913         .main_clk       = "sys_32k_ck",
1914         .prcm = {
1915                 .omap4 = {
1916                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
1917                         .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
1918                         .modulemode   = MODULEMODE_SWCTRL,
1919                 },
1920         },
1921 };
1922
1923 /*
1924  * 'mailbox' class
1925  * mailbox module allowing communication between the on-chip processors
1926  * useusing a queued mailbox-interrupt mechanism.
1927  */
1928
1929 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
1930         .rev_offs       = 0x0000,
1931         .sysc_offs      = 0x0010,
1932         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1933                            SYSC_HAS_SOFTRESET),
1934         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1935         .sysc_fields    = &omap_hwmod_sysc_type2,
1936 };
1937
1938 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
1939         .name   = "mailbox",
1940         .sysc   = &omap54xx_mailbox_sysc,
1941 };
1942
1943 /* mailbox */
1944 static struct omap_hwmod_irq_info omap54xx_mailbox_irqs[] = {
1945         { .irq = 26 + OMAP54XX_IRQ_GIC_START },
1946         { .irq = -1 }
1947 };
1948
1949 static struct omap_hwmod omap54xx_mailbox_hwmod = {
1950         .name           = "mailbox",
1951         .class          = &omap54xx_mailbox_hwmod_class,
1952         .clkdm_name     = "l4cfg_clkdm",
1953         .mpu_irqs       = omap54xx_mailbox_irqs,
1954         .main_clk       = "l4_root_clk_div",
1955         .prcm = {
1956                 .omap4 = {
1957                         .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1958                         .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1959                 },
1960         },
1961 };
1962
1963 /*
1964  * 'mcasp' class
1965  * multi-channel audio serial port controller
1966  */
1967
1968 static struct omap_hwmod_class_sysconfig omap54xx_mcasp_sysc = {
1969         .sysc_offs      = 0x0004,
1970         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1971         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1972         .sysc_fields    = &omap_hwmod_sysc_type3,
1973 };
1974
1975 static struct omap_hwmod_class omap54xx_mcasp_hwmod_class = {
1976         .name   = "mcasp",
1977         .sysc   = &omap54xx_mcasp_sysc,
1978 };
1979
1980 /* mcasp */
1981 static struct omap_hwmod_irq_info omap54xx_mcasp_irqs[] = {
1982         { .name = "arevt", .irq = 108 + OMAP54XX_IRQ_GIC_START },
1983         { .name = "axevt", .irq = 109 + OMAP54XX_IRQ_GIC_START },
1984         { .irq = -1 }
1985 };
1986
1987 static struct omap_hwmod_dma_info omap54xx_mcasp_sdma_reqs[] = {
1988         { .name = "axevt", .dma_req = 7 + OMAP54XX_DMA_REQ_START },
1989         { .name = "arevt", .dma_req = 10 + OMAP54XX_DMA_REQ_START },
1990         { .dma_req = -1 }
1991 };
1992
1993 static struct omap_hwmod omap54xx_mcasp_hwmod = {
1994         .name           = "mcasp",
1995         .class          = &omap54xx_mcasp_hwmod_class,
1996         .clkdm_name     = "abe_clkdm",
1997         .flags          = HWMOD_SWSUP_SIDLE,
1998         .mpu_irqs       = omap54xx_mcasp_irqs,
1999         .sdma_reqs      = omap54xx_mcasp_sdma_reqs,
2000         .main_clk       = "mcasp_gfclk",
2001         .prcm = {
2002                 .omap4 = {
2003                         .clkctrl_offs = OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET,
2004                         .context_offs = OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET,
2005                         .modulemode   = MODULEMODE_SWCTRL,
2006                 },
2007         },
2008 };
2009
2010 /*
2011  * 'mcbsp' class
2012  * multi channel buffered serial port controller
2013  */
2014
2015 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
2016         .sysc_offs      = 0x008c,
2017         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2018                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2019         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2020         .sysc_fields    = &omap_hwmod_sysc_type1,
2021 };
2022
2023 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
2024         .name   = "mcbsp",
2025         .sysc   = &omap54xx_mcbsp_sysc,
2026         .rev    = MCBSP_CONFIG_TYPE4,
2027 };
2028
2029 /* mcbsp1 */
2030 static struct omap_hwmod_irq_info omap54xx_mcbsp1_irqs[] = {
2031         { .name = "common", .irq = 17 + OMAP54XX_IRQ_GIC_START },
2032         { .irq = -1 }
2033 };
2034
2035 static struct omap_hwmod_dma_info omap54xx_mcbsp1_sdma_reqs[] = {
2036         { .name = "tx", .dma_req = 32 + OMAP54XX_DMA_REQ_START },
2037         { .name = "rx", .dma_req = 33 + OMAP54XX_DMA_REQ_START },
2038         { .dma_req = -1 }
2039 };
2040
2041 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
2042         { .role = "pad_fck", .clk = "pad_clks_ck" },
2043         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
2044 };
2045
2046 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
2047         .name           = "mcbsp1",
2048         .class          = &omap54xx_mcbsp_hwmod_class,
2049         .clkdm_name     = "abe_clkdm",
2050         .mpu_irqs       = omap54xx_mcbsp1_irqs,
2051         .sdma_reqs      = omap54xx_mcbsp1_sdma_reqs,
2052         .main_clk       = "mcbsp1_gfclk",
2053         .prcm = {
2054                 .omap4 = {
2055                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
2056                         .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
2057                         .modulemode   = MODULEMODE_SWCTRL,
2058                 },
2059         },
2060         .opt_clks       = mcbsp1_opt_clks,
2061         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
2062 };
2063
2064 /* mcbsp2 */
2065 static struct omap_hwmod_irq_info omap54xx_mcbsp2_irqs[] = {
2066         { .name = "common", .irq = 22 + OMAP54XX_IRQ_GIC_START },
2067         { .irq = -1 }
2068 };
2069
2070 static struct omap_hwmod_dma_info omap54xx_mcbsp2_sdma_reqs[] = {
2071         { .name = "tx", .dma_req = 16 + OMAP54XX_DMA_REQ_START },
2072         { .name = "rx", .dma_req = 17 + OMAP54XX_DMA_REQ_START },
2073         { .dma_req = -1 }
2074 };
2075
2076 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2077         { .role = "pad_fck", .clk = "pad_clks_ck" },
2078         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2079 };
2080
2081 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
2082         .name           = "mcbsp2",
2083         .class          = &omap54xx_mcbsp_hwmod_class,
2084         .clkdm_name     = "abe_clkdm",
2085         .mpu_irqs       = omap54xx_mcbsp2_irqs,
2086         .sdma_reqs      = omap54xx_mcbsp2_sdma_reqs,
2087         .main_clk       = "mcbsp2_gfclk",
2088         .prcm = {
2089                 .omap4 = {
2090                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
2091                         .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2092                         .modulemode   = MODULEMODE_SWCTRL,
2093                 },
2094         },
2095         .opt_clks       = mcbsp2_opt_clks,
2096         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2097 };
2098
2099 /* mcbsp3 */
2100 static struct omap_hwmod_irq_info omap54xx_mcbsp3_irqs[] = {
2101         { .name = "common", .irq = 23 + OMAP54XX_IRQ_GIC_START },
2102         { .irq = -1 }
2103 };
2104
2105 static struct omap_hwmod_dma_info omap54xx_mcbsp3_sdma_reqs[] = {
2106         { .name = "tx", .dma_req = 18 + OMAP54XX_DMA_REQ_START },
2107         { .name = "rx", .dma_req = 19 + OMAP54XX_DMA_REQ_START },
2108         { .dma_req = -1 }
2109 };
2110
2111 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2112         { .role = "pad_fck", .clk = "pad_clks_ck" },
2113         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2114 };
2115
2116 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
2117         .name           = "mcbsp3",
2118         .class          = &omap54xx_mcbsp_hwmod_class,
2119         .clkdm_name     = "abe_clkdm",
2120         .mpu_irqs       = omap54xx_mcbsp3_irqs,
2121         .sdma_reqs      = omap54xx_mcbsp3_sdma_reqs,
2122         .main_clk       = "mcbsp3_gfclk",
2123         .prcm = {
2124                 .omap4 = {
2125                         .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
2126                         .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2127                         .modulemode   = MODULEMODE_SWCTRL,
2128                 },
2129         },
2130         .opt_clks       = mcbsp3_opt_clks,
2131         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2132 };
2133
2134 /*
2135  * 'mcpdm' class
2136  * multi channel pdm controller (proprietary interface with phoenix power
2137  * ic)
2138  */
2139
2140 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
2141         .rev_offs       = 0x0000,
2142         .sysc_offs      = 0x0010,
2143         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2144                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2145         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2146                            SIDLE_SMART_WKUP),
2147         .sysc_fields    = &omap_hwmod_sysc_type2,
2148 };
2149
2150 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
2151         .name   = "mcpdm",
2152         .sysc   = &omap54xx_mcpdm_sysc,
2153 };
2154
2155 /* mcpdm */
2156 static struct omap_hwmod_irq_info omap54xx_mcpdm_irqs[] = {
2157         { .irq = 112 + OMAP54XX_IRQ_GIC_START },
2158         { .irq = -1 }
2159 };
2160
2161 static struct omap_hwmod_dma_info omap54xx_mcpdm_sdma_reqs[] = {
2162         { .name = "up_link", .dma_req = 64 + OMAP54XX_DMA_REQ_START },
2163         { .name = "dn_link", .dma_req = 65 + OMAP54XX_DMA_REQ_START },
2164         { .dma_req = -1 }
2165 };
2166
2167 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
2168         .name           = "mcpdm",
2169         .class          = &omap54xx_mcpdm_hwmod_class,
2170         .clkdm_name     = "abe_clkdm",
2171         /*
2172          * It's suspected that the McPDM requires an off-chip main
2173          * functional clock, controlled via I2C.  This IP block is
2174          * currently reset very early during boot, before I2C is
2175          * available, so it doesn't seem that we have any choice in
2176          * the kernel other than to avoid resetting it.  XXX This is
2177          * really a hardware issue workaround: every IP block should
2178          * be able to source its main functional clock from either
2179          * on-chip or off-chip sources.  McPDM seems to be the only
2180          * current exception.
2181          */
2182
2183         .flags          = HWMOD_EXT_OPT_MAIN_CLK,
2184         .mpu_irqs       = omap54xx_mcpdm_irqs,
2185         .sdma_reqs      = omap54xx_mcpdm_sdma_reqs,
2186         .main_clk       = "pad_clks_ck",
2187         .prcm = {
2188                 .omap4 = {
2189                         .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
2190                         .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
2191                         .modulemode   = MODULEMODE_SWCTRL,
2192                 },
2193         },
2194 };
2195
2196 /*
2197  * 'mcspi' class
2198  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2199  * bus
2200  */
2201
2202 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
2203         .rev_offs       = 0x0000,
2204         .sysc_offs      = 0x0010,
2205         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2206                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2207         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2208                            SIDLE_SMART_WKUP),
2209         .sysc_fields    = &omap_hwmod_sysc_type2,
2210 };
2211
2212 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
2213         .name   = "mcspi",
2214         .sysc   = &omap54xx_mcspi_sysc,
2215         .rev    = OMAP4_MCSPI_REV,
2216 };
2217
2218 /* mcspi1 */
2219 static struct omap_hwmod_irq_info omap54xx_mcspi1_irqs[] = {
2220         { .irq = 65 + OMAP54XX_IRQ_GIC_START },
2221         { .irq = -1 }
2222 };
2223
2224 static struct omap_hwmod_dma_info omap54xx_mcspi1_sdma_reqs[] = {
2225         { .name = "tx0", .dma_req = 34 + OMAP54XX_DMA_REQ_START },
2226         { .name = "rx0", .dma_req = 35 + OMAP54XX_DMA_REQ_START },
2227         { .name = "tx1", .dma_req = 36 + OMAP54XX_DMA_REQ_START },
2228         { .name = "rx1", .dma_req = 37 + OMAP54XX_DMA_REQ_START },
2229         { .name = "tx2", .dma_req = 38 + OMAP54XX_DMA_REQ_START },
2230         { .name = "rx2", .dma_req = 39 + OMAP54XX_DMA_REQ_START },
2231         { .name = "tx3", .dma_req = 40 + OMAP54XX_DMA_REQ_START },
2232         { .name = "rx3", .dma_req = 41 + OMAP54XX_DMA_REQ_START },
2233         { .dma_req = -1 }
2234 };
2235
2236 /* mcspi1 dev_attr */
2237 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2238         .num_chipselect = 4,
2239 };
2240
2241 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
2242         .name           = "mcspi1",
2243         .class          = &omap54xx_mcspi_hwmod_class,
2244         .clkdm_name     = "l4per_clkdm",
2245         .mpu_irqs       = omap54xx_mcspi1_irqs,
2246         .sdma_reqs      = omap54xx_mcspi1_sdma_reqs,
2247         .main_clk       = "func_48m_fclk",
2248         .prcm = {
2249                 .omap4 = {
2250                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2251                         .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2252                         .modulemode   = MODULEMODE_SWCTRL,
2253                 },
2254         },
2255         .dev_attr       = &mcspi1_dev_attr,
2256 };
2257
2258 /* mcspi2 */
2259 static struct omap_hwmod_irq_info omap54xx_mcspi2_irqs[] = {
2260         { .irq = 66 + OMAP54XX_IRQ_GIC_START },
2261         { .irq = -1 }
2262 };
2263
2264 static struct omap_hwmod_dma_info omap54xx_mcspi2_sdma_reqs[] = {
2265         { .name = "tx0", .dma_req = 42 + OMAP54XX_DMA_REQ_START },
2266         { .name = "rx0", .dma_req = 43 + OMAP54XX_DMA_REQ_START },
2267         { .name = "tx1", .dma_req = 44 + OMAP54XX_DMA_REQ_START },
2268         { .name = "rx1", .dma_req = 45 + OMAP54XX_DMA_REQ_START },
2269         { .dma_req = -1 }
2270 };
2271
2272 /* mcspi2 dev_attr */
2273 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2274         .num_chipselect = 2,
2275 };
2276
2277 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
2278         .name           = "mcspi2",
2279         .class          = &omap54xx_mcspi_hwmod_class,
2280         .clkdm_name     = "l4per_clkdm",
2281         .mpu_irqs       = omap54xx_mcspi2_irqs,
2282         .sdma_reqs      = omap54xx_mcspi2_sdma_reqs,
2283         .main_clk       = "func_48m_fclk",
2284         .prcm = {
2285                 .omap4 = {
2286                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2287                         .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2288                         .modulemode   = MODULEMODE_SWCTRL,
2289                 },
2290         },
2291         .dev_attr       = &mcspi2_dev_attr,
2292 };
2293
2294 /* mcspi3 */
2295 static struct omap_hwmod_irq_info omap54xx_mcspi3_irqs[] = {
2296         { .irq = 91 + OMAP54XX_IRQ_GIC_START },
2297         { .irq = -1 }
2298 };
2299
2300 static struct omap_hwmod_dma_info omap54xx_mcspi3_sdma_reqs[] = {
2301         { .name = "tx0", .dma_req = 14 + OMAP54XX_DMA_REQ_START },
2302         { .name = "rx0", .dma_req = 15 + OMAP54XX_DMA_REQ_START },
2303         { .dma_req = -1 }
2304 };
2305
2306 /* mcspi3 dev_attr */
2307 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2308         .num_chipselect = 2,
2309 };
2310
2311 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
2312         .name           = "mcspi3",
2313         .class          = &omap54xx_mcspi_hwmod_class,
2314         .clkdm_name     = "l4per_clkdm",
2315         .mpu_irqs       = omap54xx_mcspi3_irqs,
2316         .sdma_reqs      = omap54xx_mcspi3_sdma_reqs,
2317         .main_clk       = "func_48m_fclk",
2318         .prcm = {
2319                 .omap4 = {
2320                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2321                         .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2322                         .modulemode   = MODULEMODE_SWCTRL,
2323                 },
2324         },
2325         .dev_attr       = &mcspi3_dev_attr,
2326 };
2327
2328 /* mcspi4 */
2329 static struct omap_hwmod_irq_info omap54xx_mcspi4_irqs[] = {
2330         { .irq = 48 + OMAP54XX_IRQ_GIC_START },
2331         { .irq = -1 }
2332 };
2333
2334 static struct omap_hwmod_dma_info omap54xx_mcspi4_sdma_reqs[] = {
2335         { .name = "tx0", .dma_req = 69 + OMAP54XX_DMA_REQ_START },
2336         { .name = "rx0", .dma_req = 70 + OMAP54XX_DMA_REQ_START },
2337         { .dma_req = -1 }
2338 };
2339
2340 /* mcspi4 dev_attr */
2341 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2342         .num_chipselect = 1,
2343 };
2344
2345 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
2346         .name           = "mcspi4",
2347         .class          = &omap54xx_mcspi_hwmod_class,
2348         .clkdm_name     = "l4per_clkdm",
2349         .mpu_irqs       = omap54xx_mcspi4_irqs,
2350         .sdma_reqs      = omap54xx_mcspi4_sdma_reqs,
2351         .main_clk       = "func_48m_fclk",
2352         .prcm = {
2353                 .omap4 = {
2354                         .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2355                         .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2356                         .modulemode   = MODULEMODE_SWCTRL,
2357                 },
2358         },
2359         .dev_attr       = &mcspi4_dev_attr,
2360 };
2361
2362 /*
2363  * 'mmc' class
2364  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2365  */
2366
2367 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
2368         .rev_offs       = 0x0000,
2369         .sysc_offs      = 0x0010,
2370         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2371                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2372                            SYSC_HAS_SOFTRESET),
2373         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2374                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2375                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2376         .sysc_fields    = &omap_hwmod_sysc_type2,
2377 };
2378
2379 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
2380         .name   = "mmc",
2381         .sysc   = &omap54xx_mmc_sysc,
2382 };
2383
2384 /* mmc1 */
2385 static struct omap_hwmod_irq_info omap54xx_mmc1_irqs[] = {
2386         { .irq = 83 + OMAP54XX_IRQ_GIC_START },
2387         { .irq = -1 }
2388 };
2389
2390 static struct omap_hwmod_dma_info omap54xx_mmc1_sdma_reqs[] = {
2391         { .name = "tx", .dma_req = 60 + OMAP54XX_DMA_REQ_START },
2392         { .name = "rx", .dma_req = 61 + OMAP54XX_DMA_REQ_START },
2393         { .dma_req = -1 }
2394 };
2395
2396 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
2397         { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
2398 };
2399
2400 /* mmc1 dev_attr */
2401 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2402         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2403 };
2404
2405 static struct omap_hwmod omap54xx_mmc1_hwmod = {
2406         .name           = "mmc1",
2407         .class          = &omap54xx_mmc_hwmod_class,
2408         .clkdm_name     = "l3init_clkdm",
2409         .mpu_irqs       = omap54xx_mmc1_irqs,
2410         .sdma_reqs      = omap54xx_mmc1_sdma_reqs,
2411         .main_clk       = "mmc1_fclk",
2412         .prcm = {
2413                 .omap4 = {
2414                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2415                         .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2416                         .modulemode   = MODULEMODE_SWCTRL,
2417                 },
2418         },
2419         .opt_clks       = mmc1_opt_clks,
2420         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
2421         .dev_attr       = &mmc1_dev_attr,
2422 };
2423
2424 /* mmc2 */
2425 static struct omap_hwmod_irq_info omap54xx_mmc2_irqs[] = {
2426         { .irq = 86 + OMAP54XX_IRQ_GIC_START },
2427         { .irq = -1 }
2428 };
2429
2430 static struct omap_hwmod_dma_info omap54xx_mmc2_sdma_reqs[] = {
2431         { .name = "tx", .dma_req = 46 + OMAP54XX_DMA_REQ_START },
2432         { .name = "rx", .dma_req = 47 + OMAP54XX_DMA_REQ_START },
2433         { .dma_req = -1 }
2434 };
2435
2436 static struct omap_hwmod omap54xx_mmc2_hwmod = {
2437         .name           = "mmc2",
2438         .class          = &omap54xx_mmc_hwmod_class,
2439         .clkdm_name     = "l3init_clkdm",
2440         .mpu_irqs       = omap54xx_mmc2_irqs,
2441         .sdma_reqs      = omap54xx_mmc2_sdma_reqs,
2442         .main_clk       = "mmc2_fclk",
2443         .prcm = {
2444                 .omap4 = {
2445                         .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2446                         .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2447                         .modulemode   = MODULEMODE_SWCTRL,
2448                 },
2449         },
2450 };
2451
2452 /* mmc3 */
2453 static struct omap_hwmod_irq_info omap54xx_mmc3_irqs[] = {
2454         { .irq = 94 + OMAP54XX_IRQ_GIC_START },
2455         { .irq = -1 }
2456 };
2457
2458 static struct omap_hwmod_dma_info omap54xx_mmc3_sdma_reqs[] = {
2459         { .name = "tx", .dma_req = 76 + OMAP54XX_DMA_REQ_START },
2460         { .name = "rx", .dma_req = 77 + OMAP54XX_DMA_REQ_START },
2461         { .dma_req = -1 }
2462 };
2463
2464 static struct omap_hwmod omap54xx_mmc3_hwmod = {
2465         .name           = "mmc3",
2466         .class          = &omap54xx_mmc_hwmod_class,
2467         .clkdm_name     = "l4per_clkdm",
2468         .mpu_irqs       = omap54xx_mmc3_irqs,
2469         .sdma_reqs      = omap54xx_mmc3_sdma_reqs,
2470         .main_clk       = "func_48m_fclk",
2471         .prcm = {
2472                 .omap4 = {
2473                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
2474                         .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
2475                         .modulemode   = MODULEMODE_SWCTRL,
2476                 },
2477         },
2478 };
2479
2480 /* mmc4 */
2481 static struct omap_hwmod_irq_info omap54xx_mmc4_irqs[] = {
2482         { .irq = 96 + OMAP54XX_IRQ_GIC_START },
2483         { .irq = -1 }
2484 };
2485
2486 static struct omap_hwmod_dma_info omap54xx_mmc4_sdma_reqs[] = {
2487         { .name = "tx", .dma_req = 56 + OMAP54XX_DMA_REQ_START },
2488         { .name = "rx", .dma_req = 57 + OMAP54XX_DMA_REQ_START },
2489         { .dma_req = -1 }
2490 };
2491
2492 static struct omap_hwmod omap54xx_mmc4_hwmod = {
2493         .name           = "mmc4",
2494         .class          = &omap54xx_mmc_hwmod_class,
2495         .clkdm_name     = "l4per_clkdm",
2496         .mpu_irqs       = omap54xx_mmc4_irqs,
2497         .sdma_reqs      = omap54xx_mmc4_sdma_reqs,
2498         .main_clk       = "func_48m_fclk",
2499         .prcm = {
2500                 .omap4 = {
2501                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
2502                         .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
2503                         .modulemode   = MODULEMODE_SWCTRL,
2504                 },
2505         },
2506 };
2507
2508 /* mmc5 */
2509 static struct omap_hwmod_irq_info omap54xx_mmc5_irqs[] = {
2510         { .irq = 59 + OMAP54XX_IRQ_GIC_START },
2511         { .irq = -1 }
2512 };
2513
2514 static struct omap_hwmod_dma_info omap54xx_mmc5_sdma_reqs[] = {
2515         { .name = "tx", .dma_req = 58 + OMAP54XX_DMA_REQ_START },
2516         { .name = "rx", .dma_req = 59 + OMAP54XX_DMA_REQ_START },
2517         { .dma_req = -1 }
2518 };
2519
2520 static struct omap_hwmod omap54xx_mmc5_hwmod = {
2521         .name           = "mmc5",
2522         .class          = &omap54xx_mmc_hwmod_class,
2523         .clkdm_name     = "l4per_clkdm",
2524         .mpu_irqs       = omap54xx_mmc5_irqs,
2525         .sdma_reqs      = omap54xx_mmc5_sdma_reqs,
2526         .main_clk       = "func_96m_fclk",
2527         .prcm = {
2528                 .omap4 = {
2529                         .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
2530                         .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
2531                         .modulemode   = MODULEMODE_SWCTRL,
2532                 },
2533         },
2534 };
2535
2536 /*
2537  * 'mpu' class
2538  * mpu sub-system
2539  */
2540
2541 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
2542         .name   = "mpu",
2543 };
2544
2545 /* mpu */
2546 static struct omap_hwmod_irq_info omap54xx_mpu_irqs[] = {
2547         { .name = "mpu_cluster", .irq = 132 + OMAP54XX_IRQ_GIC_START },
2548         { .name = "wd_timer_mpu_c0", .irq = 139 + OMAP54XX_IRQ_GIC_START },
2549         { .name = "wd_timer_mpu_c1", .irq = 140 + OMAP54XX_IRQ_GIC_START },
2550         { .irq = -1 }
2551 };
2552
2553 static struct omap_hwmod omap54xx_mpu_hwmod = {
2554         .name           = "mpu",
2555         .class          = &omap54xx_mpu_hwmod_class,
2556         .clkdm_name     = "mpu_clkdm",
2557         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2558         .mpu_irqs       = omap54xx_mpu_irqs,
2559         .main_clk       = "dpll_mpu_m2_ck",
2560         .prcm = {
2561                 .omap4 = {
2562                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
2563                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
2564                 },
2565         },
2566 };
2567
2568 /*
2569  * 'ocmc_ram' class
2570  * top-level core on-chip ram
2571  */
2572
2573 static struct omap_hwmod_class omap54xx_ocmc_ram_hwmod_class = {
2574         .name   = "ocmc_ram",
2575 };
2576
2577 /* ocmc_ram */
2578 static struct omap_hwmod omap54xx_ocmc_ram_hwmod = {
2579         .name           = "ocmc_ram",
2580         .class          = &omap54xx_ocmc_ram_hwmod_class,
2581         .clkdm_name     = "l3main2_clkdm",
2582         .main_clk       = "l3_iclk_div",
2583         .prcm = {
2584                 .omap4 = {
2585                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET,
2586                         .context_offs = OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET,
2587                 },
2588         },
2589 };
2590
2591 /*
2592  * 'ocp2scp' class
2593  * bridge to transform ocp interface protocol to scp (serial control port)
2594  * protocol
2595  */
2596
2597 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
2598         .rev_offs       = 0x0000,
2599         .sysc_offs      = 0x0010,
2600         .syss_offs      = 0x0014,
2601         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2602                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2603         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2604         .sysc_fields    = &omap_hwmod_sysc_type1,
2605 };
2606
2607 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
2608         .name   = "ocp2scp",
2609         .sysc   = &omap54xx_ocp2scp_sysc,
2610 };
2611
2612 /* ocp2scp1 */
2613 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
2614         .name           = "ocp2scp1",
2615         .class          = &omap54xx_ocp2scp_hwmod_class,
2616         .clkdm_name     = "l3init_clkdm",
2617         .main_clk       = "l4_root_clk_div",
2618         .prcm = {
2619                 .omap4 = {
2620                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
2621                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
2622                         .modulemode   = MODULEMODE_HWCTRL,
2623                 },
2624         },
2625 };
2626
2627 static struct resource omap54xx_sata_phy_addrs[] = {
2628         {
2629                 .name           = "sata_phy_rx",
2630                 .start          = 0x4A096000,
2631                 .end            = 0x4A096080,
2632                 .flags          = IORESOURCE_MEM,
2633         },
2634         {
2635                 .name           = "sata_phy_tx",
2636                 .start          = 0x4A096400,
2637                 .end            = 0x4A096464,
2638                 .flags          = IORESOURCE_MEM,
2639         },
2640         {
2641                 .name           = "sata_pll",
2642                 .start          = 0x4A096800,
2643                 .end            = 0x4A096840,
2644                 .flags          = IORESOURCE_MEM,
2645         },
2646         { }
2647 };
2648
2649 static struct omap_ocp2scp_dev ocp2scp3_dev_attr[] = {
2650         {
2651                 .drv_name       = "omap-sata",
2652                 .res            = omap54xx_sata_phy_addrs,
2653         },
2654         { }
2655 };
2656
2657 /* ocp2scp3 */
2658 static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
2659 static struct omap_hwmod_addr_space omap54xx_ocp2scp3_addrs[] = {
2660         {
2661                 .name           = "ocp2scp3",
2662                 .pa_start       = 0x4a090000,
2663                 .pa_end         = 0x4a09001f,
2664                 .flags          = ADDR_TYPE_RT
2665         },
2666         { }
2667 };
2668
2669 /* l4_cfg -> ocp2scp3 */
2670 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
2671         .master         = &omap54xx_l4_cfg_hwmod,
2672         .slave          = &omap54xx_ocp2scp3_hwmod,
2673         .clk            = "l4_root_clk_div",
2674         .addr           = omap54xx_ocp2scp3_addrs,
2675         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2676 };
2677
2678 static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
2679         .name           = "ocp2scp3",
2680         .class          = &omap54xx_ocp2scp_hwmod_class,
2681         .clkdm_name     = "l3init_clkdm",
2682         .prcm = {
2683                 .omap4 = {
2684                         .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
2685                         .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
2686                         .modulemode   = MODULEMODE_HWCTRL,
2687                 },
2688         },
2689         .dev_attr       = ocp2scp3_dev_attr,
2690 };
2691
2692 /*
2693  * 'sata' class
2694  * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
2695  */
2696
2697 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2698         .sysc_offs      = 0x0000,
2699         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2700         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2701                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2702                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2703         .sysc_fields    = &omap_hwmod_sysc_type2,
2704 };
2705
2706 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2707         .name   = "sata",
2708         .sysc   = &omap54xx_sata_sysc,
2709 };
2710
2711 /* sata */
2712 static struct omap_hwmod_irq_info omap54xx_sata_irqs[] = {
2713         { .irq = 54 + OMAP54XX_IRQ_GIC_START },
2714         { .irq = -1 }
2715 };
2716
2717 static struct omap_hwmod_opt_clk sata_opt_clks[] = {
2718         { .role = "ref_clk", .clk = "sata_ref_clk" },
2719 };
2720
2721 static struct omap_hwmod omap54xx_sata_hwmod = {
2722         .name           = "sata",
2723         .class          = &omap54xx_sata_hwmod_class,
2724         .clkdm_name     = "l3init_clkdm",
2725         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2726         .mpu_irqs       = omap54xx_sata_irqs,
2727         .main_clk       = "func_48m_fclk",
2728         .prcm = {
2729                 .omap4 = {
2730                         .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2731                         .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2732                         .modulemode   = MODULEMODE_SWCTRL,
2733                 },
2734         },
2735         .opt_clks       = sata_opt_clks,
2736         .opt_clks_cnt   = ARRAY_SIZE(sata_opt_clks),
2737 };
2738
2739 /*
2740  * 'scrm' class
2741  * system clock and reset manager
2742  */
2743
2744 static struct omap_hwmod_class omap54xx_scrm_hwmod_class = {
2745         .name   = "scrm",
2746 };
2747
2748 /* scrm */
2749 static struct omap_hwmod omap54xx_scrm_hwmod = {
2750         .name           = "scrm",
2751         .class          = &omap54xx_scrm_hwmod_class,
2752         .clkdm_name     = "wkupaon_clkdm",
2753         .prcm = {
2754                 .omap4 = {
2755                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET,
2756                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2757                 },
2758         },
2759 };
2760
2761 /*
2762  * 'slimbus' class
2763  * bidirectional, multi-drop, multi-channel two-line serial interface between
2764  * the device and external components
2765  */
2766
2767 static struct omap_hwmod_class_sysconfig omap54xx_slimbus_sysc = {
2768         .rev_offs       = 0x0000,
2769         .sysc_offs      = 0x0010,
2770         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2771                            SYSC_HAS_SOFTRESET),
2772         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2773                            SIDLE_SMART_WKUP),
2774         .sysc_fields    = &omap_hwmod_sysc_type2,
2775 };
2776
2777 static struct omap_hwmod_class omap54xx_slimbus_hwmod_class = {
2778         .name   = "slimbus",
2779         .sysc   = &omap54xx_slimbus_sysc,
2780 };
2781
2782 /* slimbus1 */
2783 static struct omap_hwmod_irq_info omap54xx_slimbus1_irqs[] = {
2784         { .irq = 97 + OMAP54XX_IRQ_GIC_START },
2785         { .irq = -1 }
2786 };
2787
2788 static struct omap_hwmod_dma_info omap54xx_slimbus1_sdma_reqs[] = {
2789         { .name = "tx0", .dma_req = 84 + OMAP54XX_DMA_REQ_START },
2790         { .name = "tx1", .dma_req = 85 + OMAP54XX_DMA_REQ_START },
2791         { .name = "tx2", .dma_req = 86 + OMAP54XX_DMA_REQ_START },
2792         { .name = "tx3", .dma_req = 87 + OMAP54XX_DMA_REQ_START },
2793         { .name = "rx0", .dma_req = 88 + OMAP54XX_DMA_REQ_START },
2794         { .name = "rx1", .dma_req = 89 + OMAP54XX_DMA_REQ_START },
2795         { .name = "rx2", .dma_req = 90 + OMAP54XX_DMA_REQ_START },
2796         { .name = "rx3", .dma_req = 91 + OMAP54XX_DMA_REQ_START },
2797         { .dma_req = -1 }
2798 };
2799
2800 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2801         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2802 };
2803
2804 static struct omap_hwmod omap54xx_slimbus1_hwmod = {
2805         .name           = "slimbus1",
2806         .class          = &omap54xx_slimbus_hwmod_class,
2807         .clkdm_name     = "abe_clkdm",
2808         .mpu_irqs       = omap54xx_slimbus1_irqs,
2809         .sdma_reqs      = omap54xx_slimbus1_sdma_reqs,
2810         .main_clk       = "abe_iclk",
2811         .prcm = {
2812                 .omap4 = {
2813                         .clkctrl_offs = OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET,
2814                         .context_offs = OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET,
2815                         .modulemode   = MODULEMODE_SWCTRL,
2816                 },
2817         },
2818         .opt_clks       = slimbus1_opt_clks,
2819         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2820 };
2821
2822 /*
2823  * 'smartreflex' class
2824  * smartreflex module (monitor silicon performance and outputs a measure of
2825  * performance error)
2826  */
2827
2828 /* The IP is not compliant to type1 / type2 scheme */
2829 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2830         .sidle_shift    = 24,
2831         .enwkup_shift   = 26,
2832 };
2833
2834 static struct omap_hwmod_class_sysconfig omap54xx_smartreflex_sysc = {
2835         .sysc_offs      = 0x0038,
2836         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2837         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2838                            SIDLE_SMART_WKUP),
2839         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2840 };
2841
2842 static struct omap_hwmod_class omap54xx_smartreflex_hwmod_class = {
2843         .name   = "smartreflex",
2844         .sysc   = &omap54xx_smartreflex_sysc,
2845         .rev    = 2,
2846 };
2847
2848 /* smartreflex_core */
2849 static struct omap_hwmod_irq_info omap54xx_smartreflex_core_irqs[] = {
2850         { .irq = 19 + OMAP54XX_IRQ_GIC_START },
2851         { .irq = -1 }
2852 };
2853
2854 /* smartreflex_core dev_attr */
2855 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2856         .sensor_voltdm_name     = "core",
2857 };
2858
2859 static struct omap_hwmod omap54xx_smartreflex_core_hwmod = {
2860         .name           = "smartreflex_core",
2861         .class          = &omap54xx_smartreflex_hwmod_class,
2862         .clkdm_name     = "coreaon_clkdm",
2863         .mpu_irqs       = omap54xx_smartreflex_core_irqs,
2864         .main_clk       = "wkupaon_iclk_mux",
2865         .prcm = {
2866                 .omap4 = {
2867                         .clkctrl_offs = OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2868                         .context_offs = OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2869                         .modulemode   = MODULEMODE_SWCTRL,
2870                 },
2871         },
2872         .dev_attr       = &smartreflex_core_dev_attr,
2873 };
2874
2875 /* smartreflex_mm */
2876 static struct omap_hwmod_irq_info omap54xx_smartreflex_mm_irqs[] = {
2877         { .irq = 102 + OMAP54XX_IRQ_GIC_START },
2878         { .irq = -1 }
2879 };
2880
2881 /* smartreflex_mm dev_attr */
2882 static struct omap_smartreflex_dev_attr smartreflex_mm_dev_attr = {
2883         .sensor_voltdm_name     = "mm",
2884 };
2885
2886 static struct omap_hwmod omap54xx_smartreflex_mm_hwmod = {
2887         .name           = "smartreflex_mm",
2888         .class          = &omap54xx_smartreflex_hwmod_class,
2889         .clkdm_name     = "coreaon_clkdm",
2890         .mpu_irqs       = omap54xx_smartreflex_mm_irqs,
2891         .main_clk       = "wkupaon_iclk_mux",
2892         .prcm = {
2893                 .omap4 = {
2894                         .clkctrl_offs = OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET,
2895                         .context_offs = OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET,
2896                         .modulemode   = MODULEMODE_SWCTRL,
2897                 },
2898         },
2899         .dev_attr       = &smartreflex_mm_dev_attr,
2900 };
2901
2902 /* smartreflex_mpu */
2903 static struct omap_hwmod_irq_info omap54xx_smartreflex_mpu_irqs[] = {
2904         { .irq = 18 + OMAP54XX_IRQ_GIC_START },
2905         { .irq = -1 }
2906 };
2907
2908 /* smartreflex_mpu dev_attr */
2909 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2910         .sensor_voltdm_name     = "mpu",
2911 };
2912
2913 static struct omap_hwmod omap54xx_smartreflex_mpu_hwmod = {
2914         .name           = "smartreflex_mpu",
2915         .class          = &omap54xx_smartreflex_hwmod_class,
2916         .clkdm_name     = "coreaon_clkdm",
2917         .mpu_irqs       = omap54xx_smartreflex_mpu_irqs,
2918         .main_clk       = "wkupaon_iclk_mux",
2919         .prcm = {
2920                 .omap4 = {
2921                         .clkctrl_offs = OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2922                         .context_offs = OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2923                         .modulemode   = MODULEMODE_SWCTRL,
2924                 },
2925         },
2926         .dev_attr       = &smartreflex_mpu_dev_attr,
2927 };
2928
2929 /*
2930  * 'spinlock' class
2931  * spinlock provides hardware assistance for synchronizing the processes
2932  * running on multiple processors
2933  */
2934
2935 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
2936         .rev_offs       = 0x0000,
2937         .sysc_offs      = 0x0010,
2938         .syss_offs      = 0x0014,
2939         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2940                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2941                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2942         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2943                            SIDLE_SMART_WKUP),
2944         .sysc_fields    = &omap_hwmod_sysc_type1,
2945 };
2946
2947 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
2948         .name   = "spinlock",
2949         .sysc   = &omap54xx_spinlock_sysc,
2950 };
2951
2952 /* spinlock */
2953 static struct omap_hwmod omap54xx_spinlock_hwmod = {
2954         .name           = "spinlock",
2955         .class          = &omap54xx_spinlock_hwmod_class,
2956         .clkdm_name     = "l4cfg_clkdm",
2957         .main_clk       = "l4_root_clk_div",
2958         .prcm = {
2959                 .omap4 = {
2960                         .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2961                         .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2962                 },
2963         },
2964 };
2965
2966 /*
2967  * 'timer' class
2968  * general purpose timer module with accurate 1ms tick
2969  * This class contains several variants: ['timer_1ms', 'timer']
2970  */
2971
2972 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
2973         .rev_offs       = 0x0000,
2974         .sysc_offs      = 0x0010,
2975         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2976                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2977         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2978                            SIDLE_SMART_WKUP),
2979         .sysc_fields    = &omap_hwmod_sysc_type2,
2980         .clockact       = CLOCKACT_TEST_ICLK,
2981 };
2982
2983 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
2984         .name   = "timer",
2985         .sysc   = &omap54xx_timer_1ms_sysc,
2986 };
2987
2988 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
2989         .rev_offs       = 0x0000,
2990         .sysc_offs      = 0x0010,
2991         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2992                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2993         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2994                            SIDLE_SMART_WKUP),
2995         .sysc_fields    = &omap_hwmod_sysc_type2,
2996 };
2997
2998 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
2999         .name   = "timer",
3000         .sysc   = &omap54xx_timer_sysc,
3001 };
3002
3003 /* timer1 */
3004 static struct omap_hwmod_irq_info omap54xx_timer1_irqs[] = {
3005         { .irq = 37 + OMAP54XX_IRQ_GIC_START },
3006         { .irq = -1 }
3007 };
3008
3009 static struct omap_hwmod omap54xx_timer1_hwmod = {
3010         .name           = "timer1",
3011         .class          = &omap54xx_timer_1ms_hwmod_class,
3012         .clkdm_name     = "wkupaon_clkdm",
3013         .mpu_irqs       = omap54xx_timer1_irqs,
3014         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3015         .main_clk       = "timer1_gfclk_mux",
3016         .prcm = {
3017                 .omap4 = {
3018                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
3019                         .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
3020                         .modulemode   = MODULEMODE_SWCTRL,
3021                 },
3022         },
3023 };
3024
3025 /* timer2 */
3026 static struct omap_hwmod_irq_info omap54xx_timer2_irqs[] = {
3027         { .irq = 38 + OMAP54XX_IRQ_GIC_START },
3028         { .irq = -1 }
3029 };
3030
3031 static struct omap_hwmod omap54xx_timer2_hwmod = {
3032         .name           = "timer2",
3033         .class          = &omap54xx_timer_1ms_hwmod_class,
3034         .clkdm_name     = "l4per_clkdm",
3035         .mpu_irqs       = omap54xx_timer2_irqs,
3036         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3037         .main_clk       = "timer2_gfclk_mux",
3038         .prcm = {
3039                 .omap4 = {
3040                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
3041                         .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
3042                         .modulemode   = MODULEMODE_SWCTRL,
3043                 },
3044         },
3045 };
3046
3047 /* timer3 */
3048 static struct omap_hwmod_irq_info omap54xx_timer3_irqs[] = {
3049         { .irq = 39 + OMAP54XX_IRQ_GIC_START },
3050         { .irq = -1 }
3051 };
3052
3053 static struct omap_hwmod omap54xx_timer3_hwmod = {
3054         .name           = "timer3",
3055         .class          = &omap54xx_timer_hwmod_class,
3056         .clkdm_name     = "l4per_clkdm",
3057         .mpu_irqs       = omap54xx_timer3_irqs,
3058         .main_clk       = "timer3_gfclk_mux",
3059         .prcm = {
3060                 .omap4 = {
3061                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
3062                         .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
3063                         .modulemode   = MODULEMODE_SWCTRL,
3064                 },
3065         },
3066 };
3067
3068 /* timer4 */
3069 static struct omap_hwmod_irq_info omap54xx_timer4_irqs[] = {
3070         { .irq = 40 + OMAP54XX_IRQ_GIC_START },
3071         { .irq = -1 }
3072 };
3073
3074 static struct omap_hwmod omap54xx_timer4_hwmod = {
3075         .name           = "timer4",
3076         .class          = &omap54xx_timer_hwmod_class,
3077         .clkdm_name     = "l4per_clkdm",
3078         .mpu_irqs       = omap54xx_timer4_irqs,
3079         .main_clk       = "timer4_gfclk_mux",
3080         .prcm = {
3081                 .omap4 = {
3082                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
3083                         .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
3084                         .modulemode   = MODULEMODE_SWCTRL,
3085                 },
3086         },
3087 };
3088
3089 /* timer5 */
3090 static struct omap_hwmod_irq_info omap54xx_timer5_irqs[] = {
3091         { .irq = 41 + OMAP54XX_IRQ_GIC_START },
3092         { .irq = -1 }
3093 };
3094
3095 static struct omap_hwmod omap54xx_timer5_hwmod = {
3096         .name           = "timer5",
3097         .class          = &omap54xx_timer_hwmod_class,
3098         .clkdm_name     = "abe_clkdm",
3099         .mpu_irqs       = omap54xx_timer5_irqs,
3100         .main_clk       = "timer5_gfclk_mux",
3101         .prcm = {
3102                 .omap4 = {
3103                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
3104                         .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
3105                         .modulemode   = MODULEMODE_SWCTRL,
3106                 },
3107         },
3108 };
3109
3110 /* timer6 */
3111 static struct omap_hwmod_irq_info omap54xx_timer6_irqs[] = {
3112         { .irq = 42 + OMAP54XX_IRQ_GIC_START },
3113         { .irq = -1 }
3114 };
3115
3116 static struct omap_hwmod omap54xx_timer6_hwmod = {
3117         .name           = "timer6",
3118         .class          = &omap54xx_timer_hwmod_class,
3119         .clkdm_name     = "abe_clkdm",
3120         .mpu_irqs       = omap54xx_timer6_irqs,
3121         .main_clk       = "timer6_gfclk_mux",
3122         .prcm = {
3123                 .omap4 = {
3124                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
3125                         .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
3126                         .modulemode   = MODULEMODE_SWCTRL,
3127                 },
3128         },
3129 };
3130
3131 /* timer7 */
3132 static struct omap_hwmod_irq_info omap54xx_timer7_irqs[] = {
3133         { .irq = 43 + OMAP54XX_IRQ_GIC_START },
3134         { .irq = -1 }
3135 };
3136
3137 static struct omap_hwmod omap54xx_timer7_hwmod = {
3138         .name           = "timer7",
3139         .class          = &omap54xx_timer_hwmod_class,
3140         .clkdm_name     = "abe_clkdm",
3141         .mpu_irqs       = omap54xx_timer7_irqs,
3142         .main_clk       = "timer7_gfclk_mux",
3143         .prcm = {
3144                 .omap4 = {
3145                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
3146                         .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
3147                         .modulemode   = MODULEMODE_SWCTRL,
3148                 },
3149         },
3150 };
3151
3152 /* timer8 */
3153 static struct omap_hwmod_irq_info omap54xx_timer8_irqs[] = {
3154         { .irq = 44 + OMAP54XX_IRQ_GIC_START },
3155         { .irq = -1 }
3156 };
3157
3158 static struct omap_hwmod omap54xx_timer8_hwmod = {
3159         .name           = "timer8",
3160         .class          = &omap54xx_timer_hwmod_class,
3161         .clkdm_name     = "abe_clkdm",
3162         .mpu_irqs       = omap54xx_timer8_irqs,
3163         .main_clk       = "timer8_gfclk_mux",
3164         .prcm = {
3165                 .omap4 = {
3166                         .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
3167                         .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
3168                         .modulemode   = MODULEMODE_SWCTRL,
3169                 },
3170         },
3171 };
3172
3173 /* timer9 */
3174 static struct omap_hwmod_irq_info omap54xx_timer9_irqs[] = {
3175         { .irq = 45 + OMAP54XX_IRQ_GIC_START },
3176         { .irq = -1 }
3177 };
3178
3179 static struct omap_hwmod omap54xx_timer9_hwmod = {
3180         .name           = "timer9",
3181         .class          = &omap54xx_timer_hwmod_class,
3182         .clkdm_name     = "l4per_clkdm",
3183         .mpu_irqs       = omap54xx_timer9_irqs,
3184         .main_clk       = "timer9_gfclk_mux",
3185         .prcm = {
3186                 .omap4 = {
3187                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
3188                         .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
3189                         .modulemode   = MODULEMODE_SWCTRL,
3190                 },
3191         },
3192 };
3193
3194 /* timer10 */
3195 static struct omap_hwmod_irq_info omap54xx_timer10_irqs[] = {
3196         { .irq = 46 + OMAP54XX_IRQ_GIC_START },
3197         { .irq = -1 }
3198 };
3199
3200 static struct omap_hwmod omap54xx_timer10_hwmod = {
3201         .name           = "timer10",
3202         .class          = &omap54xx_timer_1ms_hwmod_class,
3203         .clkdm_name     = "l4per_clkdm",
3204         .mpu_irqs       = omap54xx_timer10_irqs,
3205         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3206         .main_clk       = "timer10_gfclk_mux",
3207         .prcm = {
3208                 .omap4 = {
3209                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
3210                         .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
3211                         .modulemode   = MODULEMODE_SWCTRL,
3212                 },
3213         },
3214 };
3215
3216 /* timer11 */
3217 static struct omap_hwmod_irq_info omap54xx_timer11_irqs[] = {
3218         { .irq = 47 + OMAP54XX_IRQ_GIC_START },
3219         { .irq = -1 }
3220 };
3221
3222 static struct omap_hwmod omap54xx_timer11_hwmod = {
3223         .name           = "timer11",
3224         .class          = &omap54xx_timer_hwmod_class,
3225         .clkdm_name     = "l4per_clkdm",
3226         .mpu_irqs       = omap54xx_timer11_irqs,
3227         .main_clk       = "timer11_gfclk_mux",
3228         .prcm = {
3229                 .omap4 = {
3230                         .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
3231                         .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
3232                         .modulemode   = MODULEMODE_SWCTRL,
3233                 },
3234         },
3235 };
3236
3237 /*
3238  * 'uart' class
3239  * universal asynchronous receiver/transmitter (uart)
3240  */
3241
3242 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
3243         .rev_offs       = 0x0050,
3244         .sysc_offs      = 0x0054,
3245         .syss_offs      = 0x0058,
3246         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3247                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3248                            SYSS_HAS_RESET_STATUS),
3249         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3250                            SIDLE_SMART_WKUP),
3251         .sysc_fields    = &omap_hwmod_sysc_type1,
3252 };
3253
3254 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
3255         .name   = "uart",
3256         .sysc   = &omap54xx_uart_sysc,
3257 };
3258
3259 /* uart1 */
3260 static struct omap_hwmod_irq_info omap54xx_uart1_irqs[] = {
3261         { .irq = 72 + OMAP54XX_IRQ_GIC_START },
3262         { .irq = -1 }
3263 };
3264
3265 static struct omap_hwmod_dma_info omap54xx_uart1_sdma_reqs[] = {
3266         { .name = "tx", .dma_req = 48 + OMAP54XX_DMA_REQ_START },
3267         { .name = "rx", .dma_req = 49 + OMAP54XX_DMA_REQ_START },
3268         { .dma_req = -1 }
3269 };
3270
3271 static struct omap_hwmod omap54xx_uart1_hwmod = {
3272         .name           = "uart1",
3273         .class          = &omap54xx_uart_hwmod_class,
3274         .clkdm_name     = "l4per_clkdm",
3275         .mpu_irqs       = omap54xx_uart1_irqs,
3276         .sdma_reqs      = omap54xx_uart1_sdma_reqs,
3277         .main_clk       = "func_48m_fclk",
3278         .flags          = HWMOD_SWSUP_SIDLE_ACT,
3279         .prcm = {
3280                 .omap4 = {
3281                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
3282                         .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
3283                         .modulemode   = MODULEMODE_SWCTRL,
3284                 },
3285         },
3286 };
3287
3288 /* uart2 */
3289 static struct omap_hwmod_irq_info omap54xx_uart2_irqs[] = {
3290         { .irq = 73 + OMAP54XX_IRQ_GIC_START },
3291         { .irq = -1 }
3292 };
3293
3294 static struct omap_hwmod_dma_info omap54xx_uart2_sdma_reqs[] = {
3295         { .name = "tx", .dma_req = 50 + OMAP54XX_DMA_REQ_START },
3296         { .name = "rx", .dma_req = 51 + OMAP54XX_DMA_REQ_START },
3297         { .dma_req = -1 }
3298 };
3299
3300 static struct omap_hwmod omap54xx_uart2_hwmod = {
3301         .name           = "uart2",
3302         .class          = &omap54xx_uart_hwmod_class,
3303         .clkdm_name     = "l4per_clkdm",
3304         .mpu_irqs       = omap54xx_uart2_irqs,
3305         .sdma_reqs      = omap54xx_uart2_sdma_reqs,
3306         .main_clk       = "func_48m_fclk",
3307         .flags          = HWMOD_SWSUP_SIDLE_ACT,
3308         .prcm = {
3309                 .omap4 = {
3310                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
3311                         .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
3312                         .modulemode   = MODULEMODE_SWCTRL,
3313                 },
3314         },
3315 };
3316
3317 /* uart3 */
3318 static struct omap_hwmod_irq_info omap54xx_uart3_irqs[] = {
3319         { .irq = 74 + OMAP54XX_IRQ_GIC_START },
3320         { .irq = -1 }
3321 };
3322
3323 static struct omap_hwmod_dma_info omap54xx_uart3_sdma_reqs[] = {
3324         { .name = "tx", .dma_req = 52 + OMAP54XX_DMA_REQ_START },
3325         { .name = "rx", .dma_req = 53 + OMAP54XX_DMA_REQ_START },
3326         { .dma_req = -1 }
3327 };
3328
3329 static struct omap_hwmod omap54xx_uart3_hwmod = {
3330         .name           = "uart3",
3331         .class          = &omap54xx_uart_hwmod_class,
3332         .clkdm_name     = "l4per_clkdm",
3333         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
3334                                 HWMOD_SWSUP_SIDLE_ACT,
3335         .mpu_irqs       = omap54xx_uart3_irqs,
3336         .sdma_reqs      = omap54xx_uart3_sdma_reqs,
3337         .main_clk       = "func_48m_fclk",
3338         .prcm = {
3339                 .omap4 = {
3340                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
3341                         .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
3342                         .modulemode   = MODULEMODE_SWCTRL,
3343                 },
3344         },
3345 };
3346
3347 /* uart4 */
3348 static struct omap_hwmod_irq_info omap54xx_uart4_irqs[] = {
3349         { .irq = 70 + OMAP54XX_IRQ_GIC_START },
3350         { .irq = -1 }
3351 };
3352
3353 static struct omap_hwmod_dma_info omap54xx_uart4_sdma_reqs[] = {
3354         { .name = "tx", .dma_req = 54 + OMAP54XX_DMA_REQ_START },
3355         { .name = "rx", .dma_req = 55 + OMAP54XX_DMA_REQ_START },
3356         { .dma_req = -1 }
3357 };
3358
3359 static struct omap_hwmod omap54xx_uart4_hwmod = {
3360         .name           = "uart4",
3361         .class          = &omap54xx_uart_hwmod_class,
3362         .clkdm_name     = "l4per_clkdm",
3363         .mpu_irqs       = omap54xx_uart4_irqs,
3364         .sdma_reqs      = omap54xx_uart4_sdma_reqs,
3365         .main_clk       = "func_48m_fclk",
3366         .flags          = HWMOD_SWSUP_SIDLE_ACT,
3367         .prcm = {
3368                 .omap4 = {
3369                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
3370                         .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
3371                         .modulemode   = MODULEMODE_SWCTRL,
3372                 },
3373         },
3374 };
3375
3376 /* uart5 */
3377 static struct omap_hwmod_irq_info omap54xx_uart5_irqs[] = {
3378         { .irq = 105 + OMAP54XX_IRQ_GIC_START },
3379         { .irq = -1 }
3380 };
3381
3382 static struct omap_hwmod_dma_info omap54xx_uart5_sdma_reqs[] = {
3383         { .name = "tx", .dma_req = 62 + OMAP54XX_DMA_REQ_START },
3384         { .name = "rx", .dma_req = 63 + OMAP54XX_DMA_REQ_START },
3385         { .dma_req = -1 }
3386 };
3387
3388 static struct omap_hwmod omap54xx_uart5_hwmod = {
3389         .name           = "uart5",
3390         .class          = &omap54xx_uart_hwmod_class,
3391         .clkdm_name     = "l4per_clkdm",
3392         .mpu_irqs       = omap54xx_uart5_irqs,
3393         .sdma_reqs      = omap54xx_uart5_sdma_reqs,
3394         .main_clk       = "func_48m_fclk",
3395         .flags          = HWMOD_SWSUP_SIDLE_ACT,
3396         .prcm = {
3397                 .omap4 = {
3398                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
3399                         .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
3400                         .modulemode   = MODULEMODE_SWCTRL,
3401                 },
3402         },
3403 };
3404
3405 /* uart6 */
3406 static struct omap_hwmod_irq_info omap54xx_uart6_irqs[] = {
3407         { .irq = 106 + OMAP54XX_IRQ_GIC_START },
3408         { .irq = -1 }
3409 };
3410
3411 static struct omap_hwmod_dma_info omap54xx_uart6_sdma_reqs[] = {
3412         { .name = "tx", .dma_req = 78 + OMAP54XX_DMA_REQ_START },
3413         { .name = "rx", .dma_req = 79 + OMAP54XX_DMA_REQ_START },
3414         { .dma_req = -1 }
3415 };
3416
3417 static struct omap_hwmod omap54xx_uart6_hwmod = {
3418         .name           = "uart6",
3419         .class          = &omap54xx_uart_hwmod_class,
3420         .clkdm_name     = "l4per_clkdm",
3421         .mpu_irqs       = omap54xx_uart6_irqs,
3422         .sdma_reqs      = omap54xx_uart6_sdma_reqs,
3423         .main_clk       = "func_48m_fclk",
3424         .flags          = HWMOD_SWSUP_SIDLE_ACT,
3425         .prcm = {
3426                 .omap4 = {
3427                         .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
3428                         .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
3429                         .modulemode   = MODULEMODE_SWCTRL,
3430                 },
3431         },
3432 };
3433
3434 /*
3435  * 'usb_host_hs' class
3436  * high-speed multi-port usb host controller
3437  */
3438
3439 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
3440         .rev_offs       = 0x0000,
3441         .sysc_offs      = 0x0010,
3442         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
3443                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3444         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3445                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3446                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3447         .sysc_fields    = &omap_hwmod_sysc_type2,
3448 };
3449
3450 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
3451         .name   = "usb_host_hs",
3452         .sysc   = &omap54xx_usb_host_hs_sysc,
3453 };
3454
3455 /* usb_host_hs */
3456 static struct omap_hwmod_irq_info omap54xx_usb_host_hs_irqs[] = {
3457         { .name = "ohci-irq", .irq = 76 + OMAP54XX_IRQ_GIC_START },
3458         { .name = "ehci-irq", .irq = 77 + OMAP54XX_IRQ_GIC_START },
3459         { .irq = -1 }
3460 };
3461
3462 static struct omap_hwmod_opt_clk usb_host_hs_opt_clks[] = {
3463         { .role = "hsic60m_p2_clk", .clk = "usb_host_hs_hsic60m_p2_clk" },
3464         { .role = "hsic60m_p3_clk", .clk = "usb_host_hs_hsic60m_p3_clk" },
3465         { .role = "utmi_p1_clk", .clk = "usb_host_hs_utmi_p1_clk" },
3466         { .role = "utmi_p2_clk", .clk = "usb_host_hs_utmi_p2_clk" },
3467         { .role = "utmi_p3_clk", .clk = "usb_host_hs_utmi_p3_clk" },
3468         { .role = "hsic480m_p1_clk", .clk = "usb_host_hs_hsic480m_p1_clk" },
3469         { .role = "hsic60m_p1_clk", .clk = "usb_host_hs_hsic60m_p1_clk" },
3470         { .role = "hsic480m_p3_clk", .clk = "usb_host_hs_hsic480m_p3_clk" },
3471         { .role = "hsic480m_p2_clk", .clk = "usb_host_hs_hsic480m_p2_clk" },
3472 };
3473
3474 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
3475         .name           = "usb_host_hs",
3476         .class          = &omap54xx_usb_host_hs_hwmod_class,
3477         .clkdm_name     = "l3init_clkdm",
3478         /*
3479          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3480          * id: i660
3481          *
3482          * Description:
3483          * In the following configuration :
3484          * - USBHOST module is set to smart-idle mode
3485          * - PRCM asserts idle_req to the USBHOST module ( This typically
3486          *   happens when the system is going to a low power mode : all ports
3487          *   have been suspended, the master part of the USBHOST module has
3488          *   entered the standby state, and SW has cut the functional clocks)
3489          * - an USBHOST interrupt occurs before the module is able to answer
3490          *   idle_ack, typically a remote wakeup IRQ.
3491          * Then the USB HOST module will enter a deadlock situation where it
3492          * is no more accessible nor functional.
3493          *
3494          * Workaround:
3495          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3496          */
3497
3498         /*
3499          * Errata: USB host EHCI may stall when entering smart-standby mode
3500          * Id: i571
3501          *
3502          * Description:
3503          * When the USBHOST module is set to smart-standby mode, and when it is
3504          * ready to enter the standby state (i.e. all ports are suspended and
3505          * all attached devices are in suspend mode), then it can wrongly assert
3506          * the Mstandby signal too early while there are still some residual OCP
3507          * transactions ongoing. If this condition occurs, the internal state
3508          * machine may go to an undefined state and the USB link may be stuck
3509          * upon the next resume.
3510          *
3511          * Workaround:
3512          * Don't use smart standby; use only force standby,
3513          * hence HWMOD_SWSUP_MSTANDBY
3514          */
3515
3516         /*
3517          * During system boot; If the hwmod framework resets the module
3518          * the module will have smart idle settings; which can lead to deadlock
3519          * (above Errata Id:i660); so, dont reset the module during boot;
3520          * Use HWMOD_INIT_NO_RESET.
3521          */
3522
3523         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3524                           HWMOD_INIT_NO_RESET,
3525         .mpu_irqs       = omap54xx_usb_host_hs_irqs,
3526         .main_clk       = "l3init_60m_fclk",
3527         .prcm = {
3528                 .omap4 = {
3529                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
3530                         .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
3531                         .modulemode   = MODULEMODE_SWCTRL,
3532                 },
3533         },
3534         .opt_clks       = usb_host_hs_opt_clks,
3535         .opt_clks_cnt   = ARRAY_SIZE(usb_host_hs_opt_clks),
3536 };
3537
3538 /*
3539  * 'usb_otg_ss' class
3540  * 2.0 super speed (usb_otg_ss) controller
3541  */
3542
3543 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
3544         .rev_offs       = 0x0000,
3545         .sysc_offs      = 0x0010,
3546         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
3547                            SYSC_HAS_SIDLEMODE),
3548         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3549                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3550                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3551         .sysc_fields    = &omap_hwmod_sysc_type2,
3552 };
3553
3554 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
3555         .name   = "usb_otg_ss",
3556         .sysc   = &omap54xx_usb_otg_ss_sysc,
3557 };
3558
3559 /* usb_otg_ss */
3560 static struct omap_hwmod_irq_info omap54xx_usb_otg_ss_irqs[] = {
3561         { .name = "core", .irq = 92 + OMAP54XX_IRQ_GIC_START },
3562         { .name = "wrp", .irq = 93 + OMAP54XX_IRQ_GIC_START },
3563         { .irq = -1 }
3564 };
3565
3566 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
3567         { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
3568 };
3569
3570 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
3571         .name           = "usb_otg_ss",
3572         .class          = &omap54xx_usb_otg_ss_hwmod_class,
3573         .clkdm_name     = "l3init_clkdm",
3574         .flags          = HWMOD_SWSUP_SIDLE,
3575         .mpu_irqs       = omap54xx_usb_otg_ss_irqs,
3576         .main_clk       = "dpll_core_h13x2_ck",
3577         .prcm = {
3578                 .omap4 = {
3579                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
3580                         .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
3581                         .modulemode   = MODULEMODE_HWCTRL,
3582                 },
3583         },
3584         .opt_clks       = usb_otg_ss_opt_clks,
3585         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
3586 };
3587
3588 /*
3589  * 'usb_tll_hs' class
3590  * usb_tll_hs module is the adapter on the usb_host_hs ports
3591  */
3592
3593 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
3594         .rev_offs       = 0x0000,
3595         .sysc_offs      = 0x0010,
3596         .syss_offs      = 0x0014,
3597         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3598                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3599                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3600         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3601         .sysc_fields    = &omap_hwmod_sysc_type1,
3602 };
3603
3604 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
3605         .name   = "usb_tll_hs",
3606         .sysc   = &omap54xx_usb_tll_hs_sysc,
3607 };
3608
3609 /* usb_tll_hs */
3610 static struct omap_hwmod_irq_info omap54xx_usb_tll_hs_irqs[] = {
3611         { .irq = 78 + OMAP54XX_IRQ_GIC_START },
3612         { .irq = -1 }
3613 };
3614
3615 static struct omap_hwmod_opt_clk usb_tll_hs_opt_clks[] = {
3616         { .role = "usb_ch2_clk", .clk = "usb_tll_hs_usb_ch2_clk" },
3617         { .role = "usb_ch0_clk", .clk = "usb_tll_hs_usb_ch0_clk" },
3618         { .role = "usb_ch1_clk", .clk = "usb_tll_hs_usb_ch1_clk" },
3619 };
3620
3621 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
3622         .name           = "usb_tll_hs",
3623         .class          = &omap54xx_usb_tll_hs_hwmod_class,
3624         .clkdm_name     = "l3init_clkdm",
3625         .mpu_irqs       = omap54xx_usb_tll_hs_irqs,
3626         .main_clk       = "l4_root_clk_div",
3627         .prcm = {
3628                 .omap4 = {
3629                         .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
3630                         .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
3631                         .modulemode   = MODULEMODE_HWCTRL,
3632                 },
3633         },
3634         .opt_clks       = usb_tll_hs_opt_clks,
3635         .opt_clks_cnt   = ARRAY_SIZE(usb_tll_hs_opt_clks),
3636 };
3637
3638 /*
3639  * 'wd_timer' class
3640  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3641  * overflow condition
3642  */
3643
3644 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
3645         .rev_offs       = 0x0000,
3646         .sysc_offs      = 0x0010,
3647         .syss_offs      = 0x0014,
3648         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3649                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3650         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3651                            SIDLE_SMART_WKUP),
3652         .sysc_fields    = &omap_hwmod_sysc_type1,
3653 };
3654
3655 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
3656         .name           = "wd_timer",
3657         .sysc           = &omap54xx_wd_timer_sysc,
3658         .pre_shutdown   = &omap2_wd_timer_disable,
3659 };
3660
3661 /* wd_timer2 */
3662 static struct omap_hwmod_irq_info omap54xx_wd_timer2_irqs[] = {
3663         { .irq = 80 + OMAP54XX_IRQ_GIC_START },
3664         { .irq = -1 }
3665 };
3666
3667 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
3668         .name           = "wd_timer2",
3669         .class          = &omap54xx_wd_timer_hwmod_class,
3670         .clkdm_name     = "wkupaon_clkdm",
3671         .mpu_irqs       = omap54xx_wd_timer2_irqs,
3672         .main_clk       = "sys_32k_ck",
3673         .prcm = {
3674                 .omap4 = {
3675                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
3676                         .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
3677                         .modulemode   = MODULEMODE_SWCTRL,
3678                 },
3679         },
3680 };
3681
3682 /* wd_timer3 */
3683 static struct omap_hwmod_irq_info omap54xx_wd_timer3_irqs[] = {
3684         { .irq = 36 + OMAP54XX_IRQ_GIC_START },
3685         { .irq = -1 }
3686 };
3687
3688 static struct omap_hwmod omap54xx_wd_timer3_hwmod = {
3689         .name           = "wd_timer3",
3690         .class          = &omap54xx_wd_timer_hwmod_class,
3691         .clkdm_name     = "abe_clkdm",
3692         .mpu_irqs       = omap54xx_wd_timer3_irqs,
3693         .main_clk       = "sys_32k_ck",
3694         .prcm = {
3695                 .omap4 = {
3696                         .clkctrl_offs = OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET,
3697                         .context_offs = OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET,
3698                         .modulemode   = MODULEMODE_SWCTRL,
3699                 },
3700         },
3701 };
3702
3703
3704 /*
3705  * Interfaces
3706  */
3707
3708 static struct omap_hwmod_addr_space omap54xx_dmm_addrs[] = {
3709         {
3710                 .pa_start       = 0x4e000000,
3711                 .pa_end         = 0x4e0007ff,
3712                 .flags          = ADDR_TYPE_RT
3713         },
3714         { }
3715 };
3716
3717 /* l3_main_1 -> dmm */
3718 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
3719         .master         = &omap54xx_l3_main_1_hwmod,
3720         .slave          = &omap54xx_dmm_hwmod,
3721         .clk            = "l3_iclk_div",
3722         .addr           = omap54xx_dmm_addrs,
3723         .user           = OCP_USER_SDMA,
3724 };
3725
3726 /* dmm -> emif_ocp_fw */
3727 static struct omap_hwmod_ocp_if omap54xx_dmm__emif_ocp_fw = {
3728         .master         = &omap54xx_dmm_hwmod,
3729         .slave          = &omap54xx_emif_ocp_fw_hwmod,
3730         .clk            = "l3_iclk_div",
3731         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3732 };
3733
3734 static struct omap_hwmod_addr_space omap54xx_emif_ocp_fw_addrs[] = {
3735         {
3736                 .pa_start       = 0x4a20c000,
3737                 .pa_end         = 0x4a20c0ff,
3738         },
3739         { }
3740 };
3741
3742 /* l4_cfg -> emif_ocp_fw */
3743 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__emif_ocp_fw = {
3744         .master         = &omap54xx_l4_cfg_hwmod,
3745         .slave          = &omap54xx_emif_ocp_fw_hwmod,
3746         .clk            = "l3_iclk_div",
3747         .addr           = omap54xx_emif_ocp_fw_addrs,
3748         .user           = OCP_USER_MPU,
3749 };
3750
3751 /* l3_main_3 -> l3_instr */
3752 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
3753         .master         = &omap54xx_l3_main_3_hwmod,
3754         .slave          = &omap54xx_l3_instr_hwmod,
3755         .clk            = "l3_iclk_div",
3756         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3757 };
3758
3759 /* ocp_wp_noc -> l3_instr */
3760 static struct omap_hwmod_ocp_if omap54xx_ocp_wp_noc__l3_instr = {
3761         .master         = &omap54xx_ocp_wp_noc_hwmod,
3762         .slave          = &omap54xx_l3_instr_hwmod,
3763         .clk            = "l3_iclk_div",
3764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3765 };
3766
3767 /* l3_main_2 -> l3_main_1 */
3768 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
3769         .master         = &omap54xx_l3_main_2_hwmod,
3770         .slave          = &omap54xx_l3_main_1_hwmod,
3771         .clk            = "l3_iclk_div",
3772         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3773 };
3774
3775 /* l4_cfg -> l3_main_1 */
3776 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
3777         .master         = &omap54xx_l4_cfg_hwmod,
3778         .slave          = &omap54xx_l3_main_1_hwmod,
3779         .clk            = "l3_iclk_div",
3780         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3781 };
3782
3783 static struct omap_hwmod_addr_space omap54xx_l3_main_1_addrs[] = {
3784         {
3785                 .pa_start       = 0x44000000,
3786                 .pa_end         = 0x44001fff,
3787         },
3788         { }
3789 };
3790
3791 /* mpu -> l3_main_1 */
3792 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
3793         .master         = &omap54xx_mpu_hwmod,
3794         .slave          = &omap54xx_l3_main_1_hwmod,
3795         .clk            = "l3_iclk_div",
3796         .addr           = omap54xx_l3_main_1_addrs,
3797         .user           = OCP_USER_MPU,
3798 };
3799
3800 static struct omap_hwmod_addr_space omap54xx_l3_main_2_addrs[] = {
3801         {
3802                 .pa_start       = 0x44800000,
3803                 .pa_end         = 0x44802fff,
3804         },
3805         { }
3806 };
3807
3808 /* l3_main_1 -> l3_main_2 */
3809 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
3810         .master         = &omap54xx_l3_main_1_hwmod,
3811         .slave          = &omap54xx_l3_main_2_hwmod,
3812         .clk            = "l3_iclk_div",
3813         .addr           = omap54xx_l3_main_2_addrs,
3814         .user           = OCP_USER_MPU,
3815 };
3816
3817 /* l4_cfg -> l3_main_2 */
3818 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
3819         .master         = &omap54xx_l4_cfg_hwmod,
3820         .slave          = &omap54xx_l3_main_2_hwmod,
3821         .clk            = "l3_iclk_div",
3822         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3823 };
3824
3825 static struct omap_hwmod_addr_space omap54xx_l3_main_3_addrs[] = {
3826         {
3827                 .pa_start       = 0x45000000,
3828                 .pa_end         = 0x45003fff,
3829         },
3830         { }
3831 };
3832
3833 /* l3_main_1 -> l3_main_3 */
3834 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
3835         .master         = &omap54xx_l3_main_1_hwmod,
3836         .slave          = &omap54xx_l3_main_3_hwmod,
3837         .clk            = "l3_iclk_div",
3838         .addr           = omap54xx_l3_main_3_addrs,
3839         .user           = OCP_USER_MPU,
3840 };
3841
3842 /* l3_main_2 -> l3_main_3 */
3843 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
3844         .master         = &omap54xx_l3_main_2_hwmod,
3845         .slave          = &omap54xx_l3_main_3_hwmod,
3846         .clk            = "l3_iclk_div",
3847         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3848 };
3849
3850 /* l4_cfg -> l3_main_3 */
3851 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
3852         .master         = &omap54xx_l4_cfg_hwmod,
3853         .slave          = &omap54xx_l3_main_3_hwmod,
3854         .clk            = "l3_iclk_div",
3855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3856 };
3857
3858 /* l3_main_1 -> l4_abe */
3859 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
3860         .master         = &omap54xx_l3_main_1_hwmod,
3861         .slave          = &omap54xx_l4_abe_hwmod,
3862         .clk            = "abe_iclk",
3863         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3864 };
3865
3866 /* mpu -> l4_abe */
3867 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
3868         .master         = &omap54xx_mpu_hwmod,
3869         .slave          = &omap54xx_l4_abe_hwmod,
3870         .clk            = "abe_iclk",
3871         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3872 };
3873
3874 /* l3_main_1 -> l4_cfg */
3875 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
3876         .master         = &omap54xx_l3_main_1_hwmod,
3877         .slave          = &omap54xx_l4_cfg_hwmod,
3878         .clk            = "l4_root_clk_div",
3879         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3880 };
3881
3882 /* l3_main_2 -> l4_per */
3883 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
3884         .master         = &omap54xx_l3_main_2_hwmod,
3885         .slave          = &omap54xx_l4_per_hwmod,
3886         .clk            = "l4_root_clk_div",
3887         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3888 };
3889
3890 /* l3_main_1 -> l4_wkup */
3891 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
3892         .master         = &omap54xx_l3_main_1_hwmod,
3893         .slave          = &omap54xx_l4_wkup_hwmod,
3894         .clk            = "wkupaon_iclk_mux",
3895         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3896 };
3897
3898 /* mpu -> mpu_private */
3899 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
3900         .master         = &omap54xx_mpu_hwmod,
3901         .slave          = &omap54xx_mpu_private_hwmod,
3902         .clk            = "l3_iclk_div",
3903         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3904 };
3905
3906 /* l3_main_3 -> ocp_wp_noc */
3907 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__ocp_wp_noc = {
3908         .master         = &omap54xx_l3_main_3_hwmod,
3909         .slave          = &omap54xx_ocp_wp_noc_hwmod,
3910         .clk            = "l3_iclk_div",
3911         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3912 };
3913
3914 static struct omap_hwmod_addr_space omap54xx_ocp_wp_noc_addrs[] = {
3915         {
3916                 .pa_start       = 0x4a102000,
3917                 .pa_end         = 0x4a10207f,
3918                 .flags          = ADDR_TYPE_RT
3919         },
3920         { }
3921 };
3922
3923 /* l4_cfg -> ocp_wp_noc */
3924 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp_wp_noc = {
3925         .master         = &omap54xx_l4_cfg_hwmod,
3926         .slave          = &omap54xx_ocp_wp_noc_hwmod,
3927         .clk            = "l3_iclk_div",
3928         .addr           = omap54xx_ocp_wp_noc_addrs,
3929         .user           = OCP_USER_MPU,
3930 };
3931
3932 static struct omap_hwmod_addr_space omap54xx_aess_addrs[] = {
3933         {
3934                 .name           = "aess",
3935                 .pa_start       = 0x401f1000,
3936                 .pa_end         = 0x401f13ff,
3937                 .flags          = ADDR_TYPE_RT
3938         },
3939         { }
3940 };
3941
3942 /* l4_abe -> aess */
3943 static struct omap_hwmod_ocp_if omap54xx_l4_abe__aess = {
3944         .master         = &omap54xx_l4_abe_hwmod,
3945         .slave          = &omap54xx_aess_hwmod,
3946         .clk            = "abe_iclk",
3947         .addr           = omap54xx_aess_addrs,
3948         .user           = OCP_USER_MPU,
3949 };
3950
3951 /* l3_main_2 -> bb2d */
3952 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__bb2d = {
3953         .master         = &omap54xx_l3_main_2_hwmod,
3954         .slave          = &omap54xx_bb2d_hwmod,
3955         .clk            = "l3_iclk_div",
3956         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3957 };
3958
3959 static struct omap_hwmod_addr_space omap54xx_c2c_addrs[] = {
3960         {
3961                 .pa_start       = 0x5c000000,
3962                 .pa_end         = 0x5c0000ff,
3963                 .flags          = ADDR_TYPE_RT
3964         },
3965         { }
3966 };
3967
3968 /* l3_main_2 -> c2c */
3969 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__c2c = {
3970         .master         = &omap54xx_l3_main_2_hwmod,
3971         .slave          = &omap54xx_c2c_hwmod,
3972         .clk            = "c2c_fclk",
3973         .addr           = omap54xx_c2c_addrs,
3974         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3975 };
3976
3977 static struct omap_hwmod_addr_space omap54xx_counter_32k_addrs[] = {
3978         {
3979                 .pa_start       = 0x4ae04000,
3980                 .pa_end         = 0x4ae0403f,
3981                 .flags          = ADDR_TYPE_RT
3982         },
3983         { }
3984 };
3985
3986 /* l4_wkup -> counter_32k */
3987 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
3988         .master         = &omap54xx_l4_wkup_hwmod,
3989         .slave          = &omap54xx_counter_32k_hwmod,
3990         .clk            = "wkupaon_iclk_mux",
3991         .addr           = omap54xx_counter_32k_addrs,
3992         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3993 };
3994
3995 static struct omap_hwmod_addr_space omap54xx_ctrl_module_core_addrs[] = {
3996         {
3997                 .name           = "omap_control_core_core",
3998                 .pa_start       = 0x4a002000,
3999                 .pa_end         = 0x4a0027ff,
4000                 .flags          = ADDR_TYPE_RT
4001         },
4002         {
4003                 .name           = "omap_control_core_pad",
4004                 .pa_start       = 0x4a002800,
4005                 .pa_end         = 0x4a002fff,
4006                 .flags          = ADDR_TYPE_RT
4007         },
4008         { }
4009 };
4010
4011 /* l4_cfg -> ctrl_module_core */
4012 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ctrl_module_core = {
4013         .master         = &omap54xx_l4_cfg_hwmod,
4014         .slave          = &omap54xx_ctrl_module_core_hwmod,
4015         .clk            = "l4_root_clk_div",
4016         .addr           = omap54xx_ctrl_module_core_addrs,
4017         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4018 };
4019
4020 static struct omap_hwmod_addr_space omap54xx_ctrl_module_wkup_addrs[] = {
4021         {
4022                 .name           = "omap_control_wkup_core",
4023                 .pa_start       = 0x4ae0c000,
4024                 .pa_end         = 0x4ae0c7ff,
4025                 .flags          = ADDR_TYPE_RT
4026         },
4027         {
4028                 .name           = "omap_control_wkup_pad",
4029                 .pa_start       = 0x4ae0c800,
4030                 .pa_end         = 0x4ae0cfff,
4031                 .flags          = ADDR_TYPE_RT
4032         },
4033         { }
4034 };
4035
4036 /* l4_wkup -> ctrl_module_wkup */
4037 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__ctrl_module_wkup = {
4038         .master         = &omap54xx_l4_wkup_hwmod,
4039         .slave          = &omap54xx_ctrl_module_wkup_hwmod,
4040         .clk            = "wkupaon_iclk_mux",
4041         .addr           = omap54xx_ctrl_module_wkup_addrs,
4042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4043 };
4044
4045 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
4046         {
4047                 .pa_start       = 0x4a056000,
4048                 .pa_end         = 0x4a056fff,
4049                 .flags          = ADDR_TYPE_RT
4050         },
4051         { }
4052 };
4053
4054 /* l4_cfg -> dma_system */
4055 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
4056         .master         = &omap54xx_l4_cfg_hwmod,
4057         .slave          = &omap54xx_dma_system_hwmod,
4058         .clk            = "l4_root_clk_div",
4059         .addr           = omap54xx_dma_system_addrs,
4060         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4061 };
4062
4063 static struct omap_hwmod_addr_space omap54xx_dmic_addrs[] = {
4064         {
4065                 .name           = "mpu",
4066                 .pa_start       = 0x4012e000,
4067                 .pa_end         = 0x4012e07f,
4068                 .flags          = ADDR_TYPE_RT
4069         },
4070         { }
4071 };
4072
4073 /* l4_abe -> dmic */
4074 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
4075         .master         = &omap54xx_l4_abe_hwmod,
4076         .slave          = &omap54xx_dmic_hwmod,
4077         .clk            = "abe_iclk",
4078         .addr           = omap54xx_dmic_addrs,
4079         .user           = OCP_USER_MPU,
4080 };
4081
4082 /* l4_cfg -> dsp */
4083 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dsp = {
4084         .master         = &omap54xx_l4_cfg_hwmod,
4085         .slave          = &omap54xx_dsp_hwmod,
4086         .clk            = "l4_root_clk_div",
4087         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4088 };
4089
4090 static struct omap_hwmod_addr_space omap54xx_dss_addrs[] = {
4091         {
4092                 .pa_start       = 0x58000000,
4093                 .pa_end         = 0x5800007f,
4094                 .flags          = ADDR_TYPE_RT
4095         },
4096         { }
4097 };
4098
4099 /* l3_main_2 -> dss */
4100 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
4101         .master         = &omap54xx_l3_main_2_hwmod,
4102         .slave          = &omap54xx_dss_hwmod,
4103         .clk            = "l3_iclk_div",
4104         .addr           = omap54xx_dss_addrs,
4105         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4106 };
4107
4108 static struct omap_hwmod_addr_space omap54xx_dss_dispc_addrs[] = {
4109         {
4110                 .pa_start       = 0x58001000,
4111                 .pa_end         = 0x58001fff,
4112                 .flags          = ADDR_TYPE_RT
4113         },
4114         { }
4115 };
4116
4117 /* l3_main_2 -> dss_dispc */
4118 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
4119         .master         = &omap54xx_l3_main_2_hwmod,
4120         .slave          = &omap54xx_dss_dispc_hwmod,
4121         .clk            = "l3_iclk_div",
4122         .addr           = omap54xx_dss_dispc_addrs,
4123         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4124 };
4125
4126 static struct omap_hwmod_addr_space omap54xx_dss_dsi1_a_addrs[] = {
4127         {
4128                 .pa_start       = 0x58004000,
4129                 .pa_end         = 0x580041ff,
4130                 .flags          = ADDR_TYPE_RT
4131         },
4132         { }
4133 };
4134
4135 /* l3_main_2 -> dss_dsi1_a */
4136 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
4137         .master         = &omap54xx_l3_main_2_hwmod,
4138         .slave          = &omap54xx_dss_dsi1_a_hwmod,
4139         .clk            = "l3_iclk_div",
4140         .addr           = omap54xx_dss_dsi1_a_addrs,
4141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4142 };
4143
4144 static struct omap_hwmod_addr_space omap54xx_dss_dsi1_b_addrs[] = {
4145         {
4146                 .pa_start       = 0x58005000,
4147                 .pa_end         = 0x580051ff,
4148                 .flags          = ADDR_TYPE_RT
4149         },
4150         { }
4151 };
4152
4153 /* l3_main_2 -> dss_dsi1_b */
4154 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_b = {
4155         .master         = &omap54xx_l3_main_2_hwmod,
4156         .slave          = &omap54xx_dss_dsi1_b_hwmod,
4157         .clk            = "l3_iclk_div",
4158         .addr           = omap54xx_dss_dsi1_b_addrs,
4159         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4160 };
4161
4162 static struct omap_hwmod_addr_space omap54xx_dss_dsi1_c_addrs[] = {
4163         {
4164                 .pa_start       = 0x58009000,
4165                 .pa_end         = 0x580091ff,
4166                 .flags          = ADDR_TYPE_RT
4167         },
4168         { }
4169 };
4170
4171 /* l3_main_2 -> dss_dsi1_c */
4172 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
4173         .master         = &omap54xx_l3_main_2_hwmod,
4174         .slave          = &omap54xx_dss_dsi1_c_hwmod,
4175         .clk            = "l3_iclk_div",
4176         .addr           = omap54xx_dss_dsi1_c_addrs,
4177         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4178 };
4179
4180 static struct omap_hwmod_addr_space omap54xx_dss_hdmi_addrs[] = {
4181         {
4182                 .name           = "hdmi_wp",
4183                 .pa_start       = 0x58040000,
4184                 .pa_end         = 0x580400ff,
4185                 .flags          = ADDR_TYPE_RT
4186         },
4187         {
4188                 .name           = "pllctrl",
4189                 .pa_start       = 0x58040200,
4190                 .pa_end         = 0x5804023f,
4191         },
4192         {
4193                 .name           = "hdmitxphy",
4194                 .pa_start       = 0x58040300,
4195                 .pa_end         = 0x5804033f,
4196         },
4197         {
4198                 .name           = "hdmi_core",
4199                 .pa_start       = 0x58060000,
4200                 .pa_end         = 0x58078fff,
4201         },
4202         { }
4203 };
4204
4205 /* l3_main_2 -> dss_hdmi */
4206 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
4207         .master         = &omap54xx_l3_main_2_hwmod,
4208         .slave          = &omap54xx_dss_hdmi_hwmod,
4209         .clk            = "l3_iclk_div",
4210         .addr           = omap54xx_dss_hdmi_addrs,
4211         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4212 };
4213
4214 static struct omap_hwmod_addr_space omap54xx_dss_rfbi_addrs[] = {
4215         {
4216                 .pa_start       = 0x58002000,
4217                 .pa_end         = 0x580020ff,
4218                 .flags          = ADDR_TYPE_RT
4219         },
4220         { }
4221 };
4222
4223 /* l3_main_2 -> dss_rfbi */
4224 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
4225         .master         = &omap54xx_l3_main_2_hwmod,
4226         .slave          = &omap54xx_dss_rfbi_hwmod,
4227         .clk            = "l3_iclk_div",
4228         .addr           = omap54xx_dss_rfbi_addrs,
4229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4230 };
4231
4232 static struct omap_hwmod_addr_space omap54xx_elm_addrs[] = {
4233         {
4234                 .pa_start       = 0x48078000,
4235                 .pa_end         = 0x48078fff,
4236                 .flags          = ADDR_TYPE_RT
4237         },
4238         { }
4239 };
4240
4241 /* l4_per -> elm */
4242 static struct omap_hwmod_ocp_if omap54xx_l4_per__elm = {
4243         .master         = &omap54xx_l4_per_hwmod,
4244         .slave          = &omap54xx_elm_hwmod,
4245         .clk            = "l4_root_clk_div",
4246         .addr           = omap54xx_elm_addrs,
4247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4248 };
4249
4250 /* emif_ocp_fw -> emif1 */
4251 static struct omap_hwmod_ocp_if omap54xx_emif_ocp_fw__emif1 = {
4252         .master         = &omap54xx_emif_ocp_fw_hwmod,
4253         .slave          = &omap54xx_emif1_hwmod,
4254         .clk            = "dpll_core_h11x2_ck",
4255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4256 };
4257
4258 static struct omap_hwmod_addr_space omap54xx_emif1_addrs[] = {
4259         {
4260                 .pa_start       = 0x4c000000,
4261                 .pa_end         = 0x4c0003ff,
4262                 .flags          = ADDR_TYPE_RT
4263         },
4264         { }
4265 };
4266
4267 /* mpu -> emif1 */
4268 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
4269         .master         = &omap54xx_mpu_hwmod,
4270         .slave          = &omap54xx_emif1_hwmod,
4271         .clk            = "dpll_core_h11x2_ck",
4272         .addr           = omap54xx_emif1_addrs,
4273         .user           = OCP_USER_MPU,
4274 };
4275
4276 /* emif_ocp_fw -> emif2 */
4277 static struct omap_hwmod_ocp_if omap54xx_emif_ocp_fw__emif2 = {
4278         .master         = &omap54xx_emif_ocp_fw_hwmod,
4279         .slave          = &omap54xx_emif2_hwmod,
4280         .clk            = "dpll_core_h11x2_ck",
4281         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4282 };
4283
4284 static struct omap_hwmod_addr_space omap54xx_emif2_addrs[] = {
4285         {
4286                 .pa_start       = 0x4d000000,
4287                 .pa_end         = 0x4d0003ff,
4288                 .flags          = ADDR_TYPE_RT
4289         },
4290         { }
4291 };
4292
4293 /* mpu -> emif2 */
4294 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
4295         .master         = &omap54xx_mpu_hwmod,
4296         .slave          = &omap54xx_emif2_hwmod,
4297         .clk            = "dpll_core_h11x2_ck",
4298         .addr           = omap54xx_emif2_addrs,
4299         .user           = OCP_USER_MPU,
4300 };
4301
4302 static struct omap_hwmod_addr_space omap54xx_fdif_addrs[] = {
4303         {
4304                 .pa_start       = 0x4a10a000,
4305                 .pa_end         = 0x4a10a3ff,
4306                 .flags          = ADDR_TYPE_RT
4307         },
4308         { }
4309 };
4310
4311 /* l4_cfg -> fdif */
4312 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__fdif = {
4313         .master         = &omap54xx_l4_cfg_hwmod,
4314         .slave          = &omap54xx_fdif_hwmod,
4315         .clk            = "l4_root_clk_div",
4316         .addr           = omap54xx_fdif_addrs,
4317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4318 };
4319
4320 static struct omap_hwmod_addr_space omap54xx_gpio1_addrs[] = {
4321         {
4322                 .pa_start       = 0x4ae10000,
4323                 .pa_end         = 0x4ae101ff,
4324                 .flags          = ADDR_TYPE_RT
4325         },
4326         { }
4327 };
4328
4329 /* l4_wkup -> gpio1 */
4330 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
4331         .master         = &omap54xx_l4_wkup_hwmod,
4332         .slave          = &omap54xx_gpio1_hwmod,
4333         .clk            = "wkupaon_iclk_mux",
4334         .addr           = omap54xx_gpio1_addrs,
4335         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4336 };
4337
4338 static struct omap_hwmod_addr_space omap54xx_gpio2_addrs[] = {
4339         {
4340                 .pa_start       = 0x48055000,
4341                 .pa_end         = 0x480551ff,
4342                 .flags          = ADDR_TYPE_RT
4343         },
4344         { }
4345 };
4346
4347 /* l4_per -> gpio2 */
4348 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
4349         .master         = &omap54xx_l4_per_hwmod,
4350         .slave          = &omap54xx_gpio2_hwmod,
4351         .clk            = "l4_root_clk_div",
4352         .addr           = omap54xx_gpio2_addrs,
4353         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4354 };
4355
4356 static struct omap_hwmod_addr_space omap54xx_gpio3_addrs[] = {
4357         {
4358                 .pa_start       = 0x48057000,
4359                 .pa_end         = 0x480571ff,
4360                 .flags          = ADDR_TYPE_RT
4361         },
4362         { }
4363 };
4364
4365 /* l4_per -> gpio3 */
4366 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
4367         .master         = &omap54xx_l4_per_hwmod,
4368         .slave          = &omap54xx_gpio3_hwmod,
4369         .clk            = "l4_root_clk_div",
4370         .addr           = omap54xx_gpio3_addrs,
4371         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4372 };
4373
4374 static struct omap_hwmod_addr_space omap54xx_gpio4_addrs[] = {
4375         {
4376                 .pa_start       = 0x48059000,
4377                 .pa_end         = 0x480591ff,
4378                 .flags          = ADDR_TYPE_RT
4379         },
4380         { }
4381 };
4382
4383 /* l4_per -> gpio4 */
4384 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
4385         .master         = &omap54xx_l4_per_hwmod,
4386         .slave          = &omap54xx_gpio4_hwmod,
4387         .clk            = "l4_root_clk_div",
4388         .addr           = omap54xx_gpio4_addrs,
4389         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4390 };
4391
4392 static struct omap_hwmod_addr_space omap54xx_gpio5_addrs[] = {
4393         {
4394                 .pa_start       = 0x4805b000,
4395                 .pa_end         = 0x4805b1ff,
4396                 .flags          = ADDR_TYPE_RT
4397         },
4398         { }
4399 };
4400
4401 /* l4_per -> gpio5 */
4402 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
4403         .master         = &omap54xx_l4_per_hwmod,
4404         .slave          = &omap54xx_gpio5_hwmod,
4405         .clk            = "l4_root_clk_div",
4406         .addr           = omap54xx_gpio5_addrs,
4407         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4408 };
4409
4410 static struct omap_hwmod_addr_space omap54xx_gpio6_addrs[] = {
4411         {
4412                 .pa_start       = 0x4805d000,
4413                 .pa_end         = 0x4805d1ff,
4414                 .flags          = ADDR_TYPE_RT
4415         },
4416         { }
4417 };
4418
4419 /* l4_per -> gpio6 */
4420 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
4421         .master         = &omap54xx_l4_per_hwmod,
4422         .slave          = &omap54xx_gpio6_hwmod,
4423         .clk            = "l4_root_clk_div",
4424         .addr           = omap54xx_gpio6_addrs,
4425         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4426 };
4427
4428 static struct omap_hwmod_addr_space omap54xx_gpio7_addrs[] = {
4429         {
4430                 .pa_start       = 0x48051000,
4431                 .pa_end         = 0x480511ff,
4432                 .flags          = ADDR_TYPE_RT
4433         },
4434         { }
4435 };
4436
4437 /* l4_per -> gpio7 */
4438 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
4439         .master         = &omap54xx_l4_per_hwmod,
4440         .slave          = &omap54xx_gpio7_hwmod,
4441         .clk            = "l4_root_clk_div",
4442         .addr           = omap54xx_gpio7_addrs,
4443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4444 };
4445
4446 static struct omap_hwmod_addr_space omap54xx_gpio8_addrs[] = {
4447         {
4448                 .pa_start       = 0x48053000,
4449                 .pa_end         = 0x480531ff,
4450                 .flags          = ADDR_TYPE_RT
4451         },
4452         { }
4453 };
4454
4455 /* l4_per -> gpio8 */
4456 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
4457         .master         = &omap54xx_l4_per_hwmod,
4458         .slave          = &omap54xx_gpio8_hwmod,
4459         .clk            = "l4_root_clk_div",
4460         .addr           = omap54xx_gpio8_addrs,
4461         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4462 };
4463
4464 static struct omap_hwmod_addr_space omap54xx_gpmc_addrs[] = {
4465         {
4466                 .pa_start       = 0x50000000,
4467                 .pa_end         = 0x500003ff,
4468                 .flags          = ADDR_TYPE_RT
4469         },
4470         { }
4471 };
4472
4473 /* l3_main_2 -> gpmc */
4474 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__gpmc = {
4475         .master         = &omap54xx_l3_main_2_hwmod,
4476         .slave          = &omap54xx_gpmc_hwmod,
4477         .clk            = "l3_iclk_div",
4478         .addr           = omap54xx_gpmc_addrs,
4479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4480 };
4481
4482 static struct omap_hwmod_addr_space omap54xx_gpu_addrs[] = {
4483         {
4484                 .name           = "klio",
4485                 .pa_start       = 0x56000000,
4486                 .pa_end         = 0x56001fff,
4487         },
4488         {
4489                 .name           = "hydra2",
4490                 .pa_start       = 0x56004000,
4491                 .pa_end         = 0x56004fff,
4492         },
4493         {
4494                 .name           = "klio_0",
4495                 .pa_start       = 0x56008000,
4496                 .pa_end         = 0x56009fff,
4497         },
4498         {
4499                 .name           = "klio_1",
4500                 .pa_start       = 0x5600c000,
4501                 .pa_end         = 0x5600dfff,
4502         },
4503         {
4504                 .name           = "klio_hl",
4505                 .pa_start       = 0x5600fe00,
4506                 .pa_end         = 0x5600ffff,
4507                 .flags          = ADDR_TYPE_RT
4508         },
4509         { }
4510 };
4511
4512 /* l3_main_2 -> gpu */
4513 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__gpu = {
4514         .master         = &omap54xx_l3_main_2_hwmod,
4515         .slave          = &omap54xx_gpu_hwmod,
4516         .clk            = "gpu_l3_iclk",
4517         .addr           = omap54xx_gpu_addrs,
4518         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4519 };
4520
4521 static struct omap_hwmod_addr_space omap54xx_hdq1w_addrs[] = {
4522         {
4523                 .pa_start       = 0x480b2000,
4524                 .pa_end         = 0x480b201f,
4525                 .flags          = ADDR_TYPE_RT
4526         },
4527         { }
4528 };
4529
4530 /* l4_per -> hdq1w */
4531 static struct omap_hwmod_ocp_if omap54xx_l4_per__hdq1w = {
4532         .master         = &omap54xx_l4_per_hwmod,
4533         .slave          = &omap54xx_hdq1w_hwmod,
4534         .clk            = "l4_root_clk_div",
4535         .addr           = omap54xx_hdq1w_addrs,
4536         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4537 };
4538
4539 static struct omap_hwmod_addr_space omap54xx_hsi_addrs[] = {
4540         {
4541                 .name           = "system_32",
4542                 .pa_start       = 0x4a058000,
4543                 .pa_end         = 0x4a059fff,
4544                 .flags          = ADDR_TYPE_RT
4545         },
4546         {
4547                 .name           = "dte_channels",
4548                 .pa_start       = 0x4a059800,
4549                 .pa_end         = 0x4a059bff,
4550         },
4551         {
4552                 .name           = "hsi_32",
4553                 .pa_start       = 0x4a05a000,
4554                 .pa_end         = 0x4a05bfff,
4555         },
4556         { }
4557 };
4558
4559 /* l4_cfg -> hsi */
4560 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__hsi = {
4561         .master         = &omap54xx_l4_cfg_hwmod,
4562         .slave          = &omap54xx_hsi_hwmod,
4563         .clk            = "l3_iclk_div",
4564         .addr           = omap54xx_hsi_addrs,
4565         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4566 };
4567
4568 static struct omap_hwmod_addr_space omap54xx_i2c1_addrs[] = {
4569         {
4570                 .pa_start       = 0x48070000,
4571                 .pa_end         = 0x480700ff,
4572                 .flags          = ADDR_TYPE_RT
4573         },
4574         { }
4575 };
4576
4577 /* l4_per -> i2c1 */
4578 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
4579         .master         = &omap54xx_l4_per_hwmod,
4580         .slave          = &omap54xx_i2c1_hwmod,
4581         .clk            = "l4_root_clk_div",
4582         .addr           = omap54xx_i2c1_addrs,
4583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4584 };
4585
4586 static struct omap_hwmod_addr_space omap54xx_i2c2_addrs[] = {
4587         {
4588                 .pa_start       = 0x48072000,
4589                 .pa_end         = 0x480720ff,
4590                 .flags          = ADDR_TYPE_RT
4591         },
4592         { }
4593 };
4594
4595 /* l4_per -> i2c2 */
4596 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
4597         .master         = &omap54xx_l4_per_hwmod,
4598         .slave          = &omap54xx_i2c2_hwmod,
4599         .clk            = "l4_root_clk_div",
4600         .addr           = omap54xx_i2c2_addrs,
4601         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4602 };
4603
4604 static struct omap_hwmod_addr_space omap54xx_i2c3_addrs[] = {
4605         {
4606                 .pa_start       = 0x48060000,
4607                 .pa_end         = 0x480600ff,
4608                 .flags          = ADDR_TYPE_RT
4609         },
4610         { }
4611 };
4612
4613 /* l4_per -> i2c3 */
4614 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
4615         .master         = &omap54xx_l4_per_hwmod,
4616         .slave          = &omap54xx_i2c3_hwmod,
4617         .clk            = "l4_root_clk_div",
4618         .addr           = omap54xx_i2c3_addrs,
4619         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4620 };
4621
4622 static struct omap_hwmod_addr_space omap54xx_i2c4_addrs[] = {
4623         {
4624                 .pa_start       = 0x4807a000,
4625                 .pa_end         = 0x4807a0ff,
4626                 .flags          = ADDR_TYPE_RT
4627         },
4628         { }
4629 };
4630
4631 /* l4_per -> i2c4 */
4632 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
4633         .master         = &omap54xx_l4_per_hwmod,
4634         .slave          = &omap54xx_i2c4_hwmod,
4635         .clk            = "l4_root_clk_div",
4636         .addr           = omap54xx_i2c4_addrs,
4637         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4638 };
4639
4640 static struct omap_hwmod_addr_space omap54xx_i2c5_addrs[] = {
4641         {
4642                 .pa_start       = 0x4807c000,
4643                 .pa_end         = 0x4807c0ff,
4644                 .flags          = ADDR_TYPE_RT
4645         },
4646         { }
4647 };
4648
4649 /* l4_per -> i2c5 */
4650 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
4651         .master         = &omap54xx_l4_per_hwmod,
4652         .slave          = &omap54xx_i2c5_hwmod,
4653         .clk            = "l4_root_clk_div",
4654         .addr           = omap54xx_i2c5_addrs,
4655         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4656 };
4657
4658 static struct omap_hwmod_addr_space omap54xx_ipu_addrs[] = {
4659         {
4660                 .name           = "unicache_mmu",
4661                 .pa_start       = 0x55080800,
4662                 .pa_end         = 0x55080fff,
4663         },
4664         {
4665                 .name           = "teslass_mmu",
4666                 .pa_start       = 0x55082000,
4667                 .pa_end         = 0x550820ff,
4668                 .flags          = ADDR_TYPE_RT
4669         },
4670         { }
4671 };
4672
4673 /* l3_main_2 -> ipu */
4674 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__ipu = {
4675         .master         = &omap54xx_l3_main_2_hwmod,
4676         .slave          = &omap54xx_ipu_hwmod,
4677         .clk            = "l3_iclk_div",
4678         .addr           = omap54xx_ipu_addrs,
4679         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4680 };
4681
4682 static struct omap_hwmod_addr_space omap54xx_intc_ipu_c0_addrs[] = {
4683         {
4684                 .pa_start       = 0x48211000,
4685                 .pa_end         = 0x48211fff,
4686         },
4687         { }
4688 };
4689
4690 /* l3_main_2 -> intc_ipu_c0 */
4691 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__intc_ipu_c0 = {
4692         .master         = &omap54xx_l3_main_2_hwmod,
4693         .slave          = &omap54xx_intc_ipu_c0_hwmod,
4694         .clk            = "l3_iclk_div",
4695         .addr           = omap54xx_intc_ipu_c0_addrs,
4696         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4697 };
4698
4699 static struct omap_hwmod_addr_space omap54xx_intc_ipu_c1_addrs[] = {
4700         {
4701                 .pa_start       = 0x48211000,
4702                 .pa_end         = 0x48211fff,
4703         },
4704         { }
4705 };
4706
4707 /* l3_main_2 -> intc_ipu_c1 */
4708 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__intc_ipu_c1 = {
4709         .master         = &omap54xx_l3_main_2_hwmod,
4710         .slave          = &omap54xx_intc_ipu_c1_hwmod,
4711         .clk            = "l3_iclk_div",
4712         .addr           = omap54xx_intc_ipu_c1_addrs,
4713         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4714 };
4715
4716 static struct omap_hwmod_addr_space omap54xx_iss_addrs[] = {
4717         {
4718                 .pa_start       = 0x52000000,
4719                 .pa_end         = 0x520000ff,
4720                 .flags          = ADDR_TYPE_RT
4721         },
4722         { }
4723 };
4724
4725 /* l3_main_2 -> iss */
4726 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__iss = {
4727         .master         = &omap54xx_l3_main_2_hwmod,
4728         .slave          = &omap54xx_iss_hwmod,
4729         .clk            = "dpll_core_h23x2_ck",
4730         .addr           = omap54xx_iss_addrs,
4731         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4732 };
4733
4734 static struct omap_hwmod_addr_space omap54xx_iva_addrs[] = {
4735         {
4736                 .pa_start       = 0x5a05a400,
4737                 .pa_end         = 0x5a05a47f,
4738                 .flags          = ADDR_TYPE_RT
4739         },
4740         { }
4741 };
4742
4743 /* l3_main_2 -> iva */
4744 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__iva = {
4745         .master         = &omap54xx_l3_main_2_hwmod,
4746         .slave          = &omap54xx_iva_hwmod,
4747         .clk            = "l3_iclk_div",
4748         .addr           = omap54xx_iva_addrs,
4749         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4750 };
4751
4752 static struct omap_hwmod_addr_space omap54xx_kbd_addrs[] = {
4753         {
4754                 .pa_start       = 0x4ae1c000,
4755                 .pa_end         = 0x4ae1c07f,
4756                 .flags          = ADDR_TYPE_RT
4757         },
4758         { }
4759 };
4760
4761 /* l4_wkup -> kbd */
4762 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
4763         .master         = &omap54xx_l4_wkup_hwmod,
4764         .slave          = &omap54xx_kbd_hwmod,
4765         .clk            = "wkupaon_iclk_mux",
4766         .addr           = omap54xx_kbd_addrs,
4767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4768 };
4769
4770 static struct omap_hwmod_addr_space omap54xx_mailbox_addrs[] = {
4771         {
4772                 .pa_start       = 0x4a0f4000,
4773                 .pa_end         = 0x4a0f41ff,
4774                 .flags          = ADDR_TYPE_RT
4775         },
4776         { }
4777 };
4778
4779 /* l4_cfg -> mailbox */
4780 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
4781         .master         = &omap54xx_l4_cfg_hwmod,
4782         .slave          = &omap54xx_mailbox_hwmod,
4783         .clk            = "l4_root_clk_div",
4784         .addr           = omap54xx_mailbox_addrs,
4785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4786 };
4787
4788 static struct omap_hwmod_addr_space omap54xx_mcasp_addrs[] = {
4789         {
4790                 .name           = "cfg",
4791                 .pa_start       = 0x40128000,
4792                 .pa_end         = 0x401283ff,
4793                 .flags          = ADDR_TYPE_RT
4794         },
4795         {
4796                 .name           = "dat",
4797                 .pa_start       = 0x4012a000,
4798                 .pa_end         = 0x4012a3ff,
4799                 .flags          = ADDR_TYPE_RT
4800         },
4801         { }
4802 };
4803
4804 /* l4_abe -> mcasp */
4805 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcasp = {
4806         .master         = &omap54xx_l4_abe_hwmod,
4807         .slave          = &omap54xx_mcasp_hwmod,
4808         .clk            = "abe_iclk",
4809         .addr           = omap54xx_mcasp_addrs,
4810         .user           = OCP_USER_MPU,
4811 };
4812
4813 static struct omap_hwmod_addr_space omap54xx_mcbsp1_addrs[] = {
4814         {
4815                 .name           = "mpu",
4816                 .pa_start       = 0x40122000,
4817                 .pa_end         = 0x401220ff,
4818                 .flags          = ADDR_TYPE_RT
4819         },
4820         { }
4821 };
4822
4823 /* l4_abe -> mcbsp1 */
4824 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
4825         .master         = &omap54xx_l4_abe_hwmod,
4826         .slave          = &omap54xx_mcbsp1_hwmod,
4827         .clk            = "abe_iclk",
4828         .addr           = omap54xx_mcbsp1_addrs,
4829         .user           = OCP_USER_MPU,
4830 };
4831
4832 static struct omap_hwmod_addr_space omap54xx_mcbsp2_addrs[] = {
4833         {
4834                 .name           = "mpu",
4835                 .pa_start       = 0x40124000,
4836                 .pa_end         = 0x401240ff,
4837                 .flags          = ADDR_TYPE_RT
4838         },
4839         { }
4840 };
4841
4842 /* l4_abe -> mcbsp2 */
4843 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
4844         .master         = &omap54xx_l4_abe_hwmod,
4845         .slave          = &omap54xx_mcbsp2_hwmod,
4846         .clk            = "abe_iclk",
4847         .addr           = omap54xx_mcbsp2_addrs,
4848         .user           = OCP_USER_MPU,
4849 };
4850
4851 static struct omap_hwmod_addr_space omap54xx_mcbsp3_addrs[] = {
4852         {
4853                 .name           = "mpu",
4854                 .pa_start       = 0x40126000,
4855                 .pa_end         = 0x401260ff,
4856                 .flags          = ADDR_TYPE_RT
4857         },
4858         { }
4859 };
4860
4861 /* l4_abe -> mcbsp3 */
4862 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
4863         .master         = &omap54xx_l4_abe_hwmod,
4864         .slave          = &omap54xx_mcbsp3_hwmod,
4865         .clk            = "abe_iclk",
4866         .addr           = omap54xx_mcbsp3_addrs,
4867         .user           = OCP_USER_MPU,
4868 };
4869
4870 static struct omap_hwmod_addr_space omap54xx_mcpdm_addrs[] = {
4871         {
4872                 .name           = "mpu",
4873                 .pa_start       = 0x40132000,
4874                 .pa_end         = 0x4013207f,
4875                 .flags          = ADDR_TYPE_RT
4876         },
4877         { }
4878 };
4879
4880 /* l4_abe -> mcpdm */
4881 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
4882         .master         = &omap54xx_l4_abe_hwmod,
4883         .slave          = &omap54xx_mcpdm_hwmod,
4884         .clk            = "abe_iclk",
4885         .addr           = omap54xx_mcpdm_addrs,
4886         .user           = OCP_USER_MPU,
4887 };
4888
4889 static struct omap_hwmod_addr_space omap54xx_mcspi1_addrs[] = {
4890         {
4891                 .pa_start       = 0x48098000,
4892                 .pa_end         = 0x480981ff,
4893                 .flags          = ADDR_TYPE_RT
4894         },
4895         { }
4896 };
4897
4898 /* l4_per -> mcspi1 */
4899 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
4900         .master         = &omap54xx_l4_per_hwmod,
4901         .slave          = &omap54xx_mcspi1_hwmod,
4902         .clk            = "l4_root_clk_div",
4903         .addr           = omap54xx_mcspi1_addrs,
4904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4905 };
4906
4907 static struct omap_hwmod_addr_space omap54xx_mcspi2_addrs[] = {
4908         {
4909                 .pa_start       = 0x4809a000,
4910                 .pa_end         = 0x4809a1ff,
4911                 .flags          = ADDR_TYPE_RT
4912         },
4913         { }
4914 };
4915
4916 /* l4_per -> mcspi2 */
4917 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
4918         .master         = &omap54xx_l4_per_hwmod,
4919         .slave          = &omap54xx_mcspi2_hwmod,
4920         .clk            = "l4_root_clk_div",
4921         .addr           = omap54xx_mcspi2_addrs,
4922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4923 };
4924
4925 static struct omap_hwmod_addr_space omap54xx_mcspi3_addrs[] = {
4926         {
4927                 .pa_start       = 0x480b8000,
4928                 .pa_end         = 0x480b81ff,
4929                 .flags          = ADDR_TYPE_RT
4930         },
4931         { }
4932 };
4933
4934 /* l4_per -> mcspi3 */
4935 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
4936         .master         = &omap54xx_l4_per_hwmod,
4937         .slave          = &omap54xx_mcspi3_hwmod,
4938         .clk            = "l4_root_clk_div",
4939         .addr           = omap54xx_mcspi3_addrs,
4940         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4941 };
4942
4943 static struct omap_hwmod_addr_space omap54xx_mcspi4_addrs[] = {
4944         {
4945                 .pa_start       = 0x480ba000,
4946                 .pa_end         = 0x480ba1ff,
4947                 .flags          = ADDR_TYPE_RT
4948         },
4949         { }
4950 };
4951
4952 /* l4_per -> mcspi4 */
4953 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
4954         .master         = &omap54xx_l4_per_hwmod,
4955         .slave          = &omap54xx_mcspi4_hwmod,
4956         .clk            = "l4_root_clk_div",
4957         .addr           = omap54xx_mcspi4_addrs,
4958         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4959 };
4960
4961 static struct omap_hwmod_addr_space omap54xx_mmc1_addrs[] = {
4962         {
4963                 .pa_start       = 0x4809c000,
4964                 .pa_end         = 0x4809c3ff,
4965                 .flags          = ADDR_TYPE_RT
4966         },
4967         { }
4968 };
4969
4970 /* l4_per -> mmc1 */
4971 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
4972         .master         = &omap54xx_l4_per_hwmod,
4973         .slave          = &omap54xx_mmc1_hwmod,
4974         .clk            = "l3_iclk_div",
4975         .addr           = omap54xx_mmc1_addrs,
4976         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4977 };
4978
4979 static struct omap_hwmod_addr_space omap54xx_mmc2_addrs[] = {
4980         {
4981                 .pa_start       = 0x480b4000,
4982                 .pa_end         = 0x480b43ff,
4983                 .flags          = ADDR_TYPE_RT
4984         },
4985         { }
4986 };
4987
4988 /* l4_per -> mmc2 */
4989 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
4990         .master         = &omap54xx_l4_per_hwmod,
4991         .slave          = &omap54xx_mmc2_hwmod,
4992         .clk            = "l3_iclk_div",
4993         .addr           = omap54xx_mmc2_addrs,
4994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4995 };
4996
4997 static struct omap_hwmod_addr_space omap54xx_mmc3_addrs[] = {
4998         {
4999                 .pa_start       = 0x480ad000,
5000                 .pa_end         = 0x480ad3ff,
5001                 .flags          = ADDR_TYPE_RT
5002         },
5003         { }
5004 };
5005
5006 /* l4_per -> mmc3 */
5007 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
5008         .master         = &omap54xx_l4_per_hwmod,
5009         .slave          = &omap54xx_mmc3_hwmod,
5010         .clk            = "l4_root_clk_div",
5011         .addr           = omap54xx_mmc3_addrs,
5012         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5013 };
5014
5015 static struct omap_hwmod_addr_space omap54xx_mmc4_addrs[] = {
5016         {
5017                 .pa_start       = 0x480d1000,
5018                 .pa_end         = 0x480d13ff,
5019                 .flags          = ADDR_TYPE_RT
5020         },
5021         { }
5022 };
5023
5024 /* l4_per -> mmc4 */
5025 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
5026         .master         = &omap54xx_l4_per_hwmod,
5027         .slave          = &omap54xx_mmc4_hwmod,
5028         .clk            = "l4_root_clk_div",
5029         .addr           = omap54xx_mmc4_addrs,
5030         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5031 };
5032
5033 static struct omap_hwmod_addr_space omap54xx_mmc5_addrs[] = {
5034         {
5035                 .pa_start       = 0x480d5000,
5036                 .pa_end         = 0x480d53ff,
5037                 .flags          = ADDR_TYPE_RT
5038         },
5039         { }
5040 };
5041
5042 /* l4_per -> mmc5 */
5043 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
5044         .master         = &omap54xx_l4_per_hwmod,
5045         .slave          = &omap54xx_mmc5_hwmod,
5046         .clk            = "l4_root_clk_div",
5047         .addr           = omap54xx_mmc5_addrs,
5048         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5049 };
5050
5051 static struct omap_hwmod_addr_space omap54xx_mpu_addrs[] = {
5052         {
5053                 .pa_start       = 0x48211000,
5054                 .pa_end         = 0x482af27f,
5055         },
5056         { }
5057 };
5058
5059 /* l4_cfg -> mpu */
5060 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
5061         .master         = &omap54xx_l4_cfg_hwmod,
5062         .slave          = &omap54xx_mpu_hwmod,
5063         .clk            = "l4_root_clk_div",
5064         .addr           = omap54xx_mpu_addrs,
5065         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5066 };
5067
5068 /* l3_main_2 -> ocmc_ram */
5069 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__ocmc_ram = {
5070         .master         = &omap54xx_l3_main_2_hwmod,
5071         .slave          = &omap54xx_ocmc_ram_hwmod,
5072         .clk            = "l3_iclk_div",
5073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5074 };
5075
5076 static struct omap_hwmod_addr_space omap54xx_ocp2scp1_addrs[] = {
5077         {
5078                 .pa_start       = 0x4a080000,
5079                 .pa_end         = 0x4a08001f,
5080                 .flags          = ADDR_TYPE_RT
5081         },
5082         { }
5083 };
5084
5085 /* l4_cfg -> ocp2scp1 */
5086 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
5087         .master         = &omap54xx_l4_cfg_hwmod,
5088         .slave          = &omap54xx_ocp2scp1_hwmod,
5089         .clk            = "l4_root_clk_div",
5090         .addr           = omap54xx_ocp2scp1_addrs,
5091         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5092 };
5093
5094 static struct omap_hwmod_addr_space omap54xx_sata_addrs[] = {
5095         {
5096                 .name           = "ahci",
5097                 .pa_start       = 0x4a140000,
5098                 .pa_end         = 0x4a1401ff,
5099         },
5100         {
5101                 .name           = "sysc",
5102                 .pa_start       = 0x4a141100,
5103                 .pa_end         = 0x4a141107,
5104                 .flags          = ADDR_TYPE_RT
5105         },
5106         { }
5107 };
5108
5109 /* l4_cfg -> sata */
5110 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
5111         .master         = &omap54xx_l4_cfg_hwmod,
5112         .slave          = &omap54xx_sata_hwmod,
5113         .clk            = "l3_iclk_div",
5114         .addr           = omap54xx_sata_addrs,
5115         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5116 };
5117
5118 static struct omap_hwmod_addr_space omap54xx_scrm_addrs[] = {
5119         {
5120                 .pa_start       = 0x4ae0a000,
5121                 .pa_end         = 0x4ae0a7ff,
5122         },
5123         { }
5124 };
5125
5126 /* l4_wkup -> scrm */
5127 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__scrm = {
5128         .master         = &omap54xx_l4_wkup_hwmod,
5129         .slave          = &omap54xx_scrm_hwmod,
5130         .clk            = "wkupaon_iclk_mux",
5131         .addr           = omap54xx_scrm_addrs,
5132         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5133 };
5134
5135 static struct omap_hwmod_addr_space omap54xx_slimbus1_addrs[] = {
5136         {
5137                 .name           = "mpu",
5138                 .pa_start       = 0x4012c000,
5139                 .pa_end         = 0x4012c3ff,
5140                 .flags          = ADDR_TYPE_RT
5141         },
5142         { }
5143 };
5144
5145 /* l4_abe -> slimbus1 */
5146 static struct omap_hwmod_ocp_if omap54xx_l4_abe__slimbus1 = {
5147         .master         = &omap54xx_l4_abe_hwmod,
5148         .slave          = &omap54xx_slimbus1_hwmod,
5149         .clk            = "abe_iclk",
5150         .addr           = omap54xx_slimbus1_addrs,
5151         .user           = OCP_USER_MPU,
5152 };
5153
5154 static struct omap_hwmod_addr_space omap54xx_smartreflex_core_addrs[] = {
5155         {
5156                 .pa_start       = 0x4a0dd000,
5157                 .pa_end         = 0x4a0dd03f,
5158                 .flags          = ADDR_TYPE_RT
5159         },
5160         { }
5161 };
5162
5163 /* l4_cfg -> smartreflex_core */
5164 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__smartreflex_core = {
5165         .master         = &omap54xx_l4_cfg_hwmod,
5166         .slave          = &omap54xx_smartreflex_core_hwmod,
5167         .clk            = "l4_root_clk_div",
5168         .addr           = omap54xx_smartreflex_core_addrs,
5169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5170 };
5171
5172 static struct omap_hwmod_addr_space omap54xx_smartreflex_mm_addrs[] = {
5173         {
5174                 .pa_start       = 0x4a0db000,
5175                 .pa_end         = 0x4a0db03f,
5176                 .flags          = ADDR_TYPE_RT
5177         },
5178         { }
5179 };
5180
5181 /* l4_cfg -> smartreflex_mm */
5182 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__smartreflex_mm = {
5183         .master         = &omap54xx_l4_cfg_hwmod,
5184         .slave          = &omap54xx_smartreflex_mm_hwmod,
5185         .clk            = "l4_root_clk_div",
5186         .addr           = omap54xx_smartreflex_mm_addrs,
5187         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5188 };
5189
5190 static struct omap_hwmod_addr_space omap54xx_smartreflex_mpu_addrs[] = {
5191         {
5192                 .pa_start       = 0x4a0d9000,
5193                 .pa_end         = 0x4a0d903f,
5194                 .flags          = ADDR_TYPE_RT
5195         },
5196         { }
5197 };
5198
5199 /* l4_cfg -> smartreflex_mpu */
5200 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__smartreflex_mpu = {
5201         .master         = &omap54xx_l4_cfg_hwmod,
5202         .slave          = &omap54xx_smartreflex_mpu_hwmod,
5203         .clk            = "l4_root_clk_div",
5204         .addr           = omap54xx_smartreflex_mpu_addrs,
5205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5206 };
5207
5208 static struct omap_hwmod_addr_space omap54xx_spinlock_addrs[] = {
5209         {
5210                 .pa_start       = 0x4a0f6000,
5211                 .pa_end         = 0x4a0f6fff,
5212                 .flags          = ADDR_TYPE_RT
5213         },
5214         { }
5215 };
5216
5217 /* l4_cfg -> spinlock */
5218 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
5219         .master         = &omap54xx_l4_cfg_hwmod,
5220         .slave          = &omap54xx_spinlock_hwmod,
5221         .clk            = "l4_root_clk_div",
5222         .addr           = omap54xx_spinlock_addrs,
5223         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5224 };
5225
5226 static struct omap_hwmod_addr_space omap54xx_timer1_addrs[] = {
5227         {
5228                 .pa_start       = 0x4ae18000,
5229                 .pa_end         = 0x4ae1807f,
5230                 .flags          = ADDR_TYPE_RT
5231         },
5232         { }
5233 };
5234
5235 /* l4_wkup -> timer1 */
5236 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
5237         .master         = &omap54xx_l4_wkup_hwmod,
5238         .slave          = &omap54xx_timer1_hwmod,
5239         .clk            = "wkupaon_iclk_mux",
5240         .addr           = omap54xx_timer1_addrs,
5241         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5242 };
5243
5244 static struct omap_hwmod_addr_space omap54xx_timer2_addrs[] = {
5245         {
5246                 .pa_start       = 0x48032000,
5247                 .pa_end         = 0x4803207f,
5248                 .flags          = ADDR_TYPE_RT
5249         },
5250         { }
5251 };
5252
5253 /* l4_per -> timer2 */
5254 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
5255         .master         = &omap54xx_l4_per_hwmod,
5256         .slave          = &omap54xx_timer2_hwmod,
5257         .clk            = "l4_root_clk_div",
5258         .addr           = omap54xx_timer2_addrs,
5259         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5260 };
5261
5262 static struct omap_hwmod_addr_space omap54xx_timer3_addrs[] = {
5263         {
5264                 .pa_start       = 0x48034000,
5265                 .pa_end         = 0x4803407f,
5266                 .flags          = ADDR_TYPE_RT
5267         },
5268         { }
5269 };
5270
5271 /* l4_per -> timer3 */
5272 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
5273         .master         = &omap54xx_l4_per_hwmod,
5274         .slave          = &omap54xx_timer3_hwmod,
5275         .clk            = "l4_root_clk_div",
5276         .addr           = omap54xx_timer3_addrs,
5277         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5278 };
5279
5280 static struct omap_hwmod_addr_space omap54xx_timer4_addrs[] = {
5281         {
5282                 .pa_start       = 0x48036000,
5283                 .pa_end         = 0x4803607f,
5284                 .flags          = ADDR_TYPE_RT
5285         },
5286         { }
5287 };
5288
5289 /* l4_per -> timer4 */
5290 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
5291         .master         = &omap54xx_l4_per_hwmod,
5292         .slave          = &omap54xx_timer4_hwmod,
5293         .clk            = "l4_root_clk_div",
5294         .addr           = omap54xx_timer4_addrs,
5295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5296 };
5297
5298 static struct omap_hwmod_addr_space omap54xx_timer5_addrs[] = {
5299         {
5300                 .name           = "mpu",
5301                 .pa_start       = 0x40138000,
5302                 .pa_end         = 0x4013807f,
5303                 .flags          = ADDR_TYPE_RT
5304         },
5305         { }
5306 };
5307
5308 /* l4_abe -> timer5 */
5309 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
5310         .master         = &omap54xx_l4_abe_hwmod,
5311         .slave          = &omap54xx_timer5_hwmod,
5312         .clk            = "abe_iclk",
5313         .addr           = omap54xx_timer5_addrs,
5314         .user           = OCP_USER_MPU,
5315 };
5316
5317 static struct omap_hwmod_addr_space omap54xx_timer6_addrs[] = {
5318         {
5319                 .name           = "mpu",
5320                 .pa_start       = 0x4013a000,
5321                 .pa_end         = 0x4013a07f,
5322                 .flags          = ADDR_TYPE_RT
5323         },
5324         { }
5325 };
5326
5327 /* l4_abe -> timer6 */
5328 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
5329         .master         = &omap54xx_l4_abe_hwmod,
5330         .slave          = &omap54xx_timer6_hwmod,
5331         .clk            = "abe_iclk",
5332         .addr           = omap54xx_timer6_addrs,
5333         .user           = OCP_USER_MPU,
5334 };
5335
5336 static struct omap_hwmod_addr_space omap54xx_timer7_addrs[] = {
5337         {
5338                 .name           = "mpu",
5339                 .pa_start       = 0x4013c000,
5340                 .pa_end         = 0x4013c07f,
5341                 .flags          = ADDR_TYPE_RT
5342         },
5343         { }
5344 };
5345
5346 /* l4_abe -> timer7 */
5347 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
5348         .master         = &omap54xx_l4_abe_hwmod,
5349         .slave          = &omap54xx_timer7_hwmod,
5350         .clk            = "abe_iclk",
5351         .addr           = omap54xx_timer7_addrs,
5352         .user           = OCP_USER_MPU,
5353 };
5354
5355 static struct omap_hwmod_addr_space omap54xx_timer8_addrs[] = {
5356         {
5357                 .name           = "mpu",
5358                 .pa_start       = 0x4013e000,
5359                 .pa_end         = 0x4013e07f,
5360                 .flags          = ADDR_TYPE_RT
5361         },
5362         { }
5363 };
5364
5365 /* l4_abe -> timer8 */
5366 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
5367         .master         = &omap54xx_l4_abe_hwmod,
5368         .slave          = &omap54xx_timer8_hwmod,
5369         .clk            = "abe_iclk",
5370         .addr           = omap54xx_timer8_addrs,
5371         .user           = OCP_USER_MPU,
5372 };
5373
5374 static struct omap_hwmod_addr_space omap54xx_timer9_addrs[] = {
5375         {
5376                 .pa_start       = 0x4803e000,
5377                 .pa_end         = 0x4803e07f,
5378                 .flags          = ADDR_TYPE_RT
5379         },
5380         { }
5381 };
5382
5383 /* l4_per -> timer9 */
5384 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
5385         .master         = &omap54xx_l4_per_hwmod,
5386         .slave          = &omap54xx_timer9_hwmod,
5387         .clk            = "l4_root_clk_div",
5388         .addr           = omap54xx_timer9_addrs,
5389         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5390 };
5391
5392 static struct omap_hwmod_addr_space omap54xx_timer10_addrs[] = {
5393         {
5394                 .pa_start       = 0x48086000,
5395                 .pa_end         = 0x4808607f,
5396                 .flags          = ADDR_TYPE_RT
5397         },
5398         { }
5399 };
5400
5401 /* l4_per -> timer10 */
5402 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
5403         .master         = &omap54xx_l4_per_hwmod,
5404         .slave          = &omap54xx_timer10_hwmod,
5405         .clk            = "l4_root_clk_div",
5406         .addr           = omap54xx_timer10_addrs,
5407         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5408 };
5409
5410 static struct omap_hwmod_addr_space omap54xx_timer11_addrs[] = {
5411         {
5412                 .pa_start       = 0x48088000,
5413                 .pa_end         = 0x4808807f,
5414                 .flags          = ADDR_TYPE_RT
5415         },
5416         { }
5417 };
5418
5419 /* l4_per -> timer11 */
5420 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
5421         .master         = &omap54xx_l4_per_hwmod,
5422         .slave          = &omap54xx_timer11_hwmod,
5423         .clk            = "l4_root_clk_div",
5424         .addr           = omap54xx_timer11_addrs,
5425         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5426 };
5427
5428 static struct omap_hwmod_addr_space omap54xx_uart1_addrs[] = {
5429         {
5430                 .pa_start       = 0x4806a000,
5431                 .pa_end         = 0x4806a0ff,
5432                 .flags          = ADDR_TYPE_RT
5433         },
5434         { }
5435 };
5436
5437 /* l4_per -> uart1 */
5438 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
5439         .master         = &omap54xx_l4_per_hwmod,
5440         .slave          = &omap54xx_uart1_hwmod,
5441         .clk            = "l4_root_clk_div",
5442         .addr           = omap54xx_uart1_addrs,
5443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5444 };
5445
5446 static struct omap_hwmod_addr_space omap54xx_uart2_addrs[] = {
5447         {
5448                 .pa_start       = 0x4806c000,
5449                 .pa_end         = 0x4806c0ff,
5450                 .flags          = ADDR_TYPE_RT
5451         },
5452         { }
5453 };
5454
5455 /* l4_per -> uart2 */
5456 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
5457         .master         = &omap54xx_l4_per_hwmod,
5458         .slave          = &omap54xx_uart2_hwmod,
5459         .clk            = "l4_root_clk_div",
5460         .addr           = omap54xx_uart2_addrs,
5461         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5462 };
5463
5464 static struct omap_hwmod_addr_space omap54xx_uart3_addrs[] = {
5465         {
5466                 .pa_start       = 0x48020000,
5467                 .pa_end         = 0x480200ff,
5468                 .flags          = ADDR_TYPE_RT
5469         },
5470         { }
5471 };
5472
5473 /* l4_per -> uart3 */
5474 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
5475         .master         = &omap54xx_l4_per_hwmod,
5476         .slave          = &omap54xx_uart3_hwmod,
5477         .clk            = "l4_root_clk_div",
5478         .addr           = omap54xx_uart3_addrs,
5479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5480 };
5481
5482 static struct omap_hwmod_addr_space omap54xx_uart4_addrs[] = {
5483         {
5484                 .pa_start       = 0x4806e000,
5485                 .pa_end         = 0x4806e0ff,
5486                 .flags          = ADDR_TYPE_RT
5487         },
5488         { }
5489 };
5490
5491 /* l4_per -> uart4 */
5492 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
5493         .master         = &omap54xx_l4_per_hwmod,
5494         .slave          = &omap54xx_uart4_hwmod,
5495         .clk            = "l4_root_clk_div",
5496         .addr           = omap54xx_uart4_addrs,
5497         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5498 };
5499
5500 static struct omap_hwmod_addr_space omap54xx_uart5_addrs[] = {
5501         {
5502                 .pa_start       = 0x48066000,
5503                 .pa_end         = 0x480660ff,
5504                 .flags          = ADDR_TYPE_RT
5505         },
5506         { }
5507 };
5508
5509 /* l4_per -> uart5 */
5510 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
5511         .master         = &omap54xx_l4_per_hwmod,
5512         .slave          = &omap54xx_uart5_hwmod,
5513         .clk            = "l4_root_clk_div",
5514         .addr           = omap54xx_uart5_addrs,
5515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5516 };
5517
5518 static struct omap_hwmod_addr_space omap54xx_uart6_addrs[] = {
5519         {
5520                 .pa_start       = 0x48068000,
5521                 .pa_end         = 0x480680ff,
5522                 .flags          = ADDR_TYPE_RT
5523         },
5524         { }
5525 };
5526
5527 /* l4_per -> uart6 */
5528 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
5529         .master         = &omap54xx_l4_per_hwmod,
5530         .slave          = &omap54xx_uart6_hwmod,
5531         .clk            = "l4_root_clk_div",
5532         .addr           = omap54xx_uart6_addrs,
5533         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5534 };
5535
5536 static struct omap_hwmod_addr_space omap54xx_usb_host_hs_addrs[] = {
5537         {
5538                 .name           = "uhh",
5539                 .pa_start       = 0x4a064000,
5540                 .pa_end         = 0x4a0647ff,
5541                 .flags          = ADDR_TYPE_RT
5542         },
5543         {
5544                 .name           = "ohci",
5545                 .pa_start       = 0x4a064800,
5546                 .pa_end         = 0x4a06487f,
5547         },
5548         {
5549                 .name           = "ehci",
5550                 .pa_start       = 0x4a064c00,
5551                 .pa_end         = 0x4a064cff,
5552         },
5553         { }
5554 };
5555
5556 /* l4_cfg -> usb_host_hs */
5557 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
5558         .master         = &omap54xx_l4_cfg_hwmod,
5559         .slave          = &omap54xx_usb_host_hs_hwmod,
5560         .clk            = "l3_iclk_div",
5561         .addr           = omap54xx_usb_host_hs_addrs,
5562         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5563 };
5564
5565 static struct omap_hwmod_addr_space omap54xx_usb_otg_ss_addrs[] = {
5566         {
5567                 .name           = "wrapper",
5568                 .pa_start       = 0x4a020000,
5569                 .pa_end         = 0x4a0201ff,
5570                 .flags          = ADDR_TYPE_RT
5571         },
5572         {
5573                 .name           = "dwc_usb3",
5574                 .pa_start       = 0x4a030000,
5575                 .pa_end         = 0x4a0300ff,
5576         },
5577         { }
5578 };
5579
5580 /* l4_cfg -> usb_otg_ss */
5581 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
5582         .master         = &omap54xx_l4_cfg_hwmod,
5583         .slave          = &omap54xx_usb_otg_ss_hwmod,
5584         .clk            = "dpll_core_h13x2_ck",
5585         .addr           = omap54xx_usb_otg_ss_addrs,
5586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5587 };
5588
5589 static struct omap_hwmod_addr_space omap54xx_usb_tll_hs_addrs[] = {
5590         {
5591                 .name           = "tll",
5592                 .pa_start       = 0x4a062000,
5593                 .pa_end         = 0x4a062fff,
5594                 .flags          = ADDR_TYPE_RT
5595         },
5596         { }
5597 };
5598
5599 /* l4_cfg -> usb_tll_hs */
5600 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
5601         .master         = &omap54xx_l4_cfg_hwmod,
5602         .slave          = &omap54xx_usb_tll_hs_hwmod,
5603         .clk            = "l4_root_clk_div",
5604         .addr           = omap54xx_usb_tll_hs_addrs,
5605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5606 };
5607
5608 static struct omap_hwmod_addr_space omap54xx_wd_timer2_addrs[] = {
5609         {
5610                 .pa_start       = 0x4ae14000,
5611                 .pa_end         = 0x4ae1407f,
5612                 .flags          = ADDR_TYPE_RT
5613         },
5614         { }
5615 };
5616
5617 /* l4_wkup -> wd_timer2 */
5618 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
5619         .master         = &omap54xx_l4_wkup_hwmod,
5620         .slave          = &omap54xx_wd_timer2_hwmod,
5621         .clk            = "wkupaon_iclk_mux",
5622         .addr           = omap54xx_wd_timer2_addrs,
5623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5624 };
5625
5626 static struct omap_hwmod_addr_space omap54xx_wd_timer3_addrs[] = {
5627         {
5628                 .name           = "mpu",
5629                 .pa_start       = 0x40130000,
5630                 .pa_end         = 0x4013007f,
5631                 .flags          = ADDR_TYPE_RT
5632         },
5633         { }
5634 };
5635
5636 /* l4_abe -> wd_timer3 */
5637 static struct omap_hwmod_ocp_if omap54xx_l4_abe__wd_timer3 = {
5638         .master         = &omap54xx_l4_abe_hwmod,
5639         .slave          = &omap54xx_wd_timer3_hwmod,
5640         .clk            = "abe_iclk",
5641         .addr           = omap54xx_wd_timer3_addrs,
5642         .user           = OCP_USER_MPU,
5643 };
5644
5645 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
5646         &omap54xx_l3_main_1__dmm,
5647         &omap54xx_dmm__emif_ocp_fw,
5648         &omap54xx_l4_cfg__emif_ocp_fw,
5649         &omap54xx_l3_main_3__l3_instr,
5650         &omap54xx_ocp_wp_noc__l3_instr,
5651         &omap54xx_l3_main_2__l3_main_1,
5652         &omap54xx_l4_cfg__l3_main_1,
5653         &omap54xx_mpu__l3_main_1,
5654         &omap54xx_l3_main_1__l3_main_2,
5655         &omap54xx_l4_cfg__l3_main_2,
5656         &omap54xx_l3_main_1__l3_main_3,
5657         &omap54xx_l3_main_2__l3_main_3,
5658         &omap54xx_l4_cfg__l3_main_3,
5659         &omap54xx_l3_main_1__l4_abe,
5660         &omap54xx_mpu__l4_abe,
5661         &omap54xx_l3_main_1__l4_cfg,
5662         &omap54xx_l3_main_2__l4_per,
5663         &omap54xx_l3_main_1__l4_wkup,
5664         &omap54xx_mpu__mpu_private,
5665         &omap54xx_l3_main_3__ocp_wp_noc,
5666         &omap54xx_l4_cfg__ocp_wp_noc,
5667         &omap54xx_l4_abe__aess,
5668         &omap54xx_l3_main_2__bb2d,
5669         &omap54xx_l3_main_2__c2c,
5670         &omap54xx_l4_wkup__counter_32k,
5671         &omap54xx_l4_cfg__ctrl_module_core,
5672         &omap54xx_l4_wkup__ctrl_module_wkup,
5673         &omap54xx_l4_cfg__dma_system,
5674         &omap54xx_l4_abe__dmic,
5675         &omap54xx_l4_cfg__dsp,
5676         &omap54xx_l3_main_2__dss,
5677         &omap54xx_l3_main_2__dss_dispc,
5678         &omap54xx_l3_main_2__dss_dsi1_a,
5679         &omap54xx_l3_main_2__dss_dsi1_b,
5680         &omap54xx_l3_main_2__dss_dsi1_c,
5681         &omap54xx_l3_main_2__dss_hdmi,
5682         &omap54xx_l3_main_2__dss_rfbi,
5683         &omap54xx_l4_per__elm,
5684         &omap54xx_emif_ocp_fw__emif1,
5685         &omap54xx_mpu__emif1,
5686         &omap54xx_emif_ocp_fw__emif2,
5687         &omap54xx_mpu__emif2,
5688         &omap54xx_l4_cfg__fdif,
5689         &omap54xx_l4_wkup__gpio1,
5690         &omap54xx_l4_per__gpio2,
5691         &omap54xx_l4_per__gpio3,
5692         &omap54xx_l4_per__gpio4,
5693         &omap54xx_l4_per__gpio5,
5694         &omap54xx_l4_per__gpio6,
5695         &omap54xx_l4_per__gpio7,
5696         &omap54xx_l4_per__gpio8,
5697         &omap54xx_l3_main_2__gpmc,
5698         &omap54xx_l3_main_2__gpu,
5699         &omap54xx_l4_per__hdq1w,
5700         &omap54xx_l4_cfg__hsi,
5701         &omap54xx_l4_per__i2c1,
5702         &omap54xx_l4_per__i2c2,
5703         &omap54xx_l4_per__i2c3,
5704         &omap54xx_l4_per__i2c4,
5705         &omap54xx_l4_per__i2c5,
5706         &omap54xx_l3_main_2__ipu,
5707         &omap54xx_l3_main_2__intc_ipu_c0,
5708         &omap54xx_l3_main_2__intc_ipu_c1,
5709         &omap54xx_l3_main_2__iss,
5710         &omap54xx_l3_main_2__iva,
5711         &omap54xx_l4_wkup__kbd,
5712         &omap54xx_l4_cfg__mailbox,
5713         &omap54xx_l4_abe__mcasp,
5714         &omap54xx_l4_abe__mcbsp1,
5715         &omap54xx_l4_abe__mcbsp2,
5716         &omap54xx_l4_abe__mcbsp3,
5717         &omap54xx_l4_abe__mcpdm,
5718         &omap54xx_l4_per__mcspi1,
5719         &omap54xx_l4_per__mcspi2,
5720         &omap54xx_l4_per__mcspi3,
5721         &omap54xx_l4_per__mcspi4,
5722         &omap54xx_l4_per__mmc1,
5723         &omap54xx_l4_per__mmc2,
5724         &omap54xx_l4_per__mmc3,
5725         &omap54xx_l4_per__mmc4,
5726         &omap54xx_l4_per__mmc5,
5727         &omap54xx_l4_cfg__mpu,
5728         &omap54xx_l3_main_2__ocmc_ram,
5729         &omap54xx_l4_cfg__ocp2scp1,
5730         &omap54xx_l4_cfg__ocp2scp3,
5731         &omap54xx_l4_cfg__sata,
5732         &omap54xx_l4_wkup__scrm,
5733         &omap54xx_l4_abe__slimbus1,
5734         &omap54xx_l4_cfg__smartreflex_core,
5735         &omap54xx_l4_cfg__smartreflex_mm,
5736         &omap54xx_l4_cfg__smartreflex_mpu,
5737         &omap54xx_l4_cfg__spinlock,
5738         &omap54xx_l4_wkup__timer1,
5739         &omap54xx_l4_per__timer2,
5740         &omap54xx_l4_per__timer3,
5741         &omap54xx_l4_per__timer4,
5742         &omap54xx_l4_abe__timer5,
5743         &omap54xx_l4_abe__timer6,
5744         &omap54xx_l4_abe__timer7,
5745         &omap54xx_l4_abe__timer8,
5746         &omap54xx_l4_per__timer9,
5747         &omap54xx_l4_per__timer10,
5748         &omap54xx_l4_per__timer11,
5749         &omap54xx_l4_per__uart1,
5750         &omap54xx_l4_per__uart2,
5751         &omap54xx_l4_per__uart3,
5752         &omap54xx_l4_per__uart4,
5753         &omap54xx_l4_per__uart5,
5754         &omap54xx_l4_per__uart6,
5755         &omap54xx_l4_cfg__usb_host_hs,
5756         &omap54xx_l4_cfg__usb_otg_ss,
5757         &omap54xx_l4_cfg__usb_tll_hs,
5758         &omap54xx_l4_wkup__wd_timer2,
5759         &omap54xx_l4_abe__wd_timer3,
5760         NULL,
5761 };
5762
5763 int __init omap54xx_hwmod_init(void)
5764 {
5765         omap_hwmod_init();
5766         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
5767 }
5768