1 /*
2 * Hardware modules present on the OMAP54xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
20 #include <linux/io.h>
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/platform_data/omap_ocp2scp.h>
24 #include <linux/i2c-omap.h>
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
33 #include "cm1_54xx.h"
34 #include "cm2_54xx.h"
35 #include "prm54xx.h"
36 #include "prm-regbits-54xx.h"
37 #include "i2c.h"
38 #include "mmc.h"
39 #include "wd_timer.h"
41 /* Base offset for all OMAP5 interrupts external to MPUSS */
42 #define OMAP54XX_IRQ_GIC_START 32
44 /* Base offset for all OMAP5 dma requests */
45 #define OMAP54XX_DMA_REQ_START 1
48 /*
49 * IP blocks
50 */
52 /*
53 * 'dmm' class
54 * instance(s): dmm
55 */
56 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
57 .name = "dmm",
58 };
60 /* dmm */
61 static struct omap_hwmod_irq_info omap54xx_dmm_irqs[] = {
62 { .irq = 113 + OMAP54XX_IRQ_GIC_START },
63 { .irq = -1 }
64 };
66 static struct omap_hwmod omap54xx_dmm_hwmod = {
67 .name = "dmm",
68 .class = &omap54xx_dmm_hwmod_class,
69 .clkdm_name = "emif_clkdm",
70 .mpu_irqs = omap54xx_dmm_irqs,
71 .prcm = {
72 .omap4 = {
73 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
74 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
75 },
76 },
77 };
79 /*
80 * 'emif_ocp_fw' class
81 * instance(s): emif_ocp_fw
82 */
83 static struct omap_hwmod_class omap54xx_emif_ocp_fw_hwmod_class = {
84 .name = "emif_ocp_fw",
85 };
87 /* emif_ocp_fw */
88 static struct omap_hwmod omap54xx_emif_ocp_fw_hwmod = {
89 .name = "emif_ocp_fw",
90 .class = &omap54xx_emif_ocp_fw_hwmod_class,
91 .clkdm_name = "emif_clkdm",
92 .prcm = {
93 .omap4 = {
94 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
95 .context_offs = OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
96 },
97 },
98 };
100 /*
101 * 'l3' class
102 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
103 */
104 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
105 .name = "l3",
106 };
108 /* l3_instr */
109 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
110 .name = "l3_instr",
111 .class = &omap54xx_l3_hwmod_class,
112 .clkdm_name = "l3instr_clkdm",
113 .prcm = {
114 .omap4 = {
115 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
116 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
117 .modulemode = MODULEMODE_HWCTRL,
118 },
119 },
120 };
122 /* l3_main_1 */
123 static struct omap_hwmod_irq_info omap54xx_l3_main_1_irqs[] = {
124 { .name = "dbg_err", .irq = 9 + OMAP54XX_IRQ_GIC_START },
125 { .name = "app_err", .irq = 10 + OMAP54XX_IRQ_GIC_START },
126 { .name = "stat_alarm", .irq = 16 + OMAP54XX_IRQ_GIC_START },
127 { .irq = -1 }
128 };
130 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
131 .name = "l3_main_1",
132 .class = &omap54xx_l3_hwmod_class,
133 .clkdm_name = "l3main1_clkdm",
134 .mpu_irqs = omap54xx_l3_main_1_irqs,
135 .prcm = {
136 .omap4 = {
137 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
138 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
139 },
140 },
141 };
143 /* l3_main_2 */
144 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
145 .name = "l3_main_2",
146 .class = &omap54xx_l3_hwmod_class,
147 .clkdm_name = "l3main2_clkdm",
148 .prcm = {
149 .omap4 = {
150 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
151 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
152 },
153 },
154 };
156 /* l3_main_3 */
157 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
158 .name = "l3_main_3",
159 .class = &omap54xx_l3_hwmod_class,
160 .clkdm_name = "l3instr_clkdm",
161 .prcm = {
162 .omap4 = {
163 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
164 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
165 .modulemode = MODULEMODE_HWCTRL,
166 },
167 },
168 };
170 /*
171 * 'l4' class
172 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
173 */
174 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
175 .name = "l4",
176 };
178 /* l4_abe */
179 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
180 .name = "l4_abe",
181 .class = &omap54xx_l4_hwmod_class,
182 .clkdm_name = "abe_clkdm",
183 .prcm = {
184 .omap4 = {
185 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
186 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
187 },
188 },
189 };
191 /* l4_cfg */
192 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
193 .name = "l4_cfg",
194 .class = &omap54xx_l4_hwmod_class,
195 .clkdm_name = "l4cfg_clkdm",
196 .prcm = {
197 .omap4 = {
198 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
199 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
200 },
201 },
202 };
204 /* l4_per */
205 static struct omap_hwmod omap54xx_l4_per_hwmod = {
206 .name = "l4_per",
207 .class = &omap54xx_l4_hwmod_class,
208 .clkdm_name = "l4per_clkdm",
209 .prcm = {
210 .omap4 = {
211 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
212 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
213 },
214 },
215 };
217 /* l4_wkup */
218 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
219 .name = "l4_wkup",
220 .class = &omap54xx_l4_hwmod_class,
221 .clkdm_name = "wkupaon_clkdm",
222 .prcm = {
223 .omap4 = {
224 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
225 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
226 },
227 },
228 };
230 /*
231 * 'mpu_bus' class
232 * instance(s): mpu_private
233 */
234 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
235 .name = "mpu_bus",
236 };
238 /* mpu_private */
239 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
240 .name = "mpu_private",
241 .class = &omap54xx_mpu_bus_hwmod_class,
242 .clkdm_name = "mpu_clkdm",
243 .prcm = {
244 .omap4 = {
245 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
246 },
247 },
248 };
250 /*
251 * 'ocp_wp_noc' class
252 * instance(s): ocp_wp_noc
253 */
254 static struct omap_hwmod_class omap54xx_ocp_wp_noc_hwmod_class = {
255 .name = "ocp_wp_noc",
256 };
258 /* ocp_wp_noc */
259 static struct omap_hwmod omap54xx_ocp_wp_noc_hwmod = {
260 .name = "ocp_wp_noc",
261 .class = &omap54xx_ocp_wp_noc_hwmod_class,
262 .clkdm_name = "l3instr_clkdm",
263 .prcm = {
264 .omap4 = {
265 .clkctrl_offs = OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET,
266 .context_offs = OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET,
267 .modulemode = MODULEMODE_HWCTRL,
268 },
269 },
270 };
272 /*
273 * 'aess' class
274 * audio engine sub system
275 */
277 static struct omap_hwmod_class_sysconfig omap54xx_aess_sysc = {
278 .rev_offs = 0x0000,
279 .sysc_offs = 0x0010,
280 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
281 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
282 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
283 MSTANDBY_SMART_WKUP),
284 .sysc_fields = &omap_hwmod_sysc_type2,
285 };
287 static struct omap_hwmod_class omap54xx_aess_hwmod_class = {
288 .name = "aess",
289 .sysc = &omap54xx_aess_sysc,
290 };
292 /* aess */
293 static struct omap_hwmod_irq_info omap54xx_aess_irqs[] = {
294 { .irq = 99 + OMAP54XX_IRQ_GIC_START },
295 { .irq = -1 }
296 };
298 static struct omap_hwmod_dma_info omap54xx_aess_sdma_reqs[] = {
299 { .name = "fifo0", .dma_req = 100 + OMAP54XX_DMA_REQ_START },
300 { .name = "fifo1", .dma_req = 101 + OMAP54XX_DMA_REQ_START },
301 { .name = "fifo2", .dma_req = 102 + OMAP54XX_DMA_REQ_START },
302 { .name = "fifo3", .dma_req = 103 + OMAP54XX_DMA_REQ_START },
303 { .name = "fifo4", .dma_req = 104 + OMAP54XX_DMA_REQ_START },
304 { .name = "fifo5", .dma_req = 105 + OMAP54XX_DMA_REQ_START },
305 { .name = "fifo6", .dma_req = 106 + OMAP54XX_DMA_REQ_START },
306 { .name = "fifo7", .dma_req = 107 + OMAP54XX_DMA_REQ_START },
307 { .dma_req = -1 }
308 };
310 static struct omap_hwmod omap54xx_aess_hwmod = {
311 .name = "aess",
312 .class = &omap54xx_aess_hwmod_class,
313 .clkdm_name = "abe_clkdm",
314 .mpu_irqs = omap54xx_aess_irqs,
315 .sdma_reqs = omap54xx_aess_sdma_reqs,
316 .main_clk = "aess_fclk",
317 .prcm = {
318 .omap4 = {
319 .clkctrl_offs = OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET,
320 .context_offs = OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET,
321 .modulemode = MODULEMODE_SWCTRL,
322 },
323 },
324 };
326 /*
327 * 'bb2d' class
328 * bit blit 2d accelerator
329 */
331 static struct omap_hwmod_class omap54xx_bb2d_hwmod_class = {
332 .name = "bb2d",
333 };
335 /* bb2d */
336 static struct omap_hwmod_irq_info omap54xx_bb2d_irqs[] = {
337 { .irq = 125 + OMAP54XX_IRQ_GIC_START },
338 { .irq = -1 }
339 };
341 static struct omap_hwmod omap54xx_bb2d_hwmod = {
342 .name = "bb2d",
343 .class = &omap54xx_bb2d_hwmod_class,
344 .clkdm_name = "dss_clkdm",
345 .mpu_irqs = omap54xx_bb2d_irqs,
346 .main_clk = "dpll_core_h24x2_ck",
347 .prcm = {
348 .omap4 = {
349 .clkctrl_offs = OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
350 .context_offs = OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET,
351 .modulemode = MODULEMODE_SWCTRL,
352 },
353 },
354 };
356 /*
357 * 'c2c' class
358 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
359 * soc
360 */
362 static struct omap_hwmod_class_sysconfig omap54xx_c2c_sysc = {
363 .rev_offs = 0x0000,
364 .syss_offs = 0x0008,
365 .sysc_flags = SYSS_HAS_RESET_STATUS,
366 };
368 static struct omap_hwmod_class omap54xx_c2c_hwmod_class = {
369 .name = "c2c",
370 .sysc = &omap54xx_c2c_sysc,
371 };
373 /* c2c */
374 static struct omap_hwmod_irq_info omap54xx_c2c_irqs[] = {
375 { .irq = 88 + OMAP54XX_IRQ_GIC_START },
376 { .irq = -1 }
377 };
379 static struct omap_hwmod_dma_info omap54xx_c2c_sdma_reqs[] = {
380 { .dma_req = 68 + OMAP54XX_DMA_REQ_START },
381 { .dma_req = -1 }
382 };
384 static struct omap_hwmod omap54xx_c2c_hwmod = {
385 .name = "c2c",
386 .class = &omap54xx_c2c_hwmod_class,
387 .clkdm_name = "c2c_clkdm",
388 .mpu_irqs = omap54xx_c2c_irqs,
389 .sdma_reqs = omap54xx_c2c_sdma_reqs,
390 .main_clk = "c2c_fclk",
391 .prcm = {
392 .omap4 = {
393 .clkctrl_offs = OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET,
394 .context_offs = OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET,
395 },
396 },
397 };
399 /*
400 * 'counter' class
401 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
402 */
404 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
405 .rev_offs = 0x0000,
406 .sysc_offs = 0x0010,
407 .sysc_flags = SYSC_HAS_SIDLEMODE,
408 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
409 .sysc_fields = &omap_hwmod_sysc_type1,
410 };
412 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
413 .name = "counter",
414 .sysc = &omap54xx_counter_sysc,
415 };
417 /* counter_32k */
418 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
419 .name = "counter_32k",
420 .class = &omap54xx_counter_hwmod_class,
421 .clkdm_name = "wkupaon_clkdm",
422 .flags = HWMOD_SWSUP_SIDLE,
423 .main_clk = "wkupaon_iclk_mux",
424 .prcm = {
425 .omap4 = {
426 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
427 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
428 },
429 },
430 };
432 /*
433 * 'ctrl_module' class
434 * omap5430 core control module + omap5430 wkup control module
435 */
437 static struct omap_hwmod_class_sysconfig omap54xx_ctrl_module_sysc = {
438 .rev_offs = 0x0000,
439 };
441 static struct omap_hwmod_class omap54xx_ctrl_module_hwmod_class = {
442 .name = "ctrl_module",
443 .sysc = &omap54xx_ctrl_module_sysc,
444 };
446 /* ctrl_module_core */
447 static struct omap_hwmod_irq_info omap54xx_ctrl_module_core_irqs[] = {
448 { .name = "sec_evts", .irq = 8 + OMAP54XX_IRQ_GIC_START },
449 { .name = "thermal_alert", .irq = 126 + OMAP54XX_IRQ_GIC_START },
450 { .irq = -1 }
451 };
453 static struct omap_hwmod omap54xx_ctrl_module_core_hwmod = {
454 .name = "ctrl_module_core",
455 .class = &omap54xx_ctrl_module_hwmod_class,
456 .clkdm_name = "l4cfg_clkdm",
457 .mpu_irqs = omap54xx_ctrl_module_core_irqs,
458 .prcm = {
459 .omap4 = {
460 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
461 },
462 },
463 };
465 /* ctrl_module_wkup */
466 static struct omap_hwmod omap54xx_ctrl_module_wkup_hwmod = {
467 .name = "ctrl_module_wkup",
468 .class = &omap54xx_ctrl_module_hwmod_class,
469 .clkdm_name = "wkupaon_clkdm",
470 .prcm = {
471 .omap4 = {
472 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
473 },
474 },
475 };
477 /*
478 * 'dma' class
479 * dma controller for data exchange between memory to memory (i.e. internal or
480 * external memory) and gp peripherals to memory or memory to gp peripherals
481 */
483 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
484 .rev_offs = 0x0000,
485 .sysc_offs = 0x002c,
486 .syss_offs = 0x0028,
487 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
488 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
489 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
490 SYSS_HAS_RESET_STATUS),
491 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
492 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
493 .sysc_fields = &omap_hwmod_sysc_type1,
494 };
496 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
497 .name = "dma",
498 .sysc = &omap54xx_dma_sysc,
499 };
501 /* dma dev_attr */
502 static struct omap_dma_dev_attr dma_dev_attr = {
503 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
504 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
505 .lch_count = 32,
506 };
508 /* dma_system */
509 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
510 { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
511 { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
512 { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
513 { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
514 { .irq = -1 }
515 };
517 static struct omap_hwmod omap54xx_dma_system_hwmod = {
518 .name = "dma_system",
519 .class = &omap54xx_dma_hwmod_class,
520 .clkdm_name = "dma_clkdm",
521 .mpu_irqs = omap54xx_dma_system_irqs,
522 .main_clk = "l3_iclk_div",
523 .prcm = {
524 .omap4 = {
525 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
526 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
527 },
528 },
529 .dev_attr = &dma_dev_attr,
530 };
532 /*
533 * 'dmic' class
534 * digital microphone controller
535 */
537 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
538 .rev_offs = 0x0000,
539 .sysc_offs = 0x0010,
540 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
541 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
542 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
543 SIDLE_SMART_WKUP),
544 .sysc_fields = &omap_hwmod_sysc_type2,
545 };
547 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
548 .name = "dmic",
549 .sysc = &omap54xx_dmic_sysc,
550 };
552 /* dmic */
553 static struct omap_hwmod_irq_info omap54xx_dmic_irqs[] = {
554 { .irq = 114 + OMAP54XX_IRQ_GIC_START },
555 { .irq = -1 }
556 };
558 static struct omap_hwmod_dma_info omap54xx_dmic_sdma_reqs[] = {
559 { .dma_req = 66 + OMAP54XX_DMA_REQ_START },
560 { .dma_req = -1 }
561 };
563 static struct omap_hwmod omap54xx_dmic_hwmod = {
564 .name = "dmic",
565 .class = &omap54xx_dmic_hwmod_class,
566 .clkdm_name = "abe_clkdm",
567 .mpu_irqs = omap54xx_dmic_irqs,
568 .sdma_reqs = omap54xx_dmic_sdma_reqs,
569 .main_clk = "dmic_gfclk",
570 .prcm = {
571 .omap4 = {
572 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
573 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
574 .modulemode = MODULEMODE_SWCTRL,
575 },
576 },
577 };
579 /*
580 * 'dsp' class
581 * dsp sub-system
582 */
584 static struct omap_hwmod_class omap54xx_dsp_hwmod_class = {
585 .name = "dsp",
586 };
588 /* dsp */
589 static struct omap_hwmod_irq_info omap54xx_dsp_irqs[] = {
590 { .irq = 28 + OMAP54XX_IRQ_GIC_START },
591 { .irq = -1 }
592 };
594 static struct omap_hwmod_rst_info omap54xx_dsp_resets[] = {
595 { .name = "dsp", .rst_shift = 0 },
596 { .name = "mmu_cache", .rst_shift = 1 },
597 };
599 static struct omap_hwmod omap54xx_dsp_hwmod = {
600 .name = "dsp",
601 .class = &omap54xx_dsp_hwmod_class,
602 .clkdm_name = "dsp_clkdm",
603 .mpu_irqs = omap54xx_dsp_irqs,
604 .rst_lines = omap54xx_dsp_resets,
605 .rst_lines_cnt = ARRAY_SIZE(omap54xx_dsp_resets),
606 .main_clk = "dpll_iva_h11x2_ck",
607 .prcm = {
608 .omap4 = {
609 .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
610 .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
611 .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
612 .modulemode = MODULEMODE_HWCTRL,
613 },
614 },
615 };
617 /*
618 * 'dss' class
619 * display sub-system
620 */
622 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
623 .rev_offs = 0x0000,
624 .syss_offs = 0x0014,
625 .sysc_flags = SYSS_HAS_RESET_STATUS,
626 };
628 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
629 .name = "dss",
630 .sysc = &omap54xx_dss_sysc,
631 .reset = omap_dss_reset,
632 };
634 /* dss */
635 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
636 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
637 { .role = "sys_clk", .clk = "dss_sys_clk" },
638 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
639 };
641 static struct omap_hwmod omap54xx_dss_hwmod = {
642 .name = "dss_core",
643 .class = &omap54xx_dss_hwmod_class,
644 .clkdm_name = "dss_clkdm",
645 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
646 .main_clk = "dss_dss_clk",
647 .prcm = {
648 .omap4 = {
649 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
650 .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
651 .modulemode = MODULEMODE_SWCTRL,
652 },
653 },
654 .opt_clks = dss_opt_clks,
655 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
656 };
658 /*
659 * 'dispc' class
660 * display controller
661 */
663 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
664 .rev_offs = 0x0000,
665 .sysc_offs = 0x0010,
666 .syss_offs = 0x0014,
667 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
668 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
669 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
670 SYSS_HAS_RESET_STATUS),
671 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
672 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
673 .sysc_fields = &omap_hwmod_sysc_type1,
674 };
676 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
677 .name = "dispc",
678 .sysc = &omap54xx_dispc_sysc,
679 };
681 /* dss_dispc */
682 static struct omap_hwmod_irq_info omap54xx_dss_dispc_irqs[] = {
683 { .irq = 25 + OMAP54XX_IRQ_GIC_START },
684 { .irq = -1 }
685 };
687 static struct omap_hwmod_dma_info omap54xx_dss_dispc_sdma_reqs[] = {
688 { .dma_req = 5 + OMAP54XX_DMA_REQ_START },
689 { .dma_req = -1 }
690 };
692 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
693 { .role = "sys_clk", .clk = "dss_sys_clk" },
694 };
696 /* dss_dispc dev_attr */
697 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
698 .has_framedonetv_irq = 1,
699 .manager_count = 4,
700 };
702 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
703 .name = "dss_dispc",
704 .class = &omap54xx_dispc_hwmod_class,
705 .clkdm_name = "dss_clkdm",
706 .mpu_irqs = omap54xx_dss_dispc_irqs,
707 .sdma_reqs = omap54xx_dss_dispc_sdma_reqs,
708 .main_clk = "dss_dss_clk",
709 .prcm = {
710 .omap4 = {
711 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
712 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
713 },
714 },
715 .opt_clks = dss_dispc_opt_clks,
716 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
717 .dev_attr = &dss_dispc_dev_attr,
718 };
720 /*
721 * 'dsi1' class
722 * display serial interface controller
723 */
725 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
726 .rev_offs = 0x0000,
727 .sysc_offs = 0x0010,
728 .syss_offs = 0x0014,
729 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
730 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
731 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
732 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
733 .sysc_fields = &omap_hwmod_sysc_type1,
734 };
736 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
737 .name = "dsi1",
738 .sysc = &omap54xx_dsi1_sysc,
739 };
741 /* dss_dsi1_a */
742 static struct omap_hwmod_irq_info omap54xx_dss_dsi1_a_irqs[] = {
743 { .irq = 53 + OMAP54XX_IRQ_GIC_START },
744 { .irq = -1 }
745 };
747 static struct omap_hwmod_dma_info omap54xx_dss_dsi1_a_sdma_reqs[] = {
748 { .dma_req = 74 + OMAP54XX_DMA_REQ_START },
749 { .dma_req = -1 }
750 };
752 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
753 { .role = "sys_clk", .clk = "dss_sys_clk" },
754 };
756 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
757 .name = "dss_dsi1_a",
758 .class = &omap54xx_dsi1_hwmod_class,
759 .clkdm_name = "dss_clkdm",
760 .mpu_irqs = omap54xx_dss_dsi1_a_irqs,
761 .sdma_reqs = omap54xx_dss_dsi1_a_sdma_reqs,
762 .main_clk = "dss_dss_clk",
763 .prcm = {
764 .omap4 = {
765 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
766 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
767 },
768 },
769 .opt_clks = dss_dsi1_a_opt_clks,
770 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks),
771 };
773 /* dss_dsi1_b */
774 static struct omap_hwmod omap54xx_dss_dsi1_b_hwmod = {
775 .name = "dss_dsi1_b",
776 .class = &omap54xx_dsi1_hwmod_class,
777 .clkdm_name = "dss_clkdm",
778 .main_clk = "dss_dss_clk",
779 .prcm = {
780 .omap4 = {
781 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
782 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
783 },
784 },
785 };
787 /* dss_dsi1_c */
788 static struct omap_hwmod_irq_info omap54xx_dss_dsi1_c_irqs[] = {
789 { .irq = 55 + OMAP54XX_IRQ_GIC_START },
790 { .irq = -1 }
791 };
793 static struct omap_hwmod_dma_info omap54xx_dss_dsi1_c_sdma_reqs[] = {
794 { .dma_req = 83 + OMAP54XX_DMA_REQ_START },
795 { .dma_req = -1 }
796 };
798 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
799 { .role = "sys_clk", .clk = "dss_sys_clk" },
800 };
802 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
803 .name = "dss_dsi1_c",
804 .class = &omap54xx_dsi1_hwmod_class,
805 .clkdm_name = "dss_clkdm",
806 .mpu_irqs = omap54xx_dss_dsi1_c_irqs,
807 .sdma_reqs = omap54xx_dss_dsi1_c_sdma_reqs,
808 .main_clk = "dss_dss_clk",
809 .prcm = {
810 .omap4 = {
811 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
812 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
813 },
814 },
815 .opt_clks = dss_dsi1_c_opt_clks,
816 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks),
817 };
819 /*
820 * 'hdmi' class
821 * hdmi controller
822 */
824 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
825 .rev_offs = 0x0000,
826 .sysc_offs = 0x0010,
827 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
828 SYSC_HAS_SOFTRESET),
829 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
830 SIDLE_SMART_WKUP),
831 .sysc_fields = &omap_hwmod_sysc_type2,
832 };
834 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
835 .name = "hdmi",
836 .sysc = &omap54xx_hdmi_sysc,
837 };
839 /* dss_hdmi */
840 static struct omap_hwmod_irq_info omap54xx_dss_hdmi_irqs[] = {
841 { .irq = 101 + OMAP54XX_IRQ_GIC_START },
842 { .irq = -1 }
843 };
845 static struct omap_hwmod_dma_info omap54xx_dss_hdmi_sdma_reqs[] = {
846 { .dma_req = 75 + OMAP54XX_DMA_REQ_START },
847 { .dma_req = -1 }
848 };
850 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
851 { .role = "sys_clk", .clk = "dss_sys_clk" },
852 };
854 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
855 .name = "dss_hdmi",
856 .class = &omap54xx_hdmi_hwmod_class,
857 .clkdm_name = "dss_clkdm",
858 .mpu_irqs = omap54xx_dss_hdmi_irqs,
859 .sdma_reqs = omap54xx_dss_hdmi_sdma_reqs,
860 .main_clk = "dss_48mhz_clk",
861 .prcm = {
862 .omap4 = {
863 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
864 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
865 },
866 },
867 .opt_clks = dss_hdmi_opt_clks,
868 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
869 };
871 /*
872 * 'rfbi' class
873 * remote frame buffer interface
874 */
876 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
877 .rev_offs = 0x0000,
878 .sysc_offs = 0x0010,
879 .syss_offs = 0x0014,
880 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
881 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
882 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
883 .sysc_fields = &omap_hwmod_sysc_type1,
884 };
886 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
887 .name = "rfbi",
888 .sysc = &omap54xx_rfbi_sysc,
889 };
891 /* dss_rfbi */
892 static struct omap_hwmod_dma_info omap54xx_dss_rfbi_sdma_reqs[] = {
893 { .dma_req = 13 + OMAP54XX_DMA_REQ_START },
894 { .dma_req = -1 }
895 };
897 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
898 { .role = "ick", .clk = "l3_iclk_div" },
899 };
901 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
902 .name = "dss_rfbi",
903 .class = &omap54xx_rfbi_hwmod_class,
904 .clkdm_name = "dss_clkdm",
905 .sdma_reqs = omap54xx_dss_rfbi_sdma_reqs,
906 .prcm = {
907 .omap4 = {
908 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
909 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
910 },
911 },
912 .opt_clks = dss_rfbi_opt_clks,
913 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
914 };
916 /*
917 * 'elm' class
918 * bch error location module
919 */
921 static struct omap_hwmod_class_sysconfig omap54xx_elm_sysc = {
922 .rev_offs = 0x0000,
923 .sysc_offs = 0x0010,
924 .syss_offs = 0x0014,
925 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
926 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
927 SYSS_HAS_RESET_STATUS),
928 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
929 .sysc_fields = &omap_hwmod_sysc_type1,
930 };
932 static struct omap_hwmod_class omap54xx_elm_hwmod_class = {
933 .name = "elm",
934 .sysc = &omap54xx_elm_sysc,
935 };
937 /* elm */
938 static struct omap_hwmod_irq_info omap54xx_elm_irqs[] = {
939 { .irq = 4 + OMAP54XX_IRQ_GIC_START },
940 { .irq = -1 }
941 };
943 static struct omap_hwmod omap54xx_elm_hwmod = {
944 .name = "elm",
945 .class = &omap54xx_elm_hwmod_class,
946 .clkdm_name = "l4per_clkdm",
947 .mpu_irqs = omap54xx_elm_irqs,
948 .main_clk = "l4_root_clk_div",
949 .prcm = {
950 .omap4 = {
951 .clkctrl_offs = OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
952 .context_offs = OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET,
953 },
954 },
955 };
957 /*
958 * 'emif' class
959 * external memory interface no1 (wrapper)
960 */
962 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
963 .rev_offs = 0x0000,
964 };
966 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
967 .name = "emif",
968 .sysc = &omap54xx_emif_sysc,
969 };
971 /* emif1 */
972 static struct omap_hwmod_irq_info omap54xx_emif1_irqs[] = {
973 { .irq = 110 + OMAP54XX_IRQ_GIC_START },
974 { .irq = -1 }
975 };
977 static struct omap_hwmod omap54xx_emif1_hwmod = {
978 .name = "emif1",
979 .class = &omap54xx_emif_hwmod_class,
980 .clkdm_name = "emif_clkdm",
981 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
982 .mpu_irqs = omap54xx_emif1_irqs,
983 .main_clk = "dpll_core_h11x2_ck",
984 .prcm = {
985 .omap4 = {
986 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
987 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
988 .modulemode = MODULEMODE_HWCTRL,
989 },
990 },
991 };
993 /* emif2 */
994 static struct omap_hwmod_irq_info omap54xx_emif2_irqs[] = {
995 { .irq = 111 + OMAP54XX_IRQ_GIC_START },
996 { .irq = -1 }
997 };
999 static struct omap_hwmod omap54xx_emif2_hwmod = {
1000 .name = "emif2",
1001 .class = &omap54xx_emif_hwmod_class,
1002 .clkdm_name = "emif_clkdm",
1003 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1004 .mpu_irqs = omap54xx_emif2_irqs,
1005 .main_clk = "dpll_core_h11x2_ck",
1006 .prcm = {
1007 .omap4 = {
1008 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
1009 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
1010 .modulemode = MODULEMODE_HWCTRL,
1011 },
1012 },
1013 };
1015 /*
1016 * 'fdif' class
1017 * face detection hw accelerator module
1018 */
1020 static struct omap_hwmod_class_sysconfig omap54xx_fdif_sysc = {
1021 .rev_offs = 0x0000,
1022 .sysc_offs = 0x0010,
1023 /*
1024 * FDIF needs 100 OCP clk cycles delay after a softreset before
1025 * accessing sysconfig again.
1026 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1027 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1028 *
1029 * TODO: Indicate errata when available.
1030 */
1031 .srst_udelay = 2,
1032 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1033 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1034 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1035 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1036 .sysc_fields = &omap_hwmod_sysc_type2,
1037 };
1039 static struct omap_hwmod_class omap54xx_fdif_hwmod_class = {
1040 .name = "fdif",
1041 .sysc = &omap54xx_fdif_sysc,
1042 };
1044 /* fdif */
1045 static struct omap_hwmod_irq_info omap54xx_fdif_irqs[] = {
1046 { .irq = 69 + OMAP54XX_IRQ_GIC_START },
1047 { .irq = -1 }
1048 };
1050 static struct omap_hwmod omap54xx_fdif_hwmod = {
1051 .name = "fdif",
1052 .class = &omap54xx_fdif_hwmod_class,
1053 .clkdm_name = "cam_clkdm",
1054 .mpu_irqs = omap54xx_fdif_irqs,
1055 .main_clk = "fdif_fclk",
1056 .prcm = {
1057 .omap4 = {
1058 .clkctrl_offs = OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET,
1059 .context_offs = OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET,
1060 .modulemode = MODULEMODE_SWCTRL,
1061 },
1062 },
1063 };
1065 /*
1066 * 'gpio' class
1067 * general purpose io module
1068 */
1070 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
1071 .rev_offs = 0x0000,
1072 .sysc_offs = 0x0010,
1073 .syss_offs = 0x0114,
1074 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1075 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1076 SYSS_HAS_RESET_STATUS),
1077 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1078 SIDLE_SMART_WKUP),
1079 .sysc_fields = &omap_hwmod_sysc_type1,
1080 };
1082 static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
1083 .name = "gpio",
1084 .sysc = &omap54xx_gpio_sysc,
1085 .rev = 2,
1086 };
1088 /* gpio dev_attr */
1089 static struct omap_gpio_dev_attr gpio_dev_attr = {
1090 .bank_width = 32,
1091 .dbck_flag = true,
1092 };
1094 /* gpio1 */
1095 static struct omap_hwmod_irq_info omap54xx_gpio1_irqs[] = {
1096 { .irq = 29 + OMAP54XX_IRQ_GIC_START },
1097 { .irq = -1 }
1098 };
1100 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1101 { .role = "dbclk", .clk = "gpio1_dbclk" },
1102 };
1104 static struct omap_hwmod omap54xx_gpio1_hwmod = {
1105 .name = "gpio1",
1106 .class = &omap54xx_gpio_hwmod_class,
1107 .clkdm_name = "wkupaon_clkdm",
1108 .mpu_irqs = omap54xx_gpio1_irqs,
1109 .main_clk = "wkupaon_iclk_mux",
1110 .prcm = {
1111 .omap4 = {
1112 .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
1113 .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
1114 .modulemode = MODULEMODE_HWCTRL,
1115 },
1116 },
1117 .opt_clks = gpio1_opt_clks,
1118 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1119 .dev_attr = &gpio_dev_attr,
1120 };
1122 /* gpio2 */
1123 static struct omap_hwmod_irq_info omap54xx_gpio2_irqs[] = {
1124 { .irq = 30 + OMAP54XX_IRQ_GIC_START },
1125 { .irq = -1 }
1126 };
1128 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1129 { .role = "dbclk", .clk = "gpio2_dbclk" },
1130 };
1132 static struct omap_hwmod omap54xx_gpio2_hwmod = {
1133 .name = "gpio2",
1134 .class = &omap54xx_gpio_hwmod_class,
1135 .clkdm_name = "l4per_clkdm",
1136 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1137 .mpu_irqs = omap54xx_gpio2_irqs,
1138 .main_clk = "l4_root_clk_div",
1139 .prcm = {
1140 .omap4 = {
1141 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1142 .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1143 .modulemode = MODULEMODE_HWCTRL,
1144 },
1145 },
1146 .opt_clks = gpio2_opt_clks,
1147 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1148 .dev_attr = &gpio_dev_attr,
1149 };
1151 /* gpio3 */
1152 static struct omap_hwmod_irq_info omap54xx_gpio3_irqs[] = {
1153 { .irq = 31 + OMAP54XX_IRQ_GIC_START },
1154 { .irq = -1 }
1155 };
1157 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1158 { .role = "dbclk", .clk = "gpio3_dbclk" },
1159 };
1161 static struct omap_hwmod omap54xx_gpio3_hwmod = {
1162 .name = "gpio3",
1163 .class = &omap54xx_gpio_hwmod_class,
1164 .clkdm_name = "l4per_clkdm",
1165 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1166 .mpu_irqs = omap54xx_gpio3_irqs,
1167 .main_clk = "l4_root_clk_div",
1168 .prcm = {
1169 .omap4 = {
1170 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1171 .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1172 .modulemode = MODULEMODE_HWCTRL,
1173 },
1174 },
1175 .opt_clks = gpio3_opt_clks,
1176 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1177 .dev_attr = &gpio_dev_attr,
1178 };
1180 /* gpio4 */
1181 static struct omap_hwmod_irq_info omap54xx_gpio4_irqs[] = {
1182 { .irq = 32 + OMAP54XX_IRQ_GIC_START },
1183 { .irq = -1 }
1184 };
1186 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1187 { .role = "dbclk", .clk = "gpio4_dbclk" },
1188 };
1190 static struct omap_hwmod omap54xx_gpio4_hwmod = {
1191 .name = "gpio4",
1192 .class = &omap54xx_gpio_hwmod_class,
1193 .clkdm_name = "l4per_clkdm",
1194 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1195 .mpu_irqs = omap54xx_gpio4_irqs,
1196 .main_clk = "l4_root_clk_div",
1197 .prcm = {
1198 .omap4 = {
1199 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1200 .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1201 .modulemode = MODULEMODE_HWCTRL,
1202 },
1203 },
1204 .opt_clks = gpio4_opt_clks,
1205 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1206 .dev_attr = &gpio_dev_attr,
1207 };
1209 /* gpio5 */
1210 static struct omap_hwmod_irq_info omap54xx_gpio5_irqs[] = {
1211 { .irq = 33 + OMAP54XX_IRQ_GIC_START },
1212 { .irq = -1 }
1213 };
1215 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1216 { .role = "dbclk", .clk = "gpio5_dbclk" },
1217 };
1219 static struct omap_hwmod omap54xx_gpio5_hwmod = {
1220 .name = "gpio5",
1221 .class = &omap54xx_gpio_hwmod_class,
1222 .clkdm_name = "l4per_clkdm",
1223 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1224 .mpu_irqs = omap54xx_gpio5_irqs,
1225 .main_clk = "l4_root_clk_div",
1226 .prcm = {
1227 .omap4 = {
1228 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1229 .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1230 .modulemode = MODULEMODE_HWCTRL,
1231 },
1232 },
1233 .opt_clks = gpio5_opt_clks,
1234 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1235 .dev_attr = &gpio_dev_attr,
1236 };
1238 /* gpio6 */
1239 static struct omap_hwmod_irq_info omap54xx_gpio6_irqs[] = {
1240 { .irq = 34 + OMAP54XX_IRQ_GIC_START },
1241 { .irq = -1 }
1242 };
1244 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1245 { .role = "dbclk", .clk = "gpio6_dbclk" },
1246 };
1248 static struct omap_hwmod omap54xx_gpio6_hwmod = {
1249 .name = "gpio6",
1250 .class = &omap54xx_gpio_hwmod_class,
1251 .clkdm_name = "l4per_clkdm",
1252 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1253 .mpu_irqs = omap54xx_gpio6_irqs,
1254 .main_clk = "l4_root_clk_div",
1255 .prcm = {
1256 .omap4 = {
1257 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1258 .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1259 .modulemode = MODULEMODE_HWCTRL,
1260 },
1261 },
1262 .opt_clks = gpio6_opt_clks,
1263 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1264 .dev_attr = &gpio_dev_attr,
1265 };
1267 /* gpio7 */
1268 static struct omap_hwmod_irq_info omap54xx_gpio7_irqs[] = {
1269 { .irq = 35 + OMAP54XX_IRQ_GIC_START },
1270 { .irq = -1 }
1271 };
1273 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
1274 { .role = "dbclk", .clk = "gpio7_dbclk" },
1275 };
1277 static struct omap_hwmod omap54xx_gpio7_hwmod = {
1278 .name = "gpio7",
1279 .class = &omap54xx_gpio_hwmod_class,
1280 .clkdm_name = "l4per_clkdm",
1281 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1282 .mpu_irqs = omap54xx_gpio7_irqs,
1283 .main_clk = "l4_root_clk_div",
1284 .prcm = {
1285 .omap4 = {
1286 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
1287 .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
1288 .modulemode = MODULEMODE_HWCTRL,
1289 },
1290 },
1291 .opt_clks = gpio7_opt_clks,
1292 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
1293 .dev_attr = &gpio_dev_attr,
1294 };
1296 /* gpio8 */
1297 static struct omap_hwmod_irq_info omap54xx_gpio8_irqs[] = {
1298 { .irq = 121 + OMAP54XX_IRQ_GIC_START },
1299 { .irq = -1 }
1300 };
1302 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
1303 { .role = "dbclk", .clk = "gpio8_dbclk" },
1304 };
1306 static struct omap_hwmod omap54xx_gpio8_hwmod = {
1307 .name = "gpio8",
1308 .class = &omap54xx_gpio_hwmod_class,
1309 .clkdm_name = "l4per_clkdm",
1310 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1311 .mpu_irqs = omap54xx_gpio8_irqs,
1312 .main_clk = "l4_root_clk_div",
1313 .prcm = {
1314 .omap4 = {
1315 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1316 .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1317 .modulemode = MODULEMODE_HWCTRL,
1318 },
1319 },
1320 .opt_clks = gpio8_opt_clks,
1321 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
1322 .dev_attr = &gpio_dev_attr,
1323 };
1325 /*
1326 * 'gpmc' class
1327 * general purpose memory controller
1328 */
1330 static struct omap_hwmod_class_sysconfig omap54xx_gpmc_sysc = {
1331 .rev_offs = 0x0000,
1332 .sysc_offs = 0x0010,
1333 .syss_offs = 0x0014,
1334 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1335 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1336 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1337 .sysc_fields = &omap_hwmod_sysc_type1,
1338 };
1340 static struct omap_hwmod_class omap54xx_gpmc_hwmod_class = {
1341 .name = "gpmc",
1342 .sysc = &omap54xx_gpmc_sysc,
1343 };
1345 /* gpmc */
1346 static struct omap_hwmod_irq_info omap54xx_gpmc_irqs[] = {
1347 { .irq = 20 + OMAP54XX_IRQ_GIC_START },
1348 { .irq = -1 }
1349 };
1351 static struct omap_hwmod_dma_info omap54xx_gpmc_sdma_reqs[] = {
1352 { .dma_req = 3 + OMAP54XX_DMA_REQ_START },
1353 { .dma_req = -1 }
1354 };
1356 static struct omap_hwmod omap54xx_gpmc_hwmod = {
1357 .name = "gpmc",
1358 .class = &omap54xx_gpmc_hwmod_class,
1359 .clkdm_name = "l3main2_clkdm",
1360 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1361 .mpu_irqs = omap54xx_gpmc_irqs,
1362 .sdma_reqs = omap54xx_gpmc_sdma_reqs,
1363 .main_clk = "l3_iclk_div",
1364 .prcm = {
1365 .omap4 = {
1366 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET,
1367 .context_offs = OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET,
1368 .modulemode = MODULEMODE_HWCTRL,
1369 },
1370 },
1371 };
1373 /*
1374 * 'gpu' class
1375 * 2d/3d graphics accelerator
1376 */
1378 static struct omap_hwmod_class_sysconfig omap54xx_gpu_sysc = {
1379 .rev_offs = 0x0000,
1380 .sysc_offs = 0x0010,
1381 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1382 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1383 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1384 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1385 .sysc_fields = &omap_hwmod_sysc_type2,
1386 };
1388 static struct omap_hwmod_class omap54xx_gpu_hwmod_class = {
1389 .name = "gpu",
1390 .sysc = &omap54xx_gpu_sysc,
1391 };
1393 /* gpu */
1394 static struct omap_hwmod_irq_info omap54xx_gpu_irqs[] = {
1395 { .irq = 21 + OMAP54XX_IRQ_GIC_START },
1396 { .irq = -1 }
1397 };
1399 static struct omap_hwmod omap54xx_gpu_hwmod = {
1400 .name = "gpu",
1401 .class = &omap54xx_gpu_hwmod_class,
1402 .clkdm_name = "gpu_clkdm",
1403 .mpu_irqs = omap54xx_gpu_irqs,
1404 .main_clk = "gpu_core_gclk_mux",
1405 .prcm = {
1406 .omap4 = {
1407 .clkctrl_offs = OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET,
1408 .context_offs = OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET,
1409 .modulemode = MODULEMODE_SWCTRL,
1410 },
1411 },
1412 };
1414 /*
1415 * 'hdq1w' class
1416 * hdq / 1-wire serial interface controller
1417 */
1419 static struct omap_hwmod_class_sysconfig omap54xx_hdq1w_sysc = {
1420 .rev_offs = 0x0000,
1421 .sysc_offs = 0x0014,
1422 .syss_offs = 0x0018,
1423 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1424 SYSS_HAS_RESET_STATUS),
1425 .sysc_fields = &omap_hwmod_sysc_type1,
1426 };
1428 static struct omap_hwmod_class omap54xx_hdq1w_hwmod_class = {
1429 .name = "hdq1w",
1430 .sysc = &omap54xx_hdq1w_sysc,
1431 };
1433 /* hdq1w */
1434 static struct omap_hwmod_irq_info omap54xx_hdq1w_irqs[] = {
1435 { .irq = 58 + OMAP54XX_IRQ_GIC_START },
1436 { .irq = -1 }
1437 };
1439 static struct omap_hwmod omap54xx_hdq1w_hwmod = {
1440 .name = "hdq1w",
1441 .class = &omap54xx_hdq1w_hwmod_class,
1442 .clkdm_name = "l4per_clkdm",
1443 .flags = HWMOD_INIT_NO_RESET,
1444 .mpu_irqs = omap54xx_hdq1w_irqs,
1445 .main_clk = "func_12m_fclk",
1446 .prcm = {
1447 .omap4 = {
1448 .clkctrl_offs = OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1449 .context_offs = OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1450 .modulemode = MODULEMODE_SWCTRL,
1451 },
1452 },
1453 };
1455 /*
1456 * 'hsi' class
1457 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1458 * serial if)
1459 */
1461 static struct omap_hwmod_class_sysconfig omap54xx_hsi_sysc = {
1462 .rev_offs = 0x0000,
1463 .sysc_offs = 0x0010,
1464 .syss_offs = 0x0014,
1465 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1466 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1467 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1468 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1469 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1470 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1471 .sysc_fields = &omap_hwmod_sysc_type1,
1472 };
1474 static struct omap_hwmod_class omap54xx_hsi_hwmod_class = {
1475 .name = "hsi",
1476 .sysc = &omap54xx_hsi_sysc,
1477 };
1479 /* hsi */
1480 static struct omap_hwmod_irq_info omap54xx_hsi_irqs[] = {
1481 { .name = "mpu_p1", .irq = 67 + OMAP54XX_IRQ_GIC_START },
1482 { .name = "mpu_p2", .irq = 68 + OMAP54XX_IRQ_GIC_START },
1483 { .name = "mpu_dma", .irq = 71 + OMAP54XX_IRQ_GIC_START },
1484 { .irq = -1 }
1485 };
1487 static struct omap_hwmod omap54xx_hsi_hwmod = {
1488 .name = "hsi",
1489 .class = &omap54xx_hsi_hwmod_class,
1490 .clkdm_name = "l3init_clkdm",
1491 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1492 .mpu_irqs = omap54xx_hsi_irqs,
1493 .main_clk = "hsi_fclk",
1494 .prcm = {
1495 .omap4 = {
1496 .clkctrl_offs = OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1497 .context_offs = OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET,
1498 .modulemode = MODULEMODE_HWCTRL,
1499 },
1500 },
1501 };
1503 /*
1504 * 'i2c' class
1505 * multimaster high-speed i2c controller
1506 */
1508 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
1509 .sysc_offs = 0x0010,
1510 .syss_offs = 0x0090,
1511 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1512 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1513 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1514 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1515 SIDLE_SMART_WKUP),
1516 .clockact = CLOCKACT_TEST_ICLK,
1517 .sysc_fields = &omap_hwmod_sysc_type1,
1518 };
1520 static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
1521 .name = "i2c",
1522 .sysc = &omap54xx_i2c_sysc,
1523 .reset = &omap_i2c_reset,
1524 .rev = OMAP_I2C_IP_VERSION_2,
1525 };
1527 /* i2c dev_attr */
1528 static struct omap_i2c_dev_attr i2c_dev_attr = {
1529 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1530 };
1532 /* i2c1 */
1533 static struct omap_hwmod_irq_info omap54xx_i2c1_irqs[] = {
1534 { .irq = 56 + OMAP54XX_IRQ_GIC_START },
1535 { .irq = -1 }
1536 };
1538 static struct omap_hwmod_dma_info omap54xx_i2c1_sdma_reqs[] = {
1539 { .name = "tx", .dma_req = 26 + OMAP54XX_DMA_REQ_START },
1540 { .name = "rx", .dma_req = 27 + OMAP54XX_DMA_REQ_START },
1541 { .dma_req = -1 }
1542 };
1544 static struct omap_hwmod omap54xx_i2c1_hwmod = {
1545 .name = "i2c1",
1546 .class = &omap54xx_i2c_hwmod_class,
1547 .clkdm_name = "l4per_clkdm",
1548 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1549 .mpu_irqs = omap54xx_i2c1_irqs,
1550 .sdma_reqs = omap54xx_i2c1_sdma_reqs,
1551 .main_clk = "func_96m_fclk",
1552 .prcm = {
1553 .omap4 = {
1554 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1555 .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1556 .modulemode = MODULEMODE_SWCTRL,
1557 },
1558 },
1559 .dev_attr = &i2c_dev_attr,
1560 };
1562 /* i2c2 */
1563 static struct omap_hwmod_irq_info omap54xx_i2c2_irqs[] = {
1564 { .irq = 57 + OMAP54XX_IRQ_GIC_START },
1565 { .irq = -1 }
1566 };
1568 static struct omap_hwmod_dma_info omap54xx_i2c2_sdma_reqs[] = {
1569 { .name = "tx", .dma_req = 28 + OMAP54XX_DMA_REQ_START },
1570 { .name = "rx", .dma_req = 29 + OMAP54XX_DMA_REQ_START },
1571 { .dma_req = -1 }
1572 };
1574 static struct omap_hwmod omap54xx_i2c2_hwmod = {
1575 .name = "i2c2",
1576 .class = &omap54xx_i2c_hwmod_class,
1577 .clkdm_name = "l4per_clkdm",
1578 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1579 .mpu_irqs = omap54xx_i2c2_irqs,
1580 .sdma_reqs = omap54xx_i2c2_sdma_reqs,
1581 .main_clk = "func_96m_fclk",
1582 .prcm = {
1583 .omap4 = {
1584 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1585 .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1586 .modulemode = MODULEMODE_SWCTRL,
1587 },
1588 },
1589 .dev_attr = &i2c_dev_attr,
1590 };
1592 /* i2c3 */
1593 static struct omap_hwmod_irq_info omap54xx_i2c3_irqs[] = {
1594 { .irq = 61 + OMAP54XX_IRQ_GIC_START },
1595 { .irq = -1 }
1596 };
1598 static struct omap_hwmod_dma_info omap54xx_i2c3_sdma_reqs[] = {
1599 { .name = "tx", .dma_req = 24 + OMAP54XX_DMA_REQ_START },
1600 { .name = "rx", .dma_req = 25 + OMAP54XX_DMA_REQ_START },
1601 { .dma_req = -1 }
1602 };
1604 static struct omap_hwmod omap54xx_i2c3_hwmod = {
1605 .name = "i2c3",
1606 .class = &omap54xx_i2c_hwmod_class,
1607 .clkdm_name = "l4per_clkdm",
1608 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1609 .mpu_irqs = omap54xx_i2c3_irqs,
1610 .sdma_reqs = omap54xx_i2c3_sdma_reqs,
1611 .main_clk = "func_96m_fclk",
1612 .prcm = {
1613 .omap4 = {
1614 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1615 .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1616 .modulemode = MODULEMODE_SWCTRL,
1617 },
1618 },
1619 .dev_attr = &i2c_dev_attr,
1620 };
1622 /* i2c4 */
1623 static struct omap_hwmod_irq_info omap54xx_i2c4_irqs[] = {
1624 { .irq = 62 + OMAP54XX_IRQ_GIC_START },
1625 { .irq = -1 }
1626 };
1628 static struct omap_hwmod_dma_info omap54xx_i2c4_sdma_reqs[] = {
1629 { .name = "tx", .dma_req = 123 + OMAP54XX_DMA_REQ_START },
1630 { .name = "rx", .dma_req = 124 + OMAP54XX_DMA_REQ_START },
1631 { .dma_req = -1 }
1632 };
1634 static struct omap_hwmod omap54xx_i2c4_hwmod = {
1635 .name = "i2c4",
1636 .class = &omap54xx_i2c_hwmod_class,
1637 .clkdm_name = "l4per_clkdm",
1638 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1639 .mpu_irqs = omap54xx_i2c4_irqs,
1640 .sdma_reqs = omap54xx_i2c4_sdma_reqs,
1641 .main_clk = "func_96m_fclk",
1642 .prcm = {
1643 .omap4 = {
1644 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1645 .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1646 .modulemode = MODULEMODE_SWCTRL,
1647 },
1648 },
1649 .dev_attr = &i2c_dev_attr,
1650 };
1652 /* i2c5 */
1653 static struct omap_hwmod_irq_info omap54xx_i2c5_irqs[] = {
1654 { .irq = 60 + OMAP54XX_IRQ_GIC_START },
1655 { .irq = -1 }
1656 };
1658 static struct omap_hwmod omap54xx_i2c5_hwmod = {
1659 .name = "i2c5",
1660 .class = &omap54xx_i2c_hwmod_class,
1661 .clkdm_name = "l4per_clkdm",
1662 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1663 .mpu_irqs = omap54xx_i2c5_irqs,
1664 .main_clk = "func_96m_fclk",
1665 .prcm = {
1666 .omap4 = {
1667 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
1668 .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
1669 .modulemode = MODULEMODE_SWCTRL,
1670 },
1671 },
1672 .dev_attr = &i2c_dev_attr,
1673 };
1675 /*
1676 * 'ipu' class
1677 * imaging processor unit
1678 */
1680 static struct omap_hwmod_class_sysconfig omap54xx_ipu_sysc = {
1681 .rev_offs = 0x0000,
1682 .sysc_offs = 0x0010,
1683 .syss_offs = 0x0014,
1684 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1685 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1686 SYSS_HAS_RESET_STATUS),
1687 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1688 .sysc_fields = &omap_hwmod_sysc_type1,
1689 };
1691 static struct omap_hwmod_class omap54xx_ipu_hwmod_class = {
1692 .name = "ipu",
1693 .sysc = &omap54xx_ipu_sysc,
1694 };
1696 /* ipu */
1697 static struct omap_hwmod_irq_info omap54xx_ipu_irqs[] = {
1698 { .irq = 100 + OMAP54XX_IRQ_GIC_START },
1699 { .irq = -1 }
1700 };
1702 static struct omap_hwmod_rst_info omap54xx_ipu_resets[] = {
1703 { .name = "cpu0", .rst_shift = 0 },
1704 { .name = "cpu1", .rst_shift = 1 },
1705 { .name = "mmu_cache", .rst_shift = 2 },
1706 };
1708 static struct omap_hwmod omap54xx_ipu_hwmod = {
1709 .name = "ipu",
1710 .class = &omap54xx_ipu_hwmod_class,
1711 .clkdm_name = "ipu_clkdm",
1712 .mpu_irqs = omap54xx_ipu_irqs,
1713 .rst_lines = omap54xx_ipu_resets,
1714 .rst_lines_cnt = ARRAY_SIZE(omap54xx_ipu_resets),
1715 .main_clk = "dpll_core_h22x2_ck",
1716 .prcm = {
1717 .omap4 = {
1718 .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
1719 .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
1720 .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
1721 .modulemode = MODULEMODE_HWCTRL,
1722 },
1723 },
1724 };
1726 /*
1727 * 'intc' class
1728 * nested vectored interrupt controller
1729 */
1731 static struct omap_hwmod_class omap54xx_intc_hwmod_class = {
1732 .name = "intc",
1733 };
1735 /* intc_ipu_c0 */
1736 static struct omap_hwmod omap54xx_intc_ipu_c0_hwmod = {
1737 .name = "intc_ipu_c0",
1738 .class = &omap54xx_intc_hwmod_class,
1739 .clkdm_name = "ipu_clkdm",
1740 .main_clk = "dpll_core_h22x2_ck",
1741 .prcm = {
1742 .omap4 = {
1743 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1744 },
1745 },
1746 };
1748 /* intc_ipu_c1 */
1749 static struct omap_hwmod omap54xx_intc_ipu_c1_hwmod = {
1750 .name = "intc_ipu_c1",
1751 .class = &omap54xx_intc_hwmod_class,
1752 .clkdm_name = "ipu_clkdm",
1753 .main_clk = "dpll_core_h22x2_ck",
1754 .prcm = {
1755 .omap4 = {
1756 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
1757 },
1758 },
1759 };
1761 /*
1762 * 'iss' class
1763 * external images sensor pixel data processor
1764 */
1766 static struct omap_hwmod_class_sysconfig omap54xx_iss_sysc = {
1767 .rev_offs = 0x0000,
1768 .sysc_offs = 0x0010,
1769 /*
1770 * ISS needs 100 OCP clk cycles delay after a softreset before
1771 * accessing sysconfig again.
1772 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1773 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1774 *
1775 * TODO: Indicate errata when available.
1776 */
1777 .srst_udelay = 2,
1778 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1779 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1780 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1781 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1782 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1783 .sysc_fields = &omap_hwmod_sysc_type2,
1784 };
1786 static struct omap_hwmod_class omap54xx_iss_hwmod_class = {
1787 .name = "iss",
1788 .sysc = &omap54xx_iss_sysc,
1789 };
1791 /* iss */
1792 static struct omap_hwmod_irq_info omap54xx_iss_irqs[] = {
1793 { .irq = 24 + OMAP54XX_IRQ_GIC_START },
1794 { .irq = -1 }
1795 };
1797 static struct omap_hwmod_dma_info omap54xx_iss_sdma_reqs[] = {
1798 { .name = "1", .dma_req = 8 + OMAP54XX_DMA_REQ_START },
1799 { .name = "2", .dma_req = 9 + OMAP54XX_DMA_REQ_START },
1800 { .name = "3", .dma_req = 11 + OMAP54XX_DMA_REQ_START },
1801 { .name = "4", .dma_req = 12 + OMAP54XX_DMA_REQ_START },
1802 { .name = "5", .dma_req = 30 + OMAP54XX_DMA_REQ_START },
1803 { .name = "6", .dma_req = 31 + OMAP54XX_DMA_REQ_START },
1804 { .name = "7", .dma_req = 125 + OMAP54XX_DMA_REQ_START },
1805 { .name = "8", .dma_req = 126 + OMAP54XX_DMA_REQ_START },
1806 { .dma_req = -1 }
1807 };
1809 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1810 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1811 };
1813 static struct omap_hwmod omap54xx_iss_hwmod = {
1814 .name = "iss",
1815 .class = &omap54xx_iss_hwmod_class,
1816 .clkdm_name = "cam_clkdm",
1817 .flags = HWMOD_INIT_NO_RESET,
1818 .mpu_irqs = omap54xx_iss_irqs,
1819 .sdma_reqs = omap54xx_iss_sdma_reqs,
1820 .main_clk = "dpll_core_h22x2_ck",
1821 .prcm = {
1822 .omap4 = {
1823 .clkctrl_offs = OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET,
1824 .context_offs = OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET,
1825 .modulemode = MODULEMODE_SWCTRL,
1826 },
1827 },
1828 .opt_clks = iss_opt_clks,
1829 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1830 };
1832 /*
1833 * 'iva' class
1834 * multi-standard video encoder/decoder hardware accelerator
1835 */
1837 static struct omap_hwmod_class_sysconfig omap54xx_iva_sysc = {
1838 .rev_offs = 0x0000,
1839 .sysc_offs = 0x0010,
1840 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1841 .idlemodes = (SIDLE_NO | SIDLE_SMART | MSTANDBY_NO |
1842 MSTANDBY_SMART),
1843 .sysc_fields = &omap_hwmod_sysc_type2,
1844 };
1846 static struct omap_hwmod_class omap54xx_iva_hwmod_class = {
1847 .name = "iva",
1848 .sysc = &omap54xx_iva_sysc,
1849 };
1851 /* iva */
1852 static struct omap_hwmod_irq_info omap54xx_iva_irqs[] = {
1853 { .name = "sync_1", .irq = 103 + OMAP54XX_IRQ_GIC_START },
1854 { .name = "sync_0", .irq = 104 + OMAP54XX_IRQ_GIC_START },
1855 { .name = "mailbox_0", .irq = 107 + OMAP54XX_IRQ_GIC_START },
1856 { .irq = -1 }
1857 };
1859 static struct omap_hwmod_rst_info omap54xx_iva_resets[] = {
1860 { .name = "seq0", .rst_shift = 0 },
1861 { .name = "seq1", .rst_shift = 1 },
1862 { .name = "logic", .rst_shift = 2 },
1863 };
1865 static struct omap_hwmod omap54xx_iva_hwmod = {
1866 .name = "iva",
1867 .class = &omap54xx_iva_hwmod_class,
1868 .clkdm_name = "iva_clkdm",
1869 .mpu_irqs = omap54xx_iva_irqs,
1870 .rst_lines = omap54xx_iva_resets,
1871 .rst_lines_cnt = ARRAY_SIZE(omap54xx_iva_resets),
1872 .main_clk = "dpll_iva_h12x2_ck",
1873 .prcm = {
1874 .omap4 = {
1875 .clkctrl_offs = OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET,
1876 .rstctrl_offs = OMAP54XX_RM_IVA_RSTCTRL_OFFSET,
1877 .context_offs = OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET,
1878 .modulemode = MODULEMODE_HWCTRL,
1879 },
1880 },
1881 };
1883 /*
1884 * 'kbd' class
1885 * keyboard controller
1886 */
1888 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
1889 .rev_offs = 0x0000,
1890 .sysc_offs = 0x0010,
1891 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1892 SYSC_HAS_SOFTRESET),
1893 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1894 .sysc_fields = &omap_hwmod_sysc_type1,
1895 };
1897 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
1898 .name = "kbd",
1899 .sysc = &omap54xx_kbd_sysc,
1900 };
1902 /* kbd */
1903 static struct omap_hwmod_irq_info omap54xx_kbd_irqs[] = {
1904 { .irq = 120 + OMAP54XX_IRQ_GIC_START },
1905 { .irq = -1 }
1906 };
1908 static struct omap_hwmod omap54xx_kbd_hwmod = {
1909 .name = "kbd",
1910 .class = &omap54xx_kbd_hwmod_class,
1911 .clkdm_name = "wkupaon_clkdm",
1912 .mpu_irqs = omap54xx_kbd_irqs,
1913 .main_clk = "sys_32k_ck",
1914 .prcm = {
1915 .omap4 = {
1916 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
1917 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
1918 .modulemode = MODULEMODE_SWCTRL,
1919 },
1920 },
1921 };
1923 /*
1924 * 'mailbox' class
1925 * mailbox module allowing communication between the on-chip processors
1926 * useusing a queued mailbox-interrupt mechanism.
1927 */
1929 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
1930 .rev_offs = 0x0000,
1931 .sysc_offs = 0x0010,
1932 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1933 SYSC_HAS_SOFTRESET),
1934 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1935 .sysc_fields = &omap_hwmod_sysc_type2,
1936 };
1938 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
1939 .name = "mailbox",
1940 .sysc = &omap54xx_mailbox_sysc,
1941 };
1943 /* mailbox */
1944 static struct omap_hwmod_irq_info omap54xx_mailbox_irqs[] = {
1945 { .irq = 26 + OMAP54XX_IRQ_GIC_START },
1946 { .irq = -1 }
1947 };
1949 static struct omap_hwmod omap54xx_mailbox_hwmod = {
1950 .name = "mailbox",
1951 .class = &omap54xx_mailbox_hwmod_class,
1952 .clkdm_name = "l4cfg_clkdm",
1953 .mpu_irqs = omap54xx_mailbox_irqs,
1954 .main_clk = "l4_root_clk_div",
1955 .prcm = {
1956 .omap4 = {
1957 .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1958 .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1959 },
1960 },
1961 };
1963 /*
1964 * 'mcasp' class
1965 * multi-channel audio serial port controller
1966 */
1968 static struct omap_hwmod_class_sysconfig omap54xx_mcasp_sysc = {
1969 .sysc_offs = 0x0004,
1970 .sysc_flags = SYSC_HAS_SIDLEMODE,
1971 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1972 .sysc_fields = &omap_hwmod_sysc_type3,
1973 };
1975 static struct omap_hwmod_class omap54xx_mcasp_hwmod_class = {
1976 .name = "mcasp",
1977 .sysc = &omap54xx_mcasp_sysc,
1978 };
1980 /* mcasp */
1981 static struct omap_hwmod_irq_info omap54xx_mcasp_irqs[] = {
1982 { .name = "arevt", .irq = 108 + OMAP54XX_IRQ_GIC_START },
1983 { .name = "axevt", .irq = 109 + OMAP54XX_IRQ_GIC_START },
1984 { .irq = -1 }
1985 };
1987 static struct omap_hwmod_dma_info omap54xx_mcasp_sdma_reqs[] = {
1988 { .name = "axevt", .dma_req = 7 + OMAP54XX_DMA_REQ_START },
1989 { .name = "arevt", .dma_req = 10 + OMAP54XX_DMA_REQ_START },
1990 { .dma_req = -1 }
1991 };
1993 static struct omap_hwmod omap54xx_mcasp_hwmod = {
1994 .name = "mcasp",
1995 .class = &omap54xx_mcasp_hwmod_class,
1996 .clkdm_name = "abe_clkdm",
1997 .flags = HWMOD_SWSUP_SIDLE,
1998 .mpu_irqs = omap54xx_mcasp_irqs,
1999 .sdma_reqs = omap54xx_mcasp_sdma_reqs,
2000 .main_clk = "mcasp_gfclk",
2001 .prcm = {
2002 .omap4 = {
2003 .clkctrl_offs = OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET,
2004 .context_offs = OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET,
2005 .modulemode = MODULEMODE_SWCTRL,
2006 },
2007 },
2008 };
2010 /*
2011 * 'mcbsp' class
2012 * multi channel buffered serial port controller
2013 */
2015 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
2016 .sysc_offs = 0x008c,
2017 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2018 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2019 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2020 .sysc_fields = &omap_hwmod_sysc_type1,
2021 };
2023 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
2024 .name = "mcbsp",
2025 .sysc = &omap54xx_mcbsp_sysc,
2026 .rev = MCBSP_CONFIG_TYPE4,
2027 };
2029 /* mcbsp1 */
2030 static struct omap_hwmod_irq_info omap54xx_mcbsp1_irqs[] = {
2031 { .name = "common", .irq = 17 + OMAP54XX_IRQ_GIC_START },
2032 { .irq = -1 }
2033 };
2035 static struct omap_hwmod_dma_info omap54xx_mcbsp1_sdma_reqs[] = {
2036 { .name = "tx", .dma_req = 32 + OMAP54XX_DMA_REQ_START },
2037 { .name = "rx", .dma_req = 33 + OMAP54XX_DMA_REQ_START },
2038 { .dma_req = -1 }
2039 };
2041 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
2042 { .role = "pad_fck", .clk = "pad_clks_ck" },
2043 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
2044 };
2046 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
2047 .name = "mcbsp1",
2048 .class = &omap54xx_mcbsp_hwmod_class,
2049 .clkdm_name = "abe_clkdm",
2050 .mpu_irqs = omap54xx_mcbsp1_irqs,
2051 .sdma_reqs = omap54xx_mcbsp1_sdma_reqs,
2052 .main_clk = "mcbsp1_gfclk",
2053 .prcm = {
2054 .omap4 = {
2055 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
2056 .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
2057 .modulemode = MODULEMODE_SWCTRL,
2058 },
2059 },
2060 .opt_clks = mcbsp1_opt_clks,
2061 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
2062 };
2064 /* mcbsp2 */
2065 static struct omap_hwmod_irq_info omap54xx_mcbsp2_irqs[] = {
2066 { .name = "common", .irq = 22 + OMAP54XX_IRQ_GIC_START },
2067 { .irq = -1 }
2068 };
2070 static struct omap_hwmod_dma_info omap54xx_mcbsp2_sdma_reqs[] = {
2071 { .name = "tx", .dma_req = 16 + OMAP54XX_DMA_REQ_START },
2072 { .name = "rx", .dma_req = 17 + OMAP54XX_DMA_REQ_START },
2073 { .dma_req = -1 }
2074 };
2076 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2077 { .role = "pad_fck", .clk = "pad_clks_ck" },
2078 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2079 };
2081 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
2082 .name = "mcbsp2",
2083 .class = &omap54xx_mcbsp_hwmod_class,
2084 .clkdm_name = "abe_clkdm",
2085 .mpu_irqs = omap54xx_mcbsp2_irqs,
2086 .sdma_reqs = omap54xx_mcbsp2_sdma_reqs,
2087 .main_clk = "mcbsp2_gfclk",
2088 .prcm = {
2089 .omap4 = {
2090 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
2091 .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2092 .modulemode = MODULEMODE_SWCTRL,
2093 },
2094 },
2095 .opt_clks = mcbsp2_opt_clks,
2096 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
2097 };
2099 /* mcbsp3 */
2100 static struct omap_hwmod_irq_info omap54xx_mcbsp3_irqs[] = {
2101 { .name = "common", .irq = 23 + OMAP54XX_IRQ_GIC_START },
2102 { .irq = -1 }
2103 };
2105 static struct omap_hwmod_dma_info omap54xx_mcbsp3_sdma_reqs[] = {
2106 { .name = "tx", .dma_req = 18 + OMAP54XX_DMA_REQ_START },
2107 { .name = "rx", .dma_req = 19 + OMAP54XX_DMA_REQ_START },
2108 { .dma_req = -1 }
2109 };
2111 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2112 { .role = "pad_fck", .clk = "pad_clks_ck" },
2113 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2114 };
2116 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
2117 .name = "mcbsp3",
2118 .class = &omap54xx_mcbsp_hwmod_class,
2119 .clkdm_name = "abe_clkdm",
2120 .mpu_irqs = omap54xx_mcbsp3_irqs,
2121 .sdma_reqs = omap54xx_mcbsp3_sdma_reqs,
2122 .main_clk = "mcbsp3_gfclk",
2123 .prcm = {
2124 .omap4 = {
2125 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
2126 .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2127 .modulemode = MODULEMODE_SWCTRL,
2128 },
2129 },
2130 .opt_clks = mcbsp3_opt_clks,
2131 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
2132 };
2134 /*
2135 * 'mcpdm' class
2136 * multi channel pdm controller (proprietary interface with phoenix power
2137 * ic)
2138 */
2140 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
2141 .rev_offs = 0x0000,
2142 .sysc_offs = 0x0010,
2143 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2144 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2145 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2146 SIDLE_SMART_WKUP),
2147 .sysc_fields = &omap_hwmod_sysc_type2,
2148 };
2150 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
2151 .name = "mcpdm",
2152 .sysc = &omap54xx_mcpdm_sysc,
2153 };
2155 /* mcpdm */
2156 static struct omap_hwmod_irq_info omap54xx_mcpdm_irqs[] = {
2157 { .irq = 112 + OMAP54XX_IRQ_GIC_START },
2158 { .irq = -1 }
2159 };
2161 static struct omap_hwmod_dma_info omap54xx_mcpdm_sdma_reqs[] = {
2162 { .name = "up_link", .dma_req = 64 + OMAP54XX_DMA_REQ_START },
2163 { .name = "dn_link", .dma_req = 65 + OMAP54XX_DMA_REQ_START },
2164 { .dma_req = -1 }
2165 };
2167 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
2168 .name = "mcpdm",
2169 .class = &omap54xx_mcpdm_hwmod_class,
2170 .clkdm_name = "abe_clkdm",
2171 /*
2172 * It's suspected that the McPDM requires an off-chip main
2173 * functional clock, controlled via I2C. This IP block is
2174 * currently reset very early during boot, before I2C is
2175 * available, so it doesn't seem that we have any choice in
2176 * the kernel other than to avoid resetting it. XXX This is
2177 * really a hardware issue workaround: every IP block should
2178 * be able to source its main functional clock from either
2179 * on-chip or off-chip sources. McPDM seems to be the only
2180 * current exception.
2181 */
2183 .flags = HWMOD_EXT_OPT_MAIN_CLK,
2184 .mpu_irqs = omap54xx_mcpdm_irqs,
2185 .sdma_reqs = omap54xx_mcpdm_sdma_reqs,
2186 .main_clk = "pad_clks_ck",
2187 .prcm = {
2188 .omap4 = {
2189 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
2190 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
2191 .modulemode = MODULEMODE_SWCTRL,
2192 },
2193 },
2194 };
2196 /*
2197 * 'mcspi' class
2198 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2199 * bus
2200 */
2202 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
2203 .rev_offs = 0x0000,
2204 .sysc_offs = 0x0010,
2205 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2206 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2207 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2208 SIDLE_SMART_WKUP),
2209 .sysc_fields = &omap_hwmod_sysc_type2,
2210 };
2212 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
2213 .name = "mcspi",
2214 .sysc = &omap54xx_mcspi_sysc,
2215 .rev = OMAP4_MCSPI_REV,
2216 };
2218 /* mcspi1 */
2219 static struct omap_hwmod_irq_info omap54xx_mcspi1_irqs[] = {
2220 { .irq = 65 + OMAP54XX_IRQ_GIC_START },
2221 { .irq = -1 }
2222 };
2224 static struct omap_hwmod_dma_info omap54xx_mcspi1_sdma_reqs[] = {
2225 { .name = "tx0", .dma_req = 34 + OMAP54XX_DMA_REQ_START },
2226 { .name = "rx0", .dma_req = 35 + OMAP54XX_DMA_REQ_START },
2227 { .name = "tx1", .dma_req = 36 + OMAP54XX_DMA_REQ_START },
2228 { .name = "rx1", .dma_req = 37 + OMAP54XX_DMA_REQ_START },
2229 { .name = "tx2", .dma_req = 38 + OMAP54XX_DMA_REQ_START },
2230 { .name = "rx2", .dma_req = 39 + OMAP54XX_DMA_REQ_START },
2231 { .name = "tx3", .dma_req = 40 + OMAP54XX_DMA_REQ_START },
2232 { .name = "rx3", .dma_req = 41 + OMAP54XX_DMA_REQ_START },
2233 { .dma_req = -1 }
2234 };
2236 /* mcspi1 dev_attr */
2237 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2238 .num_chipselect = 4,
2239 };
2241 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
2242 .name = "mcspi1",
2243 .class = &omap54xx_mcspi_hwmod_class,
2244 .clkdm_name = "l4per_clkdm",
2245 .mpu_irqs = omap54xx_mcspi1_irqs,
2246 .sdma_reqs = omap54xx_mcspi1_sdma_reqs,
2247 .main_clk = "func_48m_fclk",
2248 .prcm = {
2249 .omap4 = {
2250 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2251 .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2252 .modulemode = MODULEMODE_SWCTRL,
2253 },
2254 },
2255 .dev_attr = &mcspi1_dev_attr,
2256 };
2258 /* mcspi2 */
2259 static struct omap_hwmod_irq_info omap54xx_mcspi2_irqs[] = {
2260 { .irq = 66 + OMAP54XX_IRQ_GIC_START },
2261 { .irq = -1 }
2262 };
2264 static struct omap_hwmod_dma_info omap54xx_mcspi2_sdma_reqs[] = {
2265 { .name = "tx0", .dma_req = 42 + OMAP54XX_DMA_REQ_START },
2266 { .name = "rx0", .dma_req = 43 + OMAP54XX_DMA_REQ_START },
2267 { .name = "tx1", .dma_req = 44 + OMAP54XX_DMA_REQ_START },
2268 { .name = "rx1", .dma_req = 45 + OMAP54XX_DMA_REQ_START },
2269 { .dma_req = -1 }
2270 };
2272 /* mcspi2 dev_attr */
2273 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2274 .num_chipselect = 2,
2275 };
2277 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
2278 .name = "mcspi2",
2279 .class = &omap54xx_mcspi_hwmod_class,
2280 .clkdm_name = "l4per_clkdm",
2281 .mpu_irqs = omap54xx_mcspi2_irqs,
2282 .sdma_reqs = omap54xx_mcspi2_sdma_reqs,
2283 .main_clk = "func_48m_fclk",
2284 .prcm = {
2285 .omap4 = {
2286 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2287 .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2288 .modulemode = MODULEMODE_SWCTRL,
2289 },
2290 },
2291 .dev_attr = &mcspi2_dev_attr,
2292 };
2294 /* mcspi3 */
2295 static struct omap_hwmod_irq_info omap54xx_mcspi3_irqs[] = {
2296 { .irq = 91 + OMAP54XX_IRQ_GIC_START },
2297 { .irq = -1 }
2298 };
2300 static struct omap_hwmod_dma_info omap54xx_mcspi3_sdma_reqs[] = {
2301 { .name = "tx0", .dma_req = 14 + OMAP54XX_DMA_REQ_START },
2302 { .name = "rx0", .dma_req = 15 + OMAP54XX_DMA_REQ_START },
2303 { .dma_req = -1 }
2304 };
2306 /* mcspi3 dev_attr */
2307 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2308 .num_chipselect = 2,
2309 };
2311 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
2312 .name = "mcspi3",
2313 .class = &omap54xx_mcspi_hwmod_class,
2314 .clkdm_name = "l4per_clkdm",
2315 .mpu_irqs = omap54xx_mcspi3_irqs,
2316 .sdma_reqs = omap54xx_mcspi3_sdma_reqs,
2317 .main_clk = "func_48m_fclk",
2318 .prcm = {
2319 .omap4 = {
2320 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2321 .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2322 .modulemode = MODULEMODE_SWCTRL,
2323 },
2324 },
2325 .dev_attr = &mcspi3_dev_attr,
2326 };
2328 /* mcspi4 */
2329 static struct omap_hwmod_irq_info omap54xx_mcspi4_irqs[] = {
2330 { .irq = 48 + OMAP54XX_IRQ_GIC_START },
2331 { .irq = -1 }
2332 };
2334 static struct omap_hwmod_dma_info omap54xx_mcspi4_sdma_reqs[] = {
2335 { .name = "tx0", .dma_req = 69 + OMAP54XX_DMA_REQ_START },
2336 { .name = "rx0", .dma_req = 70 + OMAP54XX_DMA_REQ_START },
2337 { .dma_req = -1 }
2338 };
2340 /* mcspi4 dev_attr */
2341 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2342 .num_chipselect = 1,
2343 };
2345 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
2346 .name = "mcspi4",
2347 .class = &omap54xx_mcspi_hwmod_class,
2348 .clkdm_name = "l4per_clkdm",
2349 .mpu_irqs = omap54xx_mcspi4_irqs,
2350 .sdma_reqs = omap54xx_mcspi4_sdma_reqs,
2351 .main_clk = "func_48m_fclk",
2352 .prcm = {
2353 .omap4 = {
2354 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2355 .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2356 .modulemode = MODULEMODE_SWCTRL,
2357 },
2358 },
2359 .dev_attr = &mcspi4_dev_attr,
2360 };
2362 /*
2363 * 'mmc' class
2364 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2365 */
2367 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
2368 .rev_offs = 0x0000,
2369 .sysc_offs = 0x0010,
2370 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2371 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2372 SYSC_HAS_SOFTRESET),
2373 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2374 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2375 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2376 .sysc_fields = &omap_hwmod_sysc_type2,
2377 };
2379 static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
2380 .name = "mmc",
2381 .sysc = &omap54xx_mmc_sysc,
2382 };
2384 /* mmc1 */
2385 static struct omap_hwmod_irq_info omap54xx_mmc1_irqs[] = {
2386 { .irq = 83 + OMAP54XX_IRQ_GIC_START },
2387 { .irq = -1 }
2388 };
2390 static struct omap_hwmod_dma_info omap54xx_mmc1_sdma_reqs[] = {
2391 { .name = "tx", .dma_req = 60 + OMAP54XX_DMA_REQ_START },
2392 { .name = "rx", .dma_req = 61 + OMAP54XX_DMA_REQ_START },
2393 { .dma_req = -1 }
2394 };
2396 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
2397 { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
2398 };
2400 /* mmc1 dev_attr */
2401 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2402 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2403 };
2405 static struct omap_hwmod omap54xx_mmc1_hwmod = {
2406 .name = "mmc1",
2407 .class = &omap54xx_mmc_hwmod_class,
2408 .clkdm_name = "l3init_clkdm",
2409 .mpu_irqs = omap54xx_mmc1_irqs,
2410 .sdma_reqs = omap54xx_mmc1_sdma_reqs,
2411 .main_clk = "mmc1_fclk",
2412 .prcm = {
2413 .omap4 = {
2414 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2415 .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2416 .modulemode = MODULEMODE_SWCTRL,
2417 },
2418 },
2419 .opt_clks = mmc1_opt_clks,
2420 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
2421 .dev_attr = &mmc1_dev_attr,
2422 };
2424 /* mmc2 */
2425 static struct omap_hwmod_irq_info omap54xx_mmc2_irqs[] = {
2426 { .irq = 86 + OMAP54XX_IRQ_GIC_START },
2427 { .irq = -1 }
2428 };
2430 static struct omap_hwmod_dma_info omap54xx_mmc2_sdma_reqs[] = {
2431 { .name = "tx", .dma_req = 46 + OMAP54XX_DMA_REQ_START },
2432 { .name = "rx", .dma_req = 47 + OMAP54XX_DMA_REQ_START },
2433 { .dma_req = -1 }
2434 };
2436 static struct omap_hwmod omap54xx_mmc2_hwmod = {
2437 .name = "mmc2",
2438 .class = &omap54xx_mmc_hwmod_class,
2439 .clkdm_name = "l3init_clkdm",
2440 .mpu_irqs = omap54xx_mmc2_irqs,
2441 .sdma_reqs = omap54xx_mmc2_sdma_reqs,
2442 .main_clk = "mmc2_fclk",
2443 .prcm = {
2444 .omap4 = {
2445 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2446 .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2447 .modulemode = MODULEMODE_SWCTRL,
2448 },
2449 },
2450 };
2452 /* mmc3 */
2453 static struct omap_hwmod_irq_info omap54xx_mmc3_irqs[] = {
2454 { .irq = 94 + OMAP54XX_IRQ_GIC_START },
2455 { .irq = -1 }
2456 };
2458 static struct omap_hwmod_dma_info omap54xx_mmc3_sdma_reqs[] = {
2459 { .name = "tx", .dma_req = 76 + OMAP54XX_DMA_REQ_START },
2460 { .name = "rx", .dma_req = 77 + OMAP54XX_DMA_REQ_START },
2461 { .dma_req = -1 }
2462 };
2464 static struct omap_hwmod omap54xx_mmc3_hwmod = {
2465 .name = "mmc3",
2466 .class = &omap54xx_mmc_hwmod_class,
2467 .clkdm_name = "l4per_clkdm",
2468 .mpu_irqs = omap54xx_mmc3_irqs,
2469 .sdma_reqs = omap54xx_mmc3_sdma_reqs,
2470 .main_clk = "func_48m_fclk",
2471 .prcm = {
2472 .omap4 = {
2473 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
2474 .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
2475 .modulemode = MODULEMODE_SWCTRL,
2476 },
2477 },
2478 };
2480 /* mmc4 */
2481 static struct omap_hwmod_irq_info omap54xx_mmc4_irqs[] = {
2482 { .irq = 96 + OMAP54XX_IRQ_GIC_START },
2483 { .irq = -1 }
2484 };
2486 static struct omap_hwmod_dma_info omap54xx_mmc4_sdma_reqs[] = {
2487 { .name = "tx", .dma_req = 56 + OMAP54XX_DMA_REQ_START },
2488 { .name = "rx", .dma_req = 57 + OMAP54XX_DMA_REQ_START },
2489 { .dma_req = -1 }
2490 };
2492 static struct omap_hwmod omap54xx_mmc4_hwmod = {
2493 .name = "mmc4",
2494 .class = &omap54xx_mmc_hwmod_class,
2495 .clkdm_name = "l4per_clkdm",
2496 .mpu_irqs = omap54xx_mmc4_irqs,
2497 .sdma_reqs = omap54xx_mmc4_sdma_reqs,
2498 .main_clk = "func_48m_fclk",
2499 .prcm = {
2500 .omap4 = {
2501 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
2502 .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
2503 .modulemode = MODULEMODE_SWCTRL,
2504 },
2505 },
2506 };
2508 /* mmc5 */
2509 static struct omap_hwmod_irq_info omap54xx_mmc5_irqs[] = {
2510 { .irq = 59 + OMAP54XX_IRQ_GIC_START },
2511 { .irq = -1 }
2512 };
2514 static struct omap_hwmod_dma_info omap54xx_mmc5_sdma_reqs[] = {
2515 { .name = "tx", .dma_req = 58 + OMAP54XX_DMA_REQ_START },
2516 { .name = "rx", .dma_req = 59 + OMAP54XX_DMA_REQ_START },
2517 { .dma_req = -1 }
2518 };
2520 static struct omap_hwmod omap54xx_mmc5_hwmod = {
2521 .name = "mmc5",
2522 .class = &omap54xx_mmc_hwmod_class,
2523 .clkdm_name = "l4per_clkdm",
2524 .mpu_irqs = omap54xx_mmc5_irqs,
2525 .sdma_reqs = omap54xx_mmc5_sdma_reqs,
2526 .main_clk = "func_96m_fclk",
2527 .prcm = {
2528 .omap4 = {
2529 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
2530 .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
2531 .modulemode = MODULEMODE_SWCTRL,
2532 },
2533 },
2534 };
2536 /*
2537 * 'mpu' class
2538 * mpu sub-system
2539 */
2541 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
2542 .name = "mpu",
2543 };
2545 /* mpu */
2546 static struct omap_hwmod_irq_info omap54xx_mpu_irqs[] = {
2547 { .name = "mpu_cluster", .irq = 132 + OMAP54XX_IRQ_GIC_START },
2548 { .name = "wd_timer_mpu_c0", .irq = 139 + OMAP54XX_IRQ_GIC_START },
2549 { .name = "wd_timer_mpu_c1", .irq = 140 + OMAP54XX_IRQ_GIC_START },
2550 { .irq = -1 }
2551 };
2553 static struct omap_hwmod omap54xx_mpu_hwmod = {
2554 .name = "mpu",
2555 .class = &omap54xx_mpu_hwmod_class,
2556 .clkdm_name = "mpu_clkdm",
2557 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2558 .mpu_irqs = omap54xx_mpu_irqs,
2559 .main_clk = "dpll_mpu_m2_ck",
2560 .prcm = {
2561 .omap4 = {
2562 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
2563 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
2564 },
2565 },
2566 };
2568 /*
2569 * 'ocmc_ram' class
2570 * top-level core on-chip ram
2571 */
2573 static struct omap_hwmod_class omap54xx_ocmc_ram_hwmod_class = {
2574 .name = "ocmc_ram",
2575 };
2577 /* ocmc_ram */
2578 static struct omap_hwmod omap54xx_ocmc_ram_hwmod = {
2579 .name = "ocmc_ram",
2580 .class = &omap54xx_ocmc_ram_hwmod_class,
2581 .clkdm_name = "l3main2_clkdm",
2582 .main_clk = "l3_iclk_div",
2583 .prcm = {
2584 .omap4 = {
2585 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET,
2586 .context_offs = OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET,
2587 },
2588 },
2589 };
2591 /*
2592 * 'ocp2scp' class
2593 * bridge to transform ocp interface protocol to scp (serial control port)
2594 * protocol
2595 */
2597 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
2598 .rev_offs = 0x0000,
2599 .sysc_offs = 0x0010,
2600 .syss_offs = 0x0014,
2601 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2602 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2603 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2604 .sysc_fields = &omap_hwmod_sysc_type1,
2605 };
2607 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
2608 .name = "ocp2scp",
2609 .sysc = &omap54xx_ocp2scp_sysc,
2610 };
2612 /* ocp2scp1 */
2613 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
2614 .name = "ocp2scp1",
2615 .class = &omap54xx_ocp2scp_hwmod_class,
2616 .clkdm_name = "l3init_clkdm",
2617 .main_clk = "l4_root_clk_div",
2618 .prcm = {
2619 .omap4 = {
2620 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
2621 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
2622 .modulemode = MODULEMODE_HWCTRL,
2623 },
2624 },
2625 };
2627 /*
2628 * 'sata' class
2629 * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
2630 */
2632 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
2633 .sysc_offs = 0x0000,
2634 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2635 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2636 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2637 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2638 .sysc_fields = &omap_hwmod_sysc_type2,
2639 };
2641 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
2642 .name = "sata",
2643 .sysc = &omap54xx_sata_sysc,
2644 };
2646 /* sata */
2647 static struct omap_hwmod_irq_info omap54xx_sata_irqs[] = {
2648 { .irq = 54 + OMAP54XX_IRQ_GIC_START },
2649 { .irq = -1 }
2650 };
2652 static struct omap_hwmod_opt_clk sata_opt_clks[] = {
2653 { .role = "ref_clk", .clk = "sata_ref_clk" },
2654 };
2656 static struct omap_hwmod omap54xx_sata_hwmod = {
2657 .name = "sata",
2658 .class = &omap54xx_sata_hwmod_class,
2659 .clkdm_name = "l3init_clkdm",
2660 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2661 .mpu_irqs = omap54xx_sata_irqs,
2662 .main_clk = "func_48m_fclk",
2663 .prcm = {
2664 .omap4 = {
2665 .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2666 .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2667 .modulemode = MODULEMODE_SWCTRL,
2668 },
2669 },
2670 .opt_clks = sata_opt_clks,
2671 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
2672 };
2674 /*
2675 * 'scrm' class
2676 * system clock and reset manager
2677 */
2679 static struct omap_hwmod_class omap54xx_scrm_hwmod_class = {
2680 .name = "scrm",
2681 };
2683 /* scrm */
2684 static struct omap_hwmod omap54xx_scrm_hwmod = {
2685 .name = "scrm",
2686 .class = &omap54xx_scrm_hwmod_class,
2687 .clkdm_name = "wkupaon_clkdm",
2688 .prcm = {
2689 .omap4 = {
2690 .clkctrl_offs = OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET,
2691 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2692 },
2693 },
2694 };
2696 /*
2697 * 'slimbus' class
2698 * bidirectional, multi-drop, multi-channel two-line serial interface between
2699 * the device and external components
2700 */
2702 static struct omap_hwmod_class_sysconfig omap54xx_slimbus_sysc = {
2703 .rev_offs = 0x0000,
2704 .sysc_offs = 0x0010,
2705 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2706 SYSC_HAS_SOFTRESET),
2707 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2708 SIDLE_SMART_WKUP),
2709 .sysc_fields = &omap_hwmod_sysc_type2,
2710 };
2712 static struct omap_hwmod_class omap54xx_slimbus_hwmod_class = {
2713 .name = "slimbus",
2714 .sysc = &omap54xx_slimbus_sysc,
2715 };
2717 /* slimbus1 */
2718 static struct omap_hwmod_irq_info omap54xx_slimbus1_irqs[] = {
2719 { .irq = 97 + OMAP54XX_IRQ_GIC_START },
2720 { .irq = -1 }
2721 };
2723 static struct omap_hwmod_dma_info omap54xx_slimbus1_sdma_reqs[] = {
2724 { .name = "tx0", .dma_req = 84 + OMAP54XX_DMA_REQ_START },
2725 { .name = "tx1", .dma_req = 85 + OMAP54XX_DMA_REQ_START },
2726 { .name = "tx2", .dma_req = 86 + OMAP54XX_DMA_REQ_START },
2727 { .name = "tx3", .dma_req = 87 + OMAP54XX_DMA_REQ_START },
2728 { .name = "rx0", .dma_req = 88 + OMAP54XX_DMA_REQ_START },
2729 { .name = "rx1", .dma_req = 89 + OMAP54XX_DMA_REQ_START },
2730 { .name = "rx2", .dma_req = 90 + OMAP54XX_DMA_REQ_START },
2731 { .name = "rx3", .dma_req = 91 + OMAP54XX_DMA_REQ_START },
2732 { .dma_req = -1 }
2733 };
2735 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2736 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2737 };
2739 static struct omap_hwmod omap54xx_slimbus1_hwmod = {
2740 .name = "slimbus1",
2741 .class = &omap54xx_slimbus_hwmod_class,
2742 .clkdm_name = "abe_clkdm",
2743 .mpu_irqs = omap54xx_slimbus1_irqs,
2744 .sdma_reqs = omap54xx_slimbus1_sdma_reqs,
2745 .main_clk = "abe_iclk",
2746 .prcm = {
2747 .omap4 = {
2748 .clkctrl_offs = OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET,
2749 .context_offs = OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET,
2750 .modulemode = MODULEMODE_SWCTRL,
2751 },
2752 },
2753 .opt_clks = slimbus1_opt_clks,
2754 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2755 };
2757 /*
2758 * 'smartreflex' class
2759 * smartreflex module (monitor silicon performance and outputs a measure of
2760 * performance error)
2761 */
2763 /* The IP is not compliant to type1 / type2 scheme */
2764 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2765 .sidle_shift = 24,
2766 .enwkup_shift = 26,
2767 };
2769 static struct omap_hwmod_class_sysconfig omap54xx_smartreflex_sysc = {
2770 .sysc_offs = 0x0038,
2771 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2772 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2773 SIDLE_SMART_WKUP),
2774 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2775 };
2777 static struct omap_hwmod_class omap54xx_smartreflex_hwmod_class = {
2778 .name = "smartreflex",
2779 .sysc = &omap54xx_smartreflex_sysc,
2780 .rev = 2,
2781 };
2783 /* smartreflex_core */
2784 static struct omap_hwmod_irq_info omap54xx_smartreflex_core_irqs[] = {
2785 { .irq = 19 + OMAP54XX_IRQ_GIC_START },
2786 { .irq = -1 }
2787 };
2789 /* smartreflex_core dev_attr */
2790 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2791 .sensor_voltdm_name = "core",
2792 };
2794 static struct omap_hwmod omap54xx_smartreflex_core_hwmod = {
2795 .name = "smartreflex_core",
2796 .class = &omap54xx_smartreflex_hwmod_class,
2797 .clkdm_name = "coreaon_clkdm",
2798 .mpu_irqs = omap54xx_smartreflex_core_irqs,
2799 .main_clk = "wkupaon_iclk_mux",
2800 .prcm = {
2801 .omap4 = {
2802 .clkctrl_offs = OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2803 .context_offs = OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2804 .modulemode = MODULEMODE_SWCTRL,
2805 },
2806 },
2807 .dev_attr = &smartreflex_core_dev_attr,
2808 };
2810 /* smartreflex_mm */
2811 static struct omap_hwmod_irq_info omap54xx_smartreflex_mm_irqs[] = {
2812 { .irq = 102 + OMAP54XX_IRQ_GIC_START },
2813 { .irq = -1 }
2814 };
2816 /* smartreflex_mm dev_attr */
2817 static struct omap_smartreflex_dev_attr smartreflex_mm_dev_attr = {
2818 .sensor_voltdm_name = "mm",
2819 };
2821 static struct omap_hwmod omap54xx_smartreflex_mm_hwmod = {
2822 .name = "smartreflex_mm",
2823 .class = &omap54xx_smartreflex_hwmod_class,
2824 .clkdm_name = "coreaon_clkdm",
2825 .mpu_irqs = omap54xx_smartreflex_mm_irqs,
2826 .main_clk = "wkupaon_iclk_mux",
2827 .prcm = {
2828 .omap4 = {
2829 .clkctrl_offs = OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET,
2830 .context_offs = OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET,
2831 .modulemode = MODULEMODE_SWCTRL,
2832 },
2833 },
2834 .dev_attr = &smartreflex_mm_dev_attr,
2835 };
2837 /* smartreflex_mpu */
2838 static struct omap_hwmod_irq_info omap54xx_smartreflex_mpu_irqs[] = {
2839 { .irq = 18 + OMAP54XX_IRQ_GIC_START },
2840 { .irq = -1 }
2841 };
2843 /* smartreflex_mpu dev_attr */
2844 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2845 .sensor_voltdm_name = "mpu",
2846 };
2848 static struct omap_hwmod omap54xx_smartreflex_mpu_hwmod = {
2849 .name = "smartreflex_mpu",
2850 .class = &omap54xx_smartreflex_hwmod_class,
2851 .clkdm_name = "coreaon_clkdm",
2852 .mpu_irqs = omap54xx_smartreflex_mpu_irqs,
2853 .main_clk = "wkupaon_iclk_mux",
2854 .prcm = {
2855 .omap4 = {
2856 .clkctrl_offs = OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2857 .context_offs = OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2858 .modulemode = MODULEMODE_SWCTRL,
2859 },
2860 },
2861 .dev_attr = &smartreflex_mpu_dev_attr,
2862 };
2864 /*
2865 * 'spinlock' class
2866 * spinlock provides hardware assistance for synchronizing the processes
2867 * running on multiple processors
2868 */
2870 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
2871 .rev_offs = 0x0000,
2872 .sysc_offs = 0x0010,
2873 .syss_offs = 0x0014,
2874 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2875 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2876 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2877 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2878 SIDLE_SMART_WKUP),
2879 .sysc_fields = &omap_hwmod_sysc_type1,
2880 };
2882 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
2883 .name = "spinlock",
2884 .sysc = &omap54xx_spinlock_sysc,
2885 };
2887 /* spinlock */
2888 static struct omap_hwmod omap54xx_spinlock_hwmod = {
2889 .name = "spinlock",
2890 .class = &omap54xx_spinlock_hwmod_class,
2891 .clkdm_name = "l4cfg_clkdm",
2892 .main_clk = "l4_root_clk_div",
2893 .prcm = {
2894 .omap4 = {
2895 .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2896 .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2897 },
2898 },
2899 };
2901 /*
2902 * 'timer' class
2903 * general purpose timer module with accurate 1ms tick
2904 * This class contains several variants: ['timer_1ms', 'timer']
2905 */
2907 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
2908 .rev_offs = 0x0000,
2909 .sysc_offs = 0x0010,
2910 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2911 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2912 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2913 SIDLE_SMART_WKUP),
2914 .sysc_fields = &omap_hwmod_sysc_type2,
2915 .clockact = CLOCKACT_TEST_ICLK,
2916 };
2918 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
2919 .name = "timer",
2920 .sysc = &omap54xx_timer_1ms_sysc,
2921 };
2923 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
2924 .rev_offs = 0x0000,
2925 .sysc_offs = 0x0010,
2926 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2927 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2928 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2929 SIDLE_SMART_WKUP),
2930 .sysc_fields = &omap_hwmod_sysc_type2,
2931 };
2933 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
2934 .name = "timer",
2935 .sysc = &omap54xx_timer_sysc,
2936 };
2938 /* timer1 */
2939 static struct omap_hwmod_irq_info omap54xx_timer1_irqs[] = {
2940 { .irq = 37 + OMAP54XX_IRQ_GIC_START },
2941 { .irq = -1 }
2942 };
2944 static struct omap_hwmod omap54xx_timer1_hwmod = {
2945 .name = "timer1",
2946 .class = &omap54xx_timer_1ms_hwmod_class,
2947 .clkdm_name = "wkupaon_clkdm",
2948 .mpu_irqs = omap54xx_timer1_irqs,
2949 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2950 .main_clk = "timer1_gfclk_mux",
2951 .prcm = {
2952 .omap4 = {
2953 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2954 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2955 .modulemode = MODULEMODE_SWCTRL,
2956 },
2957 },
2958 };
2960 /* timer2 */
2961 static struct omap_hwmod_irq_info omap54xx_timer2_irqs[] = {
2962 { .irq = 38 + OMAP54XX_IRQ_GIC_START },
2963 { .irq = -1 }
2964 };
2966 static struct omap_hwmod omap54xx_timer2_hwmod = {
2967 .name = "timer2",
2968 .class = &omap54xx_timer_1ms_hwmod_class,
2969 .clkdm_name = "l4per_clkdm",
2970 .mpu_irqs = omap54xx_timer2_irqs,
2971 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2972 .main_clk = "timer2_gfclk_mux",
2973 .prcm = {
2974 .omap4 = {
2975 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2976 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2977 .modulemode = MODULEMODE_SWCTRL,
2978 },
2979 },
2980 };
2982 /* timer3 */
2983 static struct omap_hwmod_irq_info omap54xx_timer3_irqs[] = {
2984 { .irq = 39 + OMAP54XX_IRQ_GIC_START },
2985 { .irq = -1 }
2986 };
2988 static struct omap_hwmod omap54xx_timer3_hwmod = {
2989 .name = "timer3",
2990 .class = &omap54xx_timer_hwmod_class,
2991 .clkdm_name = "l4per_clkdm",
2992 .mpu_irqs = omap54xx_timer3_irqs,
2993 .main_clk = "timer3_gfclk_mux",
2994 .prcm = {
2995 .omap4 = {
2996 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2997 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2998 .modulemode = MODULEMODE_SWCTRL,
2999 },
3000 },
3001 };
3003 /* timer4 */
3004 static struct omap_hwmod_irq_info omap54xx_timer4_irqs[] = {
3005 { .irq = 40 + OMAP54XX_IRQ_GIC_START },
3006 { .irq = -1 }
3007 };
3009 static struct omap_hwmod omap54xx_timer4_hwmod = {
3010 .name = "timer4",
3011 .class = &omap54xx_timer_hwmod_class,
3012 .clkdm_name = "l4per_clkdm",
3013 .mpu_irqs = omap54xx_timer4_irqs,
3014 .main_clk = "timer4_gfclk_mux",
3015 .prcm = {
3016 .omap4 = {
3017 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
3018 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
3019 .modulemode = MODULEMODE_SWCTRL,
3020 },
3021 },
3022 };
3024 /* timer5 */
3025 static struct omap_hwmod_irq_info omap54xx_timer5_irqs[] = {
3026 { .irq = 41 + OMAP54XX_IRQ_GIC_START },
3027 { .irq = -1 }
3028 };
3030 static struct omap_hwmod omap54xx_timer5_hwmod = {
3031 .name = "timer5",
3032 .class = &omap54xx_timer_hwmod_class,
3033 .clkdm_name = "abe_clkdm",
3034 .mpu_irqs = omap54xx_timer5_irqs,
3035 .main_clk = "timer5_gfclk_mux",
3036 .prcm = {
3037 .omap4 = {
3038 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
3039 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
3040 .modulemode = MODULEMODE_SWCTRL,
3041 },
3042 },
3043 };
3045 /* timer6 */
3046 static struct omap_hwmod_irq_info omap54xx_timer6_irqs[] = {
3047 { .irq = 42 + OMAP54XX_IRQ_GIC_START },
3048 { .irq = -1 }
3049 };
3051 static struct omap_hwmod omap54xx_timer6_hwmod = {
3052 .name = "timer6",
3053 .class = &omap54xx_timer_hwmod_class,
3054 .clkdm_name = "abe_clkdm",
3055 .mpu_irqs = omap54xx_timer6_irqs,
3056 .main_clk = "timer6_gfclk_mux",
3057 .prcm = {
3058 .omap4 = {
3059 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
3060 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
3061 .modulemode = MODULEMODE_SWCTRL,
3062 },
3063 },
3064 };
3066 /* timer7 */
3067 static struct omap_hwmod_irq_info omap54xx_timer7_irqs[] = {
3068 { .irq = 43 + OMAP54XX_IRQ_GIC_START },
3069 { .irq = -1 }
3070 };
3072 static struct omap_hwmod omap54xx_timer7_hwmod = {
3073 .name = "timer7",
3074 .class = &omap54xx_timer_hwmod_class,
3075 .clkdm_name = "abe_clkdm",
3076 .mpu_irqs = omap54xx_timer7_irqs,
3077 .main_clk = "timer7_gfclk_mux",
3078 .prcm = {
3079 .omap4 = {
3080 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
3081 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
3082 .modulemode = MODULEMODE_SWCTRL,
3083 },
3084 },
3085 };
3087 /* timer8 */
3088 static struct omap_hwmod_irq_info omap54xx_timer8_irqs[] = {
3089 { .irq = 44 + OMAP54XX_IRQ_GIC_START },
3090 { .irq = -1 }
3091 };
3093 static struct omap_hwmod omap54xx_timer8_hwmod = {
3094 .name = "timer8",
3095 .class = &omap54xx_timer_hwmod_class,
3096 .clkdm_name = "abe_clkdm",
3097 .mpu_irqs = omap54xx_timer8_irqs,
3098 .main_clk = "timer8_gfclk_mux",
3099 .prcm = {
3100 .omap4 = {
3101 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
3102 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
3103 .modulemode = MODULEMODE_SWCTRL,
3104 },
3105 },
3106 };
3108 /* timer9 */
3109 static struct omap_hwmod_irq_info omap54xx_timer9_irqs[] = {
3110 { .irq = 45 + OMAP54XX_IRQ_GIC_START },
3111 { .irq = -1 }
3112 };
3114 static struct omap_hwmod omap54xx_timer9_hwmod = {
3115 .name = "timer9",
3116 .class = &omap54xx_timer_hwmod_class,
3117 .clkdm_name = "l4per_clkdm",
3118 .mpu_irqs = omap54xx_timer9_irqs,
3119 .main_clk = "timer9_gfclk_mux",
3120 .prcm = {
3121 .omap4 = {
3122 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
3123 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
3124 .modulemode = MODULEMODE_SWCTRL,
3125 },
3126 },
3127 };
3129 /* timer10 */
3130 static struct omap_hwmod_irq_info omap54xx_timer10_irqs[] = {
3131 { .irq = 46 + OMAP54XX_IRQ_GIC_START },
3132 { .irq = -1 }
3133 };
3135 static struct omap_hwmod omap54xx_timer10_hwmod = {
3136 .name = "timer10",
3137 .class = &omap54xx_timer_1ms_hwmod_class,
3138 .clkdm_name = "l4per_clkdm",
3139 .mpu_irqs = omap54xx_timer10_irqs,
3140 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3141 .main_clk = "timer10_gfclk_mux",
3142 .prcm = {
3143 .omap4 = {
3144 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
3145 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
3146 .modulemode = MODULEMODE_SWCTRL,
3147 },
3148 },
3149 };
3151 /* timer11 */
3152 static struct omap_hwmod_irq_info omap54xx_timer11_irqs[] = {
3153 { .irq = 47 + OMAP54XX_IRQ_GIC_START },
3154 { .irq = -1 }
3155 };
3157 static struct omap_hwmod omap54xx_timer11_hwmod = {
3158 .name = "timer11",
3159 .class = &omap54xx_timer_hwmod_class,
3160 .clkdm_name = "l4per_clkdm",
3161 .mpu_irqs = omap54xx_timer11_irqs,
3162 .main_clk = "timer11_gfclk_mux",
3163 .prcm = {
3164 .omap4 = {
3165 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
3166 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
3167 .modulemode = MODULEMODE_SWCTRL,
3168 },
3169 },
3170 };
3172 /*
3173 * 'uart' class
3174 * universal asynchronous receiver/transmitter (uart)
3175 */
3177 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
3178 .rev_offs = 0x0050,
3179 .sysc_offs = 0x0054,
3180 .syss_offs = 0x0058,
3181 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3182 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3183 SYSS_HAS_RESET_STATUS),
3184 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3185 SIDLE_SMART_WKUP),
3186 .sysc_fields = &omap_hwmod_sysc_type1,
3187 };
3189 static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
3190 .name = "uart",
3191 .sysc = &omap54xx_uart_sysc,
3192 };
3194 /* uart1 */
3195 static struct omap_hwmod_irq_info omap54xx_uart1_irqs[] = {
3196 { .irq = 72 + OMAP54XX_IRQ_GIC_START },
3197 { .irq = -1 }
3198 };
3200 static struct omap_hwmod_dma_info omap54xx_uart1_sdma_reqs[] = {
3201 { .name = "tx", .dma_req = 48 + OMAP54XX_DMA_REQ_START },
3202 { .name = "rx", .dma_req = 49 + OMAP54XX_DMA_REQ_START },
3203 { .dma_req = -1 }
3204 };
3206 static struct omap_hwmod omap54xx_uart1_hwmod = {
3207 .name = "uart1",
3208 .class = &omap54xx_uart_hwmod_class,
3209 .clkdm_name = "l4per_clkdm",
3210 .mpu_irqs = omap54xx_uart1_irqs,
3211 .sdma_reqs = omap54xx_uart1_sdma_reqs,
3212 .main_clk = "func_48m_fclk",
3213 .flags = HWMOD_SWSUP_SIDLE_ACT,
3214 .prcm = {
3215 .omap4 = {
3216 .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
3217 .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
3218 .modulemode = MODULEMODE_SWCTRL,
3219 },
3220 },
3221 };
3223 /* uart2 */
3224 static struct omap_hwmod_irq_info omap54xx_uart2_irqs[] = {
3225 { .irq = 73 + OMAP54XX_IRQ_GIC_START },
3226 { .irq = -1 }
3227 };
3229 static struct omap_hwmod_dma_info omap54xx_uart2_sdma_reqs[] = {
3230 { .name = "tx", .dma_req = 50 + OMAP54XX_DMA_REQ_START },
3231 { .name = "rx", .dma_req = 51 + OMAP54XX_DMA_REQ_START },
3232 { .dma_req = -1 }
3233 };
3235 static struct omap_hwmod omap54xx_uart2_hwmod = {
3236 .name = "uart2",
3237 .class = &omap54xx_uart_hwmod_class,
3238 .clkdm_name = "l4per_clkdm",
3239 .mpu_irqs = omap54xx_uart2_irqs,
3240 .sdma_reqs = omap54xx_uart2_sdma_reqs,
3241 .main_clk = "func_48m_fclk",
3242 .flags = HWMOD_SWSUP_SIDLE_ACT,
3243 .prcm = {
3244 .omap4 = {
3245 .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
3246 .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
3247 .modulemode = MODULEMODE_SWCTRL,
3248 },
3249 },
3250 };
3252 /* uart3 */
3253 static struct omap_hwmod_irq_info omap54xx_uart3_irqs[] = {
3254 { .irq = 74 + OMAP54XX_IRQ_GIC_START },
3255 { .irq = -1 }
3256 };
3258 static struct omap_hwmod_dma_info omap54xx_uart3_sdma_reqs[] = {
3259 { .name = "tx", .dma_req = 52 + OMAP54XX_DMA_REQ_START },
3260 { .name = "rx", .dma_req = 53 + OMAP54XX_DMA_REQ_START },
3261 { .dma_req = -1 }
3262 };
3264 static struct omap_hwmod omap54xx_uart3_hwmod = {
3265 .name = "uart3",
3266 .class = &omap54xx_uart_hwmod_class,
3267 .clkdm_name = "l4per_clkdm",
3268 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
3269 HWMOD_SWSUP_SIDLE_ACT,
3270 .mpu_irqs = omap54xx_uart3_irqs,
3271 .sdma_reqs = omap54xx_uart3_sdma_reqs,
3272 .main_clk = "func_48m_fclk",
3273 .prcm = {
3274 .omap4 = {
3275 .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
3276 .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
3277 .modulemode = MODULEMODE_SWCTRL,
3278 },
3279 },
3280 };
3282 /* uart4 */
3283 static struct omap_hwmod_irq_info omap54xx_uart4_irqs[] = {
3284 { .irq = 70 + OMAP54XX_IRQ_GIC_START },
3285 { .irq = -1 }
3286 };
3288 static struct omap_hwmod_dma_info omap54xx_uart4_sdma_reqs[] = {
3289 { .name = "tx", .dma_req = 54 + OMAP54XX_DMA_REQ_START },
3290 { .name = "rx", .dma_req = 55 + OMAP54XX_DMA_REQ_START },
3291 { .dma_req = -1 }
3292 };
3294 static struct omap_hwmod omap54xx_uart4_hwmod = {
3295 .name = "uart4",
3296 .class = &omap54xx_uart_hwmod_class,
3297 .clkdm_name = "l4per_clkdm",
3298 .mpu_irqs = omap54xx_uart4_irqs,
3299 .sdma_reqs = omap54xx_uart4_sdma_reqs,
3300 .main_clk = "func_48m_fclk",
3301 .flags = HWMOD_SWSUP_SIDLE_ACT,
3302 .prcm = {
3303 .omap4 = {
3304 .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
3305 .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
3306 .modulemode = MODULEMODE_SWCTRL,
3307 },
3308 },
3309 };
3311 /* uart5 */
3312 static struct omap_hwmod_irq_info omap54xx_uart5_irqs[] = {
3313 { .irq = 105 + OMAP54XX_IRQ_GIC_START },
3314 { .irq = -1 }
3315 };
3317 static struct omap_hwmod_dma_info omap54xx_uart5_sdma_reqs[] = {
3318 { .name = "tx", .dma_req = 62 + OMAP54XX_DMA_REQ_START },
3319 { .name = "rx", .dma_req = 63 + OMAP54XX_DMA_REQ_START },
3320 { .dma_req = -1 }
3321 };
3323 static struct omap_hwmod omap54xx_uart5_hwmod = {
3324 .name = "uart5",
3325 .class = &omap54xx_uart_hwmod_class,
3326 .clkdm_name = "l4per_clkdm",
3327 .mpu_irqs = omap54xx_uart5_irqs,
3328 .sdma_reqs = omap54xx_uart5_sdma_reqs,
3329 .main_clk = "func_48m_fclk",
3330 .flags = HWMOD_SWSUP_SIDLE_ACT,
3331 .prcm = {
3332 .omap4 = {
3333 .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
3334 .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
3335 .modulemode = MODULEMODE_SWCTRL,
3336 },
3337 },
3338 };
3340 /* uart6 */
3341 static struct omap_hwmod_irq_info omap54xx_uart6_irqs[] = {
3342 { .irq = 106 + OMAP54XX_IRQ_GIC_START },
3343 { .irq = -1 }
3344 };
3346 static struct omap_hwmod_dma_info omap54xx_uart6_sdma_reqs[] = {
3347 { .name = "tx", .dma_req = 78 + OMAP54XX_DMA_REQ_START },
3348 { .name = "rx", .dma_req = 79 + OMAP54XX_DMA_REQ_START },
3349 { .dma_req = -1 }
3350 };
3352 static struct omap_hwmod omap54xx_uart6_hwmod = {
3353 .name = "uart6",
3354 .class = &omap54xx_uart_hwmod_class,
3355 .clkdm_name = "l4per_clkdm",
3356 .mpu_irqs = omap54xx_uart6_irqs,
3357 .sdma_reqs = omap54xx_uart6_sdma_reqs,
3358 .main_clk = "func_48m_fclk",
3359 .flags = HWMOD_SWSUP_SIDLE_ACT,
3360 .prcm = {
3361 .omap4 = {
3362 .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
3363 .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
3364 .modulemode = MODULEMODE_SWCTRL,
3365 },
3366 },
3367 };
3369 /*
3370 * 'usb_host_hs' class
3371 * high-speed multi-port usb host controller
3372 */
3374 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
3375 .rev_offs = 0x0000,
3376 .sysc_offs = 0x0010,
3377 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
3378 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3379 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3380 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3381 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3382 .sysc_fields = &omap_hwmod_sysc_type2,
3383 };
3385 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
3386 .name = "usb_host_hs",
3387 .sysc = &omap54xx_usb_host_hs_sysc,
3388 };
3390 /* usb_host_hs */
3391 static struct omap_hwmod_irq_info omap54xx_usb_host_hs_irqs[] = {
3392 { .name = "ohci", .irq = 76 + OMAP54XX_IRQ_GIC_START },
3393 { .name = "ehci", .irq = 77 + OMAP54XX_IRQ_GIC_START },
3394 { .irq = -1 }
3395 };
3397 static struct omap_hwmod_opt_clk usb_host_hs_opt_clks[] = {
3398 { .role = "hsic60m_p2_clk", .clk = "usb_host_hs_hsic60m_p2_clk" },
3399 { .role = "hsic60m_p3_clk", .clk = "usb_host_hs_hsic60m_p3_clk" },
3400 { .role = "utmi_p1_clk", .clk = "usb_host_hs_utmi_p1_clk" },
3401 { .role = "utmi_p2_clk", .clk = "usb_host_hs_utmi_p2_clk" },
3402 { .role = "utmi_p3_clk", .clk = "usb_host_hs_utmi_p3_clk" },
3403 { .role = "hsic480m_p1_clk", .clk = "usb_host_hs_hsic480m_p1_clk" },
3404 { .role = "hsic60m_p1_clk", .clk = "usb_host_hs_hsic60m_p1_clk" },
3405 { .role = "hsic480m_p3_clk", .clk = "usb_host_hs_hsic480m_p3_clk" },
3406 { .role = "hsic480m_p2_clk", .clk = "usb_host_hs_hsic480m_p2_clk" },
3407 };
3409 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
3410 .name = "usb_host_hs",
3411 .class = &omap54xx_usb_host_hs_hwmod_class,
3412 .clkdm_name = "l3init_clkdm",
3413 /*
3414 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3415 * id: i660
3416 *
3417 * Description:
3418 * In the following configuration :
3419 * - USBHOST module is set to smart-idle mode
3420 * - PRCM asserts idle_req to the USBHOST module ( This typically
3421 * happens when the system is going to a low power mode : all ports
3422 * have been suspended, the master part of the USBHOST module has
3423 * entered the standby state, and SW has cut the functional clocks)
3424 * - an USBHOST interrupt occurs before the module is able to answer
3425 * idle_ack, typically a remote wakeup IRQ.
3426 * Then the USB HOST module will enter a deadlock situation where it
3427 * is no more accessible nor functional.
3428 *
3429 * Workaround:
3430 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3431 */
3433 /*
3434 * Errata: USB host EHCI may stall when entering smart-standby mode
3435 * Id: i571
3436 *
3437 * Description:
3438 * When the USBHOST module is set to smart-standby mode, and when it is
3439 * ready to enter the standby state (i.e. all ports are suspended and
3440 * all attached devices are in suspend mode), then it can wrongly assert
3441 * the Mstandby signal too early while there are still some residual OCP
3442 * transactions ongoing. If this condition occurs, the internal state
3443 * machine may go to an undefined state and the USB link may be stuck
3444 * upon the next resume.
3445 *
3446 * Workaround:
3447 * Don't use smart standby; use only force standby,
3448 * hence HWMOD_SWSUP_MSTANDBY
3449 */
3451 /*
3452 * During system boot; If the hwmod framework resets the module
3453 * the module will have smart idle settings; which can lead to deadlock
3454 * (above Errata Id:i660); so, dont reset the module during boot;
3455 * Use HWMOD_INIT_NO_RESET.
3456 */
3458 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3459 HWMOD_INIT_NO_RESET,
3460 .mpu_irqs = omap54xx_usb_host_hs_irqs,
3461 .main_clk = "l3init_60m_fclk",
3462 .prcm = {
3463 .omap4 = {
3464 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
3465 .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
3466 .modulemode = MODULEMODE_SWCTRL,
3467 },
3468 },
3469 .opt_clks = usb_host_hs_opt_clks,
3470 .opt_clks_cnt = ARRAY_SIZE(usb_host_hs_opt_clks),
3471 };
3473 /*
3474 * 'usb_otg_ss' class
3475 * 2.0 super speed (usb_otg_ss) controller
3476 */
3478 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
3479 .rev_offs = 0x0000,
3480 .sysc_offs = 0x0010,
3481 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
3482 SYSC_HAS_SIDLEMODE),
3483 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3484 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3485 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3486 .sysc_fields = &omap_hwmod_sysc_type2,
3487 };
3489 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
3490 .name = "usb_otg_ss",
3491 .sysc = &omap54xx_usb_otg_ss_sysc,
3492 };
3494 /* usb_otg_ss */
3495 static struct omap_hwmod_irq_info omap54xx_usb_otg_ss_irqs[] = {
3496 { .name = "core", .irq = 92 + OMAP54XX_IRQ_GIC_START },
3497 { .name = "wrp", .irq = 93 + OMAP54XX_IRQ_GIC_START },
3498 { .irq = -1 }
3499 };
3501 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
3502 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
3503 };
3505 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
3506 .name = "usb_otg_ss",
3507 .class = &omap54xx_usb_otg_ss_hwmod_class,
3508 .clkdm_name = "l3init_clkdm",
3509 .flags = HWMOD_SWSUP_SIDLE,
3510 .mpu_irqs = omap54xx_usb_otg_ss_irqs,
3511 .main_clk = "dpll_core_h13x2_ck",
3512 .prcm = {
3513 .omap4 = {
3514 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
3515 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
3516 .modulemode = MODULEMODE_HWCTRL,
3517 },
3518 },
3519 .opt_clks = usb_otg_ss_opt_clks,
3520 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
3521 };
3523 /*
3524 * 'usb_tll_hs' class
3525 * usb_tll_hs module is the adapter on the usb_host_hs ports
3526 */
3528 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
3529 .rev_offs = 0x0000,
3530 .sysc_offs = 0x0010,
3531 .syss_offs = 0x0014,
3532 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3533 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3534 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3535 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3536 .sysc_fields = &omap_hwmod_sysc_type1,
3537 };
3539 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
3540 .name = "usb_tll_hs",
3541 .sysc = &omap54xx_usb_tll_hs_sysc,
3542 };
3544 /* usb_tll_hs */
3545 static struct omap_hwmod_irq_info omap54xx_usb_tll_hs_irqs[] = {
3546 { .irq = 78 + OMAP54XX_IRQ_GIC_START },
3547 { .irq = -1 }
3548 };
3550 static struct omap_hwmod_opt_clk usb_tll_hs_opt_clks[] = {
3551 { .role = "usb_ch2_clk", .clk = "usb_tll_hs_usb_ch2_clk" },
3552 { .role = "usb_ch0_clk", .clk = "usb_tll_hs_usb_ch0_clk" },
3553 { .role = "usb_ch1_clk", .clk = "usb_tll_hs_usb_ch1_clk" },
3554 };
3556 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
3557 .name = "usb_tll_hs",
3558 .class = &omap54xx_usb_tll_hs_hwmod_class,
3559 .clkdm_name = "l3init_clkdm",
3560 .mpu_irqs = omap54xx_usb_tll_hs_irqs,
3561 .main_clk = "l4_root_clk_div",
3562 .prcm = {
3563 .omap4 = {
3564 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
3565 .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
3566 .modulemode = MODULEMODE_HWCTRL,
3567 },
3568 },
3569 .opt_clks = usb_tll_hs_opt_clks,
3570 .opt_clks_cnt = ARRAY_SIZE(usb_tll_hs_opt_clks),
3571 };
3573 /*
3574 * 'wd_timer' class
3575 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3576 * overflow condition
3577 */
3579 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
3580 .rev_offs = 0x0000,
3581 .sysc_offs = 0x0010,
3582 .syss_offs = 0x0014,
3583 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3584 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3585 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3586 SIDLE_SMART_WKUP),
3587 .sysc_fields = &omap_hwmod_sysc_type1,
3588 };
3590 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
3591 .name = "wd_timer",
3592 .sysc = &omap54xx_wd_timer_sysc,
3593 .pre_shutdown = &omap2_wd_timer_disable,
3594 };
3596 /* wd_timer2 */
3597 static struct omap_hwmod_irq_info omap54xx_wd_timer2_irqs[] = {
3598 { .irq = 80 + OMAP54XX_IRQ_GIC_START },
3599 { .irq = -1 }
3600 };
3602 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
3603 .name = "wd_timer2",
3604 .class = &omap54xx_wd_timer_hwmod_class,
3605 .clkdm_name = "wkupaon_clkdm",
3606 .mpu_irqs = omap54xx_wd_timer2_irqs,
3607 .main_clk = "sys_32k_ck",
3608 .prcm = {
3609 .omap4 = {
3610 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
3611 .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
3612 .modulemode = MODULEMODE_SWCTRL,
3613 },
3614 },
3615 };
3617 /* wd_timer3 */
3618 static struct omap_hwmod_irq_info omap54xx_wd_timer3_irqs[] = {
3619 { .irq = 36 + OMAP54XX_IRQ_GIC_START },
3620 { .irq = -1 }
3621 };
3623 static struct omap_hwmod omap54xx_wd_timer3_hwmod = {
3624 .name = "wd_timer3",
3625 .class = &omap54xx_wd_timer_hwmod_class,
3626 .clkdm_name = "abe_clkdm",
3627 .mpu_irqs = omap54xx_wd_timer3_irqs,
3628 .main_clk = "sys_32k_ck",
3629 .prcm = {
3630 .omap4 = {
3631 .clkctrl_offs = OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET,
3632 .context_offs = OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET,
3633 .modulemode = MODULEMODE_SWCTRL,
3634 },
3635 },
3636 };
3639 /*
3640 * Interfaces
3641 */
3643 static struct omap_hwmod_addr_space omap54xx_dmm_addrs[] = {
3644 {
3645 .pa_start = 0x4e000000,
3646 .pa_end = 0x4e0007ff,
3647 .flags = ADDR_TYPE_RT
3648 },
3649 { }
3650 };
3652 /* l3_main_1 -> dmm */
3653 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
3654 .master = &omap54xx_l3_main_1_hwmod,
3655 .slave = &omap54xx_dmm_hwmod,
3656 .clk = "l3_iclk_div",
3657 .addr = omap54xx_dmm_addrs,
3658 .user = OCP_USER_SDMA,
3659 };
3661 /* dmm -> emif_ocp_fw */
3662 static struct omap_hwmod_ocp_if omap54xx_dmm__emif_ocp_fw = {
3663 .master = &omap54xx_dmm_hwmod,
3664 .slave = &omap54xx_emif_ocp_fw_hwmod,
3665 .clk = "l3_iclk_div",
3666 .user = OCP_USER_MPU | OCP_USER_SDMA,
3667 };
3669 static struct omap_hwmod_addr_space omap54xx_emif_ocp_fw_addrs[] = {
3670 {
3671 .pa_start = 0x4a20c000,
3672 .pa_end = 0x4a20c0ff,
3673 },
3674 { }
3675 };
3677 /* l4_cfg -> emif_ocp_fw */
3678 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__emif_ocp_fw = {
3679 .master = &omap54xx_l4_cfg_hwmod,
3680 .slave = &omap54xx_emif_ocp_fw_hwmod,
3681 .clk = "l3_iclk_div",
3682 .addr = omap54xx_emif_ocp_fw_addrs,
3683 .user = OCP_USER_MPU,
3684 };
3686 /* l3_main_3 -> l3_instr */
3687 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
3688 .master = &omap54xx_l3_main_3_hwmod,
3689 .slave = &omap54xx_l3_instr_hwmod,
3690 .clk = "l3_iclk_div",
3691 .user = OCP_USER_MPU | OCP_USER_SDMA,
3692 };
3694 /* ocp_wp_noc -> l3_instr */
3695 static struct omap_hwmod_ocp_if omap54xx_ocp_wp_noc__l3_instr = {
3696 .master = &omap54xx_ocp_wp_noc_hwmod,
3697 .slave = &omap54xx_l3_instr_hwmod,
3698 .clk = "l3_iclk_div",
3699 .user = OCP_USER_MPU | OCP_USER_SDMA,
3700 };
3702 /* l3_main_2 -> l3_main_1 */
3703 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
3704 .master = &omap54xx_l3_main_2_hwmod,
3705 .slave = &omap54xx_l3_main_1_hwmod,
3706 .clk = "l3_iclk_div",
3707 .user = OCP_USER_MPU | OCP_USER_SDMA,
3708 };
3710 /* l4_cfg -> l3_main_1 */
3711 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
3712 .master = &omap54xx_l4_cfg_hwmod,
3713 .slave = &omap54xx_l3_main_1_hwmod,
3714 .clk = "l3_iclk_div",
3715 .user = OCP_USER_MPU | OCP_USER_SDMA,
3716 };
3718 static struct omap_hwmod_addr_space omap54xx_l3_main_1_addrs[] = {
3719 {
3720 .pa_start = 0x44000000,
3721 .pa_end = 0x44001fff,
3722 },
3723 { }
3724 };
3726 /* mpu -> l3_main_1 */
3727 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
3728 .master = &omap54xx_mpu_hwmod,
3729 .slave = &omap54xx_l3_main_1_hwmod,
3730 .clk = "l3_iclk_div",
3731 .addr = omap54xx_l3_main_1_addrs,
3732 .user = OCP_USER_MPU,
3733 };
3735 static struct omap_hwmod_addr_space omap54xx_l3_main_2_addrs[] = {
3736 {
3737 .pa_start = 0x44800000,
3738 .pa_end = 0x44802fff,
3739 },
3740 { }
3741 };
3743 /* l3_main_1 -> l3_main_2 */
3744 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
3745 .master = &omap54xx_l3_main_1_hwmod,
3746 .slave = &omap54xx_l3_main_2_hwmod,
3747 .clk = "l3_iclk_div",
3748 .addr = omap54xx_l3_main_2_addrs,
3749 .user = OCP_USER_MPU,
3750 };
3752 /* l4_cfg -> l3_main_2 */
3753 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
3754 .master = &omap54xx_l4_cfg_hwmod,
3755 .slave = &omap54xx_l3_main_2_hwmod,
3756 .clk = "l3_iclk_div",
3757 .user = OCP_USER_MPU | OCP_USER_SDMA,
3758 };
3760 static struct omap_hwmod_addr_space omap54xx_l3_main_3_addrs[] = {
3761 {
3762 .pa_start = 0x45000000,
3763 .pa_end = 0x45003fff,
3764 },
3765 { }
3766 };
3768 /* l3_main_1 -> l3_main_3 */
3769 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
3770 .master = &omap54xx_l3_main_1_hwmod,
3771 .slave = &omap54xx_l3_main_3_hwmod,
3772 .clk = "l3_iclk_div",
3773 .addr = omap54xx_l3_main_3_addrs,
3774 .user = OCP_USER_MPU,
3775 };
3777 /* l3_main_2 -> l3_main_3 */
3778 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
3779 .master = &omap54xx_l3_main_2_hwmod,
3780 .slave = &omap54xx_l3_main_3_hwmod,
3781 .clk = "l3_iclk_div",
3782 .user = OCP_USER_MPU | OCP_USER_SDMA,
3783 };
3785 /* l4_cfg -> l3_main_3 */
3786 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
3787 .master = &omap54xx_l4_cfg_hwmod,
3788 .slave = &omap54xx_l3_main_3_hwmod,
3789 .clk = "l3_iclk_div",
3790 .user = OCP_USER_MPU | OCP_USER_SDMA,
3791 };
3793 /* l3_main_1 -> l4_abe */
3794 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
3795 .master = &omap54xx_l3_main_1_hwmod,
3796 .slave = &omap54xx_l4_abe_hwmod,
3797 .clk = "abe_iclk",
3798 .user = OCP_USER_MPU | OCP_USER_SDMA,
3799 };
3801 /* mpu -> l4_abe */
3802 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
3803 .master = &omap54xx_mpu_hwmod,
3804 .slave = &omap54xx_l4_abe_hwmod,
3805 .clk = "abe_iclk",
3806 .user = OCP_USER_MPU | OCP_USER_SDMA,
3807 };
3809 /* l3_main_1 -> l4_cfg */
3810 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
3811 .master = &omap54xx_l3_main_1_hwmod,
3812 .slave = &omap54xx_l4_cfg_hwmod,
3813 .clk = "l4_root_clk_div",
3814 .user = OCP_USER_MPU | OCP_USER_SDMA,
3815 };
3817 /* l3_main_2 -> l4_per */
3818 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
3819 .master = &omap54xx_l3_main_2_hwmod,
3820 .slave = &omap54xx_l4_per_hwmod,
3821 .clk = "l4_root_clk_div",
3822 .user = OCP_USER_MPU | OCP_USER_SDMA,
3823 };
3825 /* l3_main_1 -> l4_wkup */
3826 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
3827 .master = &omap54xx_l3_main_1_hwmod,
3828 .slave = &omap54xx_l4_wkup_hwmod,
3829 .clk = "wkupaon_iclk_mux",
3830 .user = OCP_USER_MPU | OCP_USER_SDMA,
3831 };
3833 /* mpu -> mpu_private */
3834 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
3835 .master = &omap54xx_mpu_hwmod,
3836 .slave = &omap54xx_mpu_private_hwmod,
3837 .clk = "l3_iclk_div",
3838 .user = OCP_USER_MPU | OCP_USER_SDMA,
3839 };
3841 /* l3_main_3 -> ocp_wp_noc */
3842 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__ocp_wp_noc = {
3843 .master = &omap54xx_l3_main_3_hwmod,
3844 .slave = &omap54xx_ocp_wp_noc_hwmod,
3845 .clk = "l3_iclk_div",
3846 .user = OCP_USER_MPU | OCP_USER_SDMA,
3847 };
3849 static struct omap_hwmod_addr_space omap54xx_ocp_wp_noc_addrs[] = {
3850 {
3851 .pa_start = 0x4a102000,
3852 .pa_end = 0x4a10207f,
3853 .flags = ADDR_TYPE_RT
3854 },
3855 { }
3856 };
3858 /* l4_cfg -> ocp_wp_noc */
3859 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp_wp_noc = {
3860 .master = &omap54xx_l4_cfg_hwmod,
3861 .slave = &omap54xx_ocp_wp_noc_hwmod,
3862 .clk = "l3_iclk_div",
3863 .addr = omap54xx_ocp_wp_noc_addrs,
3864 .user = OCP_USER_MPU,
3865 };
3867 static struct omap_hwmod_addr_space omap54xx_aess_addrs[] = {
3868 {
3869 .name = "dmem",
3870 .pa_start = 0x40180000,
3871 .pa_end = 0x4018ffff,
3872 },
3873 {
3874 .name = "cmem",
3875 .pa_start = 0x401a0000,
3876 .pa_end = 0x401a1fff,
3877 },
3878 {
3879 .name = "smem",
3880 .pa_start = 0x401c0000,
3881 .pa_end = 0x401c5fff,
3882 },
3883 {
3884 .name = "pmem",
3885 .pa_start = 0x401e0000,
3886 .pa_end = 0x401e1fff,
3887 },
3888 {
3889 .name = "aess",
3890 .pa_start = 0x401f1000,
3891 .pa_end = 0x401f13ff,
3892 .flags = ADDR_TYPE_RT
3893 },
3894 { }
3895 };
3897 /* l4_abe -> aess */
3898 static struct omap_hwmod_ocp_if omap54xx_l4_abe__aess = {
3899 .master = &omap54xx_l4_abe_hwmod,
3900 .slave = &omap54xx_aess_hwmod,
3901 .clk = "abe_iclk",
3902 .addr = omap54xx_aess_addrs,
3903 .user = OCP_USER_MPU,
3904 };
3906 static struct omap_hwmod_addr_space omap54xx_aess_dma_addrs[] = {
3907 {
3908 .name = "dmem_dma",
3909 .pa_start = 0x49080000,
3910 .pa_end = 0x4908ffff,
3911 },
3912 {
3913 .name = "cmem_dma",
3914 .pa_start = 0x490a0000,
3915 .pa_end = 0x490a1fff,
3916 },
3917 {
3918 .name = "smem_dma",
3919 .pa_start = 0x490c0000,
3920 .pa_end = 0x490c5fff,
3921 },
3922 {
3923 .name = "pmem_dma",
3924 .pa_start = 0x490e0000,
3925 .pa_end = 0x490e1fff,
3926 },
3927 {
3928 .name = "aess_dma",
3929 .pa_start = 0x490f1000,
3930 .pa_end = 0x490f13ff,
3931 },
3932 { }
3933 };
3935 /* l4_abe -> aess (dma) */
3936 static struct omap_hwmod_ocp_if omap54xx_l4_abe__aess_dma = {
3937 .master = &omap54xx_l4_abe_hwmod,
3938 .slave = &omap54xx_aess_hwmod,
3939 .clk = "abe_iclk",
3940 .addr = omap54xx_aess_dma_addrs,
3941 .user = OCP_USER_SDMA,
3942 };
3944 /* l3_main_2 -> bb2d */
3945 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__bb2d = {
3946 .master = &omap54xx_l3_main_2_hwmod,
3947 .slave = &omap54xx_bb2d_hwmod,
3948 .clk = "l3_iclk_div",
3949 .user = OCP_USER_MPU | OCP_USER_SDMA,
3950 };
3952 static struct omap_hwmod_addr_space omap54xx_c2c_addrs[] = {
3953 {
3954 .pa_start = 0x5c000000,
3955 .pa_end = 0x5c0000ff,
3956 .flags = ADDR_TYPE_RT
3957 },
3958 { }
3959 };
3961 /* l3_main_2 -> c2c */
3962 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__c2c = {
3963 .master = &omap54xx_l3_main_2_hwmod,
3964 .slave = &omap54xx_c2c_hwmod,
3965 .clk = "c2c_fclk",
3966 .addr = omap54xx_c2c_addrs,
3967 .user = OCP_USER_MPU | OCP_USER_SDMA,
3968 };
3970 static struct omap_hwmod_addr_space omap54xx_counter_32k_addrs[] = {
3971 {
3972 .pa_start = 0x4ae04000,
3973 .pa_end = 0x4ae0403f,
3974 .flags = ADDR_TYPE_RT
3975 },
3976 { }
3977 };
3979 /* l4_wkup -> counter_32k */
3980 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
3981 .master = &omap54xx_l4_wkup_hwmod,
3982 .slave = &omap54xx_counter_32k_hwmod,
3983 .clk = "wkupaon_iclk_mux",
3984 .addr = omap54xx_counter_32k_addrs,
3985 .user = OCP_USER_MPU | OCP_USER_SDMA,
3986 };
3988 static struct omap_hwmod_addr_space omap54xx_ctrl_module_core_addrs[] = {
3989 {
3990 .name = "omap_control_core_core",
3991 .pa_start = 0x4a002000,
3992 .pa_end = 0x4a0027ff,
3993 .flags = ADDR_TYPE_RT
3994 },
3995 {
3996 .name = "omap_control_core_pad",
3997 .pa_start = 0x4a002800,
3998 .pa_end = 0x4a002fff,
3999 .flags = ADDR_TYPE_RT
4000 },
4001 { }
4002 };
4004 /* l4_cfg -> ctrl_module_core */
4005 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ctrl_module_core = {
4006 .master = &omap54xx_l4_cfg_hwmod,
4007 .slave = &omap54xx_ctrl_module_core_hwmod,
4008 .clk = "l4_root_clk_div",
4009 .addr = omap54xx_ctrl_module_core_addrs,
4010 .user = OCP_USER_MPU | OCP_USER_SDMA,
4011 };
4013 static struct omap_hwmod_addr_space omap54xx_ctrl_module_wkup_addrs[] = {
4014 {
4015 .name = "omap_control_wkup_core",
4016 .pa_start = 0x4ae0c000,
4017 .pa_end = 0x4ae0c7ff,
4018 .flags = ADDR_TYPE_RT
4019 },
4020 {
4021 .name = "omap_control_wkup_pad",
4022 .pa_start = 0x4ae0c800,
4023 .pa_end = 0x4ae0cfff,
4024 .flags = ADDR_TYPE_RT
4025 },
4026 { }
4027 };
4029 /* l4_wkup -> ctrl_module_wkup */
4030 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__ctrl_module_wkup = {
4031 .master = &omap54xx_l4_wkup_hwmod,
4032 .slave = &omap54xx_ctrl_module_wkup_hwmod,
4033 .clk = "wkupaon_iclk_mux",
4034 .addr = omap54xx_ctrl_module_wkup_addrs,
4035 .user = OCP_USER_MPU | OCP_USER_SDMA,
4036 };
4038 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
4039 {
4040 .pa_start = 0x4a056000,
4041 .pa_end = 0x4a056fff,
4042 .flags = ADDR_TYPE_RT
4043 },
4044 { }
4045 };
4047 /* l4_cfg -> dma_system */
4048 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
4049 .master = &omap54xx_l4_cfg_hwmod,
4050 .slave = &omap54xx_dma_system_hwmod,
4051 .clk = "l4_root_clk_div",
4052 .addr = omap54xx_dma_system_addrs,
4053 .user = OCP_USER_MPU | OCP_USER_SDMA,
4054 };
4056 static struct omap_hwmod_addr_space omap54xx_dmic_addrs[] = {
4057 {
4058 .name = "mpu",
4059 .pa_start = 0x4012e000,
4060 .pa_end = 0x4012e07f,
4061 .flags = ADDR_TYPE_RT
4062 },
4063 { }
4064 };
4066 /* l4_abe -> dmic */
4067 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
4068 .master = &omap54xx_l4_abe_hwmod,
4069 .slave = &omap54xx_dmic_hwmod,
4070 .clk = "abe_iclk",
4071 .addr = omap54xx_dmic_addrs,
4072 .user = OCP_USER_MPU,
4073 };
4075 static struct omap_hwmod_addr_space omap54xx_dmic_dma_addrs[] = {
4076 {
4077 .name = "dma",
4078 .pa_start = 0x4902e000,
4079 .pa_end = 0x4902e07f,
4080 },
4081 { }
4082 };
4084 /* l4_abe -> dmic (dma) */
4085 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic_dma = {
4086 .master = &omap54xx_l4_abe_hwmod,
4087 .slave = &omap54xx_dmic_hwmod,
4088 .clk = "abe_iclk",
4089 .addr = omap54xx_dmic_dma_addrs,
4090 .user = OCP_USER_SDMA,
4091 };
4093 /* l4_cfg -> dsp */
4094 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dsp = {
4095 .master = &omap54xx_l4_cfg_hwmod,
4096 .slave = &omap54xx_dsp_hwmod,
4097 .clk = "l4_root_clk_div",
4098 .user = OCP_USER_MPU | OCP_USER_SDMA,
4099 };
4101 static struct omap_hwmod_addr_space omap54xx_dss_addrs[] = {
4102 {
4103 .pa_start = 0x58000000,
4104 .pa_end = 0x5800007f,
4105 .flags = ADDR_TYPE_RT
4106 },
4107 { }
4108 };
4110 /* l3_main_2 -> dss */
4111 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
4112 .master = &omap54xx_l3_main_2_hwmod,
4113 .slave = &omap54xx_dss_hwmod,
4114 .clk = "l3_iclk_div",
4115 .addr = omap54xx_dss_addrs,
4116 .user = OCP_USER_MPU | OCP_USER_SDMA,
4117 };
4119 static struct omap_hwmod_addr_space omap54xx_dss_dispc_addrs[] = {
4120 {
4121 .pa_start = 0x58001000,
4122 .pa_end = 0x58001fff,
4123 .flags = ADDR_TYPE_RT
4124 },
4125 { }
4126 };
4128 /* l3_main_2 -> dss_dispc */
4129 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
4130 .master = &omap54xx_l3_main_2_hwmod,
4131 .slave = &omap54xx_dss_dispc_hwmod,
4132 .clk = "l3_iclk_div",
4133 .addr = omap54xx_dss_dispc_addrs,
4134 .user = OCP_USER_MPU | OCP_USER_SDMA,
4135 };
4137 static struct omap_hwmod_addr_space omap54xx_dss_dsi1_a_addrs[] = {
4138 {
4139 .pa_start = 0x58004000,
4140 .pa_end = 0x580041ff,
4141 .flags = ADDR_TYPE_RT
4142 },
4143 { }
4144 };
4146 /* l3_main_2 -> dss_dsi1_a */
4147 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
4148 .master = &omap54xx_l3_main_2_hwmod,
4149 .slave = &omap54xx_dss_dsi1_a_hwmod,
4150 .clk = "l3_iclk_div",
4151 .addr = omap54xx_dss_dsi1_a_addrs,
4152 .user = OCP_USER_MPU | OCP_USER_SDMA,
4153 };
4155 static struct omap_hwmod_addr_space omap54xx_dss_dsi1_b_addrs[] = {
4156 {
4157 .pa_start = 0x58005000,
4158 .pa_end = 0x580051ff,
4159 .flags = ADDR_TYPE_RT
4160 },
4161 { }
4162 };
4164 /* l3_main_2 -> dss_dsi1_b */
4165 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_b = {
4166 .master = &omap54xx_l3_main_2_hwmod,
4167 .slave = &omap54xx_dss_dsi1_b_hwmod,
4168 .clk = "l3_iclk_div",
4169 .addr = omap54xx_dss_dsi1_b_addrs,
4170 .user = OCP_USER_MPU | OCP_USER_SDMA,
4171 };
4173 static struct omap_hwmod_addr_space omap54xx_dss_dsi1_c_addrs[] = {
4174 {
4175 .pa_start = 0x58009000,
4176 .pa_end = 0x580091ff,
4177 .flags = ADDR_TYPE_RT
4178 },
4179 { }
4180 };
4182 /* l3_main_2 -> dss_dsi1_c */
4183 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
4184 .master = &omap54xx_l3_main_2_hwmod,
4185 .slave = &omap54xx_dss_dsi1_c_hwmod,
4186 .clk = "l3_iclk_div",
4187 .addr = omap54xx_dss_dsi1_c_addrs,
4188 .user = OCP_USER_MPU | OCP_USER_SDMA,
4189 };
4191 static struct omap_hwmod_addr_space omap54xx_dss_hdmi_addrs[] = {
4192 {
4193 .name = "hdmi_wp",
4194 .pa_start = 0x58040000,
4195 .pa_end = 0x580400ff,
4196 .flags = ADDR_TYPE_RT
4197 },
4198 {
4199 .name = "pllctrl",
4200 .pa_start = 0x58040200,
4201 .pa_end = 0x5804023f,
4202 },
4203 {
4204 .name = "hdmitxphy",
4205 .pa_start = 0x58040300,
4206 .pa_end = 0x5804033f,
4207 },
4208 {
4209 .name = "hdmi_core",
4210 .pa_start = 0x58060000,
4211 .pa_end = 0x58078fff,
4212 },
4213 { }
4214 };
4216 /* l3_main_2 -> dss_hdmi */
4217 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
4218 .master = &omap54xx_l3_main_2_hwmod,
4219 .slave = &omap54xx_dss_hdmi_hwmod,
4220 .clk = "l3_iclk_div",
4221 .addr = omap54xx_dss_hdmi_addrs,
4222 .user = OCP_USER_MPU | OCP_USER_SDMA,
4223 };
4225 static struct omap_hwmod_addr_space omap54xx_dss_rfbi_addrs[] = {
4226 {
4227 .pa_start = 0x58002000,
4228 .pa_end = 0x580020ff,
4229 .flags = ADDR_TYPE_RT
4230 },
4231 { }
4232 };
4234 /* l3_main_2 -> dss_rfbi */
4235 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
4236 .master = &omap54xx_l3_main_2_hwmod,
4237 .slave = &omap54xx_dss_rfbi_hwmod,
4238 .clk = "l3_iclk_div",
4239 .addr = omap54xx_dss_rfbi_addrs,
4240 .user = OCP_USER_MPU | OCP_USER_SDMA,
4241 };
4243 static struct omap_hwmod_addr_space omap54xx_elm_addrs[] = {
4244 {
4245 .pa_start = 0x48078000,
4246 .pa_end = 0x48078fff,
4247 .flags = ADDR_TYPE_RT
4248 },
4249 { }
4250 };
4252 /* l4_per -> elm */
4253 static struct omap_hwmod_ocp_if omap54xx_l4_per__elm = {
4254 .master = &omap54xx_l4_per_hwmod,
4255 .slave = &omap54xx_elm_hwmod,
4256 .clk = "l4_root_clk_div",
4257 .addr = omap54xx_elm_addrs,
4258 .user = OCP_USER_MPU | OCP_USER_SDMA,
4259 };
4261 /* emif_ocp_fw -> emif1 */
4262 static struct omap_hwmod_ocp_if omap54xx_emif_ocp_fw__emif1 = {
4263 .master = &omap54xx_emif_ocp_fw_hwmod,
4264 .slave = &omap54xx_emif1_hwmod,
4265 .clk = "dpll_core_h11x2_ck",
4266 .user = OCP_USER_MPU | OCP_USER_SDMA,
4267 };
4269 static struct omap_hwmod_addr_space omap54xx_emif1_addrs[] = {
4270 {
4271 .pa_start = 0x4c000000,
4272 .pa_end = 0x4c0003ff,
4273 .flags = ADDR_TYPE_RT
4274 },
4275 { }
4276 };
4278 /* mpu -> emif1 */
4279 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
4280 .master = &omap54xx_mpu_hwmod,
4281 .slave = &omap54xx_emif1_hwmod,
4282 .clk = "dpll_core_h11x2_ck",
4283 .addr = omap54xx_emif1_addrs,
4284 .user = OCP_USER_MPU,
4285 };
4287 /* emif_ocp_fw -> emif2 */
4288 static struct omap_hwmod_ocp_if omap54xx_emif_ocp_fw__emif2 = {
4289 .master = &omap54xx_emif_ocp_fw_hwmod,
4290 .slave = &omap54xx_emif2_hwmod,
4291 .clk = "dpll_core_h11x2_ck",
4292 .user = OCP_USER_MPU | OCP_USER_SDMA,
4293 };
4295 static struct omap_hwmod_addr_space omap54xx_emif2_addrs[] = {
4296 {
4297 .pa_start = 0x4d000000,
4298 .pa_end = 0x4d0003ff,
4299 .flags = ADDR_TYPE_RT
4300 },
4301 { }
4302 };
4304 /* mpu -> emif2 */
4305 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
4306 .master = &omap54xx_mpu_hwmod,
4307 .slave = &omap54xx_emif2_hwmod,
4308 .clk = "dpll_core_h11x2_ck",
4309 .addr = omap54xx_emif2_addrs,
4310 .user = OCP_USER_MPU,
4311 };
4313 static struct omap_hwmod_addr_space omap54xx_fdif_addrs[] = {
4314 {
4315 .pa_start = 0x4a10a000,
4316 .pa_end = 0x4a10a3ff,
4317 .flags = ADDR_TYPE_RT
4318 },
4319 { }
4320 };
4322 /* l4_cfg -> fdif */
4323 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__fdif = {
4324 .master = &omap54xx_l4_cfg_hwmod,
4325 .slave = &omap54xx_fdif_hwmod,
4326 .clk = "l4_root_clk_div",
4327 .addr = omap54xx_fdif_addrs,
4328 .user = OCP_USER_MPU | OCP_USER_SDMA,
4329 };
4331 static struct omap_hwmod_addr_space omap54xx_gpio1_addrs[] = {
4332 {
4333 .pa_start = 0x4ae10000,
4334 .pa_end = 0x4ae101ff,
4335 .flags = ADDR_TYPE_RT
4336 },
4337 { }
4338 };
4340 /* l4_wkup -> gpio1 */
4341 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
4342 .master = &omap54xx_l4_wkup_hwmod,
4343 .slave = &omap54xx_gpio1_hwmod,
4344 .clk = "wkupaon_iclk_mux",
4345 .addr = omap54xx_gpio1_addrs,
4346 .user = OCP_USER_MPU | OCP_USER_SDMA,
4347 };
4349 static struct omap_hwmod_addr_space omap54xx_gpio2_addrs[] = {
4350 {
4351 .pa_start = 0x48055000,
4352 .pa_end = 0x480551ff,
4353 .flags = ADDR_TYPE_RT
4354 },
4355 { }
4356 };
4358 /* l4_per -> gpio2 */
4359 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
4360 .master = &omap54xx_l4_per_hwmod,
4361 .slave = &omap54xx_gpio2_hwmod,
4362 .clk = "l4_root_clk_div",
4363 .addr = omap54xx_gpio2_addrs,
4364 .user = OCP_USER_MPU | OCP_USER_SDMA,
4365 };
4367 static struct omap_hwmod_addr_space omap54xx_gpio3_addrs[] = {
4368 {
4369 .pa_start = 0x48057000,
4370 .pa_end = 0x480571ff,
4371 .flags = ADDR_TYPE_RT
4372 },
4373 { }
4374 };
4376 /* l4_per -> gpio3 */
4377 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
4378 .master = &omap54xx_l4_per_hwmod,
4379 .slave = &omap54xx_gpio3_hwmod,
4380 .clk = "l4_root_clk_div",
4381 .addr = omap54xx_gpio3_addrs,
4382 .user = OCP_USER_MPU | OCP_USER_SDMA,
4383 };
4385 static struct omap_hwmod_addr_space omap54xx_gpio4_addrs[] = {
4386 {
4387 .pa_start = 0x48059000,
4388 .pa_end = 0x480591ff,
4389 .flags = ADDR_TYPE_RT
4390 },
4391 { }
4392 };
4394 /* l4_per -> gpio4 */
4395 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
4396 .master = &omap54xx_l4_per_hwmod,
4397 .slave = &omap54xx_gpio4_hwmod,
4398 .clk = "l4_root_clk_div",
4399 .addr = omap54xx_gpio4_addrs,
4400 .user = OCP_USER_MPU | OCP_USER_SDMA,
4401 };
4403 static struct omap_hwmod_addr_space omap54xx_gpio5_addrs[] = {
4404 {
4405 .pa_start = 0x4805b000,
4406 .pa_end = 0x4805b1ff,
4407 .flags = ADDR_TYPE_RT
4408 },
4409 { }
4410 };
4412 /* l4_per -> gpio5 */
4413 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
4414 .master = &omap54xx_l4_per_hwmod,
4415 .slave = &omap54xx_gpio5_hwmod,
4416 .clk = "l4_root_clk_div",
4417 .addr = omap54xx_gpio5_addrs,
4418 .user = OCP_USER_MPU | OCP_USER_SDMA,
4419 };
4421 static struct omap_hwmod_addr_space omap54xx_gpio6_addrs[] = {
4422 {
4423 .pa_start = 0x4805d000,
4424 .pa_end = 0x4805d1ff,
4425 .flags = ADDR_TYPE_RT
4426 },
4427 { }
4428 };
4430 /* l4_per -> gpio6 */
4431 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
4432 .master = &omap54xx_l4_per_hwmod,
4433 .slave = &omap54xx_gpio6_hwmod,
4434 .clk = "l4_root_clk_div",
4435 .addr = omap54xx_gpio6_addrs,
4436 .user = OCP_USER_MPU | OCP_USER_SDMA,
4437 };
4439 static struct omap_hwmod_addr_space omap54xx_gpio7_addrs[] = {
4440 {
4441 .pa_start = 0x48051000,
4442 .pa_end = 0x480511ff,
4443 .flags = ADDR_TYPE_RT
4444 },
4445 { }
4446 };
4448 /* l4_per -> gpio7 */
4449 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
4450 .master = &omap54xx_l4_per_hwmod,
4451 .slave = &omap54xx_gpio7_hwmod,
4452 .clk = "l4_root_clk_div",
4453 .addr = omap54xx_gpio7_addrs,
4454 .user = OCP_USER_MPU | OCP_USER_SDMA,
4455 };
4457 static struct omap_hwmod_addr_space omap54xx_gpio8_addrs[] = {
4458 {
4459 .pa_start = 0x48053000,
4460 .pa_end = 0x480531ff,
4461 .flags = ADDR_TYPE_RT
4462 },
4463 { }
4464 };
4466 /* l4_per -> gpio8 */
4467 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
4468 .master = &omap54xx_l4_per_hwmod,
4469 .slave = &omap54xx_gpio8_hwmod,
4470 .clk = "l4_root_clk_div",
4471 .addr = omap54xx_gpio8_addrs,
4472 .user = OCP_USER_MPU | OCP_USER_SDMA,
4473 };
4475 static struct omap_hwmod_addr_space omap54xx_gpmc_addrs[] = {
4476 {
4477 .pa_start = 0x50000000,
4478 .pa_end = 0x500003ff,
4479 .flags = ADDR_TYPE_RT
4480 },
4481 { }
4482 };
4484 /* l3_main_2 -> gpmc */
4485 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__gpmc = {
4486 .master = &omap54xx_l3_main_2_hwmod,
4487 .slave = &omap54xx_gpmc_hwmod,
4488 .clk = "l3_iclk_div",
4489 .addr = omap54xx_gpmc_addrs,
4490 .user = OCP_USER_MPU | OCP_USER_SDMA,
4491 };
4493 static struct omap_hwmod_addr_space omap54xx_gpu_addrs[] = {
4494 {
4495 .name = "klio",
4496 .pa_start = 0x56000000,
4497 .pa_end = 0x56001fff,
4498 },
4499 {
4500 .name = "hydra2",
4501 .pa_start = 0x56004000,
4502 .pa_end = 0x56004fff,
4503 },
4504 {
4505 .name = "klio_0",
4506 .pa_start = 0x56008000,
4507 .pa_end = 0x56009fff,
4508 },
4509 {
4510 .name = "klio_1",
4511 .pa_start = 0x5600c000,
4512 .pa_end = 0x5600dfff,
4513 },
4514 {
4515 .name = "klio_hl",
4516 .pa_start = 0x5600fe00,
4517 .pa_end = 0x5600ffff,
4518 .flags = ADDR_TYPE_RT
4519 },
4520 { }
4521 };
4523 /* l3_main_2 -> gpu */
4524 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__gpu = {
4525 .master = &omap54xx_l3_main_2_hwmod,
4526 .slave = &omap54xx_gpu_hwmod,
4527 .clk = "gpu_l3_iclk",
4528 .addr = omap54xx_gpu_addrs,
4529 .user = OCP_USER_MPU | OCP_USER_SDMA,
4530 };
4532 static struct omap_hwmod_addr_space omap54xx_hdq1w_addrs[] = {
4533 {
4534 .pa_start = 0x480b2000,
4535 .pa_end = 0x480b201f,
4536 .flags = ADDR_TYPE_RT
4537 },
4538 { }
4539 };
4541 /* l4_per -> hdq1w */
4542 static struct omap_hwmod_ocp_if omap54xx_l4_per__hdq1w = {
4543 .master = &omap54xx_l4_per_hwmod,
4544 .slave = &omap54xx_hdq1w_hwmod,
4545 .clk = "l4_root_clk_div",
4546 .addr = omap54xx_hdq1w_addrs,
4547 .user = OCP_USER_MPU | OCP_USER_SDMA,
4548 };
4550 static struct omap_hwmod_addr_space omap54xx_hsi_addrs[] = {
4551 {
4552 .name = "system_32",
4553 .pa_start = 0x4a058000,
4554 .pa_end = 0x4a059fff,
4555 .flags = ADDR_TYPE_RT
4556 },
4557 {
4558 .name = "dte_channels",
4559 .pa_start = 0x4a059800,
4560 .pa_end = 0x4a059bff,
4561 },
4562 {
4563 .name = "hsi_32",
4564 .pa_start = 0x4a05a000,
4565 .pa_end = 0x4a05bfff,
4566 },
4567 { }
4568 };
4570 /* l4_cfg -> hsi */
4571 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__hsi = {
4572 .master = &omap54xx_l4_cfg_hwmod,
4573 .slave = &omap54xx_hsi_hwmod,
4574 .clk = "l3_iclk_div",
4575 .addr = omap54xx_hsi_addrs,
4576 .user = OCP_USER_MPU | OCP_USER_SDMA,
4577 };
4579 static struct omap_hwmod_addr_space omap54xx_i2c1_addrs[] = {
4580 {
4581 .pa_start = 0x48070000,
4582 .pa_end = 0x480700ff,
4583 .flags = ADDR_TYPE_RT
4584 },
4585 { }
4586 };
4588 /* l4_per -> i2c1 */
4589 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
4590 .master = &omap54xx_l4_per_hwmod,
4591 .slave = &omap54xx_i2c1_hwmod,
4592 .clk = "l4_root_clk_div",
4593 .addr = omap54xx_i2c1_addrs,
4594 .user = OCP_USER_MPU | OCP_USER_SDMA,
4595 };
4597 static struct omap_hwmod_addr_space omap54xx_i2c2_addrs[] = {
4598 {
4599 .pa_start = 0x48072000,
4600 .pa_end = 0x480720ff,
4601 .flags = ADDR_TYPE_RT
4602 },
4603 { }
4604 };
4606 /* l4_per -> i2c2 */
4607 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
4608 .master = &omap54xx_l4_per_hwmod,
4609 .slave = &omap54xx_i2c2_hwmod,
4610 .clk = "l4_root_clk_div",
4611 .addr = omap54xx_i2c2_addrs,
4612 .user = OCP_USER_MPU | OCP_USER_SDMA,
4613 };
4615 static struct omap_hwmod_addr_space omap54xx_i2c3_addrs[] = {
4616 {
4617 .pa_start = 0x48060000,
4618 .pa_end = 0x480600ff,
4619 .flags = ADDR_TYPE_RT
4620 },
4621 { }
4622 };
4624 /* l4_per -> i2c3 */
4625 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
4626 .master = &omap54xx_l4_per_hwmod,
4627 .slave = &omap54xx_i2c3_hwmod,
4628 .clk = "l4_root_clk_div",
4629 .addr = omap54xx_i2c3_addrs,
4630 .user = OCP_USER_MPU | OCP_USER_SDMA,
4631 };
4633 static struct omap_hwmod_addr_space omap54xx_i2c4_addrs[] = {
4634 {
4635 .pa_start = 0x4807a000,
4636 .pa_end = 0x4807a0ff,
4637 .flags = ADDR_TYPE_RT
4638 },
4639 { }
4640 };
4642 /* l4_per -> i2c4 */
4643 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
4644 .master = &omap54xx_l4_per_hwmod,
4645 .slave = &omap54xx_i2c4_hwmod,
4646 .clk = "l4_root_clk_div",
4647 .addr = omap54xx_i2c4_addrs,
4648 .user = OCP_USER_MPU | OCP_USER_SDMA,
4649 };
4651 static struct omap_hwmod_addr_space omap54xx_i2c5_addrs[] = {
4652 {
4653 .pa_start = 0x4807c000,
4654 .pa_end = 0x4807c0ff,
4655 .flags = ADDR_TYPE_RT
4656 },
4657 { }
4658 };
4660 /* l4_per -> i2c5 */
4661 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
4662 .master = &omap54xx_l4_per_hwmod,
4663 .slave = &omap54xx_i2c5_hwmod,
4664 .clk = "l4_root_clk_div",
4665 .addr = omap54xx_i2c5_addrs,
4666 .user = OCP_USER_MPU | OCP_USER_SDMA,
4667 };
4669 static struct omap_hwmod_addr_space omap54xx_ipu_addrs[] = {
4670 {
4671 .name = "unicache_mmu",
4672 .pa_start = 0x55080800,
4673 .pa_end = 0x55080fff,
4674 },
4675 {
4676 .name = "teslass_mmu",
4677 .pa_start = 0x55082000,
4678 .pa_end = 0x550820ff,
4679 .flags = ADDR_TYPE_RT
4680 },
4681 { }
4682 };
4684 /* l3_main_2 -> ipu */
4685 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__ipu = {
4686 .master = &omap54xx_l3_main_2_hwmod,
4687 .slave = &omap54xx_ipu_hwmod,
4688 .clk = "l3_iclk_div",
4689 .addr = omap54xx_ipu_addrs,
4690 .user = OCP_USER_MPU | OCP_USER_SDMA,
4691 };
4693 static struct omap_hwmod_addr_space omap54xx_intc_ipu_c0_addrs[] = {
4694 {
4695 .pa_start = 0x48211000,
4696 .pa_end = 0x48211fff,
4697 },
4698 { }
4699 };
4701 /* l3_main_2 -> intc_ipu_c0 */
4702 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__intc_ipu_c0 = {
4703 .master = &omap54xx_l3_main_2_hwmod,
4704 .slave = &omap54xx_intc_ipu_c0_hwmod,
4705 .clk = "l3_iclk_div",
4706 .addr = omap54xx_intc_ipu_c0_addrs,
4707 .user = OCP_USER_MPU | OCP_USER_SDMA,
4708 };
4710 static struct omap_hwmod_addr_space omap54xx_intc_ipu_c1_addrs[] = {
4711 {
4712 .pa_start = 0x48211000,
4713 .pa_end = 0x48211fff,
4714 },
4715 { }
4716 };
4718 /* l3_main_2 -> intc_ipu_c1 */
4719 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__intc_ipu_c1 = {
4720 .master = &omap54xx_l3_main_2_hwmod,
4721 .slave = &omap54xx_intc_ipu_c1_hwmod,
4722 .clk = "l3_iclk_div",
4723 .addr = omap54xx_intc_ipu_c1_addrs,
4724 .user = OCP_USER_MPU | OCP_USER_SDMA,
4725 };
4727 static struct omap_hwmod_addr_space omap54xx_iss_addrs[] = {
4728 {
4729 .pa_start = 0x52000000,
4730 .pa_end = 0x520000ff,
4731 .flags = ADDR_TYPE_RT
4732 },
4733 { }
4734 };
4736 /* l3_main_2 -> iss */
4737 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__iss = {
4738 .master = &omap54xx_l3_main_2_hwmod,
4739 .slave = &omap54xx_iss_hwmod,
4740 .clk = "dpll_core_h23x2_ck",
4741 .addr = omap54xx_iss_addrs,
4742 .user = OCP_USER_MPU | OCP_USER_SDMA,
4743 };
4745 static struct omap_hwmod_addr_space omap54xx_iva_addrs[] = {
4746 {
4747 .pa_start = 0x5a05a400,
4748 .pa_end = 0x5a05a47f,
4749 .flags = ADDR_TYPE_RT
4750 },
4751 { }
4752 };
4754 /* l3_main_2 -> iva */
4755 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__iva = {
4756 .master = &omap54xx_l3_main_2_hwmod,
4757 .slave = &omap54xx_iva_hwmod,
4758 .clk = "l3_iclk_div",
4759 .addr = omap54xx_iva_addrs,
4760 .user = OCP_USER_MPU | OCP_USER_SDMA,
4761 };
4763 static struct omap_hwmod_addr_space omap54xx_kbd_addrs[] = {
4764 {
4765 .pa_start = 0x4ae1c000,
4766 .pa_end = 0x4ae1c07f,
4767 .flags = ADDR_TYPE_RT
4768 },
4769 { }
4770 };
4772 /* l4_wkup -> kbd */
4773 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
4774 .master = &omap54xx_l4_wkup_hwmod,
4775 .slave = &omap54xx_kbd_hwmod,
4776 .clk = "wkupaon_iclk_mux",
4777 .addr = omap54xx_kbd_addrs,
4778 .user = OCP_USER_MPU | OCP_USER_SDMA,
4779 };
4781 static struct omap_hwmod_addr_space omap54xx_mailbox_addrs[] = {
4782 {
4783 .pa_start = 0x4a0f4000,
4784 .pa_end = 0x4a0f41ff,
4785 .flags = ADDR_TYPE_RT
4786 },
4787 { }
4788 };
4790 /* l4_cfg -> mailbox */
4791 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
4792 .master = &omap54xx_l4_cfg_hwmod,
4793 .slave = &omap54xx_mailbox_hwmod,
4794 .clk = "l4_root_clk_div",
4795 .addr = omap54xx_mailbox_addrs,
4796 .user = OCP_USER_MPU | OCP_USER_SDMA,
4797 };
4799 static struct omap_hwmod_addr_space omap54xx_mcasp_addrs[] = {
4800 {
4801 .name = "cfg",
4802 .pa_start = 0x40128000,
4803 .pa_end = 0x401283ff,
4804 .flags = ADDR_TYPE_RT
4805 },
4806 {
4807 .name = "dat",
4808 .pa_start = 0x4012a000,
4809 .pa_end = 0x4012a3ff,
4810 .flags = ADDR_TYPE_RT
4811 },
4812 { }
4813 };
4815 /* l4_abe -> mcasp */
4816 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcasp = {
4817 .master = &omap54xx_l4_abe_hwmod,
4818 .slave = &omap54xx_mcasp_hwmod,
4819 .clk = "abe_iclk",
4820 .addr = omap54xx_mcasp_addrs,
4821 .user = OCP_USER_MPU,
4822 };
4824 static struct omap_hwmod_addr_space omap54xx_mcasp_dma_addrs[] = {
4825 {
4826 .name = "cfg_dma",
4827 .pa_start = 0x49028000,
4828 .pa_end = 0x490283ff,
4829 },
4830 {
4831 .name = "dat_dma",
4832 .pa_start = 0x4902a000,
4833 .pa_end = 0x4902a3ff,
4834 },
4835 { }
4836 };
4838 /* l4_abe -> mcasp (dma) */
4839 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcasp_dma = {
4840 .master = &omap54xx_l4_abe_hwmod,
4841 .slave = &omap54xx_mcasp_hwmod,
4842 .clk = "abe_iclk",
4843 .addr = omap54xx_mcasp_dma_addrs,
4844 .user = OCP_USER_SDMA,
4845 };
4847 static struct omap_hwmod_addr_space omap54xx_mcbsp1_addrs[] = {
4848 {
4849 .name = "mpu",
4850 .pa_start = 0x40122000,
4851 .pa_end = 0x401220ff,
4852 .flags = ADDR_TYPE_RT
4853 },
4854 { }
4855 };
4857 /* l4_abe -> mcbsp1 */
4858 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
4859 .master = &omap54xx_l4_abe_hwmod,
4860 .slave = &omap54xx_mcbsp1_hwmod,
4861 .clk = "abe_iclk",
4862 .addr = omap54xx_mcbsp1_addrs,
4863 .user = OCP_USER_MPU,
4864 };
4866 static struct omap_hwmod_addr_space omap54xx_mcbsp1_dma_addrs[] = {
4867 {
4868 .name = "dma",
4869 .pa_start = 0x49022000,
4870 .pa_end = 0x490220ff,
4871 },
4872 { }
4873 };
4875 /* l4_abe -> mcbsp1 (dma) */
4876 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1_dma = {
4877 .master = &omap54xx_l4_abe_hwmod,
4878 .slave = &omap54xx_mcbsp1_hwmod,
4879 .clk = "abe_iclk",
4880 .addr = omap54xx_mcbsp1_dma_addrs,
4881 .user = OCP_USER_SDMA,
4882 };
4884 static struct omap_hwmod_addr_space omap54xx_mcbsp2_addrs[] = {
4885 {
4886 .name = "mpu",
4887 .pa_start = 0x40124000,
4888 .pa_end = 0x401240ff,
4889 .flags = ADDR_TYPE_RT
4890 },
4891 { }
4892 };
4894 /* l4_abe -> mcbsp2 */
4895 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
4896 .master = &omap54xx_l4_abe_hwmod,
4897 .slave = &omap54xx_mcbsp2_hwmod,
4898 .clk = "abe_iclk",
4899 .addr = omap54xx_mcbsp2_addrs,
4900 .user = OCP_USER_MPU,
4901 };
4903 static struct omap_hwmod_addr_space omap54xx_mcbsp2_dma_addrs[] = {
4904 {
4905 .name = "dma",
4906 .pa_start = 0x49024000,
4907 .pa_end = 0x490240ff,
4908 },
4909 { }
4910 };
4912 /* l4_abe -> mcbsp2 (dma) */
4913 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2_dma = {
4914 .master = &omap54xx_l4_abe_hwmod,
4915 .slave = &omap54xx_mcbsp2_hwmod,
4916 .clk = "abe_iclk",
4917 .addr = omap54xx_mcbsp2_dma_addrs,
4918 .user = OCP_USER_SDMA,
4919 };
4921 static struct omap_hwmod_addr_space omap54xx_mcbsp3_addrs[] = {
4922 {
4923 .name = "mpu",
4924 .pa_start = 0x40126000,
4925 .pa_end = 0x401260ff,
4926 .flags = ADDR_TYPE_RT
4927 },
4928 { }
4929 };
4931 /* l4_abe -> mcbsp3 */
4932 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
4933 .master = &omap54xx_l4_abe_hwmod,
4934 .slave = &omap54xx_mcbsp3_hwmod,
4935 .clk = "abe_iclk",
4936 .addr = omap54xx_mcbsp3_addrs,
4937 .user = OCP_USER_MPU,
4938 };
4940 static struct omap_hwmod_addr_space omap54xx_mcbsp3_dma_addrs[] = {
4941 {
4942 .name = "dma",
4943 .pa_start = 0x49026000,
4944 .pa_end = 0x490260ff,
4945 },
4946 { }
4947 };
4949 /* l4_abe -> mcbsp3 (dma) */
4950 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3_dma = {
4951 .master = &omap54xx_l4_abe_hwmod,
4952 .slave = &omap54xx_mcbsp3_hwmod,
4953 .clk = "abe_iclk",
4954 .addr = omap54xx_mcbsp3_dma_addrs,
4955 .user = OCP_USER_SDMA,
4956 };
4958 static struct omap_hwmod_addr_space omap54xx_mcpdm_addrs[] = {
4959 {
4960 .name = "mpu",
4961 .pa_start = 0x40132000,
4962 .pa_end = 0x4013207f,
4963 .flags = ADDR_TYPE_RT
4964 },
4965 { }
4966 };
4968 /* l4_abe -> mcpdm */
4969 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
4970 .master = &omap54xx_l4_abe_hwmod,
4971 .slave = &omap54xx_mcpdm_hwmod,
4972 .clk = "abe_iclk",
4973 .addr = omap54xx_mcpdm_addrs,
4974 .user = OCP_USER_MPU,
4975 };
4977 static struct omap_hwmod_addr_space omap54xx_mcpdm_dma_addrs[] = {
4978 {
4979 .name = "dma",
4980 .pa_start = 0x49032000,
4981 .pa_end = 0x4903207f,
4982 },
4983 { }
4984 };
4986 /* l4_abe -> mcpdm (dma) */
4987 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm_dma = {
4988 .master = &omap54xx_l4_abe_hwmod,
4989 .slave = &omap54xx_mcpdm_hwmod,
4990 .clk = "abe_iclk",
4991 .addr = omap54xx_mcpdm_dma_addrs,
4992 .user = OCP_USER_SDMA,
4993 };
4995 static struct omap_hwmod_addr_space omap54xx_mcspi1_addrs[] = {
4996 {
4997 .pa_start = 0x48098000,
4998 .pa_end = 0x480981ff,
4999 .flags = ADDR_TYPE_RT
5000 },
5001 { }
5002 };
5004 /* l4_per -> mcspi1 */
5005 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
5006 .master = &omap54xx_l4_per_hwmod,
5007 .slave = &omap54xx_mcspi1_hwmod,
5008 .clk = "l4_root_clk_div",
5009 .addr = omap54xx_mcspi1_addrs,
5010 .user = OCP_USER_MPU | OCP_USER_SDMA,
5011 };
5013 static struct omap_hwmod_addr_space omap54xx_mcspi2_addrs[] = {
5014 {
5015 .pa_start = 0x4809a000,
5016 .pa_end = 0x4809a1ff,
5017 .flags = ADDR_TYPE_RT
5018 },
5019 { }
5020 };
5022 /* l4_per -> mcspi2 */
5023 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
5024 .master = &omap54xx_l4_per_hwmod,
5025 .slave = &omap54xx_mcspi2_hwmod,
5026 .clk = "l4_root_clk_div",
5027 .addr = omap54xx_mcspi2_addrs,
5028 .user = OCP_USER_MPU | OCP_USER_SDMA,
5029 };
5031 static struct omap_hwmod_addr_space omap54xx_mcspi3_addrs[] = {
5032 {
5033 .pa_start = 0x480b8000,
5034 .pa_end = 0x480b81ff,
5035 .flags = ADDR_TYPE_RT
5036 },
5037 { }
5038 };
5040 /* l4_per -> mcspi3 */
5041 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
5042 .master = &omap54xx_l4_per_hwmod,
5043 .slave = &omap54xx_mcspi3_hwmod,
5044 .clk = "l4_root_clk_div",
5045 .addr = omap54xx_mcspi3_addrs,
5046 .user = OCP_USER_MPU | OCP_USER_SDMA,
5047 };
5049 static struct omap_hwmod_addr_space omap54xx_mcspi4_addrs[] = {
5050 {
5051 .pa_start = 0x480ba000,
5052 .pa_end = 0x480ba1ff,
5053 .flags = ADDR_TYPE_RT
5054 },
5055 { }
5056 };
5058 /* l4_per -> mcspi4 */
5059 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
5060 .master = &omap54xx_l4_per_hwmod,
5061 .slave = &omap54xx_mcspi4_hwmod,
5062 .clk = "l4_root_clk_div",
5063 .addr = omap54xx_mcspi4_addrs,
5064 .user = OCP_USER_MPU | OCP_USER_SDMA,
5065 };
5067 static struct omap_hwmod_addr_space omap54xx_mmc1_addrs[] = {
5068 {
5069 .pa_start = 0x4809c000,
5070 .pa_end = 0x4809c3ff,
5071 .flags = ADDR_TYPE_RT
5072 },
5073 { }
5074 };
5076 /* l4_per -> mmc1 */
5077 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
5078 .master = &omap54xx_l4_per_hwmod,
5079 .slave = &omap54xx_mmc1_hwmod,
5080 .clk = "l3_iclk_div",
5081 .addr = omap54xx_mmc1_addrs,
5082 .user = OCP_USER_MPU | OCP_USER_SDMA,
5083 };
5085 static struct omap_hwmod_addr_space omap54xx_mmc2_addrs[] = {
5086 {
5087 .pa_start = 0x480b4000,
5088 .pa_end = 0x480b43ff,
5089 .flags = ADDR_TYPE_RT
5090 },
5091 { }
5092 };
5094 /* l4_per -> mmc2 */
5095 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
5096 .master = &omap54xx_l4_per_hwmod,
5097 .slave = &omap54xx_mmc2_hwmod,
5098 .clk = "l3_iclk_div",
5099 .addr = omap54xx_mmc2_addrs,
5100 .user = OCP_USER_MPU | OCP_USER_SDMA,
5101 };
5103 static struct omap_hwmod_addr_space omap54xx_mmc3_addrs[] = {
5104 {
5105 .pa_start = 0x480ad000,
5106 .pa_end = 0x480ad3ff,
5107 .flags = ADDR_TYPE_RT
5108 },
5109 { }
5110 };
5112 /* l4_per -> mmc3 */
5113 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
5114 .master = &omap54xx_l4_per_hwmod,
5115 .slave = &omap54xx_mmc3_hwmod,
5116 .clk = "l4_root_clk_div",
5117 .addr = omap54xx_mmc3_addrs,
5118 .user = OCP_USER_MPU | OCP_USER_SDMA,
5119 };
5121 static struct omap_hwmod_addr_space omap54xx_mmc4_addrs[] = {
5122 {
5123 .pa_start = 0x480d1000,
5124 .pa_end = 0x480d13ff,
5125 .flags = ADDR_TYPE_RT
5126 },
5127 { }
5128 };
5130 /* l4_per -> mmc4 */
5131 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
5132 .master = &omap54xx_l4_per_hwmod,
5133 .slave = &omap54xx_mmc4_hwmod,
5134 .clk = "l4_root_clk_div",
5135 .addr = omap54xx_mmc4_addrs,
5136 .user = OCP_USER_MPU | OCP_USER_SDMA,
5137 };
5139 static struct omap_hwmod_addr_space omap54xx_mmc5_addrs[] = {
5140 {
5141 .pa_start = 0x480d5000,
5142 .pa_end = 0x480d53ff,
5143 .flags = ADDR_TYPE_RT
5144 },
5145 { }
5146 };
5148 /* l4_per -> mmc5 */
5149 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
5150 .master = &omap54xx_l4_per_hwmod,
5151 .slave = &omap54xx_mmc5_hwmod,
5152 .clk = "l4_root_clk_div",
5153 .addr = omap54xx_mmc5_addrs,
5154 .user = OCP_USER_MPU | OCP_USER_SDMA,
5155 };
5157 static struct omap_hwmod_addr_space omap54xx_mpu_addrs[] = {
5158 {
5159 .pa_start = 0x48211000,
5160 .pa_end = 0x482af27f,
5161 },
5162 { }
5163 };
5165 /* l4_cfg -> mpu */
5166 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
5167 .master = &omap54xx_l4_cfg_hwmod,
5168 .slave = &omap54xx_mpu_hwmod,
5169 .clk = "l4_root_clk_div",
5170 .addr = omap54xx_mpu_addrs,
5171 .user = OCP_USER_MPU | OCP_USER_SDMA,
5172 };
5174 /* l3_main_2 -> ocmc_ram */
5175 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__ocmc_ram = {
5176 .master = &omap54xx_l3_main_2_hwmod,
5177 .slave = &omap54xx_ocmc_ram_hwmod,
5178 .clk = "l3_iclk_div",
5179 .user = OCP_USER_MPU | OCP_USER_SDMA,
5180 };
5182 static struct omap_hwmod_addr_space omap54xx_ocp2scp1_addrs[] = {
5183 {
5184 .pa_start = 0x4a080000,
5185 .pa_end = 0x4a08001f,
5186 .flags = ADDR_TYPE_RT
5187 },
5188 { }
5189 };
5191 /* l4_cfg -> ocp2scp1 */
5192 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
5193 .master = &omap54xx_l4_cfg_hwmod,
5194 .slave = &omap54xx_ocp2scp1_hwmod,
5195 .clk = "l4_root_clk_div",
5196 .addr = omap54xx_ocp2scp1_addrs,
5197 .user = OCP_USER_MPU | OCP_USER_SDMA,
5198 };
5200 static struct omap_hwmod_addr_space omap54xx_sata_addrs[] = {
5201 {
5202 .name = "ahci",
5203 .pa_start = 0x4a140000,
5204 .pa_end = 0x4a1401ff,
5205 },
5206 {
5207 .name = "sysc",
5208 .pa_start = 0x4a141100,
5209 .pa_end = 0x4a141107,
5210 .flags = ADDR_TYPE_RT
5211 },
5212 { }
5213 };
5215 /* l4_cfg -> sata */
5216 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
5217 .master = &omap54xx_l4_cfg_hwmod,
5218 .slave = &omap54xx_sata_hwmod,
5219 .clk = "l3_iclk_div",
5220 .addr = omap54xx_sata_addrs,
5221 .user = OCP_USER_MPU | OCP_USER_SDMA,
5222 };
5224 static struct omap_hwmod_addr_space omap54xx_scrm_addrs[] = {
5225 {
5226 .pa_start = 0x4ae0a000,
5227 .pa_end = 0x4ae0a7ff,
5228 },
5229 { }
5230 };
5232 /* l4_wkup -> scrm */
5233 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__scrm = {
5234 .master = &omap54xx_l4_wkup_hwmod,
5235 .slave = &omap54xx_scrm_hwmod,
5236 .clk = "wkupaon_iclk_mux",
5237 .addr = omap54xx_scrm_addrs,
5238 .user = OCP_USER_MPU | OCP_USER_SDMA,
5239 };
5241 static struct omap_hwmod_addr_space omap54xx_slimbus1_addrs[] = {
5242 {
5243 .name = "mpu",
5244 .pa_start = 0x4012c000,
5245 .pa_end = 0x4012c3ff,
5246 .flags = ADDR_TYPE_RT
5247 },
5248 { }
5249 };
5251 /* l4_abe -> slimbus1 */
5252 static struct omap_hwmod_ocp_if omap54xx_l4_abe__slimbus1 = {
5253 .master = &omap54xx_l4_abe_hwmod,
5254 .slave = &omap54xx_slimbus1_hwmod,
5255 .clk = "abe_iclk",
5256 .addr = omap54xx_slimbus1_addrs,
5257 .user = OCP_USER_MPU,
5258 };
5260 static struct omap_hwmod_addr_space omap54xx_slimbus1_dma_addrs[] = {
5261 {
5262 .name = "dma",
5263 .pa_start = 0x4902c000,
5264 .pa_end = 0x4902c3ff,
5265 },
5266 { }
5267 };
5269 /* l4_abe -> slimbus1 (dma) */
5270 static struct omap_hwmod_ocp_if omap54xx_l4_abe__slimbus1_dma = {
5271 .master = &omap54xx_l4_abe_hwmod,
5272 .slave = &omap54xx_slimbus1_hwmod,
5273 .clk = "abe_iclk",
5274 .addr = omap54xx_slimbus1_dma_addrs,
5275 .user = OCP_USER_SDMA,
5276 };
5278 static struct omap_hwmod_addr_space omap54xx_smartreflex_core_addrs[] = {
5279 {
5280 .pa_start = 0x4a0dd000,
5281 .pa_end = 0x4a0dd03f,
5282 .flags = ADDR_TYPE_RT
5283 },
5284 { }
5285 };
5287 /* l4_cfg -> smartreflex_core */
5288 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__smartreflex_core = {
5289 .master = &omap54xx_l4_cfg_hwmod,
5290 .slave = &omap54xx_smartreflex_core_hwmod,
5291 .clk = "l4_root_clk_div",
5292 .addr = omap54xx_smartreflex_core_addrs,
5293 .user = OCP_USER_MPU | OCP_USER_SDMA,
5294 };
5296 static struct omap_hwmod_addr_space omap54xx_smartreflex_mm_addrs[] = {
5297 {
5298 .pa_start = 0x4a0db000,
5299 .pa_end = 0x4a0db03f,
5300 .flags = ADDR_TYPE_RT
5301 },
5302 { }
5303 };
5305 /* l4_cfg -> smartreflex_mm */
5306 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__smartreflex_mm = {
5307 .master = &omap54xx_l4_cfg_hwmod,
5308 .slave = &omap54xx_smartreflex_mm_hwmod,
5309 .clk = "l4_root_clk_div",
5310 .addr = omap54xx_smartreflex_mm_addrs,
5311 .user = OCP_USER_MPU | OCP_USER_SDMA,
5312 };
5314 static struct omap_hwmod_addr_space omap54xx_smartreflex_mpu_addrs[] = {
5315 {
5316 .pa_start = 0x4a0d9000,
5317 .pa_end = 0x4a0d903f,
5318 .flags = ADDR_TYPE_RT
5319 },
5320 { }
5321 };
5323 /* l4_cfg -> smartreflex_mpu */
5324 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__smartreflex_mpu = {
5325 .master = &omap54xx_l4_cfg_hwmod,
5326 .slave = &omap54xx_smartreflex_mpu_hwmod,
5327 .clk = "l4_root_clk_div",
5328 .addr = omap54xx_smartreflex_mpu_addrs,
5329 .user = OCP_USER_MPU | OCP_USER_SDMA,
5330 };
5332 static struct omap_hwmod_addr_space omap54xx_spinlock_addrs[] = {
5333 {
5334 .pa_start = 0x4a0f6000,
5335 .pa_end = 0x4a0f6fff,
5336 .flags = ADDR_TYPE_RT
5337 },
5338 { }
5339 };
5341 /* l4_cfg -> spinlock */
5342 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
5343 .master = &omap54xx_l4_cfg_hwmod,
5344 .slave = &omap54xx_spinlock_hwmod,
5345 .clk = "l4_root_clk_div",
5346 .addr = omap54xx_spinlock_addrs,
5347 .user = OCP_USER_MPU | OCP_USER_SDMA,
5348 };
5350 static struct omap_hwmod_addr_space omap54xx_timer1_addrs[] = {
5351 {
5352 .pa_start = 0x4ae18000,
5353 .pa_end = 0x4ae1807f,
5354 .flags = ADDR_TYPE_RT
5355 },
5356 { }
5357 };
5359 /* l4_wkup -> timer1 */
5360 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
5361 .master = &omap54xx_l4_wkup_hwmod,
5362 .slave = &omap54xx_timer1_hwmod,
5363 .clk = "wkupaon_iclk_mux",
5364 .addr = omap54xx_timer1_addrs,
5365 .user = OCP_USER_MPU | OCP_USER_SDMA,
5366 };
5368 static struct omap_hwmod_addr_space omap54xx_timer2_addrs[] = {
5369 {
5370 .pa_start = 0x48032000,
5371 .pa_end = 0x4803207f,
5372 .flags = ADDR_TYPE_RT
5373 },
5374 { }
5375 };
5377 /* l4_per -> timer2 */
5378 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
5379 .master = &omap54xx_l4_per_hwmod,
5380 .slave = &omap54xx_timer2_hwmod,
5381 .clk = "l4_root_clk_div",
5382 .addr = omap54xx_timer2_addrs,
5383 .user = OCP_USER_MPU | OCP_USER_SDMA,
5384 };
5386 static struct omap_hwmod_addr_space omap54xx_timer3_addrs[] = {
5387 {
5388 .pa_start = 0x48034000,
5389 .pa_end = 0x4803407f,
5390 .flags = ADDR_TYPE_RT
5391 },
5392 { }
5393 };
5395 /* l4_per -> timer3 */
5396 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
5397 .master = &omap54xx_l4_per_hwmod,
5398 .slave = &omap54xx_timer3_hwmod,
5399 .clk = "l4_root_clk_div",
5400 .addr = omap54xx_timer3_addrs,
5401 .user = OCP_USER_MPU | OCP_USER_SDMA,
5402 };
5404 static struct omap_hwmod_addr_space omap54xx_timer4_addrs[] = {
5405 {
5406 .pa_start = 0x48036000,
5407 .pa_end = 0x4803607f,
5408 .flags = ADDR_TYPE_RT
5409 },
5410 { }
5411 };
5413 /* l4_per -> timer4 */
5414 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
5415 .master = &omap54xx_l4_per_hwmod,
5416 .slave = &omap54xx_timer4_hwmod,
5417 .clk = "l4_root_clk_div",
5418 .addr = omap54xx_timer4_addrs,
5419 .user = OCP_USER_MPU | OCP_USER_SDMA,
5420 };
5422 static struct omap_hwmod_addr_space omap54xx_timer5_addrs[] = {
5423 {
5424 .name = "mpu",
5425 .pa_start = 0x40138000,
5426 .pa_end = 0x4013807f,
5427 .flags = ADDR_TYPE_RT
5428 },
5429 { }
5430 };
5432 /* l4_abe -> timer5 */
5433 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
5434 .master = &omap54xx_l4_abe_hwmod,
5435 .slave = &omap54xx_timer5_hwmod,
5436 .clk = "abe_iclk",
5437 .addr = omap54xx_timer5_addrs,
5438 .user = OCP_USER_MPU,
5439 };
5441 static struct omap_hwmod_addr_space omap54xx_timer5_dma_addrs[] = {
5442 {
5443 .name = "dma",
5444 .pa_start = 0x49038000,
5445 .pa_end = 0x4903807f,
5446 },
5447 { }
5448 };
5450 /* l4_abe -> timer5 (dma) */
5451 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5_dma = {
5452 .master = &omap54xx_l4_abe_hwmod,
5453 .slave = &omap54xx_timer5_hwmod,
5454 .clk = "abe_iclk",
5455 .addr = omap54xx_timer5_dma_addrs,
5456 .user = OCP_USER_SDMA,
5457 };
5459 static struct omap_hwmod_addr_space omap54xx_timer6_addrs[] = {
5460 {
5461 .name = "mpu",
5462 .pa_start = 0x4013a000,
5463 .pa_end = 0x4013a07f,
5464 .flags = ADDR_TYPE_RT
5465 },
5466 { }
5467 };
5469 /* l4_abe -> timer6 */
5470 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
5471 .master = &omap54xx_l4_abe_hwmod,
5472 .slave = &omap54xx_timer6_hwmod,
5473 .clk = "abe_iclk",
5474 .addr = omap54xx_timer6_addrs,
5475 .user = OCP_USER_MPU,
5476 };
5478 static struct omap_hwmod_addr_space omap54xx_timer6_dma_addrs[] = {
5479 {
5480 .name = "dma",
5481 .pa_start = 0x4903a000,
5482 .pa_end = 0x4903a07f,
5483 },
5484 { }
5485 };
5487 /* l4_abe -> timer6 (dma) */
5488 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6_dma = {
5489 .master = &omap54xx_l4_abe_hwmod,
5490 .slave = &omap54xx_timer6_hwmod,
5491 .clk = "abe_iclk",
5492 .addr = omap54xx_timer6_dma_addrs,
5493 .user = OCP_USER_SDMA,
5494 };
5496 static struct omap_hwmod_addr_space omap54xx_timer7_addrs[] = {
5497 {
5498 .name = "mpu",
5499 .pa_start = 0x4013c000,
5500 .pa_end = 0x4013c07f,
5501 .flags = ADDR_TYPE_RT
5502 },
5503 { }
5504 };
5506 /* l4_abe -> timer7 */
5507 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
5508 .master = &omap54xx_l4_abe_hwmod,
5509 .slave = &omap54xx_timer7_hwmod,
5510 .clk = "abe_iclk",
5511 .addr = omap54xx_timer7_addrs,
5512 .user = OCP_USER_MPU,
5513 };
5515 static struct omap_hwmod_addr_space omap54xx_timer7_dma_addrs[] = {
5516 {
5517 .name = "dma",
5518 .pa_start = 0x4903c000,
5519 .pa_end = 0x4903c07f,
5520 },
5521 { }
5522 };
5524 /* l4_abe -> timer7 (dma) */
5525 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7_dma = {
5526 .master = &omap54xx_l4_abe_hwmod,
5527 .slave = &omap54xx_timer7_hwmod,
5528 .clk = "abe_iclk",
5529 .addr = omap54xx_timer7_dma_addrs,
5530 .user = OCP_USER_SDMA,
5531 };
5533 static struct omap_hwmod_addr_space omap54xx_timer8_addrs[] = {
5534 {
5535 .name = "mpu",
5536 .pa_start = 0x4013e000,
5537 .pa_end = 0x4013e07f,
5538 .flags = ADDR_TYPE_RT
5539 },
5540 { }
5541 };
5543 /* l4_abe -> timer8 */
5544 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
5545 .master = &omap54xx_l4_abe_hwmod,
5546 .slave = &omap54xx_timer8_hwmod,
5547 .clk = "abe_iclk",
5548 .addr = omap54xx_timer8_addrs,
5549 .user = OCP_USER_MPU,
5550 };
5552 static struct omap_hwmod_addr_space omap54xx_timer8_dma_addrs[] = {
5553 {
5554 .name = "dma",
5555 .pa_start = 0x4903e000,
5556 .pa_end = 0x4903e07f,
5557 },
5558 { }
5559 };
5561 /* l4_abe -> timer8 (dma) */
5562 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8_dma = {
5563 .master = &omap54xx_l4_abe_hwmod,
5564 .slave = &omap54xx_timer8_hwmod,
5565 .clk = "abe_iclk",
5566 .addr = omap54xx_timer8_dma_addrs,
5567 .user = OCP_USER_SDMA,
5568 };
5570 static struct omap_hwmod_addr_space omap54xx_timer9_addrs[] = {
5571 {
5572 .pa_start = 0x4803e000,
5573 .pa_end = 0x4803e07f,
5574 .flags = ADDR_TYPE_RT
5575 },
5576 { }
5577 };
5579 /* l4_per -> timer9 */
5580 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
5581 .master = &omap54xx_l4_per_hwmod,
5582 .slave = &omap54xx_timer9_hwmod,
5583 .clk = "l4_root_clk_div",
5584 .addr = omap54xx_timer9_addrs,
5585 .user = OCP_USER_MPU | OCP_USER_SDMA,
5586 };
5588 static struct omap_hwmod_addr_space omap54xx_timer10_addrs[] = {
5589 {
5590 .pa_start = 0x48086000,
5591 .pa_end = 0x4808607f,
5592 .flags = ADDR_TYPE_RT
5593 },
5594 { }
5595 };
5597 /* l4_per -> timer10 */
5598 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
5599 .master = &omap54xx_l4_per_hwmod,
5600 .slave = &omap54xx_timer10_hwmod,
5601 .clk = "l4_root_clk_div",
5602 .addr = omap54xx_timer10_addrs,
5603 .user = OCP_USER_MPU | OCP_USER_SDMA,
5604 };
5606 static struct omap_hwmod_addr_space omap54xx_timer11_addrs[] = {
5607 {
5608 .pa_start = 0x48088000,
5609 .pa_end = 0x4808807f,
5610 .flags = ADDR_TYPE_RT
5611 },
5612 { }
5613 };
5615 /* l4_per -> timer11 */
5616 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
5617 .master = &omap54xx_l4_per_hwmod,
5618 .slave = &omap54xx_timer11_hwmod,
5619 .clk = "l4_root_clk_div",
5620 .addr = omap54xx_timer11_addrs,
5621 .user = OCP_USER_MPU | OCP_USER_SDMA,
5622 };
5624 static struct omap_hwmod_addr_space omap54xx_uart1_addrs[] = {
5625 {
5626 .pa_start = 0x4806a000,
5627 .pa_end = 0x4806a0ff,
5628 .flags = ADDR_TYPE_RT
5629 },
5630 { }
5631 };
5633 /* l4_per -> uart1 */
5634 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
5635 .master = &omap54xx_l4_per_hwmod,
5636 .slave = &omap54xx_uart1_hwmod,
5637 .clk = "l4_root_clk_div",
5638 .addr = omap54xx_uart1_addrs,
5639 .user = OCP_USER_MPU | OCP_USER_SDMA,
5640 };
5642 static struct omap_hwmod_addr_space omap54xx_uart2_addrs[] = {
5643 {
5644 .pa_start = 0x4806c000,
5645 .pa_end = 0x4806c0ff,
5646 .flags = ADDR_TYPE_RT
5647 },
5648 { }
5649 };
5651 /* l4_per -> uart2 */
5652 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
5653 .master = &omap54xx_l4_per_hwmod,
5654 .slave = &omap54xx_uart2_hwmod,
5655 .clk = "l4_root_clk_div",
5656 .addr = omap54xx_uart2_addrs,
5657 .user = OCP_USER_MPU | OCP_USER_SDMA,
5658 };
5660 static struct omap_hwmod_addr_space omap54xx_uart3_addrs[] = {
5661 {
5662 .pa_start = 0x48020000,
5663 .pa_end = 0x480200ff,
5664 .flags = ADDR_TYPE_RT
5665 },
5666 { }
5667 };
5669 /* l4_per -> uart3 */
5670 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
5671 .master = &omap54xx_l4_per_hwmod,
5672 .slave = &omap54xx_uart3_hwmod,
5673 .clk = "l4_root_clk_div",
5674 .addr = omap54xx_uart3_addrs,
5675 .user = OCP_USER_MPU | OCP_USER_SDMA,
5676 };
5678 static struct omap_hwmod_addr_space omap54xx_uart4_addrs[] = {
5679 {
5680 .pa_start = 0x4806e000,
5681 .pa_end = 0x4806e0ff,
5682 .flags = ADDR_TYPE_RT
5683 },
5684 { }
5685 };
5687 /* l4_per -> uart4 */
5688 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
5689 .master = &omap54xx_l4_per_hwmod,
5690 .slave = &omap54xx_uart4_hwmod,
5691 .clk = "l4_root_clk_div",
5692 .addr = omap54xx_uart4_addrs,
5693 .user = OCP_USER_MPU | OCP_USER_SDMA,
5694 };
5696 static struct omap_hwmod_addr_space omap54xx_uart5_addrs[] = {
5697 {
5698 .pa_start = 0x48066000,
5699 .pa_end = 0x480660ff,
5700 .flags = ADDR_TYPE_RT
5701 },
5702 { }
5703 };
5705 /* l4_per -> uart5 */
5706 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
5707 .master = &omap54xx_l4_per_hwmod,
5708 .slave = &omap54xx_uart5_hwmod,
5709 .clk = "l4_root_clk_div",
5710 .addr = omap54xx_uart5_addrs,
5711 .user = OCP_USER_MPU | OCP_USER_SDMA,
5712 };
5714 static struct omap_hwmod_addr_space omap54xx_uart6_addrs[] = {
5715 {
5716 .pa_start = 0x48068000,
5717 .pa_end = 0x480680ff,
5718 .flags = ADDR_TYPE_RT
5719 },
5720 { }
5721 };
5723 /* l4_per -> uart6 */
5724 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
5725 .master = &omap54xx_l4_per_hwmod,
5726 .slave = &omap54xx_uart6_hwmod,
5727 .clk = "l4_root_clk_div",
5728 .addr = omap54xx_uart6_addrs,
5729 .user = OCP_USER_MPU | OCP_USER_SDMA,
5730 };
5732 static struct omap_hwmod_addr_space omap54xx_usb_host_hs_addrs[] = {
5733 {
5734 .name = "uhh",
5735 .pa_start = 0x4a064000,
5736 .pa_end = 0x4a0647ff,
5737 .flags = ADDR_TYPE_RT
5738 },
5739 {
5740 .name = "ohci",
5741 .pa_start = 0x4a064800,
5742 .pa_end = 0x4a06487f,
5743 },
5744 {
5745 .name = "ehci",
5746 .pa_start = 0x4a064c00,
5747 .pa_end = 0x4a064cff,
5748 },
5749 { }
5750 };
5752 /* l4_cfg -> usb_host_hs */
5753 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
5754 .master = &omap54xx_l4_cfg_hwmod,
5755 .slave = &omap54xx_usb_host_hs_hwmod,
5756 .clk = "l3_iclk_div",
5757 .addr = omap54xx_usb_host_hs_addrs,
5758 .user = OCP_USER_MPU | OCP_USER_SDMA,
5759 };
5761 static struct omap_hwmod_addr_space omap54xx_usb_otg_ss_addrs[] = {
5762 {
5763 .name = "wrapper",
5764 .pa_start = 0x4a020000,
5765 .pa_end = 0x4a0201ff,
5766 .flags = ADDR_TYPE_RT
5767 },
5768 {
5769 .name = "dwc_usb3",
5770 .pa_start = 0x4a030000,
5771 .pa_end = 0x4a0300ff,
5772 },
5773 { }
5774 };
5776 /* l4_cfg -> usb_otg_ss */
5777 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
5778 .master = &omap54xx_l4_cfg_hwmod,
5779 .slave = &omap54xx_usb_otg_ss_hwmod,
5780 .clk = "dpll_core_h13x2_ck",
5781 .addr = omap54xx_usb_otg_ss_addrs,
5782 .user = OCP_USER_MPU | OCP_USER_SDMA,
5783 };
5785 static struct omap_hwmod_addr_space omap54xx_usb_tll_hs_addrs[] = {
5786 {
5787 .name = "tll",
5788 .pa_start = 0x4a062000,
5789 .pa_end = 0x4a0627ff,
5790 .flags = ADDR_TYPE_RT
5791 },
5792 {
5793 .name = "ulpi",
5794 .pa_start = 0x4a062800,
5795 .pa_end = 0x4a062bff,
5796 },
5797 { }
5798 };
5800 /* l4_cfg -> usb_tll_hs */
5801 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
5802 .master = &omap54xx_l4_cfg_hwmod,
5803 .slave = &omap54xx_usb_tll_hs_hwmod,
5804 .clk = "l4_root_clk_div",
5805 .addr = omap54xx_usb_tll_hs_addrs,
5806 .user = OCP_USER_MPU | OCP_USER_SDMA,
5807 };
5809 static struct omap_hwmod_addr_space omap54xx_wd_timer2_addrs[] = {
5810 {
5811 .pa_start = 0x4ae14000,
5812 .pa_end = 0x4ae1407f,
5813 .flags = ADDR_TYPE_RT
5814 },
5815 { }
5816 };
5818 /* l4_wkup -> wd_timer2 */
5819 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
5820 .master = &omap54xx_l4_wkup_hwmod,
5821 .slave = &omap54xx_wd_timer2_hwmod,
5822 .clk = "wkupaon_iclk_mux",
5823 .addr = omap54xx_wd_timer2_addrs,
5824 .user = OCP_USER_MPU | OCP_USER_SDMA,
5825 };
5827 static struct omap_hwmod_addr_space omap54xx_wd_timer3_addrs[] = {
5828 {
5829 .name = "mpu",
5830 .pa_start = 0x40130000,
5831 .pa_end = 0x4013007f,
5832 .flags = ADDR_TYPE_RT
5833 },
5834 { }
5835 };
5837 /* l4_abe -> wd_timer3 */
5838 static struct omap_hwmod_ocp_if omap54xx_l4_abe__wd_timer3 = {
5839 .master = &omap54xx_l4_abe_hwmod,
5840 .slave = &omap54xx_wd_timer3_hwmod,
5841 .clk = "abe_iclk",
5842 .addr = omap54xx_wd_timer3_addrs,
5843 .user = OCP_USER_MPU,
5844 };
5846 static struct omap_hwmod_addr_space omap54xx_wd_timer3_dma_addrs[] = {
5847 {
5848 .name = "dma",
5849 .pa_start = 0x49030000,
5850 .pa_end = 0x4903007f,
5851 },
5852 { }
5853 };
5855 /* l4_abe -> wd_timer3 (dma) */
5856 static struct omap_hwmod_ocp_if omap54xx_l4_abe__wd_timer3_dma = {
5857 .master = &omap54xx_l4_abe_hwmod,
5858 .slave = &omap54xx_wd_timer3_hwmod,
5859 .clk = "abe_iclk",
5860 .addr = omap54xx_wd_timer3_dma_addrs,
5861 .user = OCP_USER_SDMA,
5862 };
5864 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
5865 &omap54xx_l3_main_1__dmm,
5866 &omap54xx_dmm__emif_ocp_fw,
5867 &omap54xx_l4_cfg__emif_ocp_fw,
5868 &omap54xx_l3_main_3__l3_instr,
5869 &omap54xx_ocp_wp_noc__l3_instr,
5870 &omap54xx_l3_main_2__l3_main_1,
5871 &omap54xx_l4_cfg__l3_main_1,
5872 &omap54xx_mpu__l3_main_1,
5873 &omap54xx_l3_main_1__l3_main_2,
5874 &omap54xx_l4_cfg__l3_main_2,
5875 &omap54xx_l3_main_1__l3_main_3,
5876 &omap54xx_l3_main_2__l3_main_3,
5877 &omap54xx_l4_cfg__l3_main_3,
5878 &omap54xx_l3_main_1__l4_abe,
5879 &omap54xx_mpu__l4_abe,
5880 &omap54xx_l3_main_1__l4_cfg,
5881 &omap54xx_l3_main_2__l4_per,
5882 &omap54xx_l3_main_1__l4_wkup,
5883 &omap54xx_mpu__mpu_private,
5884 &omap54xx_l3_main_3__ocp_wp_noc,
5885 &omap54xx_l4_cfg__ocp_wp_noc,
5886 &omap54xx_l4_abe__aess,
5887 &omap54xx_l4_abe__aess_dma,
5888 &omap54xx_l3_main_2__bb2d,
5889 &omap54xx_l3_main_2__c2c,
5890 &omap54xx_l4_wkup__counter_32k,
5891 &omap54xx_l4_cfg__ctrl_module_core,
5892 &omap54xx_l4_wkup__ctrl_module_wkup,
5893 &omap54xx_l4_cfg__dma_system,
5894 &omap54xx_l4_abe__dmic,
5895 &omap54xx_l4_abe__dmic_dma,
5896 &omap54xx_l4_cfg__dsp,
5897 &omap54xx_l3_main_2__dss,
5898 &omap54xx_l3_main_2__dss_dispc,
5899 &omap54xx_l3_main_2__dss_dsi1_a,
5900 &omap54xx_l3_main_2__dss_dsi1_b,
5901 &omap54xx_l3_main_2__dss_dsi1_c,
5902 &omap54xx_l3_main_2__dss_hdmi,
5903 &omap54xx_l3_main_2__dss_rfbi,
5904 &omap54xx_l4_per__elm,
5905 &omap54xx_emif_ocp_fw__emif1,
5906 &omap54xx_mpu__emif1,
5907 &omap54xx_emif_ocp_fw__emif2,
5908 &omap54xx_mpu__emif2,
5909 &omap54xx_l4_cfg__fdif,
5910 &omap54xx_l4_wkup__gpio1,
5911 &omap54xx_l4_per__gpio2,
5912 &omap54xx_l4_per__gpio3,
5913 &omap54xx_l4_per__gpio4,
5914 &omap54xx_l4_per__gpio5,
5915 &omap54xx_l4_per__gpio6,
5916 &omap54xx_l4_per__gpio7,
5917 &omap54xx_l4_per__gpio8,
5918 &omap54xx_l3_main_2__gpmc,
5919 &omap54xx_l3_main_2__gpu,
5920 &omap54xx_l4_per__hdq1w,
5921 &omap54xx_l4_cfg__hsi,
5922 &omap54xx_l4_per__i2c1,
5923 &omap54xx_l4_per__i2c2,
5924 &omap54xx_l4_per__i2c3,
5925 &omap54xx_l4_per__i2c4,
5926 &omap54xx_l4_per__i2c5,
5927 &omap54xx_l3_main_2__ipu,
5928 &omap54xx_l3_main_2__intc_ipu_c0,
5929 &omap54xx_l3_main_2__intc_ipu_c1,
5930 &omap54xx_l3_main_2__iss,
5931 &omap54xx_l3_main_2__iva,
5932 &omap54xx_l4_wkup__kbd,
5933 &omap54xx_l4_cfg__mailbox,
5934 &omap54xx_l4_abe__mcasp,
5935 &omap54xx_l4_abe__mcasp_dma,
5936 &omap54xx_l4_abe__mcbsp1,
5937 &omap54xx_l4_abe__mcbsp1_dma,
5938 &omap54xx_l4_abe__mcbsp2,
5939 &omap54xx_l4_abe__mcbsp2_dma,
5940 &omap54xx_l4_abe__mcbsp3,
5941 &omap54xx_l4_abe__mcbsp3_dma,
5942 &omap54xx_l4_abe__mcpdm,
5943 &omap54xx_l4_abe__mcpdm_dma,
5944 &omap54xx_l4_per__mcspi1,
5945 &omap54xx_l4_per__mcspi2,
5946 &omap54xx_l4_per__mcspi3,
5947 &omap54xx_l4_per__mcspi4,
5948 &omap54xx_l4_per__mmc1,
5949 &omap54xx_l4_per__mmc2,
5950 &omap54xx_l4_per__mmc3,
5951 &omap54xx_l4_per__mmc4,
5952 &omap54xx_l4_per__mmc5,
5953 &omap54xx_l4_cfg__mpu,
5954 &omap54xx_l3_main_2__ocmc_ram,
5955 &omap54xx_l4_cfg__ocp2scp1,
5956 &omap54xx_l4_cfg__sata,
5957 &omap54xx_l4_wkup__scrm,
5958 &omap54xx_l4_abe__slimbus1,
5959 &omap54xx_l4_abe__slimbus1_dma,
5960 &omap54xx_l4_cfg__smartreflex_core,
5961 &omap54xx_l4_cfg__smartreflex_mm,
5962 &omap54xx_l4_cfg__smartreflex_mpu,
5963 &omap54xx_l4_cfg__spinlock,
5964 &omap54xx_l4_wkup__timer1,
5965 &omap54xx_l4_per__timer2,
5966 &omap54xx_l4_per__timer3,
5967 &omap54xx_l4_per__timer4,
5968 &omap54xx_l4_abe__timer5,
5969 &omap54xx_l4_abe__timer5_dma,
5970 &omap54xx_l4_abe__timer6,
5971 &omap54xx_l4_abe__timer6_dma,
5972 &omap54xx_l4_abe__timer7,
5973 &omap54xx_l4_abe__timer7_dma,
5974 &omap54xx_l4_abe__timer8,
5975 &omap54xx_l4_abe__timer8_dma,
5976 &omap54xx_l4_per__timer9,
5977 &omap54xx_l4_per__timer10,
5978 &omap54xx_l4_per__timer11,
5979 &omap54xx_l4_per__uart1,
5980 &omap54xx_l4_per__uart2,
5981 &omap54xx_l4_per__uart3,
5982 &omap54xx_l4_per__uart4,
5983 &omap54xx_l4_per__uart5,
5984 &omap54xx_l4_per__uart6,
5985 &omap54xx_l4_cfg__usb_host_hs,
5986 &omap54xx_l4_cfg__usb_otg_ss,
5987 &omap54xx_l4_cfg__usb_tll_hs,
5988 &omap54xx_l4_wkup__wd_timer2,
5989 &omap54xx_l4_abe__wd_timer3,
5990 &omap54xx_l4_abe__wd_timer3_dma,
5991 NULL,
5992 };
5994 int __init omap54xx_hwmod_init(void)
5995 {
5996 omap_hwmod_init();
5997 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
5998 }